From a6163888f3c56123b1db313743c6147ba498732c Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Fri, 8 Aug 2014 14:42:07 +0300 Subject: Add third_party libs --- .../Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h | 111 + .../FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c | 634 ++ .../Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt | 3 + .../Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h | 111 + .../FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c | 633 ++ .../Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt | 3 + .../Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h | 115 + .../FreeRTOS/Demo/CORTEX_LM3S102_GCC/Makefile | 86 + .../Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c | 145 + .../Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h | 18 + .../Demo/CORTEX_LM3S102_GCC/hw_include/debug.h | 56 + .../Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h | 135 + .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h | 82 + .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h | 57 + .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h | 830 ++ .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h | 113 + .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h | 325 + .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h | 63 + .../Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h | 234 + .../Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h | 57 + .../Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c | 132 + .../Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h | 124 + .../Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h | 88 + .../Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h | 221 + .../Demo/CORTEX_LM3S102_GCC/hw_include/uart.h | 102 + .../Demo/CORTEX_LM3S102_GCC/init/startup.c | 175 + .../FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c | 634 ++ .../FreeRTOS/Demo/CORTEX_LM3S102_GCC/makedefs | 193 + .../FreeRTOS/Demo/CORTEX_LM3S102_GCC/standalone.ld | 58 + .../CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h | 112 + .../FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c | 630 ++ .../Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt | 3 + .../CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h | 112 + 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.../CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h | 115 + .../Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c | 145 + .../Demo/CORTEX_LM3S102_Rowley/Demo3/main.c | 323 + .../Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s | 121 + .../Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp | 110 + .../Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs | 105 + .../CORTEX_LM3S102_Rowley/hw_include/DriverLib.h | 20 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt | 126 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h | 112 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h | 40 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h | 56 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h | 75 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h | 135 + .../CORTEX_LM3S102_Rowley/hw_include/hw_comp.h | 113 + .../CORTEX_LM3S102_Rowley/hw_include/hw_flash.h | 141 + .../CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h | 95 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h | 157 + .../CORTEX_LM3S102_Rowley/hw_include/hw_ints.h | 82 + .../CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h | 57 + .../CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h | 830 ++ .../Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h | 113 + .../CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h | 325 + .../CORTEX_LM3S102_Rowley/hw_include/hw_timer.h | 233 + .../CORTEX_LM3S102_Rowley/hw_include/hw_types.h | 63 + .../CORTEX_LM3S102_Rowley/hw_include/hw_uart.h | 234 + .../CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h | 99 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h | 137 + .../CORTEX_LM3S102_Rowley/hw_include/interrupt.h | 57 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c | 132 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h | 124 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h | 88 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h | 221 + .../CORTEX_LM3S102_Rowley/hw_include/systick.h | 53 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h | 137 + .../Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h | 102 + .../CORTEX_LM3S102_Rowley/hw_include/watchdog.h | 63 + .../Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h | 115 + .../FreeRTOS/Demo/CORTEX_LM3S316_IAR/LM3S316.icf | 58 + .../Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c | 145 + .../FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd | 879 ++ .../FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp | 961 ++ .../FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww | 10 + .../FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c | 325 + .../FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h | 87 + .../Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h | 22 + .../Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt | 126 + .../Demo/CORTEX_LM3S316_IAR/hw_include/adc.h | 120 + .../Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h | 130 + .../Demo/CORTEX_LM3S316_IAR/hw_include/comp.h | 120 + .../Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h | 40 + .../Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c | 119 + .../Demo/CORTEX_LM3S316_IAR/hw_include/debug.h | 56 + .../Demo/CORTEX_LM3S316_IAR/hw_include/diag.h | 67 + .../CORTEX_LM3S316_IAR/hw_include/driverlib.r79 | Bin 0 -> 127268 bytes .../Demo/CORTEX_LM3S316_IAR/hw_include/flash.h | 75 + .../Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h | 136 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h | 329 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h | 118 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h | 139 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h | 103 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h | 189 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h | 96 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h | 63 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h | 830 ++ .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h | 260 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h | 120 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h | 380 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h | 235 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h | 67 + .../Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h | 239 + 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.../CORTEX_LM3S316_IAR/settings/driverlib.wsdt | 51 + .../Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h | 115 + .../FreeRTOS/Demo/CORTEX_LM3S811_GCC/Makefile | 85 + .../Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h | 39 + .../Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt | 126 + .../Demo/CORTEX_LM3S811_GCC/hw_include/adc.c | 946 ++ .../Demo/CORTEX_LM3S811_GCC/hw_include/adc.h | 126 + .../Demo/CORTEX_LM3S811_GCC/hw_include/comp.c | 448 + .../Demo/CORTEX_LM3S811_GCC/hw_include/comp.h | 120 + .../Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h | 40 + .../Demo/CORTEX_LM3S811_GCC/hw_include/debug.h | 56 + .../CORTEX_LM3S811_GCC/hw_include/driverlib.r79 | Bin 0 -> 135874 bytes .../Demo/CORTEX_LM3S811_GCC/hw_include/flash.c | 668 ++ .../Demo/CORTEX_LM3S811_GCC/hw_include/flash.h | 75 + .../Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c | 1103 ++ .../Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h | 137 + .../Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h | 343 + .../Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h | 118 + 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.../Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h | 55 + .../Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c | 1125 ++ .../Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h | 137 + .../Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c | 821 ++ .../Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h | 104 + .../CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c | 592 + .../CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h | 63 + .../FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd | 879 ++ .../FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp | 951 ++ .../FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww | 54 + .../FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c | 397 + .../FreeRTOS/Demo/CORTEX_LM3S811_IAR/startup.c | 197 + .../Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h | 115 + .../CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h | 39 + .../Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h | 329 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h | 118 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h | 139 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h | 103 + .../Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h | 197 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h | 97 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h | 64 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h | 830 ++ .../Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h | 260 + .../Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h | 176 + .../Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h | 120 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h | 409 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h | 235 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h | 67 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h | 239 + .../CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h | 116 + .../CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c | 953 ++ .../CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h | 47 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h | 124 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h | 120 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h | 40 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h | 56 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h | 75 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h | 137 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h | 137 + .../LuminaryCode/src/interrupt.h | 57 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h | 161 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h | 104 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h | 88 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h | 285 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h | 55 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h | 137 + .../CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h | 102 + .../LuminaryCode/src/watchdog.h | 63 + .../FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt | 54 + .../FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 | 116 + .../Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c | 137 + .../FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c | 399 + .../FreeRTOS/Demo/CORTEX_LM3S811_KEIL/readme.txt | 36 + .../Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S | 240 + .../RTOSDemo/FreeRTOSConfig.h | 131 + .../RTOSDemo/IntQueueTimer.c | 133 + .../RTOSDemo/IntQueueTimer.h | 74 + .../Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile | 141 + .../RTOSDemo/ParTest/ParTest.c | 113 + .../Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h | 336 + .../RTOSDemo/formike128x128x16.c | 902 ++ .../RTOSDemo/formike128x128x16.h | 51 + .../CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h | 9 + .../Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c | 459 + .../RTOSDemo/osram128x64x4.c | 933 ++ .../RTOSDemo/osram128x64x4.h | 63 + .../RTOSDemo/pack_struct_end.h | 2 + .../RTOSDemo/pack_struct_start.h | 2 + .../CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c | 981 ++ .../CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld | 60 + .../CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c | 251 + .../CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c | 176 + .../RTOSDemo/webserver/Makefile.webserver | 1 + .../RTOSDemo/webserver/clock-arch.h | 42 + .../RTOSDemo/webserver/emac.c | 313 + .../RTOSDemo/webserver/emac.h | 322 + .../RTOSDemo/webserver/http-strings | 35 + .../RTOSDemo/webserver/http-strings.c | 102 + .../RTOSDemo/webserver/http-strings.h | 34 + .../RTOSDemo/webserver/httpd-cgi.c | 293 + .../RTOSDemo/webserver/httpd-cgi.h | 84 + .../RTOSDemo/webserver/httpd-fs.c | 132 + .../RTOSDemo/webserver/httpd-fs.h | 57 + .../RTOSDemo/webserver/httpd-fs/404.html | 8 + .../RTOSDemo/webserver/httpd-fs/index.html | 13 + .../RTOSDemo/webserver/httpd-fs/index.shtml | 20 + .../RTOSDemo/webserver/httpd-fs/io.shtml | 28 + .../RTOSDemo/webserver/httpd-fs/runtime.shtml | 20 + .../RTOSDemo/webserver/httpd-fs/stats.shtml | 41 + .../RTOSDemo/webserver/httpd-fs/tcp.shtml | 21 + .../RTOSDemo/webserver/httpd-fsdata.c | 557 + .../RTOSDemo/webserver/httpd-fsdata.h | 64 + .../RTOSDemo/webserver/httpd.c | 346 + .../RTOSDemo/webserver/httpd.h | 62 + .../RTOSDemo/webserver/makefsdata | 78 + .../RTOSDemo/webserver/makestrings | 40 + .../RTOSDemo/webserver/uIP_Task.c | 338 + .../RTOSDemo/webserver/uip-conf.h | 159 + .../RTOSDemo/webserver/webserver.h | 49 + .../Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg | 28 + .../CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg | 34 + .../Demo/CORTEX_LM3Sxxxx_Eclipse/program.script | 17 + .../Backup of RTOSDemo.ewd | 586 + .../Backup of RTOSDemo.ewp | 947 ++ .../Debug/Exe/RTOSDemo.out | Bin 0 -> 460773 bytes .../Debug/Exe/RTOSDemo.sim | Bin 0 -> 35876 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/BlockQ.pbi | 38 + .../Debug/Obj/GenQTest.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/ParTest.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/PollQ.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/QPeek.pbi | 38 + .../Debug/Obj/RTOSDemo.pbd | 32 + .../Debug/Obj/blocktim.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/death.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/emac.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/flash.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/heap_2.pbi | 38 + .../Debug/Obj/http-strings.pbi | 38 + .../Debug/Obj/httpd-cgi.pbi | 38 + .../Debug/Obj/httpd-fs.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/integer.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/list.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/main.pbi | 38 + .../Debug/Obj/osram128x64x4.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/port.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/psock.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/queue.pbi | 38 + .../Debug/Obj/rit128x96x4.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/semtest.pbi | 38 + .../Debug/Obj/startup_ewarm.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/tasks.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timer.pbi | 38 + .../Debug/Obj/timertest.pbi | 38 + .../Debug/Obj/uIP_Task.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip.pbi | 38 + .../CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip_arp.pbi | 38 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h | 148 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.c | 133 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.h | 74 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf | 58 + .../CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c | 113 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2.bak | 138 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep | 990 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd | 982 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp | 1065 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww | 10 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.opt.bak | 79 + .../RTOSDemo.uvgui.a0190789 | 2646 +++++ .../RTOSDemo.uvgui_a0190789.bak | 2646 +++++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvopt | 800 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvproj | 600 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.xcl | 56 + .../RTOSDemo_FreeRTOS_Demo.dep | 471 + .../CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_uvopt.bak | 823 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h | 336 + .../CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.c | 902 ++ .../CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.h | 51 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h | 9 + .../FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c | 496 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c | 933 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h | 63 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c | 981 ++ .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/ExtDll.iex | 2 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.axf | Bin 0 -> 300528 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.bin | Bin 0 -> 32060 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.lnp | 3 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.map | 133 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.plg | 9 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.sct | 15 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.tra | 52 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blockq.crf | Bin 0 -> 26201 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blocktim.crf | Bin 0 -> 22711 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/death.crf | Bin 0 -> 21321 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.crf | Bin 0 -> 75605 bytes .../rvmdk/formike128x128x16.__i | 1 + .../rvmdk/formike128x128x16.crf | Bin 0 -> 44172 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/genqtest.crf | Bin 0 -> 27736 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.crf | Bin 0 -> 21744 bytes .../rvmdk/http-strings.__i | 1 + .../rvmdk/http-strings.crf | Bin 0 -> 1184 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.__i | 1 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.crf | Bin 0 -> 26930 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.__i | 1 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.crf | Bin 0 -> 18795 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.crf | Bin 0 -> 25683 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/integer.crf | Bin 0 -> 20925 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueue.crf | Bin 0 -> 29122 bytes .../rvmdk/intqueuetimer.crf | Bin 0 -> 30881 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.crf | Bin 0 -> 16099 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.crf | Bin 0 -> 102732 bytes .../rvmdk/osram128x64x4.__i | 1 + .../rvmdk/osram128x64x4.crf | Bin 0 -> 62421 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/partest.crf | Bin 0 -> 23041 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/pollq.crf | Bin 0 -> 25123 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.crf | Bin 0 -> 17009 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.crf | Bin 0 -> 26386 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/qpeek.crf | Bin 0 -> 26903 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.crf | Bin 0 -> 31688 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/recmutex.crf | Bin 0 -> 22509 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/rit128x96x4.crf | Bin 0 -> 62905 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/semtest.crf | Bin 0 -> 26550 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.crf | Bin 0 -> 41376 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.crf | Bin 0 -> 10663 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timertest.crf | Bin 0 -> 36552 bytes .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.__i | 1 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.crf | Bin 0 -> 32518 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.__i | 1 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.crf | Bin 0 -> 23411 bytes .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.__i | 1 + .../CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.crf | Bin 0 -> 80847 bytes .../settings/RTOSDemo.cspy.bat | 24 + .../settings/RTOSDemo.dbgdt | 80 + .../CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni | 61 + .../settings/RTOSDemo.wsdt | 49 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c | 219 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S | 251 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c | 170 + .../webserver/Makefile.webserver | 1 + .../webserver/clock-arch.h | 42 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c | 318 + .../Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h | 322 + .../webserver/http-strings | 35 + .../webserver/http-strings.c | 102 + .../webserver/http-strings.h | 34 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c | 269 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h | 84 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c | 132 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h | 57 + .../webserver/httpd-fs/404.html | 8 + .../webserver/httpd-fs/index.html | 13 + .../webserver/httpd-fs/index.shtml | 20 + .../webserver/httpd-fs/io.shtml | 28 + .../webserver/httpd-fs/stats.shtml | 41 + .../webserver/httpd-fs/tcp.shtml | 21 + .../webserver/httpd-fsdata.c | 470 + .../webserver/httpd-fsdata.h | 64 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c | 346 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h | 62 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata | 78 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings | 40 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c | 349 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h | 159 + .../CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h | 49 + .../Demo/CORTEX_LM3Sxxxx_Rowley/FreeRTOSConfig.h | 150 + .../Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.c | 133 + .../Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.h | 74 + .../Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Startup.s | 199 + .../Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Target.js | 28 + .../Demo/CORTEX_LM3Sxxxx_Rowley/ParTest/ParTest.c | 113 + .../Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzp | 121 + .../Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzs | 58 + .../FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/bitmap.h | 336 + .../CORTEX_LM3Sxxxx_Rowley/formike128x128x16.c | 902 ++ .../CORTEX_LM3Sxxxx_Rowley/formike128x128x16.h | 51 + .../Demo/CORTEX_LM3Sxxxx_Rowley/lcd_message.h | 9 + .../FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/main.c | 483 + .../Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.c | 933 ++ .../Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.h | 63 + .../Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_end.h | 2 + .../CORTEX_LM3Sxxxx_Rowley/pack_struct_start.h | 2 + .../Demo/CORTEX_LM3Sxxxx_Rowley/rit128x96x4.c | 981 ++ .../Demo/CORTEX_LM3Sxxxx_Rowley/thumb_crt0.s | 227 + .../Demo/CORTEX_LM3Sxxxx_Rowley/timertest.c | 176 + .../webserver/Makefile.webserver | 1 + .../CORTEX_LM3Sxxxx_Rowley/webserver/clock-arch.h | 42 + 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third_party/FreeRTOS/Demo/Common/include/serial.h create mode 100644 third_party/FreeRTOS/Demo/readme.txt (limited to 'third_party/FreeRTOS/Demo') diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h new file mode 100644 index 0000000..fc22d76 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h @@ -0,0 +1,111 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c new file mode 100644 index 0000000..36a2ea6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c @@ -0,0 +1,634 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt new file mode 100644 index 0000000..208a588 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 1. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h new file mode 100644 index 0000000..c8dc105 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h @@ -0,0 +1,111 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c new file mode 100644 index 0000000..e94462f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c @@ -0,0 +1,633 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static char cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt new file mode 100644 index 0000000..e22c810 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 2. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h new file mode 100644 index 0000000..6f63637 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Makefile b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Makefile new file mode 100644 index 0000000..f71d1ae --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Makefile @@ -0,0 +1,86 @@ +#****************************************************************************** +# +# Makefile - Rules for building the driver library and examples. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +include makedefs + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal + +CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= + +VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:ParTest:hw_include + + +OBJS= ${COMPILER}/main.o \ + ${COMPILER}/pdc.o \ + ${COMPILER}/list.o \ + ${COMPILER}/queue.o \ + ${COMPILER}/tasks.o \ + ${COMPILER}/port.o \ + ${COMPILER}/heap_1.o \ + ${COMPILER}/ParTest.o \ + ${COMPILER}/crflash.o \ + ${COMPILER}/croutine.o +# ${COMPILER}/pendsv_handler.o + +INIT_OBJS= ${COMPILER}/startup.o + +LIBS= hw_include/libdriver.a + + +# +# The default rule, which causes init to be built. +# +all: ${COMPILER} \ + ${COMPILER}/RTOSDemo.axf \ + +# +# The rule to clean out all the build products +# + +clean: + @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf + +# +# The rule to create the target directory +# +${COMPILER}: + @mkdir ${COMPILER} + +${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} +SCATTER_RTOSDemo=standalone.ld +ENTRY_RTOSDemo=ResetISR + +# +# +# Include the automatically generated dependency files. +# +-include ${wildcard ${COMPILER}/*.d} __dummy__ + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c new file mode 100644 index 0000000..6c5d592 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c @@ -0,0 +1,145 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 ) + +static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned char ucBit = ( unsigned char ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned char ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned char ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h new file mode 100644 index 0000000..f8383de --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h @@ -0,0 +1,18 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h new file mode 100644 index 0000000..2f259bd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h new file mode 100644 index 0000000..cdc9a5b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h @@ -0,0 +1,135 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h new file mode 100644 index 0000000..d32cec4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h new file mode 100644 index 0000000..bef5dc6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h new file mode 100644 index 0000000..77dfe71 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h new file mode 100644 index 0000000..3747232 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h new file mode 100644 index 0000000..e3ef94f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator +#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 +#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h new file mode 100644 index 0000000..a944f66 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h new file mode 100644 index 0000000..40b6ab2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h @@ -0,0 +1,234 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x100 // Ring Indicator +#define UART_FR_TXFE 0x080 // TX FIFO Empty +#define UART_FR_RXFF 0x040 // RX FIFO Full +#define UART_FR_TXFF 0x020 // TX FIFO Full +#define UART_FR_RXFE 0x010 // RX FIFO Empty +#define UART_FR_BUSY 0x008 // UART Busy + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x80 // Stick Parity Select +#define UART_LCR_H_WLEN 0x60 // Word length +#define UART_LCR_H_WLEN_8 0x60 // 8 bit data +#define UART_LCR_H_WLEN_7 0x40 // 7 bit data +#define UART_LCR_H_WLEN_6 0x20 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00 // 5 bit data +#define UART_LCR_H_FEN 0x10 // Enable FIFO +#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x04 // Even Parity Select +#define UART_LCR_H_PEN 0x02 // Parity Enable +#define UART_LCR_H_BRK 0x01 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control +#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control +#define UART_CTL_OUT2 0x2000 // OUT2 +#define UART_CTL_OUT1 0x1000 // OUT1 +#define UART_CTL_RTS 0x0800 // Request To Send +#define UART_CTL_DTR 0x0400 // Data Terminal Ready +#define UART_CTL_RXE 0x0200 // Receive Enable +#define UART_CTL_TXE 0x0100 // Transmit Enable +#define UART_CTL_LBE 0x0080 // Loopback Enable +#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode +#define UART_CTL_SIREN 0x0002 // SIR Enable +#define UART_CTL_UARTEN 0x0001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00 // 1/8 Full +#define UART_IFLS_RX2_8 0x10 // 1/4 Full +#define UART_IFLS_RX4_8 0x20 // 1/2 Full +#define UART_IFLS_RX6_8 0x30 // 3/4 Full +#define UART_IFLS_RX7_8 0x40 // 7/8 Full +#define UART_IFLS_TX1_8 0x00 // 1/8 Full +#define UART_IFLS_TX2_8 0x01 // 1/4 Full +#define UART_IFLS_TX4_8 0x02 // 1/2 Full +#define UART_IFLS_TX6_8 0x03 // 3/4 Full +#define UART_IFLS_TX7_8 0x04 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask +#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask +#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask +#define UART_IM_RIMIM 0x001 // RI Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status +#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status +#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status +#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status +#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status +#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status +#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status +#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status +#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear +#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear +#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear +#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear + +//***************************************************************************** +// +// DMA Control Register bits +// +//***************************************************************************** +#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error +#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA +#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0 +#define UART_RV_RSR 0x0 +#define UART_RV_ECR 0 +#define UART_RV_FR 0x90 +#define UART_RV_IBRD 0x0000 +#define UART_RV_FBRD 0x00 +#define UART_RV_LCR_H 0x00 +#define UART_RV_CTL 0x0300 +#define UART_RV_IFLS 0x12 +#define UART_RV_IM 0x000 +#define UART_RV_RIS 0x000 +#define UART_RV_MIS 0x000 +#define UART_RV_ICR 0x000 + +#endif // __HW_UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h new file mode 100644 index 0000000..23424af --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c new file mode 100644 index 0000000..1e82ed8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h new file mode 100644 index 0000000..aba74cd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h new file mode 100644 index 0000000..ef53b34 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h new file mode 100644 index 0000000..2e1d1e4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc +#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 +#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlBOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h new file mode 100644 index 0000000..ea39859 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/init/startup.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/init/startup.c new file mode 100644 index 0000000..592ddc6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/init/startup.c @@ -0,0 +1,175 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +void FaultISR(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); +extern void vPortSVCHandler( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void entry(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 51 +#endif +static unsigned long pulMainStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex-M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section("vectors"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)), + ResetISR, + NmiSR, + FaultISR, //FAULT + 0, // The MPU fault handler + 0, // The bus fault handler + 0, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + vPortSVCHandler, // SVCall handler + 0, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + 0, // GPIO Port A + 0, // GPIO Port B + 0, // GPIO Port C + 0, // GPIO Port D + 0, // GPIO Port E + vUART_ISR // UART0 Rx and Tx +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + Main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c new file mode 100644 index 0000000..36a2ea6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c @@ -0,0 +1,634 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/makedefs b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/makedefs new file mode 100644 index 0000000..2728ef8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/makedefs @@ -0,0 +1,193 @@ +#****************************************************************************** +# +# makedefs - Definitions common to all makefiles. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +#****************************************************************************** +# +# The compiler to be used. +# +#****************************************************************************** +ifndef COMPILER +COMPILER=gcc +endif + +#****************************************************************************** +# +# The debugger to be used. +# +#****************************************************************************** +ifndef DEBUGGER +DEBUGGER=gdb +endif + +#****************************************************************************** +# +# Definitions for using GCC. +# +#****************************************************************************** +ifeq (${COMPILER}, gcc) + +# +# The command for calling the compiler. +# +CC=arm-none-eabi-gcc + +# +# The flags passed to the assembler. +# +AFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -MD + +# +# The flags passed to the compiler. +# +CFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -O2 \ + -MD + +# +# The command for calling the library archiver. +# +AR=arm-none-eabi-ar + +# +# The command for calling the linker. +# +LD=arm-none-eabi-ld + +# +# The flags passed to the linker. +# +LDFLAGS= -Map gcc/out.map + +# +# Get the location of libgcc.a from the GCC front-end. +# +LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} + +# +# Get the location of libc.a from the GCC front-end. +# +LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} + +# +# The command for extracting images from the linked executables. +# +OBJCOPY=arm-none-eabi-objcopy + +endif + +#****************************************************************************** +# +# Tell the compiler to include debugging information if the DEBUG environment +# variable is set. +# +#****************************************************************************** +ifdef DEBUG +CFLAGS += -g +endif + +#****************************************************************************** +# +# The rule for building the object file from each C source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.c + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi + @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} +ifeq (${COMPILER}, rvds) + @mv -f ${notdir ${@:.o=.d}} ${COMPILER} +endif + +#****************************************************************************** +# +# The rule for building the object file from each assembly source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.S + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi +ifeq (${COMPILER}, rvds) + @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} + @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} + @rm ${@:.o=_.S} + @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} + @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} + @rm ${notdir ${<:.S=.d}} +endif +ifeq (${COMPILER}, gcc) + @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} +endif + +#****************************************************************************** +# +# The rule for creating an object library. +# +#****************************************************************************** +${COMPILER}/%.a: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AR ${@}"; \ + else \ + echo ${AR} -cr ${@} ${^}; \ + fi + @${AR} -cr ${@} ${^} + +#****************************************************************************** +# +# The rule for linking the application. +# +#****************************************************************************** +${COMPILER}/%.axf: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " LD ${@}"; \ + fi +ifeq (${COMPILER}, gcc) + @if [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}'; \ + fi + @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}' + @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} +endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/standalone.ld b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/standalone.ld new file mode 100644 index 0000000..11d3243 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_GCC/standalone.ld @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's Stellaris Family of microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 2K +} + +SECTIONS +{ + .text : + { + *(vectors) + *(.text) + *(.rodata*) + *(.constdata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss) + _ebss = .; + } > SRAM +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h new file mode 100644 index 0000000..31afdcf --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h @@ -0,0 +1,112 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c new file mode 100644 index 0000000..560d41d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c @@ -0,0 +1,630 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt new file mode 100644 index 0000000..10334b9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 1. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h new file mode 100644 index 0000000..29902dd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h @@ -0,0 +1,112 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c new file mode 100644 index 0000000..41d822a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c @@ -0,0 +1,638 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static char cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt new file mode 100644 index 0000000..2ddb358 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 2. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt new file mode 100644 index 0000000..cdd7176 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt @@ -0,0 +1,51 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Source),0,0,0 +GRPOPT 2,(Demo),0,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<..\..\Source\croutine.c> +OPTFFF 1,2,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,3,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,4,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,5,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_1.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 2,7,1,0,0,0,0,0,<.\main.c> +OPTFFF 2,8,2,0,0,0,0,0,<.\init\Startup.s> +OPTFFF 2,9,1,0,0,0,0,0,<..\Common\Minimal\crflash.c> +OPTFFF 2,10,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 2,11,1,0,0,0,0,0,<.\include\pdc.c> +OPTFFF 2,12,4,0,0,0,0,0,<..\Common\drivers\LuminaryMicro\Keil\driverlib.lib> + + +TARGOPT 1, (LM3S1xx) + ADSCLK=20000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\uvision\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 0 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) + OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)() + OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)) + OPTKEY 0,(UL2CM3)(-UU0226F8E -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP7 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000) + OPTDF 0x80 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 new file mode 100644 index 0000000..e72477a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 @@ -0,0 +1,112 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' + +Group (Source) +Group (Demo) + +File 1,1,<..\..\Source\croutine.c> +File 1,1,<..\..\Source\list.c> +File 1,1,<..\..\Source\queue.c> +File 1,1,<..\..\Source\tasks.c> +File 1,1,<..\..\Source\portable\MemMang\heap_1.c> +File 1,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +File 2,1,<.\main.c> +File 2,2,<.\init\Startup.s> +File 2,1,<..\Common\Minimal\crflash.c> +File 2,1,<.\ParTest\ParTest.c> +File 2,1,<.\include\pdc.c> +File 2,4,<..\Common\drivers\LuminaryMicro\Keil\driverlib.lib> + + +Options 1,0,0 // Target 'LM3S1xx' + Device (LM3S101) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(20000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) + DevID (4079) + Rgf (LM3Sxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\uvision\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\uvision\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,8,0,0 } + OCMADSIROM { 1,0,0,0,0,0,32,0,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,8,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (RVDS_ARMCM3_LM3S102) + ADSCUDEF () + ADSCINCD (C:\Keil\ARM\RV30\LIB\Luminary;..\CORTEX_LM3S102_KEIL;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;.\include) + ADSASFLG { 65,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC (--diag_suppress 1581) + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler) + ADSLDIF () + ADSLDDW (6306) + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) + OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2CM3.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h new file mode 100644 index 0000000..aaea9d7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h @@ -0,0 +1,113 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c new file mode 100644 index 0000000..8b3eebb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c @@ -0,0 +1,146 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 ) + +static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned char ucBit = ( unsigned char ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned char ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned char ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/include/pdc.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/include/pdc.c new file mode 100644 index 0000000..d1c5444 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/include/pdc.c @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#include "LM3Sxxx.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/include/pdc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/include/pdc.h new file mode 100644 index 0000000..6380806 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/include/pdc.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/init/Startup.s b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/init/Startup.s new file mode 100644 index 0000000..d5dea8b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/init/Startup.s @@ -0,0 +1,164 @@ +;/*****************************************************************************/ +;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The STARTUP.S code is executed after CPU Reset. +; */ + + +;// Stack Configuration +;// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// + +Stack_Size EQU 51 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +Heap_Mem SPACE Heap_Size + + +; System Control Register Addresses +SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address +PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control +LDOPC_OFS EQU 0x0034 ; LDO Power +SRCR0_OFS EQU 0x0040 ; Software Reset Control 0 +SRCR1_OFS EQU 0x0044 ; Software Reset Control 1 +SRCR2_OFS EQU 0x0048 ; Software Reset Control 2 +RCC_OFS EQU 0x0060 ; Run-Mode Clock Control +RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0 +RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1 +RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2 +SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0 +SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1 +SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2 +DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0 +DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1 +DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address 0. + + AREA RESET, CODE, READONLY + THUMB + + IMPORT xPortPendSVHandler + IMPORT xPortSysTickHandler + IMPORT vUART_ISR + IMPORT vPortSVCHandler + +; Vector Table + EXPORT __Vectors +__Vectors DCD Stack_Mem + Stack_Size ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD DefaultISR ; Hard Fault Handler + DCD DefaultISR ; MPU Fault Handler + DCD DefaultISR ; Bus Fault Handler + DCD DefaultISR ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD vPortSVCHandler ; SVCall Handler + DCD DefaultISR ; Debug Monitor Handler + DCD 0 ; Reserved + DCD xPortPendSVHandler ; PendSV Handler + DCD xPortSysTickHandler ; SysTick Handler + DCD DefaultISR ; GPIO Port A Handler + DCD DefaultISR ; GPIO Port B Handler + DCD DefaultISR ; GPIO Port C Handler + DCD DefaultISR ; GPIO Port D Handler + DCD DefaultISR ; GPIO Port E Handler + DCD vUART_ISR ; UART0 Rx/Tx Handler + DCD DefaultISR ; UART1 Rx/Tx Handler + DCD DefaultISR ; SSI Rx/Tx Handler + DCD DefaultISR ; I2C Master/Slave Handler + DCD DefaultISR ; PWM Fault Handler + DCD DefaultISR ; PWM Generator 0 Handler + DCD DefaultISR ; PWM Generator 1 Handler + DCD DefaultISR ; PWM Generator 2 Handler + DCD DefaultISR ; Quadrature Encoder Handler + DCD DefaultISR ; ADC Sequence 0 Handler + DCD DefaultISR ; ADC Sequence 1 Handler + DCD DefaultISR ; ADC Sequence 2 Handler + DCD DefaultISR ; ADC Sequence 3 Handler + DCD DefaultISR ; Watchdog Timer Handler + DCD DefaultISR ; Timer 0 Subtimer A Handler + DCD DefaultISR ; Timer 0 Subtimer B Handler + DCD DefaultISR ; Timer 1 Subtimer A Handler + DCD DefaultISR ; Timer 1 Subtimer B Handler + DCD DefaultISR ; Timer 2 Subtimer A Handler + DCD DefaultISR ; Timer 2 Subtimer B Handler + DCD DefaultISR ; Analog Comparator 0 Handler + DCD DefaultISR ; Analog Comparator 1 Handler + DCD DefaultISR ; Analog Comparator 2 Handler + DCD DefaultISR ; System Control Handler + DCD DefaultISR ; Flash Control Handler + +; Dummy Handlers are implemented as infinite loops which can be modified. + +NmiSR B NmiSR +FaultISR B FaultISR + EXPORT FaultISR +DefaultISR B DefaultISR + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + +; Enable Clock Gating for Peripherals +; LDR R0, =SYSCTL_BASE ; System Control Base Address +; MVN R1, #0 ; Value 0xFFFFFFFF +; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0 +; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1 +; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2 + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + + END diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/main.c new file mode 100644 index 0000000..560d41d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_KEIL/main.c @@ -0,0 +1,630 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h new file mode 100644 index 0000000..6f63637 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c new file mode 100644 index 0000000..6c5d592 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c @@ -0,0 +1,145 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 ) + +static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned char ucBit = ( unsigned char ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned char ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned char ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c new file mode 100644 index 0000000..7548d2d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c @@ -0,0 +1,647 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile + ( + " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" + ); + + /* Check the values are as expected. */ + __asm volatile + ( + " cmp r11, #10 \n" + " bne set_error_led \n" + " cmp r0, #11 \n" + " bne set_error_led \n" + " cmp r1, #12 \n" + " bne set_error_led \n" + " cmp r2, #13 \n" + " bne set_error_led \n" + " cmp r3, #14 \n" + " bne set_error_led \n" + " cmp r4, #15 \n" + " bne set_error_led \n" + " cmp r5, #16 \n" + " bne set_error_led \n" + " cmp r6, #17 \n" + " bne set_error_led \n" + " cmp r7, #18 \n" + " bne set_error_led \n" + " cmp r8, #19 \n" + " bne set_error_led \n" + " cmp r9, #20 \n" + " bne set_error_led \n" + " cmp r10, #21 \n" + " bne set_error_led \n" + " cmp r12, #22 \n" + " bne set_error_led \n" + " bx lr" + ); + + __asm volatile + ( + "set_error_led: \n" + " push {r14} \n" + " ldr r1, vSetErrorLEDConst\n" + " blx r1 \n" + " pop {r14} \n" + " bx lr \n" + " \n" + " .align 2 \n" + "vSetErrorLEDConst: .word vSetErrorLED" + ); +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s new file mode 100644 index 0000000..900b2bb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s @@ -0,0 +1,120 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vUART_ISR + .extern vPortSVCHandler + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word _start +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word vPortSVCHandler + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word vUART_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h new file mode 100644 index 0000000..0a79c09 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c new file mode 100644 index 0000000..6c5d592 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c @@ -0,0 +1,145 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 ) + +static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned char ucBit = ( unsigned char ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned char ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned char ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c new file mode 100644 index 0000000..ccc7876 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c @@ -0,0 +1,655 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const char *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static char cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const char *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const char *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static char cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile + ( + " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" + ); + + /* Check the values are as expected. */ + __asm volatile + ( + " cmp r11, #10 \n" + " bne set_error_led \n" + " cmp r0, #11 \n" + " bne set_error_led \n" + " cmp r1, #12 \n" + " bne set_error_led \n" + " cmp r2, #13 \n" + " bne set_error_led \n" + " cmp r3, #14 \n" + " bne set_error_led \n" + " cmp r4, #15 \n" + " bne set_error_led \n" + " cmp r5, #16 \n" + " bne set_error_led \n" + " cmp r6, #17 \n" + " bne set_error_led \n" + " cmp r7, #18 \n" + " bne set_error_led \n" + " cmp r8, #19 \n" + " bne set_error_led \n" + " cmp r9, #20 \n" + " bne set_error_led \n" + " cmp r10, #21 \n" + " bne set_error_led \n" + " cmp r12, #22 \n" + " bne set_error_led \n" + " bx lr" + ); + + __asm volatile + ( + "set_error_led: \n" + " push {r14} \n" + " ldr r1, vSetErrorLEDConst\n" + " blx r1 \n" + " pop {r14} \n" + " bx lr \n" + " \n" + " .align 2 \n" + "vSetErrorLEDConst: .word vSetErrorLED" + ); +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s new file mode 100644 index 0000000..900b2bb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s @@ -0,0 +1,120 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vUART_ISR + .extern vPortSVCHandler + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word _start +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word vPortSVCHandler + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word vUART_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h new file mode 100644 index 0000000..fbe50d5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 0 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 0 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c new file mode 100644 index 0000000..cbd4a22 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c @@ -0,0 +1,145 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Kernel include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/* Hardware specific include files. */ +#include "DriverLib.h" + +static const unsigned long ulLEDs[] = +{ + GPIO_PIN_6, GPIO_PIN_1, GPIO_PIN_0 +}; + +#define partstLED_PINS ( GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_6 ) + +#define partstMAX_OUTPUT_LED ( ( unsigned char ) 3 ) + +/*-----------------------------------------------------------*/ +void vParTestInitialise( void ) +{ +portBASE_TYPE xLED; + + /* The LED's are on port B. */ + GPIODirModeSet( GPIO_PORTB_BASE, partstLED_PINS, GPIO_DIR_MODE_OUT ); + + for( xLED = 0; xLED < partstMAX_OUTPUT_LED; xLED++ ) + { + vParTestSetLED( xLED, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + if( xValue == pdFALSE ) + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); + } + else + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); + } + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +portBASE_TYPE xCurrentValue; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + xCurrentValue = GPIOPinRead( GPIO_PORTB_BASE, ulLEDs[ uxLED ] ); + if( xCurrentValue ) + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); + } + else + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); + } + } + } + xTaskResumeAll(); +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c new file mode 100644 index 0000000..db9bc08 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c @@ -0,0 +1,323 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This is a mini co-routine demo for the Rowley CrossFire LM3S102 development + * board. It makes use of the boards tri-colour LED and analogue input. + * + * Four co-routines are created - an 'I2C' co-routine and three 'flash' + * co-routines. + * + * The I2C co-routine triggers an ADC conversion then blocks on a queue to + * wait for the conversion result - which it receives on the queue directly + * from the I2C interrupt service routine. The conversion result is then + * scalled to a delay period. The I2C interrupt then wakes each of the + * flash co-routines before itself delaying for the calculated period and + * then repeating the whole process. + * + * When woken by the I2C co-routine the flash co-routines each block for + * a given period, illuminate an LED for a fixed period, then go back to + * sleep to wait for the next cycle. The uxIndex parameter of the flash + * co-routines is used to ensure that each flashes a different LED, and that + * the delay periods are such that the LED's get flashed in sequence. + */ + + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* States of the I2C master interface. */ +#define mainI2C_IDLE 0 +#define mainI2C_READ_1 1 +#define mainI2C_READ_2 2 +#define mainI2C_READ_DONE 3 + +#define mainZERO_LENGTH 0 + +/* Address of the A2D IC on the CrossFire board. */ +#define mainI2CAddress 0x4D + +/* The queue used to send data from the I2C ISR to the co-routine should never +contain more than one item as the same co-routine is used to trigger the I2C +activity. */ +#define mainQUEUE_LENGTH 1 + +/* The CrossFire board contains a tri-colour LED. */ +#define mainNUM_LEDs 3 + +/* The I2C co-routine has a higher priority than the flash co-routines. This +is not really necessary as when the I2C co-routine is active the other +co-routines are delaying. */ +#define mainI2c_CO_ROUTINE_PRIORITY 1 + + +/* The current state of the I2C master. */ +static volatile unsigned portBASE_TYPE uxState = mainI2C_IDLE; + +/* The delay period derived from the A2D value. */ +static volatile portBASE_TYPE uxDelay = 250; + +/* The queue used to communicate between the I2C interrupt and the I2C +co-routine. */ +static xQueueHandle xADCQueue; + +/* The queue used to synchronise the flash co-routines. */ +static xQueueHandle xDelayQueue; + +/* + * Sets up the PLL, I2C and GPIO used by the demo. + */ +static void prvSetupHardware( void ); + +/* The co-routines as described at the top of the file. */ +static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); +static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +unsigned portBASE_TYPE uxCoRoutine; + + /* Setup all the hardware used by this demo. */ + prvSetupHardware(); + + /* Create the queue used to communicate between the ISR and I2C co-routine. + This can only ever contain one value. */ + xADCQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( portTickType ) ); + + /* Create the queue used to synchronise the flash co-routines. The queue + is used to trigger three tasks, but is for synchronisation only and does + not pass any data. It therefore has three position each of zero length. */ + xDelayQueue = xQueueCreate( mainNUM_LEDs, mainZERO_LENGTH ); + + /* Create the co-routine that initiates the i2c. */ + xCoRoutineCreate( vI2CCoRoutine, mainI2c_CO_ROUTINE_PRIORITY, 0 ); + + /* Create the flash co-routines. */ + for( uxCoRoutine = 0; uxCoRoutine < mainNUM_LEDs; uxCoRoutine++ ) + { + xCoRoutineCreate( vFlashCoRoutine, tskIDLE_PRIORITY, uxCoRoutine ); + } + + /* Start the scheduler. From this point on the co-routines should + execute. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Enable the I2C used to read the pot. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_I2C ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOB ); + GPIOPinTypeI2C( GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3 ); + + /* Initialize the I2C master. */ + I2CMasterInit( I2C_MASTER_BASE, pdFALSE ); + + /* Enable the I2C master interrupt. */ + I2CMasterIntEnable( I2C_MASTER_BASE ); + IntEnable( INT_I2C ); + + /* Initialise the hardware used to talk to the LED's. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xADCResult; +static portBASE_TYPE xResult = 0, xMilliSecs, xLED; + + crSTART( xHandle ); + + for( ;; ) + { + /* Start the I2C off to read the ADC. */ + uxState = mainI2C_READ_1; + I2CMasterSlaveAddrSet( I2C_MASTER_BASE, mainI2CAddress, pdTRUE ); + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START ); + + /* Wait to receive the conversion result. */ + crQUEUE_RECEIVE( xHandle, xADCQueue, &xADCResult, portMAX_DELAY, &xResult ); + + /* Scale the result to give a useful range of values for a visual + demo. */ + xADCResult >>= 2; + xMilliSecs = xADCResult / portTICK_RATE_MS; + + /* The delay is split between the four co-routines so they remain in + synch. */ + uxDelay = xMilliSecs / ( mainNUM_LEDs + 1 ); + + /* Trigger each of the flash co-routines. */ + for( xLED = 0; xLED < mainNUM_LEDs; xLED++ ) + { + crQUEUE_SEND( xHandle, xDelayQueue, &xLED, 0, &xResult ); + } + + /* Wait for the full delay time then start again. This delay is long + enough to ensure the flash co-routines have done their thing and gone + back to sleep. */ + crDELAY( xHandle, xMilliSecs ); + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portBASE_TYPE xResult, xNothing; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for start of next round. */ + crQUEUE_RECEIVE( xHandle, xDelayQueue, &xNothing, portMAX_DELAY, &xResult ); + + /* Wait until it is this co-routines turn to flash. */ + crDELAY( xHandle, uxDelay * uxIndex ); + + /* Turn on the LED for a fixed period. */ + vParTestSetLED( uxIndex, pdTRUE ); + crDELAY( xHandle, uxDelay ); + vParTestSetLED( uxIndex, pdFALSE ); + + /* Go back and wait for the next round. */ + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +void vI2C_ISR(void) +{ +static portTickType xReading; + + /* Clear the interrupt. */ + I2CMasterIntClear( I2C_MASTER_BASE ); + + /* Determine what to do based on the current uxState. */ + switch (uxState) + { + case mainI2C_IDLE: break; + + case mainI2C_READ_1: /* Read ADC result high byte. */ + xReading = I2CMasterDataGet( I2C_MASTER_BASE ); + xReading <<= 8; + + /* Continue the burst read. */ + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT ); + uxState = mainI2C_READ_2; + break; + + case mainI2C_READ_2: /* Read ADC result low byte. */ + xReading |= I2CMasterDataGet( I2C_MASTER_BASE ); + + /* Finish the burst read. */ + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH ); + uxState = mainI2C_READ_DONE; + break; + + case mainI2C_READ_DONE: /* Complete. */ + I2CMasterDataGet( I2C_MASTER_BASE ); + uxState = mainI2C_IDLE; + + /* Send the result to the co-routine. */ + crQUEUE_SEND_FROM_ISR( xADCQueue, &xReading, pdFALSE ); + break; + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + for( ;; ) + { + vCoRoutineSchedule(); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s new file mode 100644 index 0000000..2cc2608 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s @@ -0,0 +1,121 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vI2C_ISR + .extern faultisr + .extern vPortSVCHandler + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word _start +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word vPortSVCHandler + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word UART0_ISR + .word UART1_ISR + .word SSI_ISR + .word vI2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp new file mode 100644 index 0000000..73075f6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs new file mode 100644 index 0000000..26ef6e4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h new file mode 100644 index 0000000..3eb2ebc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h @@ -0,0 +1,20 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" +#include "hw_i2c.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" +#include "i2c.h" + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt new file mode 100644 index 0000000..cba31f7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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Use, duplication or +disclosure by the Government is subject to restrictions as set forth in +subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software +clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial +Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. +Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100, +Austin, Texas 78746. + +9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI +EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED +"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, +WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING +OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING +THE SOFTWARE (IF ANY). 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You agree that the statutes and +laws of the United States and the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and you agree that any litigation will be subject to +the exclusive jurisdiction of the state or federal courts in Austin, Travis +County, Texas, USA. You agree that regardless of any statute or law to the +contrary, any claim or cause of action arising out of or related to this +Agreement or the Software must be filed within one (1) year after such claim or +cause of action arose or be forever barred. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and LMI regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h new file mode 100644 index 0000000..a4c307b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h @@ -0,0 +1,112 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_INT_xxx, COMP_ASRCP_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h new file mode 100644 index 0000000..a93771b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h new file mode 100644 index 0000000..2f259bd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h new file mode 100644 index 0000000..6332548 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h new file mode 100644 index 0000000..cdc9a5b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h @@ -0,0 +1,135 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h new file mode 100644 index 0000000..81fb0b0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0 and COMP_ACSTAT1 +// registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0 and COMP_ACCTL1 +// registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register + +#endif // __HW_COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h new file mode 100644 index 0000000..8dd755c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h @@ -0,0 +1,141 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_REG_MASK 0x00000F00 // Register select mask +#define FLASH_FMC_REG_UDFP 0x00000000 // Select FLASH protection register +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h new file mode 100644 index 0000000..ddba2fd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h @@ -0,0 +1,95 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h new file mode 100644 index 0000000..3e2e9ee --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h @@ -0,0 +1,157 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_ICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_ICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Master masked interrupt status + +#endif // __HW_I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h new file mode 100644 index 0000000..d32cec4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h new file mode 100644 index 0000000..bef5dc6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h new file mode 100644 index 0000000..77dfe71 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h new file mode 100644 index 0000000..3747232 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h new file mode 100644 index 0000000..e3ef94f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator +#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 +#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h new file mode 100644 index 0000000..9bad906 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h @@ -0,0 +1,233 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x0000000F // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x0000000F // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h new file mode 100644 index 0000000..a944f66 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h new file mode 100644 index 0000000..40b6ab2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h @@ -0,0 +1,234 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x100 // Ring Indicator +#define UART_FR_TXFE 0x080 // TX FIFO Empty +#define UART_FR_RXFF 0x040 // RX FIFO Full +#define UART_FR_TXFF 0x020 // TX FIFO Full +#define UART_FR_RXFE 0x010 // RX FIFO Empty +#define UART_FR_BUSY 0x008 // UART Busy + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x80 // Stick Parity Select +#define UART_LCR_H_WLEN 0x60 // Word length +#define UART_LCR_H_WLEN_8 0x60 // 8 bit data +#define UART_LCR_H_WLEN_7 0x40 // 7 bit data +#define UART_LCR_H_WLEN_6 0x20 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00 // 5 bit data +#define UART_LCR_H_FEN 0x10 // Enable FIFO +#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x04 // Even Parity Select +#define UART_LCR_H_PEN 0x02 // Parity Enable +#define UART_LCR_H_BRK 0x01 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control +#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control +#define UART_CTL_OUT2 0x2000 // OUT2 +#define UART_CTL_OUT1 0x1000 // OUT1 +#define UART_CTL_RTS 0x0800 // Request To Send +#define UART_CTL_DTR 0x0400 // Data Terminal Ready +#define UART_CTL_RXE 0x0200 // Receive Enable +#define UART_CTL_TXE 0x0100 // Transmit Enable +#define UART_CTL_LBE 0x0080 // Loopback Enable +#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode +#define UART_CTL_SIREN 0x0002 // SIR Enable +#define UART_CTL_UARTEN 0x0001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00 // 1/8 Full +#define UART_IFLS_RX2_8 0x10 // 1/4 Full +#define UART_IFLS_RX4_8 0x20 // 1/2 Full +#define UART_IFLS_RX6_8 0x30 // 3/4 Full +#define UART_IFLS_RX7_8 0x40 // 7/8 Full +#define UART_IFLS_TX1_8 0x00 // 1/8 Full +#define UART_IFLS_TX2_8 0x01 // 1/4 Full +#define UART_IFLS_TX4_8 0x02 // 1/2 Full +#define UART_IFLS_TX6_8 0x03 // 3/4 Full +#define UART_IFLS_TX7_8 0x04 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask +#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask +#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask +#define UART_IM_RIMIM 0x001 // RI Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status +#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status +#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status +#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status +#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status +#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status +#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status +#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status +#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear +#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear +#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear +#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear + +//***************************************************************************** +// +// DMA Control Register bits +// +//***************************************************************************** +#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error +#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA +#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0 +#define UART_RV_RSR 0x0 +#define UART_RV_ECR 0 +#define UART_RV_FR 0x90 +#define UART_RV_IBRD 0x0000 +#define UART_RV_FBRD 0x00 +#define UART_RV_LCR_H 0x00 +#define UART_RV_CTL 0x0300 +#define UART_RV_IFLS 0x12 +#define UART_RV_IM 0x000 +#define UART_RV_RIS 0x000 +#define UART_RV_MIS 0x000 +#define UART_RV_ICR 0x000 + +#endif // __HW_UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h new file mode 100644 index 0000000..6ae5dff --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h @@ -0,0 +1,99 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_CAUSE 0x0000041C // Cause register +#define WDT_O_LOCK 0x00000C00 // Lock register + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CAUSE register. +// +//***************************************************************************** +#define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred +#define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register + +#endif // __HW_WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h new file mode 100644 index 0000000..e48c98d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h new file mode 100644 index 0000000..23424af --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c new file mode 100644 index 0000000..1e82ed8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h new file mode 100644 index 0000000..aba74cd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h new file mode 100644 index 0000000..ef53b34 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h new file mode 100644 index 0000000..2e1d1e4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc +#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 +#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlBOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h new file mode 100644 index 0000000..4f70259 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h @@ -0,0 +1,53 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h new file mode 100644 index 0000000..306b141 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000F // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000F00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerB time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h new file mode 100644 index 0000000..ea39859 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h new file mode 100644 index 0000000..2a82b72 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h new file mode 100644 index 0000000..5e1e8a5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/LM3S316.icf b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/LM3S316.icf new file mode 100644 index 0000000..2c39cba --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/LM3S316.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// boot_demo1.icf - Linker configuration file for boot_demo1. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x00003fff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20000fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c new file mode 100644 index 0000000..6c5d592 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c @@ -0,0 +1,145 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 ) + +static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned char ucBit = ( unsigned char ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned char ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned char ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned char ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd new file mode 100644 index 0000000..731a5bb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd @@ -0,0 +1,879 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp new file mode 100644 index 0000000..530a98f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp @@ -0,0 +1,961 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\commstest.c + + + $PROJ_DIR$\..\Common\Minimal\crflash.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\registertest.s + + + + FreeRTOS Source + + $PROJ_DIR$\..\..\Source\croutine.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + Luminary Code + + $PROJ_DIR$\hw_include\cspy.c + + + $PROJ_DIR$\hw_include\pdc.c + + + $PROJ_DIR$\hw_include\startup.c + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww new file mode 100644 index 0000000..239a938 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c new file mode 100644 index 0000000..59ac650 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c @@ -0,0 +1,325 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * The comms test Rx and Tx task and co-routine. See the comments at the top + * of main.c for full information. + */ + + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The LED's toggled by the various tasks. */ +#define commsFAIL_LED ( 7 ) +#define commsRX_LED ( 6 ) +#define commsTX_LED ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define commsRX_QUEUE_LEN ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define commsBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define commsFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from commsFIRST_TX_CHAR to commsLAST_TX_CHAR. */ +#define commsFIRST_TX_CHAR '0' +#define commsLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define commsTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define commsFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define commsMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define commsMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define commsOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define commsRX_DELAY ( commsMAX_TX_DELAY + 20 ) + + +static unsigned portBASE_TYPE uxCommsErrorStatus = pdPASS; + +/* The queue used to pass characters out of the ISR. */ +static xQueueHandle xCommsQueue; + +/* The next character to transmit. */ +static char cNextChar; + +/*-----------------------------------------------------------*/ + +void vSerialInit( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( commsRX_QUEUE_LEN, sizeof( char ) ); + + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~commsFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned long *pulRandomBytes = commsFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxCommsErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vParTestSetLED( commsFAIL_LED, pdTRUE ); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = commsFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( commsTX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > commsTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = commsFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= commsMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < commsMIN_TX_DELAY ) + { + xDelayPeriod = commsMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR( void ) +{ +unsigned long ulStatus; +char cRxedChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= commsLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +void vCommsRxTask( void * pvParameters ) +{ +static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = commsFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, commsRX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxCommsErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != commsLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = commsFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == commsLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( commsRX_LED ); + cExpectedChar = commsFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxGetCommsStatus( void ) +{ + return uxCommsErrorStatus; +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h new file mode 100644 index 0000000..6fbc6f4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h @@ -0,0 +1,87 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef COMMS_TEST_H +#define COMMS_TEST_H + +/* + * Initialisation routine for the UART. + */ +void vSerialInit( void ); + +/* + * The task that receives the characters from UART 0. + */ +void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +unsigned portBASE_TYPE uxGetCommsStatus( void ); + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h new file mode 100644 index 0000000..6374ddc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h @@ -0,0 +1,22 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" +#include "hw_i2c.h" +#include "hw_adc.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" +#include "i2c.h" +#include "adc.h" + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt new file mode 100644 index 0000000..cba31f7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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Use, duplication or +disclosure by the Government is subject to restrictions as set forth in +subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software +clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial +Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. +Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100, +Austin, Texas 78746. + +9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI +EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED +"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, +WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING +OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING +THE SOFTWARE (IF ANY). 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You agree that the statutes and +laws of the United States and the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and you agree that any litigation will be subject to +the exclusive jurisdiction of the state or federal courts in Austin, Travis +County, Texas, USA. You agree that regardless of any statute or law to the +contrary, any claim or cause of action arising out of or related to this +Agreement or the Software must be filed within one (1) year after such claim or +cause of action arose or be forever barred. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and LMI regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h new file mode 100644 index 0000000..1825664 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h new file mode 100644 index 0000000..4a1018a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h @@ -0,0 +1,130 @@ +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#ifdef gcc + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd + +#endif // rvmdk + +#endif // __ASMDEF_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h new file mode 100644 index 0000000..19eda38 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h new file mode 100644 index 0000000..0a2e282 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c new file mode 100644 index 0000000..398ae59 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c @@ -0,0 +1,119 @@ +//***************************************************************************** +// +// cspy.c - Routines for simply ignoring the debugger communciation APIs in +// C-Spy for now. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#include "diag.h" + +//***************************************************************************** +// +// Open a handle for stdio functions (both stdin and stdout). +// +//***************************************************************************** +int +DiagOpenStdio(void) +{ + return(-1); +} + +//***************************************************************************** +// +// Open a host file system file. +// +//***************************************************************************** +int +DiagOpen(const char *pcName, int iMode) +{ + return(-1); +} + +//***************************************************************************** +// +// Close a host file system file. +// +//***************************************************************************** +int +DiagClose(int iHandle) +{ + return(-1); +} + +//***************************************************************************** +// +// Write data to a host file system file. +// +//***************************************************************************** +int +DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, int iMode) +{ + return(-1); +} + +//***************************************************************************** +// +// Read data from a host file system file. +// +//***************************************************************************** +int +DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode) +{ + return(-1); +} + +//***************************************************************************** +// +// Get the length of a host file system file. +// +//***************************************************************************** +long +DiagFlen(int iHandle) +{ + return(-1); +} + +//***************************************************************************** +// +// Terminate the application. +// +//***************************************************************************** +void +DiagExit(int iRet) +{ + while(1) + { + } +} + +//***************************************************************************** +// +// Get the command line arguments from the debugger. +// +//***************************************************************************** +char * +DiagCommandString(char *pcBuf, unsigned long ulLen) +{ + return(0); +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h new file mode 100644 index 0000000..83dbbf3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h new file mode 100644 index 0000000..5eda186 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// diag.h - Prototypes for the diagnostic functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DIAG_H__ +#define __DIAG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed as the iMode parater to DiagOpen, DiagRead, and +// DiagWrite. +// +//***************************************************************************** +#define OPEN_R 0 // read access +#define OPEN_W 4 // write access +#define OPEN_A 8 // append to file +#define OPEN_B 1 // binary access +#define OPEN_PLUS 2 // read and write access + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern int DiagOpenStdio(void); +extern int DiagOpen(const char *pcName, int iMode); +extern int DiagClose(int iHandle); +extern int DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, + int iMode); +extern int DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode); +extern long DiagFlen(int iHandle); +extern void DiagExit(int iRet); +extern char *DiagCommandString(char *pcBuf, unsigned long ulLen); + +#ifdef __cplusplus +} +#endif + +#endif // __DIAG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 new file mode 100644 index 0000000..3ea9f15 Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h new file mode 100644 index 0000000..7220276 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h new file mode 100644 index 0000000..598fec8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h @@ -0,0 +1,136 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h new file mode 100644 index 0000000..36b8204 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h @@ -0,0 +1,329 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x30000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x03000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00300000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00030000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00003000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000300 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000030 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000003 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h new file mode 100644 index 0000000..02487e6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h new file mode 100644 index 0000000..2143551 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h new file mode 100644 index 0000000..2f85bbc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h new file mode 100644 index 0000000..2a5f4fd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h @@ -0,0 +1,189 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h new file mode 100644 index 0000000..65ce141 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h @@ -0,0 +1,96 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h new file mode 100644 index 0000000..9f701fc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h new file mode 100644 index 0000000..9e3154c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h new file mode 100644 index 0000000..b14172a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h new file mode 100644 index 0000000..c8a18fc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h new file mode 100644 index 0000000..884cdec --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h @@ -0,0 +1,380 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h new file mode 100644 index 0000000..9954a9f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h new file mode 100644 index 0000000..a3b9dcb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h new file mode 100644 index 0000000..99bdc3c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h new file mode 100644 index 0000000..e9d3f0b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h new file mode 100644 index 0000000..26bb1dd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h new file mode 100644 index 0000000..98f0f86 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c new file mode 100644 index 0000000..dfcf418 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c @@ -0,0 +1,724 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1 Mbps master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfigSetExpClk(SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Read a PDC register. +//! +//! \param ucAddr specifies the PDC register to read. +//! +//! This function will perform the SSI transfers required to read a register in +//! the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return Returns the value read from the PDC. +// +//***************************************************************************** +unsigned char +PDCRead(unsigned char ucAddr) +{ + unsigned long ulTemp; + + // + // Send address and read command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_RD); + + // + // Dummy write to force read. + // + SSIDataPut(SSI_BASE, 0x00); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // If the LCD control register or RAM is being read, then an additional + // byte needs to be transferred. + // + if((ucAddr == PDC_LCD_CSR) || (ucAddr == PDC_LCD_RAM)) + { + // + // Dummy write to force read. + // + SSIDataPut(SSI_BASE, 0x00); + + // + // Flush read data. + // + SSIDataGet(SSI_BASE, &ulTemp); + } + + // + // Read valid data. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Return the data read. + // + return(ulTemp & 0xFF); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + +//***************************************************************************** +// +//! Read the current value of the PDC DIP switches. +//! +//! This function will read the current value of the DIP switches attached to +//! the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The current state of the DIP switches. +// +//***************************************************************************** +unsigned char +PDCDIPRead(void) +{ + return(PDCRead(PDC_DSW)); +} + +//***************************************************************************** +// +//! Write to the PDC LEDs. +//! +//! \param ucLED value to write to the LEDs. +//! +//! This function set the state of the LEDs connected to the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLEDWrite(unsigned char ucLED) +{ + PDCWrite(PDC_LED, ucLED); +} + +//***************************************************************************** +// +//! Read the current status of the PDC LEDs. +//! +//! This function will read the state of the LEDs connected to the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The value currently displayed by the LEDs. +// +//***************************************************************************** +unsigned char +PDCLEDRead(void) +{ + return(PDCRead(PDC_LED)); +} + +//***************************************************************************** +// +//! Initializes the LCD display. +//! +//! This function will set up the LCD display for writing. It will set the +//! data bus to 8 bits, set the number of lines to 2, and the font size to +//! 5x10. It will also turn the display off, clear the display, turn the +//! display back on, and enable the backlight. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \note The PDC must be initialized via the PDCInit() function before this +//! function can be called. Also, it may be necessary to adjust the contrast +//! potentiometer in order to discern any output on the LCD display. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDInit(void) +{ + unsigned char pucCfg[] = + { + 0x3C, // Number of lines = 2 / font = 5x10 + 0x08, // Display off + 0x01, // Display clear + 0x06, // Entry mode [cursor dir][shift] + 0x0C, // Display on [display on][curson on][blinking on] + }; + unsigned long ulIdx; + + // + // Set the data bus width to eight bits. + // + PDCWrite(PDC_LCD_CSR, 0x30); + + // + // Wait for 4.1ms by reading the PDC version register enough times to + // guarantee that amount of time has passed. + // + for(ulIdx = 0; ulIdx < 257; ulIdx++) + { + PDCRead(PDC_VER); + } + + // + // Set the data bus width to eight bits. + // + PDCWrite(PDC_LCD_CSR, 0x30); + + // + // Wait for 100us by reading the PDC version register enough times to + // guarantee that amount of time has passed. This works out to 112us plus + // overhead. + // + for(ulIdx = 0; ulIdx < 7; ulIdx++) + { + PDCRead(PDC_VER); + } + + // + // Set the data bus width to eight bits. + // + PDCWrite(PDC_LCD_CSR, 0x30); + + // + // Configure the LCD. + // + for(ulIdx = 0; ulIdx < (sizeof(pucCfg) / sizeof(pucCfg[0])); ulIdx++) + { + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write the next configuration byte. + // + PDCWrite(PDC_LCD_CSR, pucCfg[ulIdx]); + } +} + +//***************************************************************************** +// +//! Turns on the backlight. +//! +//! This function turns on the backlight on the LCD. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDBacklightOn(void) +{ + PDCWrite(PDC_CSR, 0x01); +} + +//***************************************************************************** +// +//! Turn off the backlight. +//! +//! This function turns off the backlight on the LCD. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDBacklightOff(void) +{ + PDCWrite(PDC_CSR, 0x00); +} + +//***************************************************************************** +// +//! Clear the screen. +//! +//! This function clears the contents of the LCD screen. The cursor will be +//! returned to the upper left corner. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDClear(void) +{ + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write the clear display command. + // + PDCWrite(PDC_LCD_CSR, LCD_CLEAR); +} + +//***************************************************************************** +// +//! Write a character pattern to the LCD. +//! +//! \param ucChar is the character index to create. Valid values are zero +//! through seven. +//! \param pucData is the data for the character pattern. It contains eight +//! bytes, with the first byte being the top row of the pattern. In each byte, +//! the LSB is the right pixel of the pattern. +//! +//! This function will write a character pattern into the LCD for use as a +//! character to be displayed. After writing the pattern, it can be used on +//! the LCD by writing the corresponding character index to the display. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData) +{ + // + // Check the arguments. + // + ASSERT(ucChar < 8); + + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write the character pattern memory address. + // + PDCWrite(PDC_LCD_CSR, LCD_CGADDR + (ucChar * 8)); + + // + // Write the pattern to chacter pattern memory. + // + for(ucChar = 0; ucChar < 8; ucChar++) + { + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write this row of the pattern. + // + PDCWrite(PDC_LCD_RAM, *pucData++); + } +} + +//***************************************************************************** +// +//! Set the position of the cursor. +//! +//! \param ucX is the horizontal position. Valid values are zero through +//! fifteen. +//! \param ucY is the vertical position.. Valid values are zero and one. +//! +//! This function will move the cursor to the specified position. All +//! characters written to the LCD are placed at the current cursor position, +//! which is automatically advanced. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDSetPos(unsigned char ucX, unsigned char ucY) +{ + // + // Check the arguments. + // + ASSERT(ucX < 16); + ASSERT(ucY < 2); + + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Set the cursor position. + // + PDCWrite(PDC_LCD_CSR, LCD_DDADDR | (0x40 * ucY) + ucX); +} + +//***************************************************************************** +// +//! Writes a string to the LCD display. +//! +//! \param pcStr pointer to the string to be displayed. +//! \param ulCount is the number of characters to be displayed. +//! +//! This function will display a string on the LCD at the current cursor +//! position. It is the caller's responsibility to position the cursor to the +//! place where the string should be displayed (either explicitly via +//! PDCLCDSetPos() or implicitly from where the cursor was left after a +//! previous call to PDCLCDWrite()), and to properly account for the LCD +//! boundary (line wrapping is not automatically performed). Null characters +//! are not treated special and are written to the LCD, which interprets it as +//! a special programmable character glyph (see PDCLCDCreateChar()). +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDWrite(const char *pcStr, unsigned long ulCount) +{ + // + // Write the string to the LCD. + // + while(ulCount--) + { + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write this character to the LCD. + // + PDCWrite(PDC_LCD_RAM, *pcStr++); + } +} + +//***************************************************************************** +// +//! Reads a GPIO direction register. +//! +//! \param ucIdx is the index of the GPIO direction register to read; valid +//! values are 0, 1, and 2. +//! +//! This function reads one of the GPIO direction registers in the PDC. The +//! direction bit is set for pins that are outputs and clear for pins that are +//! inputs. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The contents of the direction register. +// +//***************************************************************************** +unsigned char +PDCGPIODirRead(unsigned char ucIdx) +{ + // + // Check the argument. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Read the requested direction register. + // + if(ucIdx == 0) + { + return(PDCRead(PDC_GPXDIR)); + } + else if(ucIdx == 1) + { + return(PDCRead(PDC_GPYDIR)); + } + else + { + return(PDCRead(PDC_GPZDIR)); + } +} + +//***************************************************************************** +// +//! Write a GPIO direction register. +//! +//! \param ucIdx is the index of the GPIO direction register to write; valid +//! values are 0, 1, and 2. +//! \param ucValue is the value to write to the GPIO direction register. +//! +//! This function writes ones of the GPIO direction registers in the PDC. The +//! direction bit should be set for pins that are to be outputs and clear for +//! pins that are to be inputs. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue) +{ + // + // Check the arguments. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Write the requested direction register. + // + if(ucIdx == 0) + { + PDCWrite(PDC_GPXDIR, ucValue); + } + else if(ucIdx == 1) + { + PDCWrite(PDC_GPYDIR, ucValue); + } + else + { + PDCWrite(PDC_GPZDIR, ucValue); + } +} + +//***************************************************************************** +// +//! Reads a GPIO data register. +//! +//! \param ucIdx is the index of the GPIO direction register to read; valid +//! values are 0, 1, and 2. +//! +//! This function reads one of the GPIO data registers in the PDC. The value +//! returned for a pin is the value being driven out for outputs or the value +//! being read for inputs. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The contents of the data register. +// +//***************************************************************************** +unsigned char +PDCGPIORead(unsigned char ucIdx) +{ + // + // Check the argument. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Read the requested data register. + // + if(ucIdx == 0) + { + return(PDCRead(PDC_GPXDAT)); + } + else if(ucIdx == 1) + { + return(PDCRead(PDC_GPYDAT)); + } + else + { + return(PDCRead(PDC_GPZDAT)); + } +} + +//***************************************************************************** +// +//! Write a GPIO data register. +//! +//! \param ucIdx is the index of the GPIO data register to write; valid values +//! are 0, 1, and 2. +//! \param ucValue is the value to write to the GPIO data register. +//! +//! This function writes one of the GPIO direction registers in the PDC. The +//! written to a pin is driven out for output pins and ignored for input pins. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue) +{ + // + // Check the arguments. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Write the requested data register. + // + if(ucIdx == 0) + { + PDCWrite(PDC_GPXDAT, ucValue); + } + else if(ucIdx == 1) + { + PDCWrite(PDC_GPYDAT, ucValue); + } + else + { + PDCWrite(PDC_GPZDAT, ucValue); + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h new file mode 100644 index 0000000..9529424 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h new file mode 100644 index 0000000..13cd4e1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h new file mode 100644 index 0000000..eb13740 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h @@ -0,0 +1,92 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c new file mode 100644 index 0000000..a76a783 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c @@ -0,0 +1,195 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); +extern void vPortSVCHandler( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 50 +#endif +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + +//***************************************************************************** +// +// The minimal vector table for a Cortex-M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, + // The initial stack pointer + __iar_program_start, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + vPortSVCHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + vUART_ISR, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + 0, // Reserved + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler // FLASH Control +}; + + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h new file mode 100644 index 0000000..f9ce18d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h @@ -0,0 +1,266 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h new file mode 100644 index 0000000..9056076 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h new file mode 100644 index 0000000..e604186 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h new file mode 100644 index 0000000..6047d3a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h new file mode 100644 index 0000000..4d6dcd2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c new file mode 100644 index 0000000..8d6fc81 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c @@ -0,0 +1,477 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application creates eight co-routines and four tasks (five + * including the idle task). The co-routines execute as part of the idle task + * hook. The application is limited in size to allow its compilation using + * the KickStart version of the IAR compiler. + * + * Six of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' waits on a message queue for messages informing it what and + * where to display text. This is the only task that accesses the LCD + * so mutual exclusion is guaranteed. + * + * The 'LCD Message Task' periodically sends strings to the LCD Task using + * the message queue. The strings are rotated to form a short message and + * are written to the top row of the LCD. + * + * The 'ADC Co-routine' periodically reads the ADC input that is connected to + * the light sensor, forms a short message from the value, and then sends this + * message to the LCD Task using the same message queue. The ADC readings are + * displayed on the bottom row of the LCD. + * + * The eighth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on + * should an error be detected in any task or co-routine. + * + * In addition the idle task makes repetitive calls to + * vSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechanism. + * + */ + +/* standard include files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" +#include "commstest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +#define mainADC_DELAY ( 200 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to send messages to the LCD task. */ +#define mainLCD_QUEUE_LEN ( 3 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) +#define mainADC_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one of each co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainADC_CO_ROUTINE_INDEX ( 0 ) + +/* The task priorities. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainMSG_TASK_PRIORITY ( mainLCD_TASK_PRIORITY - 1 ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LCD had two rows. */ +#define mainTOP_ROW 0 +#define mainBOTTOM_ROW 1 + +/* Dimension for the buffer into which the ADC value string is written. */ +#define mainMAX_ADC_STRING_LEN 20 + +/* The LED that is lit should an error be detected in any of the tasks or +co-routines. */ +#define mainFAIL_LED ( 7 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that displays text on the LCD. + */ +static void prvLCDTask( void * pvParameters ); + +/* + * The task that sends messages to be displayed on the top row of the LCD. + */ +static void prvLCDMessageTask( void * pvParameters ); + +/* + * The co-routine that reads the ADC and sends messages for display on the + * bottom row of the LCD. + */ +static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +extern void vSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( char cAddress, char cData ); + +/* + * Sets up the hardware used by the demo. + */ +static void prvSetupHardware( void ); + + +/*-----------------------------------------------------------*/ + +/* The structure that is passed on the LCD message queue. */ +typedef struct +{ + char **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ + portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ +} xLCDMessage; + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The queue used to transmit messages to the LCD task. */ +static xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +/* + * Setup the hardware, create the tasks/co-routines, then start the scheduler. + */ +void main( void ) +{ + /* Create the queue used by tasks wanting to write to the LCD. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART and the task that receives them, as described at the top of + this file. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Create the task that waits for messages to display on the LCD, plus the + task and co-routine that send messages for display (as described at the top + of this file. */ + xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); + xCoRoutineCreate( prvADCCoRoutine, mainADC_CO_ROUTINE_PRIORITY, mainADC_CO_ROUTINE_INDEX ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDMessageTask( void * pvParameters ) +{ +/* The strings that are written to the LCD. */ +char *pcStringsToDisplay[] = { + "IAR ", + "Stellaris ", + "Demo ", + "www.FreeRTOS.org", + "" + }; + +xQueueHandle *pxLCDQueue; +xLCDMessage xMessageToSend; +portBASE_TYPE xIndex = 0; + + /* To test the parameter passing mechanism, the queue on which messages are + posted is passed in as a parameter even though it is available as a file + scope variable anyway. */ + pxLCDQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + + /* Create the message object to send to the LCD task. */ + xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; + xMessageToSend.xRow = mainTOP_ROW; + + /* Post the message to be displayed. */ + if( !xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ) ) + { + uxErrorStatus = pdFAIL; + } + + /* Move onto the next message, wrapping when necessary. */ + xIndex++; + if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) + { + xIndex = 0; + + /* Delay longer before going back to the start of the messages. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + } +} +/*-----------------------------------------------------------*/ + +void prvLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +xQueueHandle *pxLCDQueue; +xLCDMessage xReceivedMessage; +char *pcString; +const unsigned char ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + + /* To test the parameter passing mechanism, the queue on which messages are + received is passed in as a parameter even though it is available as a file + scope variable anyway. */ + pxLCDQueue = ( xQueueHandle * ) pvParameters; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Wait for a message to arrive. */ + if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) + { + /* Which row does the received message say to write to? */ + PDCLCDSetPos( 0, xReceivedMessage.xRow ); + + /* Where is the string we are going to display? */ + pcString = *xReceivedMessage.ppcMessageToDisplay; + + while( *pcString ) + { + /* Don't write out the string too quickly as LCD's are usually + pretty slow devices. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static unsigned long ulADCValue; +static char cMessageBuffer[ mainMAX_ADC_STRING_LEN ]; +static char *pcMessage; +static xLCDMessage xMessageToSend; + + /* Co-routines MUST start with a call to crSTART(). */ + crSTART( xHandle ); + + for( ;; ) + { + /* Start an ADC conversion. */ + ADCProcessorTrigger( ADC_BASE, 0 ); + + /* Simply delay - when we unblock the result should be available */ + crDELAY( xHandle, mainADC_DELAY ); + + /* Get the ADC result. */ + ADCSequenceDataGet( ADC_BASE, 0, &ulADCValue ); + + /* Create a string with the result. */ + sprintf( cMessageBuffer, "ADC = %d ", ulADCValue ); + pcMessage = cMessageBuffer; + + /* Configure the message we are going to send for display. */ + xMessageToSend.ppcMessageToDisplay = ( char** ) &pcMessage; + xMessageToSend.xRow = mainBOTTOM_ROW; + + /* Send the string to the LCD task for display. We are sending + on a task queue so do not have the option to block. */ + if( !xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ) ) + { + uxErrorStatus = pdFAIL; + } + } + + /* Co-routines MUST end with a call to crEND(). */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); + + /* The ADC is used to read the light sensor. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC ); + ADCSequenceConfigure( ADC_BASE, 3, ADC_TRIGGER_PROCESSOR, 0); + ADCSequenceStepConfigure( ADC_BASE, 0, 0, ADC_CTL_CH0 | ADC_CTL_END ); + ADCSequenceEnable( ADC_BASE, 0 ); + +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( char cAddress, char cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainFAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + vSetAndCheckRegisters(); + + /* See if the comms task and co-routine has found any errors. */ + if( uxGetCommsStatus() != pdPASS ) + { + vParTestSetLED( mainFAIL_LED, pdTRUE ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/registertest.s b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/registertest.s new file mode 100644 index 0000000..7f27b5f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/registertest.s @@ -0,0 +1,60 @@ + RSEG ICODE:CODE + + EXTERN vSetErrorLED + + PUBLIC vSetAndCheckRegisters + +vSetAndCheckRegisters: + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led: + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr + + END + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 0000000..8f02612 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,65 @@ + + + + + + 300 + + + + + + + 274272727 + + + + + + + + 200 + + + + 010 + + 20 + 1004 + 267 + 66 + 300Debug-LogBreakpoints + 20011210310010020020014010010010030010300Debug-LogBuild1001001 + + + + + + + TabID-30594-29847 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo Source + + + + 0TabID-30273-20034Debug LogDebug-Log0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_LM3S316_IAR\main.c01958048804800100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2738348-2-2200202142857205703250000753564-2-22001402-2-214042021002857205703142857205703 + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni new file mode 100644 index 0000000..b96f7c2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni @@ -0,0 +1,48 @@ +[JLinkDriver] +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[CodeCoverage] +Enabled=_ 0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Disassemble mode] +mode=1 +[Breakpoints2] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 0000000..25e72a1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,58 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 238272727 + + + + + + + 30020100426766 + + + 48268826 + + + + + + + TabID-2928-28933 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo SourceRTOSDemo/Libraries + + + + 0TabID-24894-24921BuildBuildTabID-10790-31422Debug LogDebug-LogTabID-27705-5723Find in FilesFind-in-Files0 + + + + + + TextEditor$WS_DIR$\main.c000000100000010000001 + + + + + + + iaridepm.enu1-2-2738312-2-2240202142857205703186905753564-2-22001682-2-216842021002381205703142857205703 + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt new file mode 100644 index 0000000..6deb801 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt @@ -0,0 +1,51 @@ + + + + + + + + qs_dk-lm3s316/Debug + + + + + + + + + 253272727 + + 20100426766 + + + + + + TabID-9985-21059 + Workspace + Workspace + + + + + + + 0TabID-31963-22489BuildBuildTabID-12860-23630Debug LogDebug-Log0 + + + + + + TextEditorC:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\examples\Luminary\DK-LM3Sxxx\utils\cspy.c04200TextEditorC:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\examples\Luminary\DK-LM3Sxxx\examples\qs_dk-lm3s102\startup.c03900TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\examples\qs_dk-lm3s101\qs_dk-lm3s101.c02841017910179TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\utils\pdc.c0615401540TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\watchdog.c0014731480TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\uart.c0015141514TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\timer.c0015241524TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\systick.c0015131513TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\sysctl.c0015531553TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\ssi.c0015301530TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\pwm.c0015131513TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\interrupt.c0015211521TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\i2c.c0015261526TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\gpio.c0015111511TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\flash.c0015601560TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\comp.c0015261526TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\adc.c0015091509TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\examples\qs_dk-lm3s316\qs_dk-lm3s316.c05721292312923TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\utils\cspy.c03900180100000010000001 + + + + + + + iaridepm1-2-2728327-2-2200200142857205761235000751029-2-21981402-2-214042001002857205761142857205761 + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h new file mode 100644 index 0000000..2d7022f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/Makefile b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/Makefile new file mode 100644 index 0000000..e8613bd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/Makefile @@ -0,0 +1,85 @@ +#****************************************************************************** +# +# Makefile - Rules for building the driver library and examples. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +include makedefs + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal + +CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= + +VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:hw_include + +OBJS=${COMPILER}/main.o \ + ${COMPILER}/list.o \ + ${COMPILER}/queue.o \ + ${COMPILER}/tasks.o \ + ${COMPILER}/port.o \ + ${COMPILER}/heap_1.o \ + ${COMPILER}/BlockQ.o \ + ${COMPILER}/PollQ.o \ + ${COMPILER}/integer.o \ + ${COMPILER}/semtest.o \ + ${COMPILER}/osram96x16.o + +INIT_OBJS= ${COMPILER}/startup.o + +LIBS= hw_include/libdriver.a + + +# +# The default rule, which causes init to be built. +# +all: ${COMPILER} \ + ${COMPILER}/RTOSDemo.axf \ + +# +# The rule to clean out all the build products +# + +clean: + @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf + +# +# The rule to create the target directory +# +${COMPILER}: + @mkdir ${COMPILER} + +${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} +SCATTER_RTOSDemo=standalone.ld +ENTRY_RTOSDemo=ResetISR + +# +# +# Include the automatically generated dependency files. +# +-include ${wildcard ${COMPILER}/*.d} __dummy__ + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h new file mode 100644 index 0000000..47531fb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h @@ -0,0 +1,39 @@ +#ifndef DRIVER_LIB_H +#define DRIVER_LIB_H + +#include "DriverLib.h" +#include "hw_adc.h" +#include "hw_comp.h" +#include "hw_flash.h" +#include "hw_gpio.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_pwm.h" +#include "hw_qei.h" +#include "hw_ssi.h" +#include "hw_sysctl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_watchdog.h" +#include "osram96x16.h" +#include "adc.h" +#include "comp.h" +#include "cpu.h" +#include "debug.h" +#include "flash.h" +#include "gpio.h" +#include "i2c.h" +#include "interrupt.h" +#include "pwm.h" +#include "qei.h" +#include "ssi.h" +#include "sysctl.h" +#include "systick.h" +#include "timer.h" +#include "uart.h" +#include "watchdog.h" + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt new file mode 100644 index 0000000..02c57b2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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You agree to fully defend and indemnify LMI from any and +all claims, liabilities, and costs (including reasonable attorney's fees) +related to (1) your use (including your sub-licensee's use, if permitted) of +the Software or (2) your violation of the terms and conditions of this +Agreement. + +5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault +tolerant and is not designed, manufactured or intended by LMI for incorporation +into products intended for use or resale in on-line control equipment in +hazardous, dangerous to life or potentially life-threatening environments +requiring fail-safe performance, such as in the operation of nuclear +facilities, aircraft navigation or communication systems, air traffic control, +direct life support machines or weapons systems, in which the failure of +products could lead directly to death, personal injury or severe physical or +environmental damage ("High Risk Activities"). You specifically represent and +warrant that you will not use the Software or any derivative work of the +Software for High Risk Activities. + +6. PRODUCT LABELING. You are not authorized to use any LMI trademarks, +brand names, or logos. + +7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software +in accordance with all applicable U.S. laws, regulations and statutes. You +agree that neither you nor your licensees (if any) intend to or will, directly +or indirectly, export or transmit the Software to any country in violation of +U.S. export restrictions. + +8. GOVERNMENT USE. Use of the Software and any corresponding +documentation, if any, is provided with RESTRICTED RIGHTS. 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You agree that the statutes and +laws of the United States and the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and you agree that any litigation will be subject to +the exclusive jurisdiction of the state or federal courts in Austin, Travis +County, Texas, USA. You agree that regardless of any statute or law to the +contrary, any claim or cause of action arising out of or related to this +Agreement or the Software must be filed within one (1) year after such claim or +cause of action arose or be forever barred. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and LMI regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c new file mode 100644 index 0000000..53f3adf --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c @@ -0,0 +1,946 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include "../hw_adc.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "adc.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL) +unsigned char g_pucOversampleFactor[3]; +#else +extern unsigned char g_pucOversampleFactor[3]; +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This will enable the global interrupt in the interrupt +//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It +//! is the interrupt handler's responsibility to clear the interrupt source via +//! ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This will disable the +//! global interrupt in the interrupt controller; the sequence interrupt must +//! be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified sample sequence. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); + } + else + { + return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); + } +} +#endif + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence should be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulTrigger is the trigger source that initiates the sample sequence; +//! must be one of the \b ADC_TRIGGER_* values. +//! \param ulPriority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequences range from zero to three; sequence zero will capture +//! up to eight samples, sequences one and two will capture up to four samples, +//! and sequence three will capture a single sample. The trigger condition and +//! priority (with respect to other sample sequence execution) is set. +//! +//! The parameter \b ulTrigger can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! Note that not all trigger sources are available on all Stellaris family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents +//! the highest priority and 3 the lowest. Note that when programming the +//! priority among a set of sample sequences, each must have unique priority; +//! it is up to the caller to guarantee the uniqueness of the priorities. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulTrigger, unsigned long ulPriority) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || + (ulTrigger == ADC_TRIGGER_COMP0) || + (ulTrigger == ADC_TRIGGER_COMP1) || + (ulTrigger == ADC_TRIGGER_COMP2) || + (ulTrigger == ADC_TRIGGER_EXTERNAL) || + (ulTrigger == ADC_TRIGGER_TIMER) || + (ulTrigger == ADC_TRIGGER_PWM0) || + (ulTrigger == ADC_TRIGGER_PWM1) || + (ulTrigger == ADC_TRIGGER_PWM2) || + (ulTrigger == ADC_TRIGGER_ALWAYS)); + ASSERT(ulPriority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ulSequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & + ~(0xf << ulSequenceNum)) | + ((ulTrigger & 0xf) << ulSequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & + ~(0xf << ulSequenceNum)) | + ((ulPriority & 0x3) << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step; must be a logical OR of +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). +//! +//! This function will set the configuration of the ADC for one step of a +//! sample sequence. The ADC can be configured for single-ended or +//! differential operation (the \b ADC_CTL_D bit selects differential +//! operation when set), the channel to be sampled can be chosen (the +//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature +//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step +//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it +//! can be configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the +//! appropriate time when the trigger for this sequence occurs. +//! +//! The \b ulStep parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequence, from zero to three for the second and +//! third sample sequence, and can only be zero for the fourth sample sequence. +//! +//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1). +//! The channel select must be the number of the channel pair to sample (e.g. +//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined +//! results will be returned by the ADC. Additionally, if differential mode is +//! selected when the temperature sensor is being sampled, undefined results +//! will be returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulStep, unsigned long ulConfig) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || + ((ulSequenceNum == 1) && (ulStep < 4)) || + ((ulSequenceNum == 2) && (ulStep < 4)) || + ((ulSequenceNum == 3) && (ulStep < 1))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence overflow has occurred. This will +//! happen if the captured samples are not read from the FIFO before the next +//! trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence underflow has occurred. This will +//! happen if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer. The number of samples available in the hardware +//! FIFO are copied into the buffer, which is assumed to be large enough to +//! hold that many samples. This will only return the samples that are +//! presently available, which may not be the entire sample sequence if it is +//! in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer) +{ + unsigned long ulCount; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ulCount = 0; + while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) && + (ulCount < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO); + + // + // Increment the count of samples read. + // + ulCount++; + } + + // + // Return the number of samples read. + // + return(ulCount); +} +#endif + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (i.e. the fourth sample sequencer is not supported). +//! Oversampling by 2x (for example) divides the depth of the sample sequencer +//! by two; so 2x oversampling on the first sample sequencer can only provide +//! four samples per trigger. This also means that 8x oversampling is only +//! available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && + ((ulSequenceNum == 0) || (ulFactor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Save the sfiht factor. + // + g_pucOversampleFactor[ulSequenceNum] = ulValue; +} +#endif + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; + ulSequenceNum; ulSequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + if(ulSequenceNum != 1) + { + HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 | + ADC_SSCTL_END0) << ulStep); + } + + // + // Go to the next hardware step. + // + ulStep += 4; + } +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! \param ulCount is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items +//! then incorrect results will be returned. It is the caller's responsibility +//! to read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer, unsigned long ulCount) +{ + unsigned long ulIdx, ulAccum; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ulCount--) + { + // + // Compute the sum of the samples. + // + ulAccum = 0; + for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; + } +} +#endif + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero will disable the hardware +//! oversampler. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 KSps ADC to 62.5 KSps. +//! +//! \note Hardware oversampling is available beginning with Rev C0 of the +//! Stellaris microcontroller. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || + (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || + (ulFactor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ulBase + ADC_O_SAC) = ulValue; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h new file mode 100644 index 0000000..c1fa37d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h @@ -0,0 +1,126 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c new file mode 100644 index 0000000..aed156e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c @@ -0,0 +1,448 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include "../hw_comp.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "comp.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function will configure a comparator. The \e ulConfig parameter is +//! the result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device +//! pin. +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Configure this comparator. + // + HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulRef is the desired reference voltage. +//! +//! This function will set the internal reference voltage value. The voltage +//! is specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ulBase + COMP_O_REFCTL) = ulRef; +} +#endif + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This sets the handler to be called when the comparator interrupt occurs. +//! This will enable the interrupt in the interrupt controller; it is the +//! interrupt-handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0 + ulComp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0 + ulComp); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function will clear the handler to be called when a comparator +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0 + ulComp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0 + ulComp); +} +#endif + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the comparator. Either the raw or +//! the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false); + } + else + { + return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! must be done in the interrupt handler to keep it from being called again +//! immediately upon exit. Note that for a level triggered interrupt, the +//! interrupt cannot be cleared until it stops asserting. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Clear the interrupt. + // + HWREG(ulBase + COMP_O_MIS) = 1 << ulComp; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h new file mode 100644 index 0000000..9349982 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h new file mode 100644 index 0000000..688c522 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h new file mode 100644 index 0000000..e46e2a7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 new file mode 100644 index 0000000..0d2184f Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/flash.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/flash.c new file mode 100644 index 0000000..ab7335f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/flash.c @@ -0,0 +1,668 @@ +//***************************************************************************** +// +// flash.c - Driver for programming the on-chip flash. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "../hw_flash.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_sysctl.h" +#include "../hw_types.h" +#include "debug.h" +#include "flash.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Gets the number of processor clocks per micro-second. +//! +//! This function returns the number of clocks per micro-second, as presently +//! known by the flash controller. +//! +//! \return Returns the number of processor clocks per micro-second. +// +//***************************************************************************** +#if defined(GROUP_usecget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +FlashUsecGet(void) +{ + // + // Return the number of clocks per micro-second. + // + return(HWREG(FLASH_USECRL) + 1); +} +#endif + +//***************************************************************************** +// +//! Sets the number of processor clocks per micro-second. +//! +//! \param ulClocks is the number of processor clocks per micro-second. +//! +//! This function is used to tell the flash controller the number of processor +//! clocks per micro-second. This value must be programmed correctly or the +//! flash most likely will not program correctly; it has no affect on reading +//! flash. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_usecset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashUsecSet(unsigned long ulClocks) +{ + // + // Set the number of clocks per micro-second. + // + HWREG(FLASH_USECRL) = ulClocks - 1; +} +#endif + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 1 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +#if defined(GROUP_erase) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashErase(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); + + // + // Clear the flash access interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; + + // + // Erase the block. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) + { + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) + { + return(-1); + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will program a sequence of words into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a word can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +#if defined(GROUP_program) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; + + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Program the next word. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMD) = *pulData; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE) + { + } + + // + // Increment to the next word. + // + pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) + { + return(-1); + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be queried. +//! +//! This function will get the current protection for the specified 2 kB block +//! of flash. Each block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +#if defined(GROUP_protectget) || defined(BUILD_ALL) || defined(DOXYGEN) +tFlashProtection +FlashProtectGet(unsigned long ulAddress) +{ + unsigned long ulFMPRE, ulFMPPE; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + + // + // Read the flash protection register and get the bits that apply to the + // specified block. + // + ulFMPRE = HWREG(FLASH_FMPRE); + ulFMPPE = HWREG(FLASH_FMPPE); + switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (i.e. it can not be erased or + // programmed, and the only reads allowed are via the instruction fecth + // interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (i.e. it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} +#endif + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function will set the protection for the specified 2 kB block of +//! flash. Blocks which are read/write can be made read-only or execute-only. +//! Blocks which are read-only can be made execute-only. Blocks which are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (i.e. read-only to read/write) will result +//! in a failure (and be prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This allows the application to be executed in the desired flash protection +//! environment to check for inappropriate flash access (via the flash +//! interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) +{ + unsigned long ulProtectRE, ulProtectPE; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ulAddress /= FLASH_PROTECT_SIZE; + + // + // Get the current protection. + // + ulProtectRE = HWREG(FLASH_FMPRE); + ulProtectPE = HWREG(FLASH_FMPPE); + + // + // Set the protection based on the requested proection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) + { + return(-1); + } + + // + // Make this block read only. + // + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) || + (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // Set the new protection. + // + HWREG(FLASH_FMPRE) = ulProtectRE; + HWREG(FLASH_FMPPE) = ulProtectPE; + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function will make the currently programmed flash protection settings +//! permanent. This is a non-reversible operation; a chip reset or power cycle +//! will not change the flash protection. +//! +//! This function will not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSave(void) +{ + // + // Tell the flash controller to write the flash read protection register. + // + HWREG(FLASH_FMA) = 0; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the flash program protection + // register. + // + HWREG(FLASH_FMA) = 1; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS. +// +//***************************************************************************** +#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +FlashIntGetStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS +//! values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h new file mode 100644 index 0000000..9c41dda --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c new file mode 100644 index 0000000..a49602e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c @@ -0,0 +1,1103 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "../hw_gpio.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Get GPIO interrupt number. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +#if defined(GROUP_getintnumber) || defined(BUILD_ALL) +long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIO_PORTA_BASE: + { + ulInt = INT_GPIOA; + break; + } + + case GPIO_PORTB_BASE: + { + ulInt = INT_GPIOB; + break; + } + + case GPIO_PORTC_BASE: + { + ulInt = INT_GPIOC; + break; + } + + case GPIO_PORTD_BASE: + { + ulInt = INT_GPIOD; + break; + } + + case GPIO_PORTE_BASE: + { + ulInt = INT_GPIOE; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} +#else +extern long GPIOGetIntNumber(unsigned long ulPort); +#endif + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pins of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulPinIO pin direction and/or mode +//! +//! This function will set the specified pins on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output, and +//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under +//! hardware control. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || + (ulPinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? + (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AFSEL) & + ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the direction and mode of a specified pin of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir, ulAFSEL; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_DIR); + ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); + return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulIntType specifies the type of interrupt trigger mechanism +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pins on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! where the different values describe the interrupt detection mechanism +//! (edge or level) and the particular triggering event (falling, rising, +//! or both edges for edge detect, low or high for level detect). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || + (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || + (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt type for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_IBE); + ulIS = HWREG(ulPort + GPIO_O_IS); + ulIEV = HWREG(ulPort + GPIO_O_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins bit-packed representation of the specified pins. +//! \param ulStrength specifies the output drive strength. +//! \param ulPinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pins +//! on the selected GPIO port. For pins configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ulStrength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! The parameter \e ulPinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_OD_WPU +//! - \b GPIO_PIN_TYPE_OD_WPD +//! - \b GPIO_PIN_TYPE_ANALOG +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an +//! analog input (for the comparators). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, unsigned long ulPinType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulStrength == GPIO_STRENGTH_2MA) || + (ulStrength == GPIO_STRENGTH_4MA) || + (ulStrength == GPIO_STRENGTH_8MA) || + (ulStrength == GPIO_STRENGTH_8MA_SC)); + ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || + (ulPinType == GPIO_PIN_TYPE_STD_WPU) || + (ulPinType == GPIO_PIN_TYPE_STD_WPD) || + (ulPinType == GPIO_PIN_TYPE_OD) || + (ulPinType == GPIO_PIN_TYPE_OD_WPU) || + (ulPinType == GPIO_PIN_TYPE_OD_WPD) || + (ulPinType == GPIO_PIN_TYPE_ANALOG)) + + // + // Set the output drive strength. + // + HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? + (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? + (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? + (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? + (HWREG(ulPort + GPIO_O_SLR) | ucPins) : + (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); + + // + // Set the pin type. + // + HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? + (HWREG(ulPort + GPIO_O_ODR) | ucPins) : + (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? + (HWREG(ulPort + GPIO_O_PUR) | ucPins) : + (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? + (HWREG(ulPort + GPIO_O_PDR) | ucPins) : + (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? + (HWREG(ulPort + GPIO_O_DEN) | ucPins) : + (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the pad configuration for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! \param pulStrength pointer to storage for the output drive strength +//! \param pulPinType pointer to storage for the output drive type +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e eStrength and \e eOutType +//! correspond to the values used in GPIOPadConfigSet(). This function also +//! works for pins configured as input pins; however, the only meaningful +//! data returned is whether the pin is terminated with a pull-up or +//! down resistor. +//! +//! \return None +// +//***************************************************************************** +#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, unsigned long *pulPinType) +{ + unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = (1 << ucPin); + + // + // Get the drive strength for this pin. + // + ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); + ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); + ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); + ulTemp4 = HWREG(ulPort + GPIO_O_SLR); + *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); + + // + // Get the pin type. + // + ulTemp1 = HWREG(ulPort + GPIO_O_ODR); + ulTemp2 = HWREG(ulPort + GPIO_O_PUR); + ulTemp3 = HWREG(ulPort + GPIO_O_PDR); + ulTemp4 = HWREG(ulPort + GPIO_O_DEN); + *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Unmasks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) |= ucPins; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Masks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for all the pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param bMasked specifies whether masked or raw interrupt +//! status is returned +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns a bit-packed byte, where each bit that is set identifies +//! an active masked or raw interrupt, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits +//! 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the interrupt for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Clears the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_ICR) = ucPins; +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param pfIntHandler pointer to the GPIO port interrupt handling function +//! +//! This function will ensure that the interrupt handler specified by \e +//! pfIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO +//! interrupt in the interrupt controller; individual pin interrupts and +//! interrupt sources must be enabled with GPIOPinIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOPinIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} +#endif + +//***************************************************************************** +// +//! Reads the values present at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The values at the specified pins are read, as specified by \e ucPins. +//! Values are returned for both input and output pins, and the value +//! for pins that are not specified by \e ucPins are set to 0. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); +} +#endif + +//***************************************************************************** +// +//! Writes a value at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ucVal value to write to the specified pins +//! +//! Writes the corresponding bit values to the output pins specified +//! by \e ucPins. Writing to a pin configured as an input pin has no +//! effect. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an analog comparator input; +//! it only configures an analog comparator pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2C peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an I2C pin; it only +//! configures an I2C pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, not using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a timer pin; it only +//! configures a timer pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a UART pin; it only +//! configures a UART pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h new file mode 100644 index 0000000..88d6572 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h new file mode 100644 index 0000000..022b9e9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h @@ -0,0 +1,343 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h new file mode 100644 index 0000000..991b7a0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h new file mode 100644 index 0000000..53128b4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h new file mode 100644 index 0000000..bf25d3f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h new file mode 100644 index 0000000..2c9f46d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h new file mode 100644 index 0000000..2204a2c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h new file mode 100644 index 0000000..2b11f35 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h new file mode 100644 index 0000000..6598ef8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h new file mode 100644 index 0000000..cc42015 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h new file mode 100644 index 0000000..864459f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h new file mode 100644 index 0000000..e4650af --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h new file mode 100644 index 0000000..4f6b55e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h @@ -0,0 +1,409 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h new file mode 100644 index 0000000..210c340 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h new file mode 100644 index 0000000..ec05e54 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h new file mode 100644 index 0000000..6f421b6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h new file mode 100644 index 0000000..2b013ad --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c new file mode 100644 index 0000000..b460ad6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c @@ -0,0 +1,972 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include "../hw_i2c.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "i2c.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! \param bFast set up for fast data transfers +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have +//! set the bus speed for the master, and will have enabled the I2C Master +//! block. +//! +//! If the parameter \e bFast is \b true, then the master block will be +//! set up to transfer data at 400 kbps; otherwise, it will be set up to +//! transfer data at 100 kbps. +//! +//! The I2C clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the I2C clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterInit(unsigned long ulBase, tBoolean bFast) +{ + unsigned long ulSysClk; + unsigned long ulSCLFreq; + unsigned long ulTPR; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ulBase); + + // + // Get the system clock speed. + // + ulSysClk = SysCtlClockGet(); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ulSCLFreq = I2C_SCL_FAST; + } + else + { + ulSCLFreq = I2C_SCL_STANDARD; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biases to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) / + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1); + HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR; +} +#endif + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have +//! set the slave address and have enabled the I2C Slave block. +//! +//! The parameter \e ucSlaveAddr is the value that will be compared +//! against the slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ulBase); + + // + // Set up the slave address. + // + HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will enable operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will enable operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE; + + // + // Enable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will disable operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE); +} +#endif + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will disable operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module +//! +//! \param ulBase base address of the I2C module +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an I2C interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific I2C +//! interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_I2C, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ulBase base address of the I2C module +//! +//! This function will clear the handler to be called when an I2C +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_I2C); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 1; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 1; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 0; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 0; +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase base address of the I2C Master module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase base address of the I2C Slave module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase base address of the I2C Master module +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Stellaris + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC; +} +#endif + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC; +} +#endif + +//***************************************************************************** +// +//! Sets the address that the I2C Master will place on the bus. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucSlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the parameter \e bReceive is set +//! to \b true, the address will indicate that the I2C Master is initiating +//! a read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, + tBoolean bReceive) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive; +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C bus is +//! busy. This function can be used in a multi-master environment to +//! determine if another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the bus busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! \param ulCmd command to be issued to the I2C Master module +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The parameter \e ucCmd can be one of the following +//! values: +//! +//! - I2C_MASTER_CMD_SINGLE_SEND +//! - I2C_MASTER_CMD_SINGLE_RECEIVE +//! - I2C_MASTER_CMD_BURST_SEND_START +//! - I2C_MASTER_CMD_BURST_SEND_CONT +//! - I2C_MASTER_CMD_BURST_SEND_FINISH +//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - I2C_MASTER_CMD_BURST_RECEIVE_START +//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // + // Send the command. + // + HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd; +} +#endif + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function is used to obtain the error status of the Master module +//! send and receive operations. It returns one of the following values: +//! +//! - I2C_MASTER_ERR_NONE +//! - I2C_MASTER_ERR_ADDR_ACK +//! - I2C_MASTER_ERR_DATA_ACK +//! - I2C_MASTER_ERR_ARB_LOST +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterErr(unsigned long ulBase) +{ + unsigned long ulErr; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Get the raw error state + // + ulErr = HWREG(ulBase + I2C_MASTER_O_CS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ulErr & I2C_MASTER_CS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ulErr & I2C_MASTER_CS_ERROR) + { + return(ulErr & (I2C_MASTER_CS_ERR_MASK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucData data to be transmitted from the I2C Master +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_MASTER_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_MASTER_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function will return the action requested from a master, if any. The +//! possible values returned are: +//! +//! - I2C_SLAVE_ACT_NONE +//! - I2C_SLAVE_ACT_RREQ +//! - I2C_SLAVE_ACT_TREQ +//! +//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the +//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent +//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C +//! master has requested that the I2C Slave module send data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return the slave status. + // + return(HWREG(ulBase + I2C_SLAVE_O_CSR)); +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucData data to be transmitted from the I2C Slave +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_SLAVE_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_SLAVE_O_DR)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h new file mode 100644 index 0000000..bfe8c85 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c new file mode 100644 index 0000000..7224a05 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c @@ -0,0 +1,552 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +#if defined(GROUP_pulpriority) || defined(BUILD_ALL) +const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; +#else +extern const unsigned long g_pulPriority[]; +#endif + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +#if defined(GROUP_pulregs) || defined(BUILD_ALL) +const unsigned long g_pulRegs[12] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7 +}; +#else +extern const unsigned long g_pulRegs[12]; +#endif + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_defaulthandler) || defined(BUILD_ALL) +void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} +#else +extern void IntDefaultHandler(void); +#endif + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +#if defined(GROUP_vtable) || defined(BUILD_ALL) +#ifdef ewarm +__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#else +__attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif +#else +extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + CPUcpsie(); +} +#endif + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + CPUcpsid(); +} +#endif + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise NVIC will not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts; +//! some tool chains, such as the evaluation version of RV-MDK, do not support +//! linker scripts and therefore will not produce a valid executable. See the +//! discussion of compile-time versus run-time interrupt handler registration +//! in the introduction to this chapter. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long ulIdx; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) + { + g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4); + } + + // + // Point NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = pfnHandler; +} +#endif + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntUnregister(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; +} +#endif + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Stellaris family it can range from 0 to 3. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY_BITS); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} +#endif + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < 8; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} +#endif + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. The remaining bits can be +//! used to sub-prioritize the interrupt sources, and may be used by the +//! hardware priority mechanism on a future part. This arrangement allows +//! priorities to migrate to different NVIC implementations without changing +//! the gross prioritization of the interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} +#endif + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} +#endif + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h new file mode 100644 index 0000000..37d414d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.c new file mode 100644 index 0000000..6479049 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.c @@ -0,0 +1,975 @@ +//***************************************************************************** +// +// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1049 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ev_lm3s811_api +//! @{ +// +//***************************************************************************** + +#include "hw_i2c.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "i2c.h" +#include "sysctl.h" +#include "osram96x16.h" + +//***************************************************************************** +// +// The I2C slave address of the SSD0303 controller on the OLED display. +// +//***************************************************************************** +#define SSD0303_ADDR 0x3d + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +//***************************************************************************** +static const unsigned char g_pucFont[95][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the I2C transfer, followed by that many bytes of command data. +// +//***************************************************************************** +static const unsigned char g_pucOSRAMInit[] = +{ + // + // Turn off the panel + // + 0x04, 0x80, 0xae, 0x80, 0xe3, + + // + // Set lower column address + // + 0x04, 0x80, 0x04, 0x80, 0xe3, + + // + // Set higher column address + // + 0x04, 0x80, 0x12, 0x80, 0xe3, + + // + // Set contrast control register + // + 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3, + + // + // Set segment re-map + // + 0x04, 0x80, 0xa1, 0x80, 0xe3, + + // + // Set display start line + // + 0x04, 0x80, 0x40, 0x80, 0xe3, + + // + // Set display offset + // + 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3, + + // + // Set multiplex ratio + // + 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set the display to normal mode + // + 0x04, 0x80, 0xa4, 0x80, 0xe3, + + // + // Non-inverted display + // + 0x04, 0x80, 0xa6, 0x80, 0xe3, + + // + // Set the page address + // + 0x04, 0x80, 0xb0, 0x80, 0xe3, + + // + // Set COM output scan direction + // + 0x04, 0x80, 0xc8, 0x80, 0xe3, + + // + // Set display clock divide ratio/oscillator frequency + // + 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3, + + // + // Enable mono mode + // + 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3, + + // + // Set pre-charge period + // + 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3, + + // + // Set COM pins hardware configuration + // + 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3, + + // + // Set VCOM deslect level + // + 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set DC-DC on + // + 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3, + + // + // Turn on the panel + // + 0x04, 0x80, 0xaf, 0x80, 0xe3, +}; + +//***************************************************************************** +// +// The inter-byte delay required by the SSD0303 OLED controller. +// +//***************************************************************************** +static unsigned long g_ulDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Provide a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! Since the SSD0303 controller needs a delay between bytes written to it over +//! the I2C bus, this function provides a means of generating that delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) +static void +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(gcc) +static void __attribute__((naked)) +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +OSRAMDelay(unsigned long ulCount) +{ + subs r0, #1; + bne OSRAMDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Start a transfer to the SSD0303 controller. +//! +//! \param ucChar is the first byte to be written to the controller. +//! +//! This function will start a transfer to the SSD0303 controller via the I2C +//! bus. +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFirst(unsigned char ucChar) +{ + // + // Set the slave address. + // + I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); + + // + // Write the first byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Start the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a byte to the SSD0303 controller. +//! +//! \param ucChar is the byte to be transmitted to the controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing +//! another byte over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled faashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteByte(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of bytes to the SSD0303 controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing a +//! sequence of bytes over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); + ulCount--; + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Finish a transfer to the SSD0303 controller. +//! +//! \param ucChar is the final byte to be written to the controller. +//! +//! This function will finish a transfer to the SSD0303 controller via the I2C +//! bus. This must only be called after calling OSRAMWriteFirst(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFinal(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the final byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Finish the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); + + // + // Wait until the final byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display. All pixels in the display will be +//! turned off. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMClear(void) +{ + static const unsigned char pucRow1[] = + { + 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + static const unsigned char pucRow2[] = + { + 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + unsigned long ulIdx; + + // + // Move the display cursor to the first column of the first row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow1, sizeof(pucRow1)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); + + // + // Move the display cursor to the first column of the second row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow2, sizeof(pucRow2)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + + // + // Move the display cursor to the requested position on the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte((ulX + 36) & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // See if there is enough space on the display for this entire + // character. + // + if(ulX <= 90) + { + // + // Write the contents of this character to the display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); + + // + // See if this is the last character to display (either because the + // right edge has been reached or because there are no more + // characters). + // + if((ulX == 90) || (pcStr[1] == 0)) + { + // + // Write the final column of the display. + // + OSRAMWriteFinal(0x00); + + // + // The string has been displayed. + // + return; + } + + // + // Write the inter-character padding column. + // + OSRAMWriteByte(0x00); + } + else + { + // + // Write the portion of the character that will fit onto the + // display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); + OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); + + // + // The string has been displayed. + // + return; + } + + // + // Advance to the next character. + // + pcStr++; + + // + // Increment the X coordinate by the six columns that were just + // written. + // + ulX += 6; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in eight row blocks +//! (i.e. only 1 and 2 are valid). +//! +//! This function will display a bitmap graphic on the display. The image to +//! be displayed must be a multiple of eight scan lines high (i.e. one row) and +//! will be drawn at a vertical position that is a multiple of eight scan lines +//! (i.e. scan line zero or scan line eight, corresponding to row zero or row +//! one). +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for the eight scan lines of the column, with the top scan +//! line being in the least significant bit of the byte and the bottom scan +//! line being in the most significant bit of the byte. +//! +//! For example, an image four columns wide and sixteen scan lines tall would +//! be arranged as follows (showing how the eight bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! \endverbatim +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + ASSERT((ulX + ulWidth) <= 96); + ASSERT((ulY + ulHeight) <= 2); + + // + // The first 36 columns of the LCD buffer are not displayed, so increment + // the X coorddinate by 36 to account for the non-displayed frame buffer + // memory. + // + ulX += 36; + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write the starting address within this row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte(ulX & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Write this row of image data. + // + OSRAMWriteArray(pucImage, ulWidth - 1); + OSRAMWriteFinal(pucImage[ulWidth - 1]); + + // + // Advance to the next row of the image. + // + pucImage += ulWidth; + ulY++; + } +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param bFast is a boolean that is \e true if the I2C interface should be +//! run at 400 kbps and \e false if it should be run at 100 kbps. +//! +//! This function initializes the I2C interface to the OLED display and +//! configures the SSD0303 controller on the panel. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMInit(tBoolean bFast) +{ + unsigned long ulIdx; + + // + // Enable the I2C and GPIO port B blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + // + // Configure the I2C SCL and SDA pins for I2C operation. + // + GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); + + // + // Initialize the I2C master. + // + I2CMasterInit(I2C_MASTER_BASE, bFast); + + // + // Compute the inter-byte delay for the SSD0303 controller. This delay is + // dependent upon the I2C bus clock rate; the slower the clock the longer + // the delay required. + // + // The derivation of this formula is based on a measured delay of + // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz + // (referred to as C). To scale this to the delay for a different CPU + // speed (since this is just a CPU-based delay loop) is: + // + // f(CPU) + // C * ---------- + // 50,000,000 + // + // To then scale this to the actual I2C rate (since it won't always be + // precisely 100 kHz): + // + // f(CPU) 100,000 + // C * ---------- * ------- + // 50,000,000 f(I2C) + // + // This equation will give the inter-byte delay required for any + // configuration of the I2C master. But, as arranged it is impossible to + // directly compute in 32-bit arithmetic (without loosing a lot of + // accuracy). So, the equation is simplified. + // + // Since f(I2C) is generated by dividing down from f(CPU), replace it with + // the equivalent (where TPR is the value programmed into the Master Timer + // Period Register of the I2C master, with the 1 added back): + // + // 100,000 + // f(CPU) ------- + // C * ---------- * f(CPU) + // 50,000,000 ------------ + // 2 * 10 * TPR + // + // Inverting the dividend in the last term: + // + // f(CPU) 100,000 * 2 * 10 * TPR + // C * ---------- * ---------------------- + // 50,000,000 f(CPU) + // + // The f(CPU) now cancels out. + // + // 100,000 * 2 * 10 * TPR + // C * ---------------------- + // 50,000,000 + // + // Since there are no clock frequencies left in the equation, this equation + // also works for 400 kHz bus operation as well, since the 100,000 in the + // numerator becomes 400,000 but C is 1/4, which cancel out each other. + // Reducing the constants gives: + // + // TPR TPR TPR + // C * --- = 1700 * --- = 340 * --- = 68 * TPR + // 25 25 5 + // + // Note that the constant C is actually a bit larger than it needs to be in + // order to provide some safety margin. + // + g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1); + + // + // Initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } + + // + // Clear the frame buffer. + // + OSRAMClear(); +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOn(void) +{ + unsigned long ulIdx; + + // + // Re-initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOff(void) +{ + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xae); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0x8a); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h new file mode 100644 index 0000000..0c9cd36 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h @@ -0,0 +1,47 @@ +//***************************************************************************** +// +// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED +// display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM96X16_H__ +#define __OSRAM96X16_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAMClear(void); +extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY); +extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAMInit(tBoolean bFast); +extern void OSRAMDisplayOn(void); +extern void OSRAMDisplayOff(void); + +#endif // __OSRAM96X16_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c new file mode 100644 index 0000000..6697566 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c @@ -0,0 +1,1291 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_pwm.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to configure. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulConfig is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it will count from a value down to zero, +//! and then reset to the preset value. This will produce left-aligned PWM +//! signals (i.e. the rising edge of the two PWM signals produced by the +//! generator will occur at the same time). In count up/down mode, it will +//! count up from zero to the preset value, count back down to zero, and then +//! repeat the process. This will produce center-aligned PWM signals (i.e. the +//! middle of the high/low period of the PWM signals produced by the generator +//! will occur at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their affect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This allows multiple parameters to be modified and take affect +//! simultaneously, instead of one at a time. Additionally, parameters to +//! multiple PWM generators in synchronous mode can be updated simultaneously, +//! allowing them to be treated as if they were a unified generator. In +//! non-synchronous mode, the parameter updates are not delayed until a +//! synchronization event. In either mode, the parameter updates only occur +//! when the counter is at zero to help prevent oddly formed PWM signals during +//! the update (i.e. a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it will continue to +//! count until it reaches zero, at which point it will pause until the +//! processor is restarted. If configured to continue running, it will keep +//! counting as if nothing had happened. +//! +//! The \b ulConfig parameter contains the desired configuration. It is the +//! logical OR of the following: \b PWM_GEN_MODE_DOWN or +//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC +//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and +//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior. +//! +//! \note Changes to the counter mode will affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Change the global configuration of the generator. + // + HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ulConfig); + + // + // Set the individual PWM generator controls. + // + if(ulConfig & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (i.e. center align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_A_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_B_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (i.e. left align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } +} +#endif + +//***************************************************************************** +// +//! Set the period of a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be modified. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulPeriod specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of \b PWM +//! clock ticks between pulses on the generator block \b zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ulPeriod / 2) < 65536); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; + } +} +#endif + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of \b PWM clock +//! ticks between pulses on the generator block \b zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in \b PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Figure out the counter mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ulGen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ulGen + PWM_O_X_LOAD) + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be enabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function allows the \b PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenEnable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be disabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function blocks the \b PWM clock from driving the timer/counter for +//! the specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! \param ulWidth specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of \b PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth) +{ + unsigned long ulGenBase, ulReg; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulWidth /= 2; + } + + // + // Get the period. + // + ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ulWidth < ulReg); + + // + // Compute the compare value. + // + ulReg = ulReg - ulWidth; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; + } + else + { + HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; + } +} +#endif + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! +//! This function gets the currently programmed pulse width for the +//! specified PWM output. If the update of the comparator for the specified +//! output has yet to be completed, the value returned may not be the active +//! pulse width. The value returned is the programmed pulse width, measured +//! in \b PWM clock ticks. +//! +//! \return Returns the width of the pulse in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) +{ + unsigned long ulGenBase, ulReg, ulLoad; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load-compare)*2. Otherwise, set width = load - compare + // + ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); + } + else + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); + } + ulReg = ulLoad - ulReg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulReg = ulReg * 2; + } + + // + // Return the pulse width. + // + return(ulReg); +} +#endif + +//***************************************************************************** +// +//! Enables the PWM dead band output, and sets the dead band delays. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param usRise specifies the width of delay from the rising edge. +//! \param usFall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, +//! where the dead bands are defined as the number of \b PWM clock ticks +//! from the rising or falling edge of the generator's \b OutA signal. +//! Note that this function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + ASSERT(usRise < 4096); + ASSERT(usFall < 4096); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Write the dead band delay values. + // + HWREG(ulGen + PWM_O_X_DBRISE) = usRise; + HWREG(ulGen + PWM_O_X_DBFALL) = usFall; + + // + // Enable the deadband functionality. + // + HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be updated. Must be the +//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Update the PWM timing registers. + // + HWREG(ulBase + PWM_O_CTL) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be +//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base +//! of the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Synchronize the counters in the specified generators by writing to + // the module's synchronization register. + // + HWREG(ulBase + PWM_O_SYNC) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function is used to enable or disable the selected PWM outputs. The +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's ENABLE output control register, and set or clear + // the requested bits. + // + if(bEnable == true) + { + HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function will cause the specified +//! PWM output signals to be inverted, or made active low. If \e bInvert is +//! \b false, the specified output will be passed through as is, or be made +//! active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's INVERT output control register, and set or clear + // the requested bits. + // + if(bInvert == true) + { + HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bFaultKill determines if the signal is killed or passed through +//! during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bFaultKill determines the fault handling characteristics +//! for the selected outputs. If \e bFaultKill is \b true, then the selected +//! outputs will be made inactive. If \e bFaultKill is \b false, then the +//! selected outputs are unaffected by the detected fault. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's FAULT output control register, and set or clear + // the requested bits. + // + if(bFaultKill == true) + { + HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function will also enable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! +//! This function will unregister the interrupt handler for the specified +//! PWM generator block. This function will also disable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Disable the PWMx interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function will also enable the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(INT_PWM_FAULT, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function will remove the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function will also disable the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Disable the PWM fault interrupt. + // + IntDisable(INT_PWM_FAULT); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers enabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be enabled. +//! +//! Unmasks the specified interrupt(s) and trigger(s) by setting the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers disabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be disabled. +//! +//! Masks the specified interrupt(s) and trigger(s) by clearing the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the contents of the interrupt status register, or the +//! contents of the raw interrupt status register, for the specified +//! PWM generator. +// +//***************************************************************************** +#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ulGen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ulGen + PWM_O_X_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulInts specifies the interrupts to be cleared. +//! +//! Clears the specified interrupt(s) by writing a 1 to the specified bits +//! of the interrupt status register for the specified PWM generator. The +//! defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be enabled. Must be a logical +//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or +//! \b PWM_INT_FAULT. +//! +//! Unmasks the specified interrupt(s) by setting the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and enable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; +} +#endif + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be disabled. Must be a +//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, +//! or \b PWM_INT_FAULT. +//! +//! Masks the specified interrupt(s) by clearing the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and disable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); +} +#endif + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! Clears the fault interrupt by writing to the appropriate bit of the +//! interrupt status register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT; +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT. +//! +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ulBase + PWM_O_ISC)); + } + else + { + return(HWREG(ulBase + PWM_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h new file mode 100644 index 0000000..db835ba --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c new file mode 100644 index 0000000..eb982de --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c @@ -0,0 +1,630 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_qei.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the quadrature encoder module. It must be +//! configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulConfig is the configuration for the quadrature encoder. See below +//! for a description of this parameter. +//! \param ulMaxPosition specifies the maximum position value. +//! +//! This will configure the operation of the quadrature encoder. The +//! \e ulConfig parameter provides the configuration of the encoder and is the +//! logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Write the new configuration to the hardware. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ulConfig); + + // + // Set the maximum position. + // + HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current position of the encoder. Depending upon the +//! configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (i.e. if in reset on index +//! mode, if an index pulse has not been encountered, the position counter will +//! not be aligned with the index pulse yet). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIPositionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the current position counter. + // + return(HWREG(ulBase + QEI_O_POS)); +} +#endif + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPosition is the new position for the encoder. +//! +//! This sets the current position of the encoder; the encoder position will +//! then be measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Set the position counter. + // + HWREG(ulBase + QEI_O_POS) = ulPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current direction of rotation. In this case, current +//! means the most recently detected direction of the encoder; it may not be +//! presently moving but this is the direction it last moved before it stopped. +//! +//! \return 1 if moving in the forward direction or -1 if moving in the reverse +//! direction. +// +//***************************************************************************** +#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +QEIDirectionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the direction of rotation. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} +#endif + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the error indicator for the quadrature encoder. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return true if an error has occurred and false otherwise. +// +//***************************************************************************** +#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +QEIErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the error indicator. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the velocity capture in the quadrature +//! encoder module. It must be configured before it is enabled. Velocity +//! capture will not occur if the quadrature encoder is not enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; +} +#endif + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} +#endif + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2, +//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or +//! QEI_VELDIV_128. +//! \param ulPeriod specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This will configure the operation of the velocity capture portion of the +//! quadrature encoder. The position increment signal is predivided as +//! specified by \e ulPreDiv before being accumulated by the velocity capture. +//! The divided signal is accumulated over \e ulPeriod system clock before +//! being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ulPeriod != 0); + + // + // Set the velocity predivider. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ulPreDiv); + + // + // Set the timer period. + // + HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current speed of the encoder. The value returned is the +//! number of pulses detected in the specified time period; this number can be +//! multiplied by the number of time periods per second and divided by the +//! number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return The number of pulses captured in the given time period. +// +//***************************************************************************** +#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIVelocityGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the speed capture value. + // + return(HWREG(ulBase + QEI_O_SPEED)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This sets the handler to be called when a quadrature encoder interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). +//! It is the interrupt handler's responsibility to clear the interrupt source +//! via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_QEI, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function will clear the handler to be called when a quadrature encoder +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_QEI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Enables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Disables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the quadrature encoder module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + QEI_O_ISC)); + } + else + { + return(HWREG(ulBase + QEI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to keep +//! it from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + QEI_O_ISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h new file mode 100644 index 0000000..3eaafae --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c new file mode 100644 index 0000000..095aaab --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c @@ -0,0 +1,609 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_ssi.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "ssi.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulProtocol specifies the data transfer protocol. +//! \param ulMode specifies the mode of operation. +//! \param ulBitRate specifies the clock rate. +//! \param ulDataWidth specifies number of bits transfered per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The parameter \e ulProtocol defines the data frame format. The parameter +//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0, +//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, +//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the +//! following polarity and phase configurations: +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The parameter \e ulMode defines the operating mode of the SSI module. The +//! SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. The parameter +//! \e ulMode can be one of the following values: SSI_MODE_MASTER, +//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD. +//! +//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate +//! must satisfy the following clock ratio criteria: +//! - FSSI >= 2 * bit rate (master mode) +//! - FSSI >= 12 * bit rate (slave modes) +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The parameter \e ulDataWidth defines the width of the data transfers. +//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive. +//! +//! The SSI clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the SSI clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, unsigned long ulDataWidth) +{ + unsigned long ulMaxBitRate; + unsigned long ulRegVal; + unsigned long ulPreDiv; + unsigned long ulSCR; + unsigned long ulSPH_SPO; + unsigned long ulClock; + + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || + (ulProtocol == SSI_FRF_MOTO_MODE_1) || + (ulProtocol == SSI_FRF_MOTO_MODE_2) || + (ulProtocol == SSI_FRF_MOTO_MODE_3) || + (ulProtocol == SSI_FRF_TI) || + (ulProtocol == SSI_FRF_NMW)); + ASSERT((ulMode == SSI_MODE_MASTER) || + (ulMode == SSI_MODE_SLAVE) || + (ulMode == SSI_MODE_SLAVE_OD)); + ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); + + // + // Get the processor clock rate. + // + ulClock = SysCtlClockGet(); + + // + // Validate the clock speed. + // + ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) || + ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12)))); + ASSERT((ulClock / ulBitRate) <= (254 * 256)); + + // + // Set the mode. + // + ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ulBase + SSI_O_CR1) = ulRegVal; + + // + // Set the clock predivider. + // + ulMaxBitRate = ulClock / ulBitRate; + ulPreDiv = 0; + do + { + ulPreDiv += 2; + ulSCR = (ulMaxBitRate / ulPreDiv) - 1; + } + while(ulSCR > 255); + HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; + + // + // Set protocol and clock rate. + // + ulSPH_SPO = ulProtocol << 6; + ulProtocol &= SSI_CR0_FRF_MASK; + ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); + HWREG(ulBase + SSI_O_CR0) = ulRegVal; +} +#endif + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will enable operation of the synchronous serial interface. It must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; +} +#endif + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will disable operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an SSI interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SSI, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_SSI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. The parameter \e ulIntFlags Can be +//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SSI interrupt sources. The parameter +//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, +//! or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the SSI module base address. +//! \param bMasked is false if the raw interrupt status is required and +//! true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the SSI module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SSIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + SSI_O_MIS)); + } + else + { + return(HWREG(ulBase + SSI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SSI interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to +//! keep it from being called again immediately upon exit. +//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO +//! and SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + SSI_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ulBase + SSI_O_DR) = ulData; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. If there is no space in the FIFO, then this +//! function will return a zero. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Check for space to write. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ulBase + SSI_O_DR) = ulData; + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of the specified +//! SSI module, and place that data into the location specified by the +//! \e pulData parameter. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pulData = HWREG(ulBase + SSI_O_DR); +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of +//! the specified SSI module, and place that data into the location specified +//! by the \e ulData parameter. If there is no data in the FIFO, then this +//! function will return a zero. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Check for data to read. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) + { + *pulData = HWREG(ulBase + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h new file mode 100644 index 0000000..045d8cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c new file mode 100644 index 0000000..539d0f7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c @@ -0,0 +1,1889 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_nvic.h" +#include "../hw_sysctl.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that +// contains the peripheral present bit for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_puldcregs) || defined(BUILD_ALL) +const unsigned long g_pulDCRegs[] = +{ + SYSCTL_DC1, + SYSCTL_DC2, + SYSCTL_DC4, + SYSCTL_DC1 +}; +#else +extern const unsigned long g_pulDCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that +// controls the software reset for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL) +const unsigned long g_pulSRCRRegs[] = +{ + SYSCTL_SRCR0, + SYSCTL_SRCR1, + SYSCTL_SRCR2 +}; +#else +extern const unsigned long g_pulSRCRRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that +// controls the run-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL) +const unsigned long g_pulRCGCRegs[] = +{ + SYSCTL_RCGC0, + SYSCTL_RCGC1, + SYSCTL_RCGC2 +}; +#else +extern const unsigned long g_pulRCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that +// controls the sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL) +const unsigned long g_pulSCGCRegs[] = +{ + SYSCTL_SCGC0, + SYSCTL_SCGC1, + SYSCTL_SCGC2 +}; +#else +extern const unsigned long g_pulSCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that +// controls the deep-sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL) +const unsigned long g_pulDCGCRegs[] = +{ + SYSCTL_DCGC0, + SYSCTL_DCGC1, + SYSCTL_DCGC2 +}; +#else +extern const unsigned long g_pulDCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +#if defined(GROUP_pulxtals) || defined(BUILD_ALL) +const unsigned long g_pulXtals[] = +{ + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000 +}; +#else +extern const unsigned long g_pulXtals[]; +#endif + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Stellaris device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlSRAMSizeGet(void) +{ + // + // Compute the size of the SRAM. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100); +} +#endif + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Stellaris device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlFlashSizeGet(void) +{ + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800); +} +#endif + +//***************************************************************************** +// +//! Determines if a pin is present. +//! +//! \param ulPin is the pin in question. +//! +//! Determines if a particular pin is present in the device. The PWM, analog +//! comparators, ADC, and timers have a varying number of pins across members +//! of the Stellaris family; this will determine which are present on this +//! device. +//! +//! The \b ulPin argument must be only one of the following values: +//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, +//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, +//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, +//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, +//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, +//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, +//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, +//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, +//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, +//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ. +//! +//! \return Returns \b true if the specified pin is present and \b false if it +//! is not. +// +//***************************************************************************** +#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPinPresent(unsigned long ulPin) +{ + // + // Check the arguments. + // + ASSERT((ulPin == SYSCTL_PIN_PWM0) || + (ulPin == SYSCTL_PIN_PWM1) || + (ulPin == SYSCTL_PIN_PWM2) || + (ulPin == SYSCTL_PIN_PWM3) || + (ulPin == SYSCTL_PIN_PWM4) || + (ulPin == SYSCTL_PIN_PWM5) || + (ulPin == SYSCTL_PIN_C0MINUS) || + (ulPin == SYSCTL_PIN_C0PLUS) || + (ulPin == SYSCTL_PIN_C0O) || + (ulPin == SYSCTL_PIN_C1MINUS) || + (ulPin == SYSCTL_PIN_C1PLUS) || + (ulPin == SYSCTL_PIN_C1O) || + (ulPin == SYSCTL_PIN_C2MINUS) || + (ulPin == SYSCTL_PIN_C2PLUS) || + (ulPin == SYSCTL_PIN_C2O) || + (ulPin == SYSCTL_PIN_ADC0) || + (ulPin == SYSCTL_PIN_ADC1) || + (ulPin == SYSCTL_PIN_ADC2) || + (ulPin == SYSCTL_PIN_ADC3) || + (ulPin == SYSCTL_PIN_ADC4) || + (ulPin == SYSCTL_PIN_ADC5) || + (ulPin == SYSCTL_PIN_ADC6) || + (ulPin == SYSCTL_PIN_ADC7) || + (ulPin == SYSCTL_PIN_CCP0) || + (ulPin == SYSCTL_PIN_CCP1) || + (ulPin == SYSCTL_PIN_CCP2) || + (ulPin == SYSCTL_PIN_CCP3) || + (ulPin == SYSCTL_PIN_CCP4) || + (ulPin == SYSCTL_PIN_CCP5) || + (ulPin == SYSCTL_PIN_32KHZ)) + + // + // Determine if this pin is present. + // + if(HWREG(SYSCTL_DC3) & ulPin) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! Determines if a particular peripheral is present in the device. Each +//! member of the Stellaris family has a different peripheral set; this will +//! determine which are present on this device. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or +//! \b SYSCTL_PERIPH_PLL. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPeripheralPresent(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_TEMP) || + (ulPeripheral == SYSCTL_PERIPH_PLL)); + + // + // Read the correct DC register and determine if this peripheral exists. + // + if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! deasserted, leaving the peripheral in a operating state but in its reset +//! condition. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ulPeripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ulPeripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. Those that must run at a particular frequency +//! (such as a UART) will not work as expected if the clock changes. It is the +//! responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled they are clocked +//! according to the configuration set by SysCtlPeripheralSleepEnable(), +//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and +//! SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralClockGating(tBoolean bEnable) +{ + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This sets the handler to be called when a system control interrupt occurs. +//! This will enable the global interrupt in the interrupt controller; specific +//! system control interrupts must be enabled via SysCtlIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function will clear the handler to be called when a system control +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Enables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntEnable(unsigned long ulInts) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ulInts; +} +#endif + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Disables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntDisable(unsigned long ulInts) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ulInts); +} +#endif + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntClear(unsigned long ulInts) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the system controller. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, +//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and +//! \b SYSCTL_INT_PLL_FAIL. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Sets the output voltage of the LDO. +//! +//! \param ulVoltage is the required output voltage from the LDO. Must be one +//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +//! +//! This function sets the output voltage of the LDO. The default voltage is +//! 2.5 V; it can be adjusted +/- 10%. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOSet(unsigned long ulVoltage) +{ + // + // Check the arguments. + // + ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || + (ulVoltage == SYSCTL_LDO_2_30V) || + (ulVoltage == SYSCTL_LDO_2_35V) || + (ulVoltage == SYSCTL_LDO_2_40V) || + (ulVoltage == SYSCTL_LDO_2_45V) || + (ulVoltage == SYSCTL_LDO_2_50V) || + (ulVoltage == SYSCTL_LDO_2_55V) || + (ulVoltage == SYSCTL_LDO_2_60V) || + (ulVoltage == SYSCTL_LDO_2_65V) || + (ulVoltage == SYSCTL_LDO_2_70V) || + (ulVoltage == SYSCTL_LDO_2_75V)); + + // + // Set the LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOPCTL) = ulVoltage; +} +#endif + +//***************************************************************************** +// +//! Gets the output voltage of the LDO. +//! +//! This function determines the output voltage of the LDO, as specified by the +//! control register. +//! +//! \return Returns the current voltage of the LDO; will be one of +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +// +//***************************************************************************** +#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlLDOGet(void) +{ + // + // Return the LDO voltage setting. + // + return(HWREG(SYSCTL_LDOPCTL)); +} +#endif + +//***************************************************************************** +// +//! Configures the LDO failure control. +//! +//! \param ulConfig is the required LDO failure control setting; can be either +//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. +//! +//! This function allows the LDO to be configured to cause a processor reset +//! when the output voltage becomes unregulated. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOConfigSet(unsigned long ulConfig) +{ + // + // Check hte arguments. + // + ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || + (ulConfig == SYSCTL_LDOCFG_NORST)); + + // + // Set the reset control as requested. + // + HWREG(SYSCTL_LDOARST) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function will perform a software reset of the entire device. The +//! processor and all peripherals will be reset and all device registers will +//! return to their default values (with the exception of the reset cause +//! register, which will maintain its current value but have the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This will cause the device to reset, + // no further code will be executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} +#endif + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} +#endif + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} +#endif + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return The reason(s) for a reset. +// +//***************************************************************************** +#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} +#endif + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ulCauses are the reset causes to be cleared; must be a logical OR of +//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, +//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlResetCauseClear(unsigned long ulCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ulCauses); +} +#endif + +//***************************************************************************** +// +//! Configures the brown-out control. +//! +//! \param ulConfig is the desired configuration of the brown-out control. +//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or +//! \b SYSCTL_BOR_RESAMPLE. +//! \param ulDelay is the number of internal oscillator cycles to wait before +//! resampling an asserted brown-out signal. This value only has meaning when +//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. +//! +//! This function configures how the brown-out control operates. It can detect +//! a brown-out by looking at only the brown-out output, or it can wait for it +//! to be active for two consecutive samples separated by a configurable time. +//! When it detects a brown-out condition, it can either reset the device or +//! generate a processor interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) +{ + // + // Check the arguments. + // + ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); + ASSERT(ulDelay < 8192); + + // + // Configure the brown-out reset control. + // + HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ulConfig is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \b ulConfig parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, +//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6, +//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9, +//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12, +//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or +//! \b SYSCTL_SYSDIV_16. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ, +//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ, +//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ, +//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device will be prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (i.e. via +//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function will delay until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlClockSet(unsigned long ulConfig) +{ + volatile unsigned long ulDelay; + unsigned long ulRCC; + + // + // Get the current value of the RCC register. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Bypass the PLL and system clock dividers for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Make sure that the PLL and system clock dividers are bypassed for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | + (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); + + // + // Set the new crystal value, oscillator source, and PLL configuration. + // + ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. One of the oscillators may need to be started as well. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Disable the appropriate oscillators. + // + ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Set the requested system divider. This will not get written + // immediately. + // + ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + + // + // See if the PLL output is being used to clock the system. + // + if(!(ulConfig & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ulDelay = 32768; ulDelay > 0; ulDelay--) + { + if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + { + break; + } + } + + // + // Enable use of the PLL. + // + ulRCC &= ~(SYSCTL_RCC_BYPASS); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Delay for a little bit so that the system divider takes effect. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } +} +#endif + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. This is +//! also the clock rate of all the peripheral modules (with the exception of +//! PWM, which has its own clock divider). +//! +//! \note This will not return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the later case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlClockGet(void) +{ + unsigned long ulRCC, ulPLL, ulClk; + + // + // Read RCC. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Get the base clock rate. + // + switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >> + SYSCTL_RCC_XTAL_SHIFT) - + (SYSCTL_RCC_XTAL_3_57MHZ >> + SYSCTL_RCC_XTAL_SHIFT)]; + break; + } + + // + // The internal oscillator is the source clock. This is not an + // accurate clock (it is +/- 50%); what is used is the nominal. + // + case SYSCTL_RCC_OSCSRC_INT: + { + ulClk = 15000000; + break; + } + + // + // The internal oscillator divided by four is the source clock. This + // is not an accurate clock (it is +/- 50%); what is used is the + // nominal. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + ulClk = 15000000 / 4; + break; + } + + // + // An unknown setting, so return a zero clock (i.e. an unknown clock + // rate). + // + default: + { + return(0); + } + } + + // + // See if the PLL is being used. + // + if(!(ulRCC & SYSCTL_RCC_BYPASS)) + { + // + // Get the PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // Compute the PLL output frequency based on its input frequency. + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >> + SYSCTL_PLLCFG_F_SHIFT) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_MASK) >> + SYSCTL_PLLCFG_R_SHIFT) + 2)); + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } + } + + // + // See if the system divider is being used. + // + if(ulRCC & SYSCTL_RCC_USE_SYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >> + SYSCTL_RCC_SYSDIV_SHIFT) + 1; + } + + // + // Return the computed clock rate. + // + return(ulClk); +} +#endif + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ulConfig is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function sets the rate of the clock provided to the PWM module as a +//! ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPWMClockSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_PWMDIV_1) || + (ulConfig == SYSCTL_PWMDIV_2) || + (ulConfig == SYSCTL_PWMDIV_4) || + (ulConfig == SYSCTL_PWMDIV_8) || + (ulConfig == SYSCTL_PWMDIV_16) || + (ulConfig == SYSCTL_PWMDIV_32) || + (ulConfig == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) | + ulConfig); +} +#endif + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return The current PWM clock configuration; will be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +// +//***************************************************************************** +#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Return the current PWM clock configuration. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)); +} +#endif + +//***************************************************************************** +// +//! Sets the sample rate of the ADC. +//! +//! \param ulSpeed is the desired sample rate of the ADC; must be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +//! +//! This function sets the rate at which the ADC samples are captured by the +//! ADC block. The sampling speed may be limited by the hardware, so the +//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() +//! will return the actual speed in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlADCSpeedSet(unsigned long ulSpeed) +{ + // + // Check the arguments. + // + ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || + (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); + + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Set the ADC speed in run, sleep, and deep-sleep mode. + // + HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); +} +#endif + +//***************************************************************************** +// +//! Gets the sample rate of the ADC. +//! +//! This function gets the current sample rate of the ADC. +//! +//! \return Returns the current ADC sample rate; will be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +// +//***************************************************************************** +#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlADCSpeedGet(void) +{ + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Return the current ADC speed. + // + return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK); +} +#endif + +//***************************************************************************** +// +//! Configures the internal oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the internal oscillator +//! verification timer should be enabled. +//! +//! This function allows the internal oscillator verification timer to be +//! enabled or disabled. When enabled, an interrupt will be generated if the +//! internal oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the main oscillator will verify the +//! internal oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlIOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the internal oscillator verification timer as + // requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the main oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the main oscillator +//! verification timer should be enabled. +//! +//! This function allows the main oscillator verification timer to be enabled +//! or disabled. When enabled, an interrupt will be generated if the main +//! oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the internal oscillator will verify the +//! main oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlMOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the main oscillator verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the PLL verification timer. +//! +//! \param bEnable is a boolean that is \b true if the PLL verification timer +//! should be enabled. +//! +//! This function allows the PLL verification timer to be enabled or disabled. +//! When enabled, an interrupt will be generated if the PLL ceases to operate. +//! +//! \note The main oscillator must be enabled for this verification timer to +//! operate as it is used to check the PLL. Also, the verification timer +//! should be disabled while the PLL is being reconfigured via +//! SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPLLVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the PLL verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); + } +} +#endif + +//***************************************************************************** +// +//! Clears the clock verification status. +//! +//! This function clears the status of the clock verification timers, allowing +//! them to assert another failure if detected. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlClkVerificationClear(void) +{ + // + // Clear the clock verification. + // + HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR; + + // + // The bit does not self-reset, so clear it. + // + HWREG(SYSCTL_CLKVCLR) = 0; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h new file mode 100644 index 0000000..ebe01cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h @@ -0,0 +1,285 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c new file mode 100644 index 0000000..3825335 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c @@ -0,0 +1,262 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This sets the handler to be called when a SysTick interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} +#endif + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} +#endif + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h new file mode 100644 index 0000000..bfddfb1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c new file mode 100644 index 0000000..46ce19a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c @@ -0,0 +1,1125 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_timer.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "timer.h" + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will enable operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} +#endif + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will disable operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} +#endif + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured, and is left in the disabled +//! state. The configuration is specified in \e ulConfig as one of the +//! following values: +//! +//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer +//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer +//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer +//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers +//! +//! When configured for a pair of 16-bit timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer +//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer +//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture +//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture +//! - \b TIMER_CFG_A_PWM - 16-bit PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || + (ulConfig == TIMER_CFG_32_BIT_PER) || + (ulConfig == TIMER_CFG_32_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; + HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; +} +#endif + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function sets the PWM output level for the specified timer. If the +//! parameter \e bInvert is \b true, then the timer's output will be made +//! active low; otherwise, it will be made active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enables or disables the trigger output. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired trigger state. +//! +//! This function controls the trigger output for the specified timer. If the +//! parameter \e bEnable is \b true, then the timer's output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the trigger output as requested. + // + ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ulBase + TIMER_O_CTL) = (bEnable ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function sets the signal edge(s) that will trigger the timer when in +//! capture mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK); + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & + ~(TIMER_CTL_TAEVENT_MSK | + TIMER_CTL_TBEVENT_MSK)) | ulEvent); +} +#endif + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! parameter \e bStall is \b true, then the timer will stop counting if the +//! processor enters debug mode; otherwise the timer will keep running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this will do nothing. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} +#endif + +//***************************************************************************** +// +//! Disable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value; must be between 0 and 255, +//! inclusive. +//! +//! This function sets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale match value; must be between 0 and +//! 255, inclusive. +//! +//! This function sets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescale match if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPMR) = ulValue; + } + + // + // Set the timer B prescale match if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPMR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : + HWREG(ulBase + TIMER_O_TBPMR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the load value. +//! +//! This function sets the timer load value; if the timer is running then the +//! value will be immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} +#endif + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : + HWREG(ulBase + TIMER_O_TBR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the match value. +//! +//! This function sets the match value for a timer. This is used in capture +//! count mode to determine when to interrupt the processor and in PWM mode to +//! determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This sets the handler to be called when a timer interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific +//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function will clear the handler to be called when a timer interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags must be the logical OR of any combination of +//! the following: +//! +//! - TIMER_CAPB_EVENT - Capture B event interrupt +//! - TIMER_CAPB_MATCH - Capture B match interrupt +//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - TIMER_RTC_MATCH - RTC interrupt mask +//! - TIMER_CAPA_EVENT - Capture A event interrupt +//! - TIMER_CAPA_MATCH - Capture A match interrupt +//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the timer module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} +#endif + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts the timer into its reset state. +//! +//! \param ulBase is the base address of the timer module. +//! +//! The specified timer is disabled, and all its interrupts are disabled, +//! cleared, and unregistered. Then the timer registers are set to their reset +//! value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerQuiesce(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the timer. + // + HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; + + // + // Disable all the timer interrupts. + // + HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; + + // + // Clear all the timer interrupts. + // + HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; + + // + // Unregister the interrupt handler. This also disables interrupts to the + // core. + // + TimerIntUnregister(ulBase, TIMER_BOTH); + + // + // Set all the registers to their reset value. + // + HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; + HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; + HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; + HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; + HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; + HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; + HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; + HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; + HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; + HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; + HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; + HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; + HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; + HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; + HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h new file mode 100644 index 0000000..660c325 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c new file mode 100644 index 0000000..cbae1b0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c @@ -0,0 +1,821 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_uart.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it will always be either be one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) & + ~(UART_LCR_H_SPS | UART_LCR_H_EPS | + UART_LCR_H_PEN)) | ulParity); +} +#endif + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! \return The current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function will configure the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the +//! data format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig) +{ + unsigned long ulUARTClk, ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Determine the UART clock rate. + // + ulUARTClk = SysCtlClockGet(); + + // + // Compute the fractional baud rate divider. + // + ulInt = ulUARTClk / (16 * ulBaud); + ulFrac = ulUARTClk % (16 * ulBaud); + ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2); + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulInt; + HWREG(ulBase + UART_O_FBRD) = ulFrac; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCR_H) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} +#endif + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined. The returned +//! baud rate is the actual baud rate; it may not be the exact baud rate +//! requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSet(). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be computed incorrectly. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig) + +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac); + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 | + UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO, and \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO, +//! and \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 will be returned if there are no characters present in +//! the receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharNonBlockingGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} +#endif + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function will wait until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as an +//! \e int. +// +//***************************************************************************** +#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application will have to retry the function +//! later. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO, and \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function will +//! wait until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true will assert a +//! break condition on the UART. Calling this function with \e bBreakState set +//! to \b false will remove the break condition. For proper transmission of a +//! break command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCR_H) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) : + (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK))); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags is the logical OR of any of the following: +//! +//! - UART_INT_OE - Overrun Error interrupt +//! - UART_INT_BE - Break Error interrupt +//! - UART_INT_PE - Parity Error interrupt +//! - UART_INT_FE - Framing Error interrupt +//! - UART_INT_RT - Receive Timeout interrupt +//! - UART_INT_TX - Transmit interrupt +//! - UART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h new file mode 100644 index 0000000..b82f2ee --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c new file mode 100644 index 0000000..53332d0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_watchdog.h" +#include "debug.h" +#include "interrupt.h" +#include "watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will check to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will enable the watchdog timer counter and interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Disables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Locks out write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} +#endif + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function sets the value to load into the watchdog timer when the count +//! reaches zero for the first time; if the watchdog timer is running when this +//! function is called, then the value will be immediately loaded into the +//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} +#endif + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; the watchdog +//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function will clear the handler to be called when a watchdog timer +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the watchdog timer interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog interrupt. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the watchdog timer module. Either +//! the raw interrupt status or the status of interrupt that is allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, where a 1 indicates that the watchdog +//! interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} +#endif + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog will instead +//! expired after the appropriate number of processor cycles have been executed +//! while debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} +#endif + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h new file mode 100644 index 0000000..9378504 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/init/startup.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/init/startup.c new file mode 100644 index 0000000..93da079 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/init/startup.c @@ -0,0 +1,222 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1049 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); +extern void vGPIO_ISR( void ); +extern void vPortSVCHandler( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 64 +#endif +static unsigned long pulStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex-M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + vPortSVCHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + vGPIO_ISR, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + vUART_ISR, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler // FLASH Control +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied main() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c new file mode 100644 index 0000000..08ef3da --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c @@ -0,0 +1,398 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ + + + +/* Environment includes. */ +#include "DriverLib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" + +/* Delay between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* UART configuration - note this does not use the FIFO so is not very +efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) + +/* Demo task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Demo board specifics. */ +#define mainPUSH_BUTTON GPIO_PIN_4 + +/* Misc. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) +#define mainNO_DELAY ( ( portTickType ) 0 ) +/* + * Configure the processor and peripherals for this demo. + */ +static void prvSetupHardware( void ); + +/* + * The 'check' task, as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that is woken by the ISR that processes GPIO interrupts originating + * from the push button. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/* + * The task that controls access to the LCD. + */ +static void vPrintTask( void *pvParameter ); + +/* String that is transmitted on the UART. */ +static portCHAR *cMessage = "Task woken by button interrupt! --- "; +static volatile portCHAR *pcNextChar; + +/* The semaphore used to wake the button handler task from within the GPIO +interrupt handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue used to send strings to the print task for display on the LCD. */ +xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); + + /* Create the semaphore used to wake the button handler task from the GPIO + ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap to start the + scheduler. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const portCHAR *pcPassMessage = "PASS"; +const portCHAR *pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. We do not write directly to the LCD, but instead + queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Setup the push button. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); + + + + /* Enable the UART. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We don't want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); + + + /* Initialise the LCD> */ + OSRAMInit( false ); + OSRAMStringDraw("www.FreeRTOS.org", 0, 0); + OSRAMStringDraw("LM3S811 demo", 16, 1); +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +const portCHAR *pcInterruptMessage = "Int"; + + for( ;; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } +} + +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != 0 ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + pcNextChar++; + } + } +} +/*-----------------------------------------------------------*/ + +void vGPIO_ISR( void ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt. */ + GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + + /* Wake the button handler task. */ + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +portCHAR *pcMessage; +unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ;; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/makedefs b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/makedefs new file mode 100644 index 0000000..17d00db --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/makedefs @@ -0,0 +1,208 @@ +#****************************************************************************** +# +# makedefs - Definitions common to all makefiles. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +#****************************************************************************** +# +# Get the operating system name. If this is Cygwin, the .d files will be +# munged to convert c: into /cygdrive/c so that "make" will be happy with the +# auto-generated dependencies. +# +#****************************************************************************** +os:=${shell uname -s} + +#****************************************************************************** +# +# The compiler to be used. +# +#****************************************************************************** +ifndef COMPILER +COMPILER=gcc +endif + +#****************************************************************************** +# +# The debugger to be used. +# +#****************************************************************************** +ifndef DEBUGGER +DEBUGGER=gdb +endif + +#****************************************************************************** +# +# Definitions for using GCC. +# +#****************************************************************************** +ifeq (${COMPILER}, gcc) + +# +# The command for calling the compiler. +# +CC=arm-none-eabi-gcc + +# +# The flags passed to the assembler. +# +AFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -MD + +# +# The flags passed to the compiler. +# +CFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -O2 \ + -MD + +# +# The command for calling the library archiver. +# +AR=arm-none-eabi-ar + +# +# The command for calling the linker. +# +LD=arm-none-eabi-ld + +# +# The flags passed to the linker. +# +LDFLAGS= -Map gcc/out.map + +# +# Get the location of libgcc.a from the GCC front-end. +# +LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} + +# +# Get the location of libc.a from the GCC front-end. +# +LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} + +# +# The command for extracting images from the linked executables. +# +OBJCOPY=arm-none-eabi-objcopy + +endif + +#****************************************************************************** +# +# Tell the compiler to include debugging information if the DEBUG environment +# variable is set. +# +#****************************************************************************** +ifdef DEBUG +CFLAGS += -g +endif + +#****************************************************************************** +# +# The rule for building the object file from each C source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.c + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi + @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} +ifeq (${COMPILER}, rvds) + @mv -f ${notdir ${@:.o=.d}} ${COMPILER} +endif +ifneq ($(findstring CYGWIN, ${os}), ) + @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} +endif + +#****************************************************************************** +# +# The rule for building the object file from each assembly source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.S + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi +ifeq (${COMPILER}, rvds) + @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} + @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} + @rm ${@:.o=_.S} + @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} + @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} + @rm ${notdir ${<:.S=.d}} +endif +ifeq (${COMPILER}, gcc) + @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} +endif +ifneq ($(findstring CYGWIN, ${os}), ) + @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} +endif + +#****************************************************************************** +# +# The rule for creating an object library. +# +#****************************************************************************** +${COMPILER}/%.a: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AR ${@}"; \ + else \ + echo ${AR} -cr ${@} ${^}; \ + fi + @${AR} -cr ${@} ${^} + +#****************************************************************************** +# +# The rule for linking the application. +# +#****************************************************************************** +${COMPILER}/%.axf: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " LD ${@}"; \ + fi +ifeq (${COMPILER}, gcc) + @if [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}'; \ + fi + @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}' + @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} +endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/standalone.ld b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/standalone.ld new file mode 100644 index 0000000..8ee3fe2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_GCC/standalone.ld @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 1049 of the Stellaris Driver Library. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h new file mode 100644 index 0000000..79edf3b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LM3S811.icf b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LM3S811.icf new file mode 100644 index 0000000..5131af0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LM3S811.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// boot_demo1.icf - Linker configuration file for boot_demo1. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0000ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20001fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h new file mode 100644 index 0000000..47531fb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h @@ -0,0 +1,39 @@ +#ifndef DRIVER_LIB_H +#define DRIVER_LIB_H + +#include "DriverLib.h" +#include "hw_adc.h" +#include "hw_comp.h" +#include "hw_flash.h" +#include "hw_gpio.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_pwm.h" +#include "hw_qei.h" +#include "hw_ssi.h" +#include "hw_sysctl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_watchdog.h" +#include "osram96x16.h" +#include "adc.h" +#include "comp.h" +#include "cpu.h" +#include "debug.h" +#include "flash.h" +#include "gpio.h" +#include "i2c.h" +#include "interrupt.h" +#include "pwm.h" +#include "qei.h" +#include "ssi.h" +#include "sysctl.h" +#include "systick.h" +#include "timer.h" +#include "uart.h" +#include "watchdog.h" + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt new file mode 100644 index 0000000..02c57b2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive, +non-transferable right (1) to use the Software, (2) to reproduce the Software, +(3) to prepare derivative works of the Software, (4) to distribute the Software +and derivative works thereof in source (human-readable) form and object +(machine-readable) form, and (5) to sublicense to others the right to use the +distributed Software. If you violate any of the terms or restrictions of this +Agreement, LMI may immediately terminate this Agreement, and require that you +stop using and delete all copies of the Software in your possession or control. + +2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the +Software, and United States copyright laws and international treaty provisions +protect the Software. Therefore, you must treat the Software like any other +copyrighted material (e.g. a book or musical recording). You may not use or +copy the Software for any other purpose than what is described in this +Agreement. Except as expressly provided herein, LMI does not grant to you any +express or implied rights under any LMI or third-party patents, copyrights, +trademarks, or trade secrets. Additionally, you must reproduce and apply any +copyright or other proprietary rights notices included on or embedded in the +Software to any copies or derivative works made thereof, in whole or in part, +if any. + +3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new +releases of the Software. If you wish, you may contact LMI and report problems +and provide suggestions regarding the Software. LMI has no obligation +whatsoever to respond in any way to such a problem report or suggestion. LMI +may make changes to the Software at any time, without any obligation to notify +or provide updated versions of the Software to you. + +4. INDEMNITY. You agree to fully defend and indemnify LMI from any and +all claims, liabilities, and costs (including reasonable attorney's fees) +related to (1) your use (including your sub-licensee's use, if permitted) of +the Software or (2) your violation of the terms and conditions of this +Agreement. + +5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault +tolerant and is not designed, manufactured or intended by LMI for incorporation +into products intended for use or resale in on-line control equipment in +hazardous, dangerous to life or potentially life-threatening environments +requiring fail-safe performance, such as in the operation of nuclear +facilities, aircraft navigation or communication systems, air traffic control, +direct life support machines or weapons systems, in which the failure of +products could lead directly to death, personal injury or severe physical or +environmental damage ("High Risk Activities"). You specifically represent and +warrant that you will not use the Software or any derivative work of the +Software for High Risk Activities. + +6. PRODUCT LABELING. You are not authorized to use any LMI trademarks, +brand names, or logos. + +7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software +in accordance with all applicable U.S. laws, regulations and statutes. You +agree that neither you nor your licensees (if any) intend to or will, directly +or indirectly, export or transmit the Software to any country in violation of +U.S. export restrictions. + +8. GOVERNMENT USE. Use of the Software and any corresponding +documentation, if any, is provided with RESTRICTED RIGHTS. Use, duplication or +disclosure by the Government is subject to restrictions as set forth in +subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software +clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial +Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. +Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100, +Austin, Texas 78746. + +9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI +EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED +"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, +WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING +OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING +THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A +WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK +DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF +THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES. + +10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN +CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, +CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR +ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, +SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. + +11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and +laws of the United States and the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and you agree that any litigation will be subject to +the exclusive jurisdiction of the state or federal courts in Austin, Travis +County, Texas, USA. You agree that regardless of any statute or law to the +contrary, any claim or cause of action arising out of or related to this +Agreement or the Software must be filed within one (1) year after such claim or +cause of action arose or be forever barred. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and LMI regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c new file mode 100644 index 0000000..53f3adf --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c @@ -0,0 +1,946 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include "../hw_adc.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "adc.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL) +unsigned char g_pucOversampleFactor[3]; +#else +extern unsigned char g_pucOversampleFactor[3]; +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This will enable the global interrupt in the interrupt +//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It +//! is the interrupt handler's responsibility to clear the interrupt source via +//! ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This will disable the +//! global interrupt in the interrupt controller; the sequence interrupt must +//! be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified sample sequence. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); + } + else + { + return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); + } +} +#endif + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence should be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulTrigger is the trigger source that initiates the sample sequence; +//! must be one of the \b ADC_TRIGGER_* values. +//! \param ulPriority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequences range from zero to three; sequence zero will capture +//! up to eight samples, sequences one and two will capture up to four samples, +//! and sequence three will capture a single sample. The trigger condition and +//! priority (with respect to other sample sequence execution) is set. +//! +//! The parameter \b ulTrigger can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! Note that not all trigger sources are available on all Stellaris family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents +//! the highest priority and 3 the lowest. Note that when programming the +//! priority among a set of sample sequences, each must have unique priority; +//! it is up to the caller to guarantee the uniqueness of the priorities. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulTrigger, unsigned long ulPriority) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || + (ulTrigger == ADC_TRIGGER_COMP0) || + (ulTrigger == ADC_TRIGGER_COMP1) || + (ulTrigger == ADC_TRIGGER_COMP2) || + (ulTrigger == ADC_TRIGGER_EXTERNAL) || + (ulTrigger == ADC_TRIGGER_TIMER) || + (ulTrigger == ADC_TRIGGER_PWM0) || + (ulTrigger == ADC_TRIGGER_PWM1) || + (ulTrigger == ADC_TRIGGER_PWM2) || + (ulTrigger == ADC_TRIGGER_ALWAYS)); + ASSERT(ulPriority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ulSequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & + ~(0xf << ulSequenceNum)) | + ((ulTrigger & 0xf) << ulSequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & + ~(0xf << ulSequenceNum)) | + ((ulPriority & 0x3) << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step; must be a logical OR of +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). +//! +//! This function will set the configuration of the ADC for one step of a +//! sample sequence. The ADC can be configured for single-ended or +//! differential operation (the \b ADC_CTL_D bit selects differential +//! operation when set), the channel to be sampled can be chosen (the +//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature +//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step +//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it +//! can be configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the +//! appropriate time when the trigger for this sequence occurs. +//! +//! The \b ulStep parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequence, from zero to three for the second and +//! third sample sequence, and can only be zero for the fourth sample sequence. +//! +//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1). +//! The channel select must be the number of the channel pair to sample (e.g. +//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined +//! results will be returned by the ADC. Additionally, if differential mode is +//! selected when the temperature sensor is being sampled, undefined results +//! will be returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulStep, unsigned long ulConfig) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || + ((ulSequenceNum == 1) && (ulStep < 4)) || + ((ulSequenceNum == 2) && (ulStep < 4)) || + ((ulSequenceNum == 3) && (ulStep < 1))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence overflow has occurred. This will +//! happen if the captured samples are not read from the FIFO before the next +//! trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence underflow has occurred. This will +//! happen if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer. The number of samples available in the hardware +//! FIFO are copied into the buffer, which is assumed to be large enough to +//! hold that many samples. This will only return the samples that are +//! presently available, which may not be the entire sample sequence if it is +//! in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer) +{ + unsigned long ulCount; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ulCount = 0; + while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) && + (ulCount < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO); + + // + // Increment the count of samples read. + // + ulCount++; + } + + // + // Return the number of samples read. + // + return(ulCount); +} +#endif + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (i.e. the fourth sample sequencer is not supported). +//! Oversampling by 2x (for example) divides the depth of the sample sequencer +//! by two; so 2x oversampling on the first sample sequencer can only provide +//! four samples per trigger. This also means that 8x oversampling is only +//! available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && + ((ulSequenceNum == 0) || (ulFactor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Save the sfiht factor. + // + g_pucOversampleFactor[ulSequenceNum] = ulValue; +} +#endif + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; + ulSequenceNum; ulSequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + if(ulSequenceNum != 1) + { + HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 | + ADC_SSCTL_END0) << ulStep); + } + + // + // Go to the next hardware step. + // + ulStep += 4; + } +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! \param ulCount is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items +//! then incorrect results will be returned. It is the caller's responsibility +//! to read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer, unsigned long ulCount) +{ + unsigned long ulIdx, ulAccum; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ulCount--) + { + // + // Compute the sum of the samples. + // + ulAccum = 0; + for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; + } +} +#endif + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero will disable the hardware +//! oversampler. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 KSps ADC to 62.5 KSps. +//! +//! \note Hardware oversampling is available beginning with Rev C0 of the +//! Stellaris microcontroller. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || + (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || + (ulFactor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ulBase + ADC_O_SAC) = ulValue; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h new file mode 100644 index 0000000..c1fa37d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h @@ -0,0 +1,126 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c new file mode 100644 index 0000000..aed156e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c @@ -0,0 +1,448 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include "../hw_comp.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "comp.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function will configure a comparator. The \e ulConfig parameter is +//! the result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device +//! pin. +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Configure this comparator. + // + HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulRef is the desired reference voltage. +//! +//! This function will set the internal reference voltage value. The voltage +//! is specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ulBase + COMP_O_REFCTL) = ulRef; +} +#endif + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This sets the handler to be called when the comparator interrupt occurs. +//! This will enable the interrupt in the interrupt controller; it is the +//! interrupt-handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0 + ulComp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0 + ulComp); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function will clear the handler to be called when a comparator +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0 + ulComp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0 + ulComp); +} +#endif + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the comparator. Either the raw or +//! the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false); + } + else + { + return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! must be done in the interrupt handler to keep it from being called again +//! immediately upon exit. Note that for a level triggered interrupt, the +//! interrupt cannot be cleared until it stops asserting. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Clear the interrupt. + // + HWREG(ulBase + COMP_O_MIS) = 1 << ulComp; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h new file mode 100644 index 0000000..9349982 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h new file mode 100644 index 0000000..688c522 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h new file mode 100644 index 0000000..e46e2a7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 new file mode 100644 index 0000000..0d2184f Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c new file mode 100644 index 0000000..ab7335f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c @@ -0,0 +1,668 @@ +//***************************************************************************** +// +// flash.c - Driver for programming the on-chip flash. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "../hw_flash.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_sysctl.h" +#include "../hw_types.h" +#include "debug.h" +#include "flash.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Gets the number of processor clocks per micro-second. +//! +//! This function returns the number of clocks per micro-second, as presently +//! known by the flash controller. +//! +//! \return Returns the number of processor clocks per micro-second. +// +//***************************************************************************** +#if defined(GROUP_usecget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +FlashUsecGet(void) +{ + // + // Return the number of clocks per micro-second. + // + return(HWREG(FLASH_USECRL) + 1); +} +#endif + +//***************************************************************************** +// +//! Sets the number of processor clocks per micro-second. +//! +//! \param ulClocks is the number of processor clocks per micro-second. +//! +//! This function is used to tell the flash controller the number of processor +//! clocks per micro-second. This value must be programmed correctly or the +//! flash most likely will not program correctly; it has no affect on reading +//! flash. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_usecset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashUsecSet(unsigned long ulClocks) +{ + // + // Set the number of clocks per micro-second. + // + HWREG(FLASH_USECRL) = ulClocks - 1; +} +#endif + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 1 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +#if defined(GROUP_erase) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashErase(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); + + // + // Clear the flash access interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; + + // + // Erase the block. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) + { + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) + { + return(-1); + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will program a sequence of words into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a word can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +#if defined(GROUP_program) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; + + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Program the next word. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMD) = *pulData; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE) + { + } + + // + // Increment to the next word. + // + pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) + { + return(-1); + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be queried. +//! +//! This function will get the current protection for the specified 2 kB block +//! of flash. Each block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +#if defined(GROUP_protectget) || defined(BUILD_ALL) || defined(DOXYGEN) +tFlashProtection +FlashProtectGet(unsigned long ulAddress) +{ + unsigned long ulFMPRE, ulFMPPE; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + + // + // Read the flash protection register and get the bits that apply to the + // specified block. + // + ulFMPRE = HWREG(FLASH_FMPRE); + ulFMPPE = HWREG(FLASH_FMPPE); + switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (i.e. it can not be erased or + // programmed, and the only reads allowed are via the instruction fecth + // interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (i.e. it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} +#endif + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function will set the protection for the specified 2 kB block of +//! flash. Blocks which are read/write can be made read-only or execute-only. +//! Blocks which are read-only can be made execute-only. Blocks which are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (i.e. read-only to read/write) will result +//! in a failure (and be prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This allows the application to be executed in the desired flash protection +//! environment to check for inappropriate flash access (via the flash +//! interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) +{ + unsigned long ulProtectRE, ulProtectPE; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ulAddress /= FLASH_PROTECT_SIZE; + + // + // Get the current protection. + // + ulProtectRE = HWREG(FLASH_FMPRE); + ulProtectPE = HWREG(FLASH_FMPPE); + + // + // Set the protection based on the requested proection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) + { + return(-1); + } + + // + // Make this block read only. + // + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) || + (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // Set the new protection. + // + HWREG(FLASH_FMPRE) = ulProtectRE; + HWREG(FLASH_FMPPE) = ulProtectPE; + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function will make the currently programmed flash protection settings +//! permanent. This is a non-reversible operation; a chip reset or power cycle +//! will not change the flash protection. +//! +//! This function will not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSave(void) +{ + // + // Tell the flash controller to write the flash read protection register. + // + HWREG(FLASH_FMA) = 0; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the flash program protection + // register. + // + HWREG(FLASH_FMA) = 1; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS. +// +//***************************************************************************** +#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +FlashIntGetStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS +//! values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h new file mode 100644 index 0000000..9c41dda --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c new file mode 100644 index 0000000..a49602e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c @@ -0,0 +1,1103 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "../hw_gpio.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Get GPIO interrupt number. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +#if defined(GROUP_getintnumber) || defined(BUILD_ALL) +long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIO_PORTA_BASE: + { + ulInt = INT_GPIOA; + break; + } + + case GPIO_PORTB_BASE: + { + ulInt = INT_GPIOB; + break; + } + + case GPIO_PORTC_BASE: + { + ulInt = INT_GPIOC; + break; + } + + case GPIO_PORTD_BASE: + { + ulInt = INT_GPIOD; + break; + } + + case GPIO_PORTE_BASE: + { + ulInt = INT_GPIOE; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} +#else +extern long GPIOGetIntNumber(unsigned long ulPort); +#endif + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pins of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulPinIO pin direction and/or mode +//! +//! This function will set the specified pins on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output, and +//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under +//! hardware control. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || + (ulPinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? + (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AFSEL) & + ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the direction and mode of a specified pin of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir, ulAFSEL; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_DIR); + ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); + return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulIntType specifies the type of interrupt trigger mechanism +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pins on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! where the different values describe the interrupt detection mechanism +//! (edge or level) and the particular triggering event (falling, rising, +//! or both edges for edge detect, low or high for level detect). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || + (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || + (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt type for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_IBE); + ulIS = HWREG(ulPort + GPIO_O_IS); + ulIEV = HWREG(ulPort + GPIO_O_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins bit-packed representation of the specified pins. +//! \param ulStrength specifies the output drive strength. +//! \param ulPinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pins +//! on the selected GPIO port. For pins configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ulStrength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! The parameter \e ulPinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_OD_WPU +//! - \b GPIO_PIN_TYPE_OD_WPD +//! - \b GPIO_PIN_TYPE_ANALOG +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an +//! analog input (for the comparators). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, unsigned long ulPinType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulStrength == GPIO_STRENGTH_2MA) || + (ulStrength == GPIO_STRENGTH_4MA) || + (ulStrength == GPIO_STRENGTH_8MA) || + (ulStrength == GPIO_STRENGTH_8MA_SC)); + ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || + (ulPinType == GPIO_PIN_TYPE_STD_WPU) || + (ulPinType == GPIO_PIN_TYPE_STD_WPD) || + (ulPinType == GPIO_PIN_TYPE_OD) || + (ulPinType == GPIO_PIN_TYPE_OD_WPU) || + (ulPinType == GPIO_PIN_TYPE_OD_WPD) || + (ulPinType == GPIO_PIN_TYPE_ANALOG)) + + // + // Set the output drive strength. + // + HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? + (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? + (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? + (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? + (HWREG(ulPort + GPIO_O_SLR) | ucPins) : + (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); + + // + // Set the pin type. + // + HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? + (HWREG(ulPort + GPIO_O_ODR) | ucPins) : + (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? + (HWREG(ulPort + GPIO_O_PUR) | ucPins) : + (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? + (HWREG(ulPort + GPIO_O_PDR) | ucPins) : + (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? + (HWREG(ulPort + GPIO_O_DEN) | ucPins) : + (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the pad configuration for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! \param pulStrength pointer to storage for the output drive strength +//! \param pulPinType pointer to storage for the output drive type +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e eStrength and \e eOutType +//! correspond to the values used in GPIOPadConfigSet(). This function also +//! works for pins configured as input pins; however, the only meaningful +//! data returned is whether the pin is terminated with a pull-up or +//! down resistor. +//! +//! \return None +// +//***************************************************************************** +#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, unsigned long *pulPinType) +{ + unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = (1 << ucPin); + + // + // Get the drive strength for this pin. + // + ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); + ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); + ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); + ulTemp4 = HWREG(ulPort + GPIO_O_SLR); + *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); + + // + // Get the pin type. + // + ulTemp1 = HWREG(ulPort + GPIO_O_ODR); + ulTemp2 = HWREG(ulPort + GPIO_O_PUR); + ulTemp3 = HWREG(ulPort + GPIO_O_PDR); + ulTemp4 = HWREG(ulPort + GPIO_O_DEN); + *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Unmasks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) |= ucPins; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Masks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for all the pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param bMasked specifies whether masked or raw interrupt +//! status is returned +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns a bit-packed byte, where each bit that is set identifies +//! an active masked or raw interrupt, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits +//! 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the interrupt for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Clears the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_ICR) = ucPins; +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param pfIntHandler pointer to the GPIO port interrupt handling function +//! +//! This function will ensure that the interrupt handler specified by \e +//! pfIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO +//! interrupt in the interrupt controller; individual pin interrupts and +//! interrupt sources must be enabled with GPIOPinIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOPinIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} +#endif + +//***************************************************************************** +// +//! Reads the values present at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The values at the specified pins are read, as specified by \e ucPins. +//! Values are returned for both input and output pins, and the value +//! for pins that are not specified by \e ucPins are set to 0. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); +} +#endif + +//***************************************************************************** +// +//! Writes a value at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ucVal value to write to the specified pins +//! +//! Writes the corresponding bit values to the output pins specified +//! by \e ucPins. Writing to a pin configured as an input pin has no +//! effect. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an analog comparator input; +//! it only configures an analog comparator pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2C peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an I2C pin; it only +//! configures an I2C pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, not using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a timer pin; it only +//! configures a timer pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a UART pin; it only +//! configures a UART pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h new file mode 100644 index 0000000..88d6572 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h new file mode 100644 index 0000000..022b9e9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h @@ -0,0 +1,343 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h new file mode 100644 index 0000000..991b7a0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h new file mode 100644 index 0000000..53128b4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h new file mode 100644 index 0000000..bf25d3f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h new file mode 100644 index 0000000..2c9f46d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h new file mode 100644 index 0000000..2204a2c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h new file mode 100644 index 0000000..2b11f35 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h new file mode 100644 index 0000000..6598ef8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h new file mode 100644 index 0000000..cc42015 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h new file mode 100644 index 0000000..864459f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h new file mode 100644 index 0000000..e4650af --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h new file mode 100644 index 0000000..4f6b55e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h @@ -0,0 +1,409 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h new file mode 100644 index 0000000..210c340 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h new file mode 100644 index 0000000..ec05e54 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h new file mode 100644 index 0000000..6f421b6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h new file mode 100644 index 0000000..2b013ad --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c new file mode 100644 index 0000000..b460ad6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c @@ -0,0 +1,972 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include "../hw_i2c.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "i2c.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! \param bFast set up for fast data transfers +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have +//! set the bus speed for the master, and will have enabled the I2C Master +//! block. +//! +//! If the parameter \e bFast is \b true, then the master block will be +//! set up to transfer data at 400 kbps; otherwise, it will be set up to +//! transfer data at 100 kbps. +//! +//! The I2C clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the I2C clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterInit(unsigned long ulBase, tBoolean bFast) +{ + unsigned long ulSysClk; + unsigned long ulSCLFreq; + unsigned long ulTPR; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ulBase); + + // + // Get the system clock speed. + // + ulSysClk = SysCtlClockGet(); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ulSCLFreq = I2C_SCL_FAST; + } + else + { + ulSCLFreq = I2C_SCL_STANDARD; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biases to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) / + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1); + HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR; +} +#endif + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have +//! set the slave address and have enabled the I2C Slave block. +//! +//! The parameter \e ucSlaveAddr is the value that will be compared +//! against the slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ulBase); + + // + // Set up the slave address. + // + HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will enable operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will enable operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE; + + // + // Enable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will disable operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE); +} +#endif + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will disable operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module +//! +//! \param ulBase base address of the I2C module +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an I2C interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific I2C +//! interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_I2C, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ulBase base address of the I2C module +//! +//! This function will clear the handler to be called when an I2C +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_I2C); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 1; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 1; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 0; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 0; +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase base address of the I2C Master module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase base address of the I2C Slave module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase base address of the I2C Master module +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Stellaris + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC; +} +#endif + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC; +} +#endif + +//***************************************************************************** +// +//! Sets the address that the I2C Master will place on the bus. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucSlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the parameter \e bReceive is set +//! to \b true, the address will indicate that the I2C Master is initiating +//! a read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, + tBoolean bReceive) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive; +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C bus is +//! busy. This function can be used in a multi-master environment to +//! determine if another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the bus busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! \param ulCmd command to be issued to the I2C Master module +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The parameter \e ucCmd can be one of the following +//! values: +//! +//! - I2C_MASTER_CMD_SINGLE_SEND +//! - I2C_MASTER_CMD_SINGLE_RECEIVE +//! - I2C_MASTER_CMD_BURST_SEND_START +//! - I2C_MASTER_CMD_BURST_SEND_CONT +//! - I2C_MASTER_CMD_BURST_SEND_FINISH +//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - I2C_MASTER_CMD_BURST_RECEIVE_START +//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // + // Send the command. + // + HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd; +} +#endif + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function is used to obtain the error status of the Master module +//! send and receive operations. It returns one of the following values: +//! +//! - I2C_MASTER_ERR_NONE +//! - I2C_MASTER_ERR_ADDR_ACK +//! - I2C_MASTER_ERR_DATA_ACK +//! - I2C_MASTER_ERR_ARB_LOST +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterErr(unsigned long ulBase) +{ + unsigned long ulErr; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Get the raw error state + // + ulErr = HWREG(ulBase + I2C_MASTER_O_CS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ulErr & I2C_MASTER_CS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ulErr & I2C_MASTER_CS_ERROR) + { + return(ulErr & (I2C_MASTER_CS_ERR_MASK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucData data to be transmitted from the I2C Master +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_MASTER_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_MASTER_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function will return the action requested from a master, if any. The +//! possible values returned are: +//! +//! - I2C_SLAVE_ACT_NONE +//! - I2C_SLAVE_ACT_RREQ +//! - I2C_SLAVE_ACT_TREQ +//! +//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the +//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent +//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C +//! master has requested that the I2C Slave module send data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return the slave status. + // + return(HWREG(ulBase + I2C_SLAVE_O_CSR)); +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucData data to be transmitted from the I2C Slave +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_SLAVE_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_SLAVE_O_DR)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h new file mode 100644 index 0000000..a9b4ad9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c new file mode 100644 index 0000000..7224a05 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c @@ -0,0 +1,552 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +#if defined(GROUP_pulpriority) || defined(BUILD_ALL) +const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; +#else +extern const unsigned long g_pulPriority[]; +#endif + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +#if defined(GROUP_pulregs) || defined(BUILD_ALL) +const unsigned long g_pulRegs[12] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7 +}; +#else +extern const unsigned long g_pulRegs[12]; +#endif + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_defaulthandler) || defined(BUILD_ALL) +void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} +#else +extern void IntDefaultHandler(void); +#endif + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +#if defined(GROUP_vtable) || defined(BUILD_ALL) +#ifdef ewarm +__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#else +__attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif +#else +extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + CPUcpsie(); +} +#endif + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + CPUcpsid(); +} +#endif + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise NVIC will not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts; +//! some tool chains, such as the evaluation version of RV-MDK, do not support +//! linker scripts and therefore will not produce a valid executable. See the +//! discussion of compile-time versus run-time interrupt handler registration +//! in the introduction to this chapter. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long ulIdx; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) + { + g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4); + } + + // + // Point NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = pfnHandler; +} +#endif + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntUnregister(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; +} +#endif + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Stellaris family it can range from 0 to 3. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY_BITS); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} +#endif + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < 8; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} +#endif + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. The remaining bits can be +//! used to sub-prioritize the interrupt sources, and may be used by the +//! hardware priority mechanism on a future part. This arrangement allows +//! priorities to migrate to different NVIC implementations without changing +//! the gross prioritization of the interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} +#endif + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} +#endif + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h new file mode 100644 index 0000000..37d414d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c new file mode 100644 index 0000000..1af1b6c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c @@ -0,0 +1,968 @@ +//***************************************************************************** +// +// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ev_lm3s811_api +//! @{ +// +//***************************************************************************** + +#include "DriverLib.h" +#include "osram96x16.h" +#define ewarm +//***************************************************************************** +// +// The I2C slave address of the SSD0303 controller on the OLED display. +// +//***************************************************************************** +#define SSD0303_ADDR 0x3d + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +//***************************************************************************** +static const unsigned char g_pucFont[95][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the I2C transfer, followed by that many bytes of command data. +// +//***************************************************************************** +static const unsigned char g_pucOSRAMInit[] = +{ + // + // Turn off the panel + // + 0x04, 0x80, 0xae, 0x80, 0xe3, + + // + // Set lower column address + // + 0x04, 0x80, 0x04, 0x80, 0xe3, + + // + // Set higher column address + // + 0x04, 0x80, 0x12, 0x80, 0xe3, + + // + // Set contrast control register + // + 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3, + + // + // Set segment re-map + // + 0x04, 0x80, 0xa1, 0x80, 0xe3, + + // + // Set display start line + // + 0x04, 0x80, 0x40, 0x80, 0xe3, + + // + // Set display offset + // + 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3, + + // + // Set multiplex ratio + // + 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set the display to normal mode + // + 0x04, 0x80, 0xa4, 0x80, 0xe3, + + // + // Non-inverted display + // + 0x04, 0x80, 0xa6, 0x80, 0xe3, + + // + // Set the page address + // + 0x04, 0x80, 0xb0, 0x80, 0xe3, + + // + // Set COM output scan direction + // + 0x04, 0x80, 0xc8, 0x80, 0xe3, + + // + // Set display clock divide ratio/oscillator frequency + // + 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3, + + // + // Enable mono mode + // + 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3, + + // + // Set pre-charge period + // + 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3, + + // + // Set COM pins hardware configuration + // + 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3, + + // + // Set VCOM deslect level + // + 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set DC-DC on + // + 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3, + + // + // Turn on the panel + // + 0x04, 0x80, 0xaf, 0x80, 0xe3, +}; + +//***************************************************************************** +// +// The inter-byte delay required by the SSD0303 OLED controller. +// +//***************************************************************************** +static unsigned long g_ulDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Provide a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! Since the SSD0303 controller needs a delay between bytes written to it over +//! the I2C bus, this function provides a means of generating that delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) +static void +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne.n OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(gcc) +static void __attribute__((naked)) +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +OSRAMDelay(unsigned long ulCount) +{ + subs r0, #1; + bne OSRAMDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Start a transfer to the SSD0303 controller. +//! +//! \param ucChar is the first byte to be written to the controller. +//! +//! This function will start a transfer to the SSD0303 controller via the I2C +//! bus. +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFirst(unsigned char ucChar) +{ + // + // Set the slave address. + // + I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); + + // + // Write the first byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Start the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a byte to the SSD0303 controller. +//! +//! \param ucChar is the byte to be transmitted to the controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing +//! another byte over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled faashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteByte(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of bytes to the SSD0303 controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing a +//! sequence of bytes over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); + ulCount--; + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Finish a transfer to the SSD0303 controller. +//! +//! \param ucChar is the final byte to be written to the controller. +//! +//! This function will finish a transfer to the SSD0303 controller via the I2C +//! bus. This must only be called after calling OSRAMWriteFirst(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFinal(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the final byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Finish the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); + + // + // Wait until the final byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display. All pixels in the display will be +//! turned off. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMClear(void) +{ + static const unsigned char pucRow1[] = + { + 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + static const unsigned char pucRow2[] = + { + 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + unsigned long ulIdx; + + // + // Move the display cursor to the first column of the first row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow1, sizeof(pucRow1)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); + + // + // Move the display cursor to the first column of the second row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow2, sizeof(pucRow2)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + + // + // Move the display cursor to the requested position on the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte((ulX + 36) & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // See if there is enough space on the display for this entire + // character. + // + if(ulX <= 90) + { + // + // Write the contents of this character to the display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); + + // + // See if this is the last character to display (either because the + // right edge has been reached or because there are no more + // characters). + // + if((ulX == 90) || (pcStr[1] == 0)) + { + // + // Write the final column of the display. + // + OSRAMWriteFinal(0x00); + + // + // The string has been displayed. + // + return; + } + + // + // Write the inter-character padding column. + // + OSRAMWriteByte(0x00); + } + else + { + // + // Write the portion of the character that will fit onto the + // display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); + OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); + + // + // The string has been displayed. + // + return; + } + + // + // Advance to the next character. + // + pcStr++; + + // + // Increment the X coordinate by the six columns that were just + // written. + // + ulX += 6; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in eight row blocks +//! (i.e. only 1 and 2 are valid). +//! +//! This function will display a bitmap graphic on the display. The image to +//! be displayed must be a multiple of eight scan lines high (i.e. one row) and +//! will be drawn at a vertical position that is a multiple of eight scan lines +//! (i.e. scan line zero or scan line eight, corresponding to row zero or row +//! one). +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for the eight scan lines of the column, with the top scan +//! line being in the least significant bit of the byte and the bottom scan +//! line being in the most significant bit of the byte. +//! +//! For example, an image four columns wide and sixteen scan lines tall would +//! be arranged as follows (showing how the eight bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! \endverbatim +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + ASSERT((ulX + ulWidth) <= 96); + ASSERT((ulY + ulHeight) <= 2); + + // + // The first 36 columns of the LCD buffer are not displayed, so increment + // the X coorddinate by 36 to account for the non-displayed frame buffer + // memory. + // + ulX += 36; + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write the starting address within this row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte(ulX & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Write this row of image data. + // + OSRAMWriteArray(pucImage, ulWidth - 1); + OSRAMWriteFinal(pucImage[ulWidth - 1]); + + // + // Advance to the next row of the image. + // + pucImage += ulWidth; + ulY++; + } +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param bFast is a boolean that is \e true if the I2C interface should be +//! run at 400 kbps and \e false if it should be run at 100 kbps. +//! +//! This function initializes the I2C interface to the OLED display and +//! configures the SSD0303 controller on the panel. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMInit(tBoolean bFast) +{ + unsigned long ulIdx; + + // + // Enable the I2C and GPIO port B blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + // + // Configure the I2C SCL and SDA pins for I2C operation. + // + GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); + + // + // Initialize the I2C master. + // + I2CMasterInitExpClk(I2C_MASTER_BASE, SysCtlClockGet(), bFast); + + // + // Compute the inter-byte delay for the SSD0303 controller. This delay is + // dependent upon the I2C bus clock rate; the slower the clock the longer + // the delay required. + // + // The derivation of this formula is based on a measured delay of + // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz + // (referred to as C). To scale this to the delay for a different CPU + // speed (since this is just a CPU-based delay loop) is: + // + // f(CPU) + // C * ---------- + // 50,000,000 + // + // To then scale this to the actual I2C rate (since it won't always be + // precisely 100 kHz): + // + // f(CPU) 100,000 + // C * ---------- * ------- + // 50,000,000 f(I2C) + // + // This equation will give the inter-byte delay required for any + // configuration of the I2C master. But, as arranged it is impossible to + // directly compute in 32-bit arithmetic (without loosing a lot of + // accuracy). So, the equation is simplified. + // + // Since f(I2C) is generated by dividing down from f(CPU), replace it with + // the equivalent (where TPR is the value programmed into the Master Timer + // Period Register of the I2C master, with the 1 added back): + // + // 100,000 + // f(CPU) ------- + // C * ---------- * f(CPU) + // 50,000,000 ------------ + // 2 * 10 * TPR + // + // Inverting the dividend in the last term: + // + // f(CPU) 100,000 * 2 * 10 * TPR + // C * ---------- * ---------------------- + // 50,000,000 f(CPU) + // + // The f(CPU) now cancels out. + // + // 100,000 * 2 * 10 * TPR + // C * ---------------------- + // 50,000,000 + // + // Since there are no clock frequencies left in the equation, this equation + // also works for 400 kHz bus operation as well, since the 100,000 in the + // numerator becomes 400,000 but C is 1/4, which cancel out each other. + // Reducing the constants gives: + // + // TPR TPR TPR + // C * --- = 1700 * --- = 340 * --- = 68 * TPR + // 25 25 5 + // + // Note that the constant C is actually a bit larger than it needs to be in + // order to provide some safety margin. + // + g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1); + + // + // Initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } + + // + // Clear the frame buffer. + // + OSRAMClear(); +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOn(void) +{ + unsigned long ulIdx; + + // + // Re-initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOff(void) +{ + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xae); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0x8a); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h new file mode 100644 index 0000000..0c9cd36 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h @@ -0,0 +1,47 @@ +//***************************************************************************** +// +// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED +// display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM96X16_H__ +#define __OSRAM96X16_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAMClear(void); +extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY); +extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAMInit(tBoolean bFast); +extern void OSRAMDisplayOn(void); +extern void OSRAMDisplayOff(void); + +#endif // __OSRAM96X16_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c new file mode 100644 index 0000000..6697566 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c @@ -0,0 +1,1291 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_pwm.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to configure. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulConfig is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it will count from a value down to zero, +//! and then reset to the preset value. This will produce left-aligned PWM +//! signals (i.e. the rising edge of the two PWM signals produced by the +//! generator will occur at the same time). In count up/down mode, it will +//! count up from zero to the preset value, count back down to zero, and then +//! repeat the process. This will produce center-aligned PWM signals (i.e. the +//! middle of the high/low period of the PWM signals produced by the generator +//! will occur at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their affect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This allows multiple parameters to be modified and take affect +//! simultaneously, instead of one at a time. Additionally, parameters to +//! multiple PWM generators in synchronous mode can be updated simultaneously, +//! allowing them to be treated as if they were a unified generator. In +//! non-synchronous mode, the parameter updates are not delayed until a +//! synchronization event. In either mode, the parameter updates only occur +//! when the counter is at zero to help prevent oddly formed PWM signals during +//! the update (i.e. a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it will continue to +//! count until it reaches zero, at which point it will pause until the +//! processor is restarted. If configured to continue running, it will keep +//! counting as if nothing had happened. +//! +//! The \b ulConfig parameter contains the desired configuration. It is the +//! logical OR of the following: \b PWM_GEN_MODE_DOWN or +//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC +//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and +//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior. +//! +//! \note Changes to the counter mode will affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Change the global configuration of the generator. + // + HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ulConfig); + + // + // Set the individual PWM generator controls. + // + if(ulConfig & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (i.e. center align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_A_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_B_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (i.e. left align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } +} +#endif + +//***************************************************************************** +// +//! Set the period of a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be modified. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulPeriod specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of \b PWM +//! clock ticks between pulses on the generator block \b zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ulPeriod / 2) < 65536); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; + } +} +#endif + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of \b PWM clock +//! ticks between pulses on the generator block \b zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in \b PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Figure out the counter mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ulGen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ulGen + PWM_O_X_LOAD) + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be enabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function allows the \b PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenEnable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be disabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function blocks the \b PWM clock from driving the timer/counter for +//! the specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! \param ulWidth specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of \b PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth) +{ + unsigned long ulGenBase, ulReg; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulWidth /= 2; + } + + // + // Get the period. + // + ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ulWidth < ulReg); + + // + // Compute the compare value. + // + ulReg = ulReg - ulWidth; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; + } + else + { + HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; + } +} +#endif + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! +//! This function gets the currently programmed pulse width for the +//! specified PWM output. If the update of the comparator for the specified +//! output has yet to be completed, the value returned may not be the active +//! pulse width. The value returned is the programmed pulse width, measured +//! in \b PWM clock ticks. +//! +//! \return Returns the width of the pulse in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) +{ + unsigned long ulGenBase, ulReg, ulLoad; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load-compare)*2. Otherwise, set width = load - compare + // + ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); + } + else + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); + } + ulReg = ulLoad - ulReg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulReg = ulReg * 2; + } + + // + // Return the pulse width. + // + return(ulReg); +} +#endif + +//***************************************************************************** +// +//! Enables the PWM dead band output, and sets the dead band delays. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param usRise specifies the width of delay from the rising edge. +//! \param usFall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, +//! where the dead bands are defined as the number of \b PWM clock ticks +//! from the rising or falling edge of the generator's \b OutA signal. +//! Note that this function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + ASSERT(usRise < 4096); + ASSERT(usFall < 4096); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Write the dead band delay values. + // + HWREG(ulGen + PWM_O_X_DBRISE) = usRise; + HWREG(ulGen + PWM_O_X_DBFALL) = usFall; + + // + // Enable the deadband functionality. + // + HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be updated. Must be the +//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Update the PWM timing registers. + // + HWREG(ulBase + PWM_O_CTL) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be +//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base +//! of the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Synchronize the counters in the specified generators by writing to + // the module's synchronization register. + // + HWREG(ulBase + PWM_O_SYNC) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function is used to enable or disable the selected PWM outputs. The +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's ENABLE output control register, and set or clear + // the requested bits. + // + if(bEnable == true) + { + HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function will cause the specified +//! PWM output signals to be inverted, or made active low. If \e bInvert is +//! \b false, the specified output will be passed through as is, or be made +//! active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's INVERT output control register, and set or clear + // the requested bits. + // + if(bInvert == true) + { + HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bFaultKill determines if the signal is killed or passed through +//! during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bFaultKill determines the fault handling characteristics +//! for the selected outputs. If \e bFaultKill is \b true, then the selected +//! outputs will be made inactive. If \e bFaultKill is \b false, then the +//! selected outputs are unaffected by the detected fault. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's FAULT output control register, and set or clear + // the requested bits. + // + if(bFaultKill == true) + { + HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function will also enable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! +//! This function will unregister the interrupt handler for the specified +//! PWM generator block. This function will also disable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Disable the PWMx interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function will also enable the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(INT_PWM_FAULT, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function will remove the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function will also disable the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Disable the PWM fault interrupt. + // + IntDisable(INT_PWM_FAULT); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers enabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be enabled. +//! +//! Unmasks the specified interrupt(s) and trigger(s) by setting the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers disabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be disabled. +//! +//! Masks the specified interrupt(s) and trigger(s) by clearing the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the contents of the interrupt status register, or the +//! contents of the raw interrupt status register, for the specified +//! PWM generator. +// +//***************************************************************************** +#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ulGen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ulGen + PWM_O_X_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulInts specifies the interrupts to be cleared. +//! +//! Clears the specified interrupt(s) by writing a 1 to the specified bits +//! of the interrupt status register for the specified PWM generator. The +//! defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be enabled. Must be a logical +//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or +//! \b PWM_INT_FAULT. +//! +//! Unmasks the specified interrupt(s) by setting the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and enable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; +} +#endif + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be disabled. Must be a +//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, +//! or \b PWM_INT_FAULT. +//! +//! Masks the specified interrupt(s) by clearing the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and disable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); +} +#endif + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! Clears the fault interrupt by writing to the appropriate bit of the +//! interrupt status register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT; +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT. +//! +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ulBase + PWM_O_ISC)); + } + else + { + return(HWREG(ulBase + PWM_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h new file mode 100644 index 0000000..db835ba --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c new file mode 100644 index 0000000..eb982de --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c @@ -0,0 +1,630 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_qei.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the quadrature encoder module. It must be +//! configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulConfig is the configuration for the quadrature encoder. See below +//! for a description of this parameter. +//! \param ulMaxPosition specifies the maximum position value. +//! +//! This will configure the operation of the quadrature encoder. The +//! \e ulConfig parameter provides the configuration of the encoder and is the +//! logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Write the new configuration to the hardware. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ulConfig); + + // + // Set the maximum position. + // + HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current position of the encoder. Depending upon the +//! configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (i.e. if in reset on index +//! mode, if an index pulse has not been encountered, the position counter will +//! not be aligned with the index pulse yet). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIPositionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the current position counter. + // + return(HWREG(ulBase + QEI_O_POS)); +} +#endif + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPosition is the new position for the encoder. +//! +//! This sets the current position of the encoder; the encoder position will +//! then be measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Set the position counter. + // + HWREG(ulBase + QEI_O_POS) = ulPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current direction of rotation. In this case, current +//! means the most recently detected direction of the encoder; it may not be +//! presently moving but this is the direction it last moved before it stopped. +//! +//! \return 1 if moving in the forward direction or -1 if moving in the reverse +//! direction. +// +//***************************************************************************** +#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +QEIDirectionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the direction of rotation. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} +#endif + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the error indicator for the quadrature encoder. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return true if an error has occurred and false otherwise. +// +//***************************************************************************** +#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +QEIErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the error indicator. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the velocity capture in the quadrature +//! encoder module. It must be configured before it is enabled. Velocity +//! capture will not occur if the quadrature encoder is not enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; +} +#endif + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} +#endif + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2, +//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or +//! QEI_VELDIV_128. +//! \param ulPeriod specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This will configure the operation of the velocity capture portion of the +//! quadrature encoder. The position increment signal is predivided as +//! specified by \e ulPreDiv before being accumulated by the velocity capture. +//! The divided signal is accumulated over \e ulPeriod system clock before +//! being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ulPeriod != 0); + + // + // Set the velocity predivider. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ulPreDiv); + + // + // Set the timer period. + // + HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current speed of the encoder. The value returned is the +//! number of pulses detected in the specified time period; this number can be +//! multiplied by the number of time periods per second and divided by the +//! number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return The number of pulses captured in the given time period. +// +//***************************************************************************** +#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIVelocityGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the speed capture value. + // + return(HWREG(ulBase + QEI_O_SPEED)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This sets the handler to be called when a quadrature encoder interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). +//! It is the interrupt handler's responsibility to clear the interrupt source +//! via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_QEI, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function will clear the handler to be called when a quadrature encoder +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_QEI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Enables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Disables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the quadrature encoder module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + QEI_O_ISC)); + } + else + { + return(HWREG(ulBase + QEI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to keep +//! it from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + QEI_O_ISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h new file mode 100644 index 0000000..3eaafae --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c new file mode 100644 index 0000000..095aaab --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c @@ -0,0 +1,609 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_ssi.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "ssi.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulProtocol specifies the data transfer protocol. +//! \param ulMode specifies the mode of operation. +//! \param ulBitRate specifies the clock rate. +//! \param ulDataWidth specifies number of bits transfered per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The parameter \e ulProtocol defines the data frame format. The parameter +//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0, +//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, +//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the +//! following polarity and phase configurations: +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The parameter \e ulMode defines the operating mode of the SSI module. The +//! SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. The parameter +//! \e ulMode can be one of the following values: SSI_MODE_MASTER, +//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD. +//! +//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate +//! must satisfy the following clock ratio criteria: +//! - FSSI >= 2 * bit rate (master mode) +//! - FSSI >= 12 * bit rate (slave modes) +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The parameter \e ulDataWidth defines the width of the data transfers. +//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive. +//! +//! The SSI clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the SSI clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, unsigned long ulDataWidth) +{ + unsigned long ulMaxBitRate; + unsigned long ulRegVal; + unsigned long ulPreDiv; + unsigned long ulSCR; + unsigned long ulSPH_SPO; + unsigned long ulClock; + + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || + (ulProtocol == SSI_FRF_MOTO_MODE_1) || + (ulProtocol == SSI_FRF_MOTO_MODE_2) || + (ulProtocol == SSI_FRF_MOTO_MODE_3) || + (ulProtocol == SSI_FRF_TI) || + (ulProtocol == SSI_FRF_NMW)); + ASSERT((ulMode == SSI_MODE_MASTER) || + (ulMode == SSI_MODE_SLAVE) || + (ulMode == SSI_MODE_SLAVE_OD)); + ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); + + // + // Get the processor clock rate. + // + ulClock = SysCtlClockGet(); + + // + // Validate the clock speed. + // + ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) || + ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12)))); + ASSERT((ulClock / ulBitRate) <= (254 * 256)); + + // + // Set the mode. + // + ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ulBase + SSI_O_CR1) = ulRegVal; + + // + // Set the clock predivider. + // + ulMaxBitRate = ulClock / ulBitRate; + ulPreDiv = 0; + do + { + ulPreDiv += 2; + ulSCR = (ulMaxBitRate / ulPreDiv) - 1; + } + while(ulSCR > 255); + HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; + + // + // Set protocol and clock rate. + // + ulSPH_SPO = ulProtocol << 6; + ulProtocol &= SSI_CR0_FRF_MASK; + ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); + HWREG(ulBase + SSI_O_CR0) = ulRegVal; +} +#endif + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will enable operation of the synchronous serial interface. It must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; +} +#endif + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will disable operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an SSI interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SSI, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_SSI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. The parameter \e ulIntFlags Can be +//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SSI interrupt sources. The parameter +//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, +//! or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the SSI module base address. +//! \param bMasked is false if the raw interrupt status is required and +//! true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the SSI module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SSIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + SSI_O_MIS)); + } + else + { + return(HWREG(ulBase + SSI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SSI interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to +//! keep it from being called again immediately upon exit. +//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO +//! and SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + SSI_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ulBase + SSI_O_DR) = ulData; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. If there is no space in the FIFO, then this +//! function will return a zero. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Check for space to write. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ulBase + SSI_O_DR) = ulData; + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of the specified +//! SSI module, and place that data into the location specified by the +//! \e pulData parameter. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pulData = HWREG(ulBase + SSI_O_DR); +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of +//! the specified SSI module, and place that data into the location specified +//! by the \e ulData parameter. If there is no data in the FIFO, then this +//! function will return a zero. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Check for data to read. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) + { + *pulData = HWREG(ulBase + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h new file mode 100644 index 0000000..045d8cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c new file mode 100644 index 0000000..539d0f7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c @@ -0,0 +1,1889 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_nvic.h" +#include "../hw_sysctl.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that +// contains the peripheral present bit for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_puldcregs) || defined(BUILD_ALL) +const unsigned long g_pulDCRegs[] = +{ + SYSCTL_DC1, + SYSCTL_DC2, + SYSCTL_DC4, + SYSCTL_DC1 +}; +#else +extern const unsigned long g_pulDCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that +// controls the software reset for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL) +const unsigned long g_pulSRCRRegs[] = +{ + SYSCTL_SRCR0, + SYSCTL_SRCR1, + SYSCTL_SRCR2 +}; +#else +extern const unsigned long g_pulSRCRRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that +// controls the run-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL) +const unsigned long g_pulRCGCRegs[] = +{ + SYSCTL_RCGC0, + SYSCTL_RCGC1, + SYSCTL_RCGC2 +}; +#else +extern const unsigned long g_pulRCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that +// controls the sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL) +const unsigned long g_pulSCGCRegs[] = +{ + SYSCTL_SCGC0, + SYSCTL_SCGC1, + SYSCTL_SCGC2 +}; +#else +extern const unsigned long g_pulSCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that +// controls the deep-sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL) +const unsigned long g_pulDCGCRegs[] = +{ + SYSCTL_DCGC0, + SYSCTL_DCGC1, + SYSCTL_DCGC2 +}; +#else +extern const unsigned long g_pulDCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +#if defined(GROUP_pulxtals) || defined(BUILD_ALL) +const unsigned long g_pulXtals[] = +{ + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000 +}; +#else +extern const unsigned long g_pulXtals[]; +#endif + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Stellaris device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlSRAMSizeGet(void) +{ + // + // Compute the size of the SRAM. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100); +} +#endif + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Stellaris device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlFlashSizeGet(void) +{ + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800); +} +#endif + +//***************************************************************************** +// +//! Determines if a pin is present. +//! +//! \param ulPin is the pin in question. +//! +//! Determines if a particular pin is present in the device. The PWM, analog +//! comparators, ADC, and timers have a varying number of pins across members +//! of the Stellaris family; this will determine which are present on this +//! device. +//! +//! The \b ulPin argument must be only one of the following values: +//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, +//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, +//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, +//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, +//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, +//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, +//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, +//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, +//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, +//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ. +//! +//! \return Returns \b true if the specified pin is present and \b false if it +//! is not. +// +//***************************************************************************** +#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPinPresent(unsigned long ulPin) +{ + // + // Check the arguments. + // + ASSERT((ulPin == SYSCTL_PIN_PWM0) || + (ulPin == SYSCTL_PIN_PWM1) || + (ulPin == SYSCTL_PIN_PWM2) || + (ulPin == SYSCTL_PIN_PWM3) || + (ulPin == SYSCTL_PIN_PWM4) || + (ulPin == SYSCTL_PIN_PWM5) || + (ulPin == SYSCTL_PIN_C0MINUS) || + (ulPin == SYSCTL_PIN_C0PLUS) || + (ulPin == SYSCTL_PIN_C0O) || + (ulPin == SYSCTL_PIN_C1MINUS) || + (ulPin == SYSCTL_PIN_C1PLUS) || + (ulPin == SYSCTL_PIN_C1O) || + (ulPin == SYSCTL_PIN_C2MINUS) || + (ulPin == SYSCTL_PIN_C2PLUS) || + (ulPin == SYSCTL_PIN_C2O) || + (ulPin == SYSCTL_PIN_ADC0) || + (ulPin == SYSCTL_PIN_ADC1) || + (ulPin == SYSCTL_PIN_ADC2) || + (ulPin == SYSCTL_PIN_ADC3) || + (ulPin == SYSCTL_PIN_ADC4) || + (ulPin == SYSCTL_PIN_ADC5) || + (ulPin == SYSCTL_PIN_ADC6) || + (ulPin == SYSCTL_PIN_ADC7) || + (ulPin == SYSCTL_PIN_CCP0) || + (ulPin == SYSCTL_PIN_CCP1) || + (ulPin == SYSCTL_PIN_CCP2) || + (ulPin == SYSCTL_PIN_CCP3) || + (ulPin == SYSCTL_PIN_CCP4) || + (ulPin == SYSCTL_PIN_CCP5) || + (ulPin == SYSCTL_PIN_32KHZ)) + + // + // Determine if this pin is present. + // + if(HWREG(SYSCTL_DC3) & ulPin) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! Determines if a particular peripheral is present in the device. Each +//! member of the Stellaris family has a different peripheral set; this will +//! determine which are present on this device. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or +//! \b SYSCTL_PERIPH_PLL. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPeripheralPresent(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_TEMP) || + (ulPeripheral == SYSCTL_PERIPH_PLL)); + + // + // Read the correct DC register and determine if this peripheral exists. + // + if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! deasserted, leaving the peripheral in a operating state but in its reset +//! condition. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ulPeripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ulPeripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. Those that must run at a particular frequency +//! (such as a UART) will not work as expected if the clock changes. It is the +//! responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled they are clocked +//! according to the configuration set by SysCtlPeripheralSleepEnable(), +//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and +//! SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralClockGating(tBoolean bEnable) +{ + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This sets the handler to be called when a system control interrupt occurs. +//! This will enable the global interrupt in the interrupt controller; specific +//! system control interrupts must be enabled via SysCtlIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function will clear the handler to be called when a system control +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Enables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntEnable(unsigned long ulInts) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ulInts; +} +#endif + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Disables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntDisable(unsigned long ulInts) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ulInts); +} +#endif + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntClear(unsigned long ulInts) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the system controller. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, +//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and +//! \b SYSCTL_INT_PLL_FAIL. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Sets the output voltage of the LDO. +//! +//! \param ulVoltage is the required output voltage from the LDO. Must be one +//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +//! +//! This function sets the output voltage of the LDO. The default voltage is +//! 2.5 V; it can be adjusted +/- 10%. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOSet(unsigned long ulVoltage) +{ + // + // Check the arguments. + // + ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || + (ulVoltage == SYSCTL_LDO_2_30V) || + (ulVoltage == SYSCTL_LDO_2_35V) || + (ulVoltage == SYSCTL_LDO_2_40V) || + (ulVoltage == SYSCTL_LDO_2_45V) || + (ulVoltage == SYSCTL_LDO_2_50V) || + (ulVoltage == SYSCTL_LDO_2_55V) || + (ulVoltage == SYSCTL_LDO_2_60V) || + (ulVoltage == SYSCTL_LDO_2_65V) || + (ulVoltage == SYSCTL_LDO_2_70V) || + (ulVoltage == SYSCTL_LDO_2_75V)); + + // + // Set the LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOPCTL) = ulVoltage; +} +#endif + +//***************************************************************************** +// +//! Gets the output voltage of the LDO. +//! +//! This function determines the output voltage of the LDO, as specified by the +//! control register. +//! +//! \return Returns the current voltage of the LDO; will be one of +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +// +//***************************************************************************** +#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlLDOGet(void) +{ + // + // Return the LDO voltage setting. + // + return(HWREG(SYSCTL_LDOPCTL)); +} +#endif + +//***************************************************************************** +// +//! Configures the LDO failure control. +//! +//! \param ulConfig is the required LDO failure control setting; can be either +//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. +//! +//! This function allows the LDO to be configured to cause a processor reset +//! when the output voltage becomes unregulated. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOConfigSet(unsigned long ulConfig) +{ + // + // Check hte arguments. + // + ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || + (ulConfig == SYSCTL_LDOCFG_NORST)); + + // + // Set the reset control as requested. + // + HWREG(SYSCTL_LDOARST) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function will perform a software reset of the entire device. The +//! processor and all peripherals will be reset and all device registers will +//! return to their default values (with the exception of the reset cause +//! register, which will maintain its current value but have the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This will cause the device to reset, + // no further code will be executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} +#endif + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} +#endif + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} +#endif + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return The reason(s) for a reset. +// +//***************************************************************************** +#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} +#endif + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ulCauses are the reset causes to be cleared; must be a logical OR of +//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, +//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlResetCauseClear(unsigned long ulCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ulCauses); +} +#endif + +//***************************************************************************** +// +//! Configures the brown-out control. +//! +//! \param ulConfig is the desired configuration of the brown-out control. +//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or +//! \b SYSCTL_BOR_RESAMPLE. +//! \param ulDelay is the number of internal oscillator cycles to wait before +//! resampling an asserted brown-out signal. This value only has meaning when +//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. +//! +//! This function configures how the brown-out control operates. It can detect +//! a brown-out by looking at only the brown-out output, or it can wait for it +//! to be active for two consecutive samples separated by a configurable time. +//! When it detects a brown-out condition, it can either reset the device or +//! generate a processor interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) +{ + // + // Check the arguments. + // + ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); + ASSERT(ulDelay < 8192); + + // + // Configure the brown-out reset control. + // + HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ulConfig is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \b ulConfig parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, +//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6, +//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9, +//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12, +//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or +//! \b SYSCTL_SYSDIV_16. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ, +//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ, +//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ, +//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device will be prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (i.e. via +//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function will delay until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlClockSet(unsigned long ulConfig) +{ + volatile unsigned long ulDelay; + unsigned long ulRCC; + + // + // Get the current value of the RCC register. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Bypass the PLL and system clock dividers for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Make sure that the PLL and system clock dividers are bypassed for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | + (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); + + // + // Set the new crystal value, oscillator source, and PLL configuration. + // + ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. One of the oscillators may need to be started as well. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Disable the appropriate oscillators. + // + ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Set the requested system divider. This will not get written + // immediately. + // + ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + + // + // See if the PLL output is being used to clock the system. + // + if(!(ulConfig & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ulDelay = 32768; ulDelay > 0; ulDelay--) + { + if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + { + break; + } + } + + // + // Enable use of the PLL. + // + ulRCC &= ~(SYSCTL_RCC_BYPASS); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Delay for a little bit so that the system divider takes effect. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } +} +#endif + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. This is +//! also the clock rate of all the peripheral modules (with the exception of +//! PWM, which has its own clock divider). +//! +//! \note This will not return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the later case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlClockGet(void) +{ + unsigned long ulRCC, ulPLL, ulClk; + + // + // Read RCC. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Get the base clock rate. + // + switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >> + SYSCTL_RCC_XTAL_SHIFT) - + (SYSCTL_RCC_XTAL_3_57MHZ >> + SYSCTL_RCC_XTAL_SHIFT)]; + break; + } + + // + // The internal oscillator is the source clock. This is not an + // accurate clock (it is +/- 50%); what is used is the nominal. + // + case SYSCTL_RCC_OSCSRC_INT: + { + ulClk = 15000000; + break; + } + + // + // The internal oscillator divided by four is the source clock. This + // is not an accurate clock (it is +/- 50%); what is used is the + // nominal. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + ulClk = 15000000 / 4; + break; + } + + // + // An unknown setting, so return a zero clock (i.e. an unknown clock + // rate). + // + default: + { + return(0); + } + } + + // + // See if the PLL is being used. + // + if(!(ulRCC & SYSCTL_RCC_BYPASS)) + { + // + // Get the PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // Compute the PLL output frequency based on its input frequency. + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >> + SYSCTL_PLLCFG_F_SHIFT) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_MASK) >> + SYSCTL_PLLCFG_R_SHIFT) + 2)); + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } + } + + // + // See if the system divider is being used. + // + if(ulRCC & SYSCTL_RCC_USE_SYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >> + SYSCTL_RCC_SYSDIV_SHIFT) + 1; + } + + // + // Return the computed clock rate. + // + return(ulClk); +} +#endif + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ulConfig is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function sets the rate of the clock provided to the PWM module as a +//! ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPWMClockSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_PWMDIV_1) || + (ulConfig == SYSCTL_PWMDIV_2) || + (ulConfig == SYSCTL_PWMDIV_4) || + (ulConfig == SYSCTL_PWMDIV_8) || + (ulConfig == SYSCTL_PWMDIV_16) || + (ulConfig == SYSCTL_PWMDIV_32) || + (ulConfig == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) | + ulConfig); +} +#endif + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return The current PWM clock configuration; will be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +// +//***************************************************************************** +#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Return the current PWM clock configuration. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)); +} +#endif + +//***************************************************************************** +// +//! Sets the sample rate of the ADC. +//! +//! \param ulSpeed is the desired sample rate of the ADC; must be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +//! +//! This function sets the rate at which the ADC samples are captured by the +//! ADC block. The sampling speed may be limited by the hardware, so the +//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() +//! will return the actual speed in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlADCSpeedSet(unsigned long ulSpeed) +{ + // + // Check the arguments. + // + ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || + (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); + + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Set the ADC speed in run, sleep, and deep-sleep mode. + // + HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); +} +#endif + +//***************************************************************************** +// +//! Gets the sample rate of the ADC. +//! +//! This function gets the current sample rate of the ADC. +//! +//! \return Returns the current ADC sample rate; will be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +// +//***************************************************************************** +#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlADCSpeedGet(void) +{ + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Return the current ADC speed. + // + return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK); +} +#endif + +//***************************************************************************** +// +//! Configures the internal oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the internal oscillator +//! verification timer should be enabled. +//! +//! This function allows the internal oscillator verification timer to be +//! enabled or disabled. When enabled, an interrupt will be generated if the +//! internal oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the main oscillator will verify the +//! internal oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlIOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the internal oscillator verification timer as + // requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the main oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the main oscillator +//! verification timer should be enabled. +//! +//! This function allows the main oscillator verification timer to be enabled +//! or disabled. When enabled, an interrupt will be generated if the main +//! oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the internal oscillator will verify the +//! main oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlMOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the main oscillator verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the PLL verification timer. +//! +//! \param bEnable is a boolean that is \b true if the PLL verification timer +//! should be enabled. +//! +//! This function allows the PLL verification timer to be enabled or disabled. +//! When enabled, an interrupt will be generated if the PLL ceases to operate. +//! +//! \note The main oscillator must be enabled for this verification timer to +//! operate as it is used to check the PLL. Also, the verification timer +//! should be disabled while the PLL is being reconfigured via +//! SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPLLVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the PLL verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); + } +} +#endif + +//***************************************************************************** +// +//! Clears the clock verification status. +//! +//! This function clears the status of the clock verification timers, allowing +//! them to assert another failure if detected. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlClkVerificationClear(void) +{ + // + // Clear the clock verification. + // + HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR; + + // + // The bit does not self-reset, so clear it. + // + HWREG(SYSCTL_CLKVCLR) = 0; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h new file mode 100644 index 0000000..ebe01cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h @@ -0,0 +1,285 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c new file mode 100644 index 0000000..3825335 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c @@ -0,0 +1,262 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This sets the handler to be called when a SysTick interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} +#endif + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} +#endif + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h new file mode 100644 index 0000000..bfddfb1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c new file mode 100644 index 0000000..46ce19a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c @@ -0,0 +1,1125 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_timer.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "timer.h" + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will enable operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} +#endif + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will disable operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} +#endif + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured, and is left in the disabled +//! state. The configuration is specified in \e ulConfig as one of the +//! following values: +//! +//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer +//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer +//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer +//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers +//! +//! When configured for a pair of 16-bit timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer +//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer +//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture +//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture +//! - \b TIMER_CFG_A_PWM - 16-bit PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || + (ulConfig == TIMER_CFG_32_BIT_PER) || + (ulConfig == TIMER_CFG_32_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; + HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; +} +#endif + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function sets the PWM output level for the specified timer. If the +//! parameter \e bInvert is \b true, then the timer's output will be made +//! active low; otherwise, it will be made active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enables or disables the trigger output. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired trigger state. +//! +//! This function controls the trigger output for the specified timer. If the +//! parameter \e bEnable is \b true, then the timer's output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the trigger output as requested. + // + ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ulBase + TIMER_O_CTL) = (bEnable ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function sets the signal edge(s) that will trigger the timer when in +//! capture mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK); + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & + ~(TIMER_CTL_TAEVENT_MSK | + TIMER_CTL_TBEVENT_MSK)) | ulEvent); +} +#endif + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! parameter \e bStall is \b true, then the timer will stop counting if the +//! processor enters debug mode; otherwise the timer will keep running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this will do nothing. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} +#endif + +//***************************************************************************** +// +//! Disable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value; must be between 0 and 255, +//! inclusive. +//! +//! This function sets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale match value; must be between 0 and +//! 255, inclusive. +//! +//! This function sets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescale match if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPMR) = ulValue; + } + + // + // Set the timer B prescale match if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPMR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : + HWREG(ulBase + TIMER_O_TBPMR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the load value. +//! +//! This function sets the timer load value; if the timer is running then the +//! value will be immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} +#endif + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : + HWREG(ulBase + TIMER_O_TBR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the match value. +//! +//! This function sets the match value for a timer. This is used in capture +//! count mode to determine when to interrupt the processor and in PWM mode to +//! determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This sets the handler to be called when a timer interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific +//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function will clear the handler to be called when a timer interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags must be the logical OR of any combination of +//! the following: +//! +//! - TIMER_CAPB_EVENT - Capture B event interrupt +//! - TIMER_CAPB_MATCH - Capture B match interrupt +//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - TIMER_RTC_MATCH - RTC interrupt mask +//! - TIMER_CAPA_EVENT - Capture A event interrupt +//! - TIMER_CAPA_MATCH - Capture A match interrupt +//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the timer module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} +#endif + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts the timer into its reset state. +//! +//! \param ulBase is the base address of the timer module. +//! +//! The specified timer is disabled, and all its interrupts are disabled, +//! cleared, and unregistered. Then the timer registers are set to their reset +//! value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerQuiesce(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the timer. + // + HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; + + // + // Disable all the timer interrupts. + // + HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; + + // + // Clear all the timer interrupts. + // + HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; + + // + // Unregister the interrupt handler. This also disables interrupts to the + // core. + // + TimerIntUnregister(ulBase, TIMER_BOTH); + + // + // Set all the registers to their reset value. + // + HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; + HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; + HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; + HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; + HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; + HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; + HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; + HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; + HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; + HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; + HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; + HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; + HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; + HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; + HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h new file mode 100644 index 0000000..660c325 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c new file mode 100644 index 0000000..cbae1b0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c @@ -0,0 +1,821 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_uart.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it will always be either be one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) & + ~(UART_LCR_H_SPS | UART_LCR_H_EPS | + UART_LCR_H_PEN)) | ulParity); +} +#endif + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! \return The current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function will configure the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the +//! data format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig) +{ + unsigned long ulUARTClk, ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Determine the UART clock rate. + // + ulUARTClk = SysCtlClockGet(); + + // + // Compute the fractional baud rate divider. + // + ulInt = ulUARTClk / (16 * ulBaud); + ulFrac = ulUARTClk % (16 * ulBaud); + ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2); + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulInt; + HWREG(ulBase + UART_O_FBRD) = ulFrac; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCR_H) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} +#endif + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined. The returned +//! baud rate is the actual baud rate; it may not be the exact baud rate +//! requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSet(). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be computed incorrectly. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig) + +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac); + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 | + UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO, and \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO, +//! and \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 will be returned if there are no characters present in +//! the receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharNonBlockingGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} +#endif + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function will wait until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as an +//! \e int. +// +//***************************************************************************** +#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application will have to retry the function +//! later. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO, and \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function will +//! wait until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true will assert a +//! break condition on the UART. Calling this function with \e bBreakState set +//! to \b false will remove the break condition. For proper transmission of a +//! break command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCR_H) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) : + (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK))); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags is the logical OR of any of the following: +//! +//! - UART_INT_OE - Overrun Error interrupt +//! - UART_INT_BE - Break Error interrupt +//! - UART_INT_PE - Parity Error interrupt +//! - UART_INT_FE - Framing Error interrupt +//! - UART_INT_RT - Receive Timeout interrupt +//! - UART_INT_TX - Transmit interrupt +//! - UART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h new file mode 100644 index 0000000..ee89308 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c new file mode 100644 index 0000000..53332d0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_watchdog.h" +#include "debug.h" +#include "interrupt.h" +#include "watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will check to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will enable the watchdog timer counter and interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Disables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Locks out write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} +#endif + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function sets the value to load into the watchdog timer when the count +//! reaches zero for the first time; if the watchdog timer is running when this +//! function is called, then the value will be immediately loaded into the +//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} +#endif + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; the watchdog +//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function will clear the handler to be called when a watchdog timer +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the watchdog timer interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog interrupt. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the watchdog timer module. Either +//! the raw interrupt status or the status of interrupt that is allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, where a 1 indicates that the watchdog +//! interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} +#endif + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog will instead +//! expired after the appropriate number of processor cycles have been executed +//! while debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} +#endif + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h new file mode 100644 index 0000000..9378504 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd new file mode 100644 index 0000000..25834c6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd @@ -0,0 +1,879 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp new file mode 100644 index 0000000..ee85a1c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp @@ -0,0 +1,951 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\LuminaryCode\osram96x16.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\startup.c + + + + Scheduler Source + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww new file mode 100644 index 0000000..b7687f6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww @@ -0,0 +1,54 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + All Examples + + driverlib + Debug + + + bitband + Debug + + + gpio_jtag + Debug + + + hello + Debug + + + interrupts + Debug + + + pwmgen + Debug + + + qs_ev-lm3s811 + Debug + + + timers + Debug + + + uart_echo + Debug + + + watchdog + Debug + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c new file mode 100644 index 0000000..721c404 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c @@ -0,0 +1,397 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ + + + +/* Environment includes. */ +#include "DriverLib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" + +/* Delay between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* UART configuration - note this does not use the FIFO so is not very +efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) + +/* Demo task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Demo board specifics. */ +#define mainPUSH_BUTTON GPIO_PIN_4 + +/* Misc. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) +#define mainNO_DELAY ( ( portTickType ) 0 ) +/* + * Configure the processor and peripherals for this demo. + */ +static void prvSetupHardware( void ); + +/* + * The 'check' task, as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that is woken by the ISR that processes GPIO interrupts originating + * from the push button. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/* + * The task that controls access to the LCD. + */ +static void vPrintTask( void *pvParameter ); + +/* String that is transmitted on the UART. */ +static portCHAR *cMessage = "Task woken by button interrupt! --- "; +static volatile portCHAR *pcNextChar; + +/* The semaphore used to wake the button handler task from within the GPIO +interrupt handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue used to send strings to the print task for display on the LCD. */ +xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); + + /* Create the semaphore used to wake the button handler task from the GPIO + ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap to start the + scheduler. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const portCHAR *pcPassMessage = "PASS"; +const portCHAR *pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. We do not write directly to the LCD, but instead + queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Setup the push button. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); + + + + /* Enable the UART. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We don't want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); + + + /* Initialise the LCD> */ + OSRAMInit( false ); + OSRAMStringDraw("www.FreeRTOS.org", 0, 0); + OSRAMStringDraw("LM3S811 demo", 16, 1); +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +const portCHAR *pcInterruptMessage = "Int"; + + for( ;; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } +} + +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != NULL ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + pcNextChar++; + } + } +} +/*-----------------------------------------------------------*/ + +void vGPIO_ISR( void ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt. */ + GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + + /* Wake the button handler task. */ + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +portCHAR *pcMessage; +unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ;; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/startup.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/startup.c new file mode 100644 index 0000000..84e3fc8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_IAR/startup.c @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// startup_ewarm.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vGPIO_ISR(void); +extern void vUART_ISR(void); +extern void vPortSVCHandler( void ); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 64 +#endif +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + +//***************************************************************************** +// +// The minimal vector table for a Cortex-M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, + // The initial stack pointer + __iar_program_start, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + vPortSVCHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + vGPIO_ISR, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + vUART_ISR, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler // FLASH Control +}; + + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h new file mode 100644 index 0000000..0700763 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */ + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h new file mode 100644 index 0000000..956bf12 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h @@ -0,0 +1,39 @@ +#ifndef DRIVER_LIB_H +#define DRIVER_LIB_H + +#include "DriverLib.h" +#include "hw_adc.h" +#include "hw_comp.h" +#include "hw_flash.h" +#include "hw_gpio.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_pwm.h" +#include "hw_qei.h" +#include "hw_ssi.h" +#include "hw_sysctl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_watchdog.h" +#include "osram96x16.h" +#include "src\adc.h" +#include "src\comp.h" +#include "src\cpu.h" +#include "src\debug.h" +#include "src\flash.h" +#include "src\gpio.h" +#include "src\i2c.h" +#include "src\interrupt.h" +#include "src\pwm.h" +#include "src\qei.h" +#include "src\ssi.h" +#include "src\sysctl.h" +#include "src\systick.h" +#include "src\timer.h" +#include "src\uart.h" +#include "src\watchdog.h" + +#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h new file mode 100644 index 0000000..4d981c6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h @@ -0,0 +1,329 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h new file mode 100644 index 0000000..9c5212b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h new file mode 100644 index 0000000..d27ebcf --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h new file mode 100644 index 0000000..10bf23b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h new file mode 100644 index 0000000..2a3900c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h new file mode 100644 index 0000000..820d5cd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h new file mode 100644 index 0000000..4340d63 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h new file mode 100644 index 0000000..692af25 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h new file mode 100644 index 0000000..a324eaa --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h new file mode 100644 index 0000000..64ebcd1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h new file mode 100644 index 0000000..9ebf627 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h new file mode 100644 index 0000000..fbc6982 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h @@ -0,0 +1,409 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h new file mode 100644 index 0000000..6a09cd8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h new file mode 100644 index 0000000..0a6084a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h new file mode 100644 index 0000000..a688a6a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h new file mode 100644 index 0000000..e6e3fa5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c new file mode 100644 index 0000000..370d53e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c @@ -0,0 +1,953 @@ +//***************************************************************************** +// +// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ev_lm3s811_api +//! @{ +// +//***************************************************************************** + +#include "hw_i2c.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "src/debug.h" +#include "src/gpio.h" +#include "src/i2c.h" +#include "src/sysctl.h" +#include "osram96x16.h" + +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, tBoolean bFast); +//***************************************************************************** +// +// The I2C slave address of the SSD0303 controller on the OLED display. +// +//***************************************************************************** +#define SSD0303_ADDR 0x3d + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +//***************************************************************************** +static const unsigned char g_pucFont[95][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the I2C transfer, followed by that many bytes of command data. +// +//***************************************************************************** +static const unsigned char g_pucOSRAMInit[] = +{ + // + // Turn off the panel + // + 0x02, 0x80, 0xae, + + // + // Set lower column address + // + 0x02, 0x80, 0x04, + + // + // Set higher column address + // + 0x02, 0x80, 0x12, + + // + // Set contrast control register + // + 0x04, 0x80, 0x81, 0x80, 0x2b, + + // + // Set segment re-map + // + 0x02, 0x80, 0xa1, + + // + // Set display start line + // + 0x02, 0x80, 0x40, + + // + // Set display offset + // + 0x04, 0x80, 0xd3, 0x80, 0x00, + + // + // Set multiplex ratio + // + 0x04, 0x80, 0xa8, 0x80, 0x0f, + + // + // Set the display to normal mode + // + 0x02, 0x80, 0xa4, + + // + // Non-inverted display + // + 0x02, 0x80, 0xa6, + + // + // Set the page address + // + 0x02, 0x80, 0xb0, + + // + // Set COM output scan direction + // + 0x02, 0x80, 0xc8, + + // + // Set display clock divide ratio/oscillator frequency + // + 0x04, 0x80, 0xd5, 0x80, 0x72, + + // + // Enable mono mode + // + 0x04, 0x80, 0xd8, 0x80, 0x00, + + // + // Set pre-charge period + // + 0x04, 0x80, 0xd9, 0x80, 0x22, + + // + // Set COM pins hardware configuration + // + 0x04, 0x80, 0xda, 0x80, 0x12, + + // + // Set VCOM deslect level + // + 0x04, 0x80, 0xdb, 0x80, 0x0f, + + // + // Set DC-DC on + // + 0x04, 0x80, 0xad, 0x80, 0x8b, + + // + // Turn on the panel + // + 0x02, 0x80, 0xaf, +}; + +//***************************************************************************** +// +// The inter-byte delay required by the SSD0303 OLED controller. +// +//***************************************************************************** +static unsigned long g_ulDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Provide a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! Since the SSD0303 controller needs a delay between bytes written to it over +//! the I2C bus, this function provides a means of generating that delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) +static void +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(gcc) +static void __attribute__((naked)) +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +OSRAMDelay(unsigned long ulCount) +{ + subs r0, #1; + bne OSRAMDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Start a transfer to the SSD0303 controller. +//! +//! \param ucChar is the first byte to be written to the controller. +//! +//! This function will start a transfer to the SSD0303 controller via the I2C +//! bus. +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFirst(unsigned char ucChar) +{ + // + // Set the slave address. + // + I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); + + // + // Write the first byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Start the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a byte to the SSD0303 controller. +//! +//! \param ucChar is the byte to be transmitted to the controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing +//! another byte over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled faashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteByte(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of bytes to the SSD0303 controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing a +//! sequence of bytes over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); + ulCount--; + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Finish a transfer to the SSD0303 controller. +//! +//! \param ucChar is the final byte to be written to the controller. +//! +//! This function will finish a transfer to the SSD0303 controller via the I2C +//! bus. This must only be called after calling OSRAMWriteFirst(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFinal(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the final byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Finish the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); + + // + // Wait until the final byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display. All pixels in the display will be +//! turned off. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMClear(void) +{ + static const unsigned char pucRow1[] = + { + 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + static const unsigned char pucRow2[] = + { + 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + unsigned long ulIdx; + + // + // Move the display cursor to the first column of the first row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow1, sizeof(pucRow1)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); + + // + // Move the display cursor to the first column of the second row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow2, sizeof(pucRow2)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + + // + // Move the display cursor to the requested position on the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte((ulX + 36) & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // See if there is enough space on the display for this entire + // character. + // + if(ulX <= 90) + { + // + // Write the contents of this character to the display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); + + // + // See if this is the last character to display (either because the + // right edge has been reached or because there are no more + // characters). + // + if((ulX == 90) || (pcStr[1] == 0)) + { + // + // Write the final column of the display. + // + OSRAMWriteFinal(0x00); + + // + // The string has been displayed. + // + return; + } + + // + // Write the inter-character padding column. + // + OSRAMWriteByte(0x00); + } + else + { + // + // Write the portion of the character that will fit onto the + // display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); + OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); + + // + // The string has been displayed. + // + return; + } + + // + // Advance to the next character. + // + pcStr++; + + // + // Increment the X coordinate by the six columns that were just + // written. + // + ulX += 6; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in eight row blocks +//! (i.e. only 1 and 2 are valid). +//! +//! This function will display a bitmap graphic on the display. The image to +//! be displayed must be a multiple of eight scan lines high (i.e. one row) and +//! will be drawn at a vertical position that is a multiple of eight scan lines +//! (i.e. scan line zero or scan line eight, corresponding to row zero or row +//! one). +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for the eight scan lines of the column, with the top scan +//! line being in the least significant bit of the byte and the bottom scan +//! line being in the most significant bit of the byte. +//! +//! For example, an image four columns wide and sixteen scan lines tall would +//! be arranged as follows (showing how the eight bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + ASSERT((ulX + ulWidth) <= 96); + ASSERT((ulY + ulHeight) <= 2); + + // + // The first 36 columns of the LCD buffer are not displayed, so increment + // the X coorddinate by 36 to account for the non-displayed frame buffer + // memory. + // + ulX += 36; + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write the starting address within this row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte(ulX & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Write this row of image data. + // + OSRAMWriteArray(pucImage, ulWidth - 1); + OSRAMWriteFinal(pucImage[ulWidth - 1]); + + // + // Advance to the next row of the image. + // + pucImage += ulWidth; + ulY++; + } +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param bFast is a boolean that is \e true if the I2C interface should be +//! run at 400 kbps and \e false if it should be run at 100 kbps. +//! +//! This function initializes the I2C interface to the OLED display and +//! configures the SSD0303 controller on the panel. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMInit(tBoolean bFast) +{ + unsigned long ulIdx; + + // + // Enable the I2C and GPIO port B blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + // + // Configure the I2C SCL and SDA pins for I2C operation. + // + GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); + + // + // Initialize the I2C master. + // + I2CMasterInitExpClk(I2C_MASTER_BASE, SysCtlClockGet(), bFast); + + // + // Compute the inter-byte delay for the SSD0303 controller. This delay is + // dependent upon the I2C bus clock rate; the slower the clock the longer + // the delay required. + // + // The derivation of this formula is based on a measured delay of + // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz + // (referred to as C). To scale this to the delay for a different CPU + // speed (since this is just a CPU-based delay loop) is: + // + // f(CPU) + // C * ---------- + // 50,000,000 + // + // To then scale this to the actual I2C rate (since it won't always be + // precisely 100 kHz): + // + // f(CPU) 100,000 + // C * ---------- * ------- + // 50,000,000 f(I2C) + // + // This equation will give the inter-byte delay required for any + // configuration of the I2C master. But, as arranged it is impossible to + // directly compute in 32-bit arithmetic (without loosing a lot of + // accuracy). So, the equation is simplified. + // + // Since f(I2C) is generated by dividing down from f(CPU), replace it with + // the equivalent (where TPR is the value programmed into the Master Timer + // Period Register of the I2C master, with the 1 added back): + // + // 100,000 + // f(CPU) ------- + // C * ---------- * f(CPU) + // 50,000,000 ------------ + // 2 * 10 * TPR + // + // Inverting the dividend in the last term: + // + // f(CPU) 100,000 * 2 * 10 * TPR + // C * ---------- * ---------------------- + // 50,000,000 f(CPU) + // + // The f(CPU) now cancels out. + // + // 100,000 * 2 * 10 * TPR + // C * ---------------------- + // 50,000,000 + // + // Since there are no clock frequencies left in the equation, this equation + // also works for 400 kHz bus operation as well, since the 100,000 in the + // numerator becomes 400,000 but C is 1/4, which cancel out each other. + // Reducing the constants gives: + // + // TPR TPR TPR + // C * --- = 1700 * --- = 340 * --- + // 25 25 5 + // + // Note that the constant C is actually a bit larger than it needs to be in + // order to provide some safety margin. + // + // When the panel is being initialized, the value of C actually needs to be + // a bit longer (3200 instead of 1700). So, set the larger value for now. + // + g_ulDelay = (640 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5; + + // + // Initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } + + // + // Now, switch to the actual value of C. + // + g_ulDelay = (340 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5; + + // + // Clear the frame buffer. + // + OSRAMClear(); +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOn(void) +{ + // + // Turn on the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x8b); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0xaf); +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOff(void) +{ + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x8a); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0xae); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h new file mode 100644 index 0000000..54cf421 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h @@ -0,0 +1,47 @@ +//***************************************************************************** +// +// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED +// display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 852 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM96X16_H__ +#define __OSRAM96X16_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAMClear(void); +extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY); +extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAMInit(tBoolean bFast); +extern void OSRAMDisplayOn(void); +extern void OSRAMDisplayOff(void); + +#endif // __OSRAM96X16_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h new file mode 100644 index 0000000..ee06b9c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h new file mode 100644 index 0000000..1475122 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h new file mode 100644 index 0000000..a71928c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h new file mode 100644 index 0000000..0000ed3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h new file mode 100644 index 0000000..f8ff60a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h new file mode 100644 index 0000000..ec682b5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h new file mode 100644 index 0000000..88234a8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h new file mode 100644 index 0000000..edd8a08 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h new file mode 100644 index 0000000..0986833 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h new file mode 100644 index 0000000..9cea48b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h new file mode 100644 index 0000000..b697a10 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h new file mode 100644 index 0000000..de5273f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h @@ -0,0 +1,285 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h new file mode 100644 index 0000000..beffd88 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h new file mode 100644 index 0000000..ef98c0d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h new file mode 100644 index 0000000..43eb8d5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h new file mode 100644 index 0000000..ad8bc45 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt new file mode 100644 index 0000000..425ad06 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt @@ -0,0 +1,54 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Demo_Source),1,0,0 +GRPOPT 2,(Libraries),0,0,0 +GRPOPT 3,(RTOS_Source),0,0,0 +GRPOPT 4,(Documentation),0,0,0 + +OPTFFF 1,1,2,301989888,0,0,0,0,<.\startup_rvmdk.S> +OPTFFF 1,2,1,167772160,0,0,0,0,<.\LuminaryCode\osram96x16.c> +OPTFFF 1,3,1,2,0,148,161,0,<.\main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,100,0,0,0,12,0,0,0,27,4,0,0,178,1,0,0 } +OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 1,5,1,989855744,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,6,1,939524096,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 1,7,1,201326592,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 1,8,1,0,0,0,0,0,<.\heap\heap_1.c> +OPTFFF 2,9,4,0,0,0,0,0, +OPTFFF 3,10,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 3,11,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 3,12,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 3,13,1,335544320,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 4,14,5,0,0,0,0,0,<.\readme.txt> + + +TARGOPT 1, (FreeRTOS_Demo) + ADSCLK=50000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\rvmdk\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 0 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811) + OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTKEY 0,(LMIDK-AGDI)(-B0 -O1792) + OPTDF 0x84 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 new file mode 100644 index 0000000..11d87f4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 @@ -0,0 +1,116 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' + +Group (Demo_Source) +Group (Libraries) +Group (RTOS_Source) +Group (Documentation) + +File 1,2,<.\startup_rvmdk.S> +File 1,1,<.\LuminaryCode\osram96x16.c> +File 1,1,<.\main.c> +File 1,1,<..\Common\Minimal\semtest.c> +File 1,1,<..\Common\Minimal\integer.c> +File 1,1,<..\Common\Minimal\PollQ.c> +File 1,1,<..\Common\Minimal\BlockQ.c> +File 1,1,<.\heap\heap_1.c> +File 2,4,<..\Common\drivers\LuminaryMicro\keil\driverlib.lib> +File 3,1,<..\..\Source\tasks.c> +File 3,1,<..\..\Source\list.c> +File 3,1,<..\..\Source\queue.c> +File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +File 4,5,<.\readme.txt> + + +Options 1,0,0 // Target 'FreeRTOS_Demo' + Device (LM3S811) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x20001fff) IROM(0-0xffff) CLOCK(50000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (LMIDK-AGDI(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) + DevID (4079) + Rgf (LM3Sxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\rvmdk\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\rvmdk\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 176,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,32,0,0 } + OCMADSIROM { 1,0,0,0,0,0,0,1,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,32,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (RVDS_ARMCM3_LM3S102) + ADSCUDEF () + ADSCINCD (.;./LuminaryCode;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler --last xHeap) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811) + OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\LMIDK-AGDI.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c new file mode 100644 index 0000000..8224dde --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c @@ -0,0 +1,137 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c and heap_3.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ +#include +#include "FreeRTOS.h" +#include "task.h" + + +/* Allocate the memory for the heap. The struct is used to force byte +alignment without using any non-portable code. */ +extern struct xRTOS_HEAP +{ + unsigned long ulDummy; + unsigned char ucHeap[ configTOTAL_HEAP_SIZE ]; +} xHeap; + +static size_t xNextFreeByte = ( size_t ) 0; +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +void *pvReturn = NULL; + + /* Ensure that blocks are always aligned to the required number of bytes. */ + #if portBYTE_ALIGNMENT != 1 + if( xWantedSize & portBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + } + #endif + + vTaskSuspendAll(); + { + /* Check there is enough room left for the allocation. */ + if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && + ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ + { + /* Return the next free byte then increment the index past this + block. */ + pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); + xNextFreeByte += xWantedSize; + } + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c + for alternative implementations, and the memory management pages of + http://www.FreeRTOS.org for more information. */ + ( void ) pv; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c new file mode 100644 index 0000000..8538660 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c @@ -0,0 +1,399 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ + + + +/* Environment includes. */ +#include "DriverLib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" + +/* Delay between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* UART configuration - note this does not use the FIFO so is not very +efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) + +/* Demo task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Demo board specifics. */ +#define mainPUSH_BUTTON GPIO_PIN_4 + +/* Misc. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) +#define mainNO_DELAY ( ( portTickType ) 0 ) +/* + * Configure the processor and peripherals for this demo. + */ +static void prvSetupHardware( void ); + +/* + * The 'check' task, as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that is woken by the ISR that processes GPIO interrupts originating + * from the push button. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/* + * The task that controls access to the LCD. + */ +static void vPrintTask( void *pvParameter ); + +/* String that is transmitted on the UART. */ +static char *cMessage = "Task woken by button interrupt! --- "; +static volatile char *pcNextChar; + +/* The semaphore used to wake the button handler task from within the GPIO +interrupt handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue used to send strings to the print task for display on the LCD. */ +xQueueHandle xPrintQueue; + +/* Newer library version. */ +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, unsigned long ulBaud, unsigned long ulConfig); +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); + + /* Create the semaphore used to wake the button handler task from the GPIO + ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap to start the + scheduler. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const char *pcPassMessage = "PASS"; +const char *pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. We do not write directly to the LCD, but instead + queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Setup the push button. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); + + + + /* Enable the UART. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We don't want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); + + + /* Initialise the LCD> */ + OSRAMInit( false ); + OSRAMStringDraw("www.FreeRTOS.org", 0, 0); + OSRAMStringDraw("LM3S811 demo", 16, 1); +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +const char *pcInterruptMessage = "Int"; + + for( ;; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } +} + +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned long ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != NULL ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + pcNextChar++; + } + } +} +/*-----------------------------------------------------------*/ + +void vGPIO_ISR( void ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt. */ + GPIOPinIntClear( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + + /* Wake the button handler task. */ + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +char *pcMessage; +unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ;; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/readme.txt b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/readme.txt new file mode 100644 index 0000000..371a25b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/readme.txt @@ -0,0 +1,36 @@ +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S new file mode 100644 index 0000000..8cd8aaa --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S @@ -0,0 +1,240 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for Stellaris. +; +; Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +; +; Software License Agreement +; +; Luminary Micro, Inc. (LMI) is supplying this software for use solely and +; exclusively on LMI's Stellaris Family of microcontroller products. +; +; The software is owned by LMI and/or its suppliers, and is protected under +; applicable copyright laws. All rights are reserved. Any use in violation of +; the foregoing restrictions may subject the user to criminal sanctions under +; applicable laws, as well as to civil liability for the breach of the terms +; and conditions of this license. +; +; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 816 of the Stellaris Driver Library. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +; +;****************************************************************************** +Stack EQU 0x00000100 + +;****************************************************************************** +; +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +HeapMem + SPACE Heap + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; MPU Fault Handler + DCD IntDefaultHandler ; Bus Fault Handler + DCD IntDefaultHandler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD vPortSVCHandler ; SVCall Handler + DCD IntDefaultHandler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD xPortPendSVHandler ; PendSV Handler + DCD xPortSysTickHandler ; SysTick Handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD vGPIO_ISR ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD vUART_ISR ; UART0 + DCD IntDefaultHandler ; UART1 + DCD IntDefaultHandler ; SSI + DCD IntDefaultHandler ; I2C + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog + DCD IntDefaultHandler ; Timer 0A + DCD IntDefaultHandler ; Timer 0B + DCD IntDefaultHandler ; Timer 1A + DCD IntDefaultHandler ; Timer 1B + DCD IntDefaultHandler ; Timer 2A + DCD IntDefaultHandler ; Timer 2B + DCD IntDefaultHandler ; Comp 0 + DCD IntDefaultHandler ; Comp 1 + DCD IntDefaultHandler ; Comp 2 + DCD IntDefaultHandler ; System Control + DCD IntDefaultHandler ; Flash Control + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Call __main() in the C library, which will call the application + ; supplied main(). + ; + IMPORT __main + IMPORT vGPIO_ISR + IMPORT vUART_ISR + IMPORT xPortPendSVHandler + IMPORT xPortSysTickHandler + IMPORT vPortSVCHandler + + LDR R0, =__main + BX R0 + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. +; +;****************************************************************************** + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +; Note: +; Using READWRITE places Section .RTOSHeap in Region ER_RW. +; Using NOINIT places Section .RTOSHeap in Region ER_ZI,which means +; "ZEROINITIALIZE" (sic), and which is the last region in memory. Then +; we need to make this section the last section, which is somewhat tricky, +; because we cannot use the sectionname, but need to use a defined symbol: +; Linker option: "--last xHeap" + + EXPORT xHeap + + AREA RTOSHeap, DATA, NOINIT +xHeap + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 0000000..e2671c5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,131 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 50000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 10 +#define configGENERATE_RUN_TIME_STATS 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +#define configKERNEL_INTERRUPT_PRIORITY ( ( unsigned char ) 7 << ( unsigned char ) 5 ) /* Priority 7, or 255 as only the top three bits are implemented. This is the lowest priority. */ +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( ( unsigned char ) 5 << ( unsigned char ) 5 ) /* Priority 5, or 160 as only the top three bits are implemented. */ + +extern volatile unsigned long ulHighFrequencyTimerTicks; +/* There is already a high frequency timer running - just reset its count back +to zero. */ +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() ( ulHighFrequencyTimerTicks = 0UL ) +#define portGET_RUN_TIME_COUNTER_VALUE() ulHighFrequencyTimerTicks + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.c new file mode 100644 index 0000000..5d360cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.c @@ -0,0 +1,133 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +#define tmrTIMER_2_FREQUENCY ( 2000UL ) +#define tmrTIMER_3_FREQUENCY ( 2001UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ +unsigned long ulFrequency; + + /* Timer 2 and 3 are utilised for this test. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER2 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER3 ); + TimerConfigure( TIMER2_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER3_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + IntPrioritySet( INT_TIMER2A, configMAX_SYSCALL_INTERRUPT_PRIORITY + ( 1 << 5 ) ); /* Shift left 5 as only the top 3 bits are implemented. */ + IntPrioritySet( INT_TIMER3A, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + + /* The rate at which the timers will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY; + TimerLoadSet( TIMER2_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER2A ); + TimerIntEnable( TIMER2_BASE, TIMER_TIMA_TIMEOUT ); + + /* The rate at which the timers will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_3_FREQUENCY; + TimerLoadSet( TIMER3_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER3A ); + TimerIntEnable( TIMER3_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER2_BASE, TIMER_A ); + TimerEnable( TIMER3_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void vT2InterruptHandler( void ) +{ + TimerIntClear( TIMER2_BASE, TIMER_TIMA_TIMEOUT ); + portEND_SWITCHING_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +void vT3InterruptHandler( void ) +{ + TimerIntClear( TIMER3_BASE, TIMER_TIMA_TIMEOUT ); + portEND_SWITCHING_ISR( xSecondTimerHandler() ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.h new file mode 100644 index 0000000..83edd5d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile new file mode 100644 index 0000000..367ff9c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile @@ -0,0 +1,141 @@ +#/* +# FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. +# +# +# *************************************************************************** +# * * +# * FreeRTOS tutorial books are available in pdf and paperback. * +# * Complete, revised, and edited pdf reference manuals are also * +# * available. * +# * * +# * Purchasing FreeRTOS documentation will not only help you, by * +# * ensuring you get running as quickly as possible and with an * +# * in-depth knowledge of how to use FreeRTOS, it will also help * +# * the FreeRTOS project to continue with its mission of providing * +# * professional grade, cross platform, de facto standard solutions * +# * for microcontrollers - completely free of charge! * +# * * +# * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * +# * * +# * Thank you for using FreeRTOS, and thank you for your support! * +# * * +# *************************************************************************** +# +# +# This file is part of the FreeRTOS distribution. +# +# FreeRTOS is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License (version 2) as published by the +# Free Software Foundation AND MODIFIED BY the FreeRTOS exception. +# >>>NOTE<<< The modification to the GPL is included to allow you to +# distribute a combined work that includes FreeRTOS without being obliged to +# provide the source code for proprietary components outside of the FreeRTOS +# kernel. FreeRTOS is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. You should have received a copy of the GNU General Public +# License and the FreeRTOS license exception along with FreeRTOS; if not it +# can be viewed here: http://www.freertos.org/a00114.html and also obtained +# by writing to Richard Barry, contact details for whom are available on the +# FreeRTOS WEB site. +# +# 1 tab == 4 spaces! +# +# http://www.FreeRTOS.org - Documentation, latest information, license and +# contact details. +# +# http://www.SafeRTOS.com - A version that is certified for use in safety +# critical systems. +# +# http://www.OpenRTOS.com - Commercial support, development, porting, +# licensing and training services. +#*/ + + +#/************************************************************************* +# * Please ensure to read http://www.freertos.org/portLM3Sxxxx_Eclipse.html +# * which provides information on configuring and running this demo for the +# * various Luminary Micro EKs. +# *************************************************************************/ + +RTOS_SOURCE_DIR=../../../Source +DEMO_COMMON_DIR=../../Common/Minimal +DEMO_INCLUDE_DIR=../../Common/include +UIP_COMMON_DIR=../../Common/ethernet/uIP/uip-1.0/uip +LUMINARY_DRIVER_DIR=../../Common/drivers/LuminaryMicro + +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy +LDSCRIPT=standalone.ld + +# should use --gc-sections but the debugger does not seem to be able to cope with the option. +LINKER_FLAGS=-nostartfiles -Xlinker -oRTOSDemo.axf -Xlinker -M -Xlinker -Map=rtosdemo.map -Xlinker --no-gc-sections + +DEBUG=-g +OPTIM=-O0 + + +CFLAGS=$(DEBUG) -I . -I $(RTOS_SOURCE_DIR)/include -I $(RTOS_SOURCE_DIR)/portable/GCC/ARM_CM3 \ + -I $(DEMO_INCLUDE_DIR) -D GCC_ARMCM3_LM3S102 -D inline= -mthumb -mcpu=cortex-m3 $(OPTIM) -T$(LDSCRIPT) \ + -D PACK_STRUCT_END=__attribute\(\(packed\)\) -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -D sprintf=usprintf -D snprintf=usnprintf -D printf=uipprintf \ + -I $(UIP_COMMON_DIR) -I ./webserver -ffunction-sections -fdata-sections -I $(LUMINARY_DRIVER_DIR) + +SOURCE= main.c \ + timertest.c \ + ./ParTest/ParTest.c \ + rit128x96x4.c \ + osram128x64x4.c \ + formike128x128x16.c \ + $(LUMINARY_DRIVER_DIR)/ustdlib.c \ + $(DEMO_COMMON_DIR)/BlockQ.c \ + $(DEMO_COMMON_DIR)/blocktim.c \ + $(DEMO_COMMON_DIR)/death.c \ + $(DEMO_COMMON_DIR)/integer.c \ + $(DEMO_COMMON_DIR)/PollQ.c \ + $(DEMO_COMMON_DIR)/semtest.c \ + $(DEMO_COMMON_DIR)/GenQTest.c \ + $(DEMO_COMMON_DIR)/QPeek.c \ + $(DEMO_COMMON_DIR)/recmutex.c \ + $(DEMO_COMMON_DIR)/IntQueue.c \ + ./IntQueueTimer.c \ + ./webserver/uIP_Task.c \ + ./webserver/emac.c \ + ./webserver/httpd.c \ + ./webserver/httpd-cgi.c \ + ./webserver/httpd-fs.c \ + ./webserver/http-strings.c \ + $(UIP_COMMON_DIR)/uip_arp.c \ + $(UIP_COMMON_DIR)/psock.c \ + $(UIP_COMMON_DIR)/timer.c \ + $(UIP_COMMON_DIR)/uip.c \ + $(RTOS_SOURCE_DIR)/list.c \ + $(RTOS_SOURCE_DIR)/queue.c \ + $(RTOS_SOURCE_DIR)/tasks.c \ + $(RTOS_SOURCE_DIR)/portable/GCC/ARM_CM3/port.c \ + $(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c + +LIBS= $(LUMINARY_DRIVER_DIR)/arm-none-eabi-gcc/libdriver.a $(LUMINARY_DRIVER_DIR)/arm-none-eabi-gcc/libgr.a + +OBJS = $(SOURCE:.c=.o) + +all: RTOSDemo.bin + +RTOSDemo.bin : RTOSDemo.axf + $(OBJCOPY) RTOSDemo.axf -O binary RTOSDemo.bin + +RTOSDemo.axf : $(OBJS) startup.o Makefile + $(CC) $(CFLAGS) $(OBJS) startup.o $(LIBS) $(LINKER_FLAGS) + +$(OBJS) : %.o : %.c Makefile FreeRTOSConfig.h + $(CC) -c $(CFLAGS) $< -o $@ + +startup.o : startup.c Makefile + $(CC) -c $(CFLAGS) -O1 startup.c -o startup.o + +clean : + touch Makefile + cs-rm $(OBJS) + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c new file mode 100644 index 0000000..f7b26ef --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c @@ -0,0 +1,113 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Library includes. */ +#include "hw_types.h" +#include "gpio.h" +#include "hw_memmap.h" + + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); + GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h new file mode 100644 index 0000000..29f813f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h @@ -0,0 +1,336 @@ +#ifndef BITMAP_H +#define BITMAP_H + +#define bmpBITMAP_HEIGHT 50 +#define bmpBITMAP_WIDTH 128 + +const unsigned char pucBasicBitmap[] = +{ +0x00, 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+#endif diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/formike128x128x16.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/formike128x128x16.c new file mode 100644 index 0000000..87ff5fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/formike128x128x16.c @@ -0,0 +1,902 @@ +//***************************************************************************** +// +// formike128x128x16.c - Display driver for the Formike Electronic +// KWH015C04-F01 CSTN panel with an ST7637 controller. +// +// Copyright (c) 2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3s3748_api +//! @{ +// +//***************************************************************************** + +#include "hw_gpio.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "sysctl.h" +#include "rom.h" +#include "grlib.h" +#include "formike128x128x16.h" +#include + +//***************************************************************************** +// +// Defines for the pins that are used to communicate with the ST7637. +// +//***************************************************************************** +#define LCD_A0_BASE GPIO_PORTB_BASE +#define LCD_A0_PIN GPIO_PIN_2 +#define LCD_WR_BASE GPIO_PORTC_BASE +#define LCD_WR_PIN GPIO_PIN_4 +#define LCD_RD_BASE GPIO_PORTC_BASE +#define LCD_RD_PIN GPIO_PIN_5 +#define LCD_BL_BASE GPIO_PORTF_BASE +#define LCD_BL_PIN GPIO_PIN_1 +#define LCD_DATA_BASE GPIO_PORTG_BASE + +//***************************************************************************** +// +// Translates a 24-bit RGB color to a display driver-specific color. +// +// \param c is the 24-bit RGB color. The least-significant byte is the blue +// channel, the next byte is the green channel, and the third byte is the red +// channel. +// +// This macro translates a 24-bit RGB color into a value that can be written +// into the display's frame buffer in order to reproduce that color, or the +// closest possible approximation of that color. +// +// \return Returns the display-driver specific color. +// +//***************************************************************************** +#define DPYCOLORTRANSLATE(c) ((((c) & 0x00ff0000) >> 19) | \ + ((((c) & 0x0000ff00) >> 5) & 0x000007e0) | \ + ((((c) & 0x000000ff) << 8) & 0x0000f800)) + +//***************************************************************************** +// +// Writes a data word to the ST7637. +// +//***************************************************************************** +static void +WriteData(unsigned char ucData) +{ + // + // Write the data to the data bus. + // + HWREG(LCD_DATA_BASE + GPIO_O_DATA + (0xff << 2)) = ucData; + + // + // Assert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = 0; + + // + // Deassert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = LCD_WR_PIN; +} + +//***************************************************************************** +// +// Writes a command to the ST7637. +// +//***************************************************************************** +static void +WriteCommand(unsigned char ucData) +{ + // + // Write the command to the data bus. + // + HWREG(LCD_DATA_BASE + GPIO_O_DATA + (0xff << 2)) = ucData; + + // + // Set the A0 signal low, indicating a command. + // + HWREG(LCD_A0_BASE + GPIO_O_DATA + (LCD_A0_PIN << 2)) = 0; + + // + // Assert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = 0; + + // + // Deassert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = LCD_WR_PIN; + + // + // Set the A0 signal high, indicating that following writes are data. + // + HWREG(LCD_A0_BASE + GPIO_O_DATA + (LCD_A0_PIN << 2)) = LCD_A0_PIN; +} + +//***************************************************************************** +// +//! Initializes the display driver. +//! +//! This function initializes the ST7637 display controller on the panel, +//! preparing it to display data. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16Init(void) +{ + unsigned long ulClockMS, ulCount; + + // + // Get the value to pass to SysCtlDelay() in order to delay for 1 ms. + // + ulClockMS = SysCtlClockGet() / (3 * 1000); + + // + // Enable the GPIO peripherals used to interface to the ST7637. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); + + // + // Configure the pins that connect to the LCD as GPIO outputs. + // + GPIOPinTypeGPIOOutput(LCD_A0_BASE, LCD_A0_PIN); + GPIOPinTypeGPIOOutput(LCD_WR_BASE, LCD_WR_PIN); + GPIOPinTypeGPIOOutput(LCD_RD_BASE, LCD_RD_PIN); + GPIOPinTypeGPIOOutput(LCD_BL_BASE, LCD_BL_PIN); + GPIOPinTypeGPIOOutput(LCD_DATA_BASE, 0xff); + + // + // Set the LCD control pins to their default values. + // + GPIOPinWrite(LCD_A0_BASE, LCD_A0_PIN, LCD_A0_PIN); + GPIOPinWrite(LCD_WR_BASE, LCD_WR_PIN | LCD_RD_PIN, + LCD_WR_PIN | LCD_RD_PIN); + GPIOPinWrite(LCD_BL_BASE, LCD_BL_PIN, 0); + GPIOPinWrite(LCD_DATA_BASE, 0xff, 0x00); + + // + // Perform a software reset of the ST7637. + // + WriteCommand(0x01); + + // + // Delay for 120ms. + // + SysCtlDelay(ulClockMS * 120); + + // + // Disable auto-load of mask rom data. + // + WriteCommand(0xD7); + WriteData(0xBF); + + // + // Set the OTP control mode to read. + // + WriteCommand(0xE0); + WriteData(0x00); + + // + // Delay for 10ms. + // + SysCtlDelay(ulClockMS * 10); + + // + // Start the OTP read. + // + WriteCommand(0xE3); + + // + // Delay for 20ms. + // + SysCtlDelay(ulClockMS * 20); + + // + // Cancel the OTP read (it should have finished by now). + // + WriteCommand(0xE1); + + // + // Turn off the display. + // + WriteCommand(0x28); + + // + // Exit sleep mode. + // + WriteCommand(0x11); + + // + // Delay for 50ms. + // + SysCtlDelay(ulClockMS * 50); + + // + // Program the LCD supply voltage V0 to 14V. + // + WriteCommand(0xC0); + WriteData(0x04); + WriteData(0x01); + + // + // Select an LCD bias voltage ratio of 1/12. + // + WriteCommand(0xC3); + WriteData(0x00); + + // + // Enable the x8 booster circuit. + // + WriteCommand(0xC4); + WriteData(0x07); + + // + // Invert the column scan direction for the panel. + // + WriteCommand(0xB7); + WriteData(0xC0); + + // + // Select 16bpp, 5-6-5 data input mode. + // + WriteCommand(0x3A); + WriteData(0x05); + + // + // Select the memory scanning direction. The scanning mode does not matter + // for this driver since the row/column selects will constrain the writes + // to the desired area of the display. + // + WriteCommand(0x36); + WriteData(0x00); + + // + // Turn on the display. + // + WriteCommand(0x29); + + // + // Clear the contents of the display buffer. + // + WriteCommand(0x2A); + WriteData(0x00); + WriteData(0x7F); + WriteCommand(0x2B); + WriteData(0x01); + WriteData(0x80); + WriteCommand(0x2c); + for(ulCount = 0; ulCount < (128 * 128); ulCount++) + { + WriteData(0x00); + WriteData(0x00); + } + + // + // Enable normal operation of the LCD. + // + WriteCommand(0x13); +} + +//***************************************************************************** +// +//! Turns on the backlight. +//! +//! This function turns on the backlight on the display. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16BacklightOn(void) +{ + // + // Assert the signal that turns on the backlight. + // + HWREG(LCD_BL_BASE + GPIO_O_DATA + (LCD_BL_PIN << 2)) = LCD_BL_PIN; +} + +//***************************************************************************** +// +//! Turns off the backlight. +//! +//! This function turns off the backlight on the display. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16BacklightOff(void) +{ + // + // Deassert the signal that turns on the backlight. + // + HWREG(LCD_BL_BASE + GPIO_O_DATA + (LCD_BL_PIN << 2)) = 0; +} + +//***************************************************************************** +// +//! Draws a pixel on the screen. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the pixel. +//! \param lY is the Y coordinate of the pixel. +//! \param ulValue is the color of the pixel. +//! +//! This function sets the given pixel to a particular color. The coordinates +//! of the pixel are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16PixelDraw(void *pvDisplayData, long lX, long lY, + unsigned long ulValue) +{ + // + // Set the X address of the display cursor. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the pixel value. + // + WriteCommand(0x2c); + WriteData(ulValue >> 8); + WriteData(ulValue); +} + +//***************************************************************************** +// +//! Draws a horizontal sequence of pixels on the screen. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the first pixel. +//! \param lY is the Y coordinate of the first pixel. +//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1 +//! or 4 bit per pixel formats. +//! \param lCount is the number of pixels to draw. +//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8. +//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel +//! formats, the most significant bit(s) represent the left-most pixel. +//! \param pucPalette is a pointer to the palette used to draw the pixels. +//! +//! This function draws a horizontal sequence of pixels on the screen, using +//! the supplied palette. For 1 bit per pixel format, the palette contains +//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette +//! contains 24-bit RGB values that must be translated before being written to +//! the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16PixelDrawMultiple(void *pvDisplayData, long lX, long lY, + long lX0, long lCount, long lBPP, + const unsigned char *pucData, + const unsigned char *pucPalette) +{ + unsigned long ulByte; + + // + // Set the extent of the line along the X axis. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX + lCount - 1); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Determine how to interpret the pixel data based on the number of bits + // per pixel. + // + switch(lBPP) + { + // + // The pixel data is in 1 bit per pixel format. + // + case 1: + { + // + // Loop while there are more pixels to draw. + // + while(lCount) + { + // + // Get the next byte of image data. + // + ulByte = *pucData++; + + // + // Loop through the pixels in this byte of image data. + // + for(; (lX0 < 8) && lCount; lX0++, lCount--) + { + // + // Draw this pixel in the appropriate color. + // + lBPP = ((unsigned long *)pucPalette)[(ulByte >> + (7 - lX0)) & 1]; + WriteData(lBPP >> 8); + WriteData(lBPP); + } + + // + // Start at the beginning of the next byte of image data. + // + lX0 = 0; + } + + // + // The image data has been drawn. + // + break; + } + + // + // The pixel data is in 4 bit per pixel format. + // + case 4: + { + // + // Loop while there are more pixels to draw. "Duff's device" is + // used to jump into the middle of the loop if the first nibble of + // the pixel data should not be used. Duff's device makes use of + // the fact that a case statement is legal anywhere within a + // sub-block of a switch statement. See + // http://en.wikipedia.org/wiki/Duff's_device for detailed + // information about Duff's device. + // + switch(lX0 & 1) + { + case 0: + while(lCount) + { + // + // Get the upper nibble of the next byte of pixel data + // and extract the corresponding entry from the + // palette. + // + ulByte = (*pucData >> 4) * 3; + ulByte = (*(unsigned long *)(pucPalette + ulByte) & + 0x00ffffff); + + // + // Translate this palette entry and write it to the + // screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + + // + // Decrement the count of pixels to draw. + // + lCount--; + + // + // See if there is another pixel to draw. + // + if(lCount) + { + case 1: + // + // Get the lower nibble of the next byte of pixel + // data and extract the corresponding entry from + // the palette. + // + ulByte = (*pucData++ & 15) * 3; + ulByte = (*(unsigned long *)(pucPalette + ulByte) & + 0x00ffffff); + + // + // Translate this palette entry and write it to the + // screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + + // + // Decrement the count of pixels to draw. + // + lCount--; + } + } + } + + // + // The image data has been drawn. + // + break; + } + + // + // The pixel data is in 8 bit per pixel format. + // + case 8: + { + // + // Loop while there are more pixels to draw. + // + while(lCount--) + { + // + // Get the next byte of pixel data and extract the + // corresponding entry from the palette. + // + ulByte = *pucData++ * 3; + ulByte = *(unsigned long *)(pucPalette + ulByte) & 0x00ffffff; + + // + // Translate this palette entry and write it to the screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + } + + // + // The image data has been drawn. + // + break; + } + } +} + +//***************************************************************************** +// +//! Flushes any cached drawing operations. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! +//! This functions flushes any cached drawing operations to the display. This +//! is useful when a local frame buffer is used for drawing operations, and the +//! flush would copy the local frame buffer to the display. For the ST7637 +//! driver, the flush is a no operation. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16Flush(void *pvDisplayData) +{ + // + // There is nothing to be done. + // +} + +//***************************************************************************** +// +//! Draws a horizontal line. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX1 is the X coordinate of the start of the line. +//! \param lX2 is the X coordinate of the end of the line. +//! \param lY is the Y coordinate of the line. +//! \param ulValue is the color of the line. +//! +//! This function draws a horizontal line on the display. The coordinates of +//! the line are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16LineDrawH(void *pvDisplayData, long lX1, long lX2, long lY, + unsigned long ulValue) +{ + // + // Set the extent of the line along the X axis. + // + WriteCommand(0x2a); + WriteData(lX1); + WriteData(lX2); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels of this horizontal line. + // + while(lX1++ <= lX2) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Draws a vertical line. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the line. +//! \param lY1 is the Y coordinate of the start of the line. +//! \param lY2 is the Y coordinate of the end of the line. +//! \param ulValue is the color of the line. +//! +//! This function draws a vertical line on the display. The coordinates of the +//! line are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16LineDrawV(void *pvDisplayData, long lX, long lY1, long lY2, + unsigned long ulValue) +{ + // + // Set the X address of the display cursor. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX); + + // + // Set the extent of the line along the Y axis. + // + WriteCommand(0x2b); + WriteData(lY1 + 1); + WriteData(lY2 + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels of this vertical line. + // + while(lY1++ <= lY2) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Fills a rectangle. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param pRect is a pointer to the structure describing the rectangle. +//! \param ulValue is the color of the rectangle. +//! +//! This function fills a rectangle on the display. The coordinates of the +//! rectangle are assumed to be within the extents of the display, and the +//! rectangle specification is fully inclusive (i.e. both sXMin and sXMax are +//! drawn, along with sYMin and sYMax). +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16RectFill(void *pvDisplayData, const tRectangle *pRect, + unsigned long ulValue) +{ + long lCount; + + // + // Set the extent of the rectangle along the X axis. + // + WriteCommand(0x2a); + WriteData(pRect->sXMin); + WriteData(pRect->sXMax); + + // + // Set the extent of the rectangle along the Y axis. + // + WriteCommand(0x2b); + WriteData(pRect->sYMin + 1); + WriteData(pRect->sYMax + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels in this rectangle. + // + for(lCount = ((pRect->sXMax - pRect->sXMin + 1) * + (pRect->sYMax - pRect->sYMin + 1)); lCount > 0; lCount--) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Translates a 24-bit RGB color to a display driver-specific color. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param ulValue is the 24-bit RGB color. The least-significant byte is the +//! blue channel, the next byte is the green channel, and the third byte is the +//! red channel. +//! +//! This function translates a 24-bit RGB color into a value that can be +//! written into the display's frame buffer in order to reproduce that color, +//! or the closest possible approximation of that color. +//! +//! \return Returns the display-driver specific color. +// +//***************************************************************************** +static unsigned long +Formike128x128x16ColorTranslate(void *pvDisplayData, unsigned long ulValue) +{ + // + // Translate from a 24-bit RGB color to a 5-6-5 RGB color. + // + return(DPYCOLORTRANSLATE(ulValue)); +} + +//***************************************************************************** +// +//! The display structure that describes the driver for the Formike Electronic +//! KWH015C04-F01 CSTN panel with an ST7637 controller. +// +//***************************************************************************** +const tDisplay g_sFormike128x128x16 = +{ + sizeof(tDisplay), + 0, + 128, + 128, + Formike128x128x16PixelDraw, + Formike128x128x16PixelDrawMultiple, + Formike128x128x16LineDrawH, + Formike128x128x16LineDrawV, + Formike128x128x16RectFill, + Formike128x128x16ColorTranslate, + Formike128x128x16Flush +}; + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + + + + + + + + + + + + + + + +/* FreeRTOS.org demo wrappers. These are required so the prototypes for the +functions are the same as for the display drivers used by other evaluation +kits. */ + +static tContext sContext; + +void vFormike128x128x16Clear( void ) +{ +const tRectangle xRectangle = { 0, 0, 127, 127 }; + + GrContextForegroundSet( &sContext, ClrBlack ); + GrRectFill( &sContext, &xRectangle ); + GrContextForegroundSet(&sContext, ClrWhite); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16StringDraw( const char *pcString, unsigned long lX, unsigned long lY, unsigned char ucColor ) +{ + GrContextForegroundSet(&sContext, ClrWhite); + GrStringDraw( &sContext, pcString, strlen( pcString ), lX, lY, false ); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16Init( unsigned long ul ) +{ +tRectangle rectScreen; +const unsigned char *pcAppName = "www.FreeRTOS.org"; + + ( void ) ul; + + Formike128x128x16Init(); + Formike128x128x16BacklightOn(); + GrContextInit(&sContext, &g_sFormike128x128x16); + GrContextFontSet(&sContext, &g_sFontCmss12); + rectScreen.sXMin = 0; + + /* Fill the screen with a black rectangle. */ + rectScreen.sYMin = 0; + rectScreen.sXMax = g_sFormike128x128x16.usWidth - 1; + rectScreen.sYMax = g_sFormike128x128x16.usHeight - 1; + GrContextForegroundSet(&sContext, ClrBlack); + GrRectFill(&sContext, &rectScreen); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16ImageDraw( const unsigned char *pucImage, unsigned long ulX, unsigned long ulY, unsigned long ulWidth, unsigned long ulHeight ) +{ + GrImageDraw( &sContext, pucImage, ( long ) ulX, ( long ) ulY); +} + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/formike128x128x16.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/formike128x128x16.h new file mode 100644 index 0000000..feaec75 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/formike128x128x16.h @@ -0,0 +1,51 @@ +//***************************************************************************** +// +// formike128x128x16.h - Prototypes for the Formike Electronic KWH015C04-F01 +// display driver. +// +// Copyright (c) 2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FORMIKE128X128X16_H__ +#define __FORMIKE128X128X16_H__ + +//***************************************************************************** +// +// Prototypes for the globals exported by this driver. +// +//***************************************************************************** +extern void Formike128x128x16Init(void); +extern void Formike128x128x16BacklightOn(void); +extern void Formike128x128x16BacklightOff(void); +extern const tDisplay g_sFormike128x128x16; + +/* FreeRTOS.org demo wrappers. These are required so the prototypes for the +functions are the same as for the display drivers used by other evaluation +kits. */ +void vFormike128x128x16Clear( void ); +void vFormike128x128x16StringDraw( const char *pcString, unsigned long lX, unsigned long lY, unsigned char ucColor ); +void vFormike128x128x16Init( unsigned long ul ); +void vFormike128x128x16ImageDraw( const unsigned char *pucImage, unsigned long ulX, unsigned long ulY, unsigned long ulWidth, unsigned long ulHeight ); + +#endif // __FORMIKE128X128X16_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h new file mode 100644 index 0000000..ced7a1d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h @@ -0,0 +1,9 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +typedef struct +{ + char *pcMessage; +} xOLEDMessage; + +#endif /* LCD_MESSAGE_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c new file mode 100644 index 0000000..5054784 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c @@ -0,0 +1,459 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the OLED display by the 'OLED' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the OLED send the message on a queue to the OLED task instead of + * accessing the OLED themselves. The OLED task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" hook - This only executes every five seconds from the tick hook. + * Its main function is to check that all the standard demo tasks are still + * operational. Should any unexpected behaviour within a demo task be discovered + * the tick hook will write an error to the OLED (via the OLED task). If all the + * demo tasks are executing with their expected behaviour then the check task + * writes PASS to the OLED (again via the OLED task), as described above. + * + * "uIP" task - This is the task that handles the uIP stack. All TCP/IP + * processing is performed in this task. + */ + + + + +/************************************************************************* + * Please ensure to read http://www.freertos.org/portLM3Sxxxx_Eclipse.html + * which provides information on configuring and running this demo for the + * various Luminary Micro EKs. + *************************************************************************/ + + + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Hardware library includes. */ +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_sysctl.h" +#include "sysctl.h" +#include "gpio.h" +#include "grlib.h" +#include "rit128x96x4.h" +#include "osram128x64x4.h" +#include "formike128x128x16.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "PollQ.h" +#include "lcd_message.h" +#include "bitmap.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "IntQueue.h" + +/*-----------------------------------------------------------*/ + +/* The time between cycles of the 'check' functionality (defined within the +tick hook. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* Size of the stack allocated to the uIP task. */ +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The OLED task uses the sprintf function so requires a little more stack too. */ +#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainOLED_QUEUE_SIZE ( 3 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The period of the system clock in nano seconds. This is used to calculate +the jitter time in nano seconds. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Constants used when writing strings to the display. */ +#define mainCHARACTER_HEIGHT ( 9 ) +#define mainMAX_ROWS_128 ( mainCHARACTER_HEIGHT * 14 ) +#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) +#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) +#define mainFULL_SCALE ( 15 ) +#define ulSSI_FREQUENCY ( 3500000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The display is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the display directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vOLEDTask( void *pvParameters ); + +/* + * Configure the hardware for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Configures the high frequency timers - those used to measure the timing + * jitter while the real time kernel is executing. + */ +extern void vSetupHighFrequencyTimer( void ); + +/* + * The idle hook is used to run a test of the scheduler context switch + * mechanism. + */ +void vApplicationIdleHook( void ) __attribute__((naked)); +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the OLED task. */ +xQueueHandle xOLEDQueue; + +/* The welcome text. */ +const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; + +/* Variables used to detect the test in the idle hook failing. */ +unsigned portLONG ulIdleError = pdFALSE; + +/*-----------------------------------------------------------*/ + +/************************************************************************* + * Please ensure to read http://www.freertos.org/portLM3Sxxxx_Eclipse.html + * which provides information on configuring and running this demo for the + * various Luminary Micro EKs. + *************************************************************************/ +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by the OLED task. Messages for display on the OLED + are received via this queue. */ + xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); + + /* Create the uIP task if running on a processor that includes a MAC and + PHY. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + } + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartInterruptQueueTasks(); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Configure the high frequency interrupt used to measure the interrupt + jitter time. */ + vSetupHighFrequencyTimer(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +void prvSetupHardware( void ) +{ + /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is + a workaround to allow the PLL to operate reliably. */ + if( DEVICE_IS_REVA2 ) + { + SysCtlLDOSet( SYSCTL_LDO_2_75V ); + } + + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); + + /* Enable Port F for Ethernet LEDs + LED0 Bit 3 Output + LED1 Bit 2 Output */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); + GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); + GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static xOLEDMessage xMessage = { "PASS" }; +static unsigned portLONG ulTicksSinceLastDisplay = 0; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Called from every tick interrupt. Have enough ticks passed to make it + time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN CREATE"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN REC MUTEX"; + } + else if( ulIdleError != pdFALSE ) + { + xMessage.pcMessage = "ERROR IN HOOK"; + } + else if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN INT QUEUE"; + } + + + /* Send the message to the OLED gatekeeper for display. */ + xHigherPriorityTaskWoken = pdFALSE; + xQueueSendFromISR( xOLEDQueue, &xMessage, &xHigherPriorityTaskWoken ); + } +} +/*-----------------------------------------------------------*/ + +void vOLEDTask( void *pvParameters ) +{ +xOLEDMessage xMessage; +unsigned portLONG ulY, ulMaxY; +static portCHAR cMessage[ mainMAX_MSG_LEN ]; +extern volatile unsigned portLONG ulMaxJitter; +unsigned portBASE_TYPE uxUnusedStackOnEntry, uxUnusedStackNow; +const unsigned portCHAR *pucImage; + +/* Functions to access the OLED. The one used depends on the dev kit +being used. */ +void ( *vOLEDInit )( unsigned portLONG ) = NULL; +void ( *vOLEDStringDraw )( const portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portCHAR ) = NULL; +void ( *vOLEDImageDraw )( const unsigned portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portLONG, unsigned portLONG ) = NULL; +void ( *vOLEDClear )( void ) = NULL; + + /* Just for demo purposes. */ + uxUnusedStackOnEntry = uxTaskGetStackHighWaterMark( NULL ); + + /* Map the OLED access functions to the driver functions that are appropriate + for the evaluation kit being used. */ + switch( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) + { + case SYSCTL_DID1_PRTNO_6965 : + case SYSCTL_DID1_PRTNO_2965 : vOLEDInit = OSRAM128x64x4Init; + vOLEDStringDraw = OSRAM128x64x4StringDraw; + vOLEDImageDraw = OSRAM128x64x4ImageDraw; + vOLEDClear = OSRAM128x64x4Clear; + ulMaxY = mainMAX_ROWS_64; + pucImage = pucBasicBitmap; + break; + + case SYSCTL_DID1_PRTNO_1968 : + case SYSCTL_DID1_PRTNO_8962 : vOLEDInit = RIT128x96x4Init; + vOLEDStringDraw = RIT128x96x4StringDraw; + vOLEDImageDraw = RIT128x96x4ImageDraw; + vOLEDClear = RIT128x96x4Clear; + ulMaxY = mainMAX_ROWS_96; + pucImage = pucBasicBitmap; + break; + + default : vOLEDInit = vFormike128x128x16Init; + vOLEDStringDraw = vFormike128x128x16StringDraw; + vOLEDImageDraw = vFormike128x128x16ImageDraw; + vOLEDClear = vFormike128x128x16Clear; + ulMaxY = mainMAX_ROWS_128; + pucImage = pucGrLibBitmap; + break; + } + + ulY = ulMaxY; + + /* Initialise the OLED and display a startup message. */ + vOLEDInit( ulSSI_FREQUENCY ); + vOLEDStringDraw( "POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); + vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); + + /* Write the message on the next available row. */ + ulY += mainCHARACTER_HEIGHT; + if( ulY >= ulMaxY ) + { + ulY = mainCHARACTER_HEIGHT; + vOLEDClear(); + vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); + } + + /* Display the message along with the maximum jitter time from the + high priority time test. */ + sprintf( cMessage, "%s [%uns]", xMessage.pcMessage, ulMaxJitter * mainNS_PER_CLOCK ); + vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName ) +{ + for( ;; ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.c new file mode 100644 index 0000000..3353a82 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.c @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sx965_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "osram128x64x4.h" + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for OSRAM usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-39 on one side, 40-79 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define OSRAM_INIT_REMAP 0x52 +#define OSRAM_INIT_OFFSET 0x4C +static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from OSRAM App Note AN018. +// +//***************************************************************************** +static const unsigned char g_pucOSRAM128x64x4Init[] = +{ + // + // Column Address + // + 4, 0x15, 0, 63, 0xe3, + + // + // Row Address + // + 4, 0x75, 0, 63, 0xe3, + + // + // Contrast Control + // + 3, 0x81, 50, 0xe3, + + // + // Half Current Range + // + 2, 0x85, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Multiplex Ratio + // + 3, 0xA8, 63, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x22, 0xe3, + + // + // Row Period + // + 3, 0xB2, 70, 0xe3, + + // + // Display Clock Divide + // + 3, 0xB3, 0xF1, 0xe3, + + // + // VSL + // + 3, 0xBF, 0x0D, 0xe3, + + // + // VCOMH + // + 3, 0xBE, 0x02, 0xe3, + + // + // VP + // + 3, 0xBC, 0x10, 0xe3, + + // + // Gamma + // + 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, + + // + // Set DC-DC + 3, 0xAD, 0x03, 0xe3, + + // + // Display ON/OFF + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; + unsigned long ulRow, ulColumn; + static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; + + // + // Set the window to fill the entire display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); + OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // In vertical address increment mode, loop through each column, filling + // each row with 0. + // + for(ulColumn = 0; ulColumn < (128/2); ulColumn++) + { + // + // 8 rows (bytes) per row of text. + // + for(ulRow = 0; ulRow < 80; ulRow += 8) + { + OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + static unsigned char pucBuffer[8]; + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = 63; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + 7; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + OSRAMWriteData(pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (/e ulX) and the number of +//! columns (/e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+--3------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by` +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + static unsigned char pucBuffer[8]; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 64); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = (ulX + ulWidth - 2) / 2; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + ulHeight - 1; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, + sizeof(g_pucOSRAM128x64x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + OSRAMWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the OSRAM driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the OSRAM driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); + +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD0323 controller on the panel. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the PC7 pin as a D/Cn signal for OLED device. + // + GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD); + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Configure and enable the SSI0 port for master mode. + // + OSRAM128x64x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + OSRAM128x64x4Clear(); + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xAD, 0x02 + }; + + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.h new file mode 100644 index 0000000..2ba7cb9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical +// OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM128X64X4_H__ +#define __OSRAM128X64X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAM128x64x4Clear(void); +extern void OSRAM128x64x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAM128x64x4Init(unsigned long ulFrequency); +extern void OSRAM128x64x4Enable(unsigned long ulFrequency); +extern void OSRAM128x64x4Disable(void); +extern void OSRAM128x64x4DisplayOn(void); +extern void OSRAM128x64x4DisplayOff(void); + +//***************************************************************************** +// +// The following macro(s) map old names for the OSRAM functions to the new +// names. In new code, the new names should be used in favor of the old names. +// +//***************************************************************************** +#ifndef DEPRECATED +#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable +#endif + +#endif // __OSRAM128X64X4_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/pack_struct_end.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/pack_struct_end.h new file mode 100644 index 0000000..621c9fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/pack_struct_end.h @@ -0,0 +1,2 @@ +/* Note used by this port of uIP, but required for compilation. */ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/pack_struct_start.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/pack_struct_start.h new file mode 100644 index 0000000..621c9fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/pack_struct_start.h @@ -0,0 +1,2 @@ +/* Note used by this port of uIP, but required for compilation. */ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c new file mode 100644 index 0000000..cff38d5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c @@ -0,0 +1,981 @@ +//***************************************************************************** +// +// rit128x96x4.c - Driver for the RIT 128x96x4 graphical OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1504-conf of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sLM3S8962_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "rit128x96x4.h" + +//***************************************************************************** +// +// Macros that define the peripheral, port, and pin used for the OLEDDC +// panel control signal. +// +//***************************************************************************** + +unsigned long ulGPIOId = 0, ulGPIOBase = 0, ulOLEDDC_PIN = 0, ulOLEDEN_PIN = 0; + +#define LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOA +#define LM3S8962_GPIO_OLEDDC_BASE GPIO_PORTA_BASE +#define LM3S8962_GPIO_OLEDDC_PIN GPIO_PIN_6 +#define LM3S8962_GPIO_OLEDEN_PIN GPIO_PIN_7 + +#define LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOH +#define LM3S1968_GPIO_OLEDDC_BASE GPIO_PORTH_BASE +#define LM3S1968_GPIO_OLEDDC_PIN GPIO_PIN_2 +#define LM3S1968_GPIO_OLEDEN_PIN GPIO_PIN_3 + + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for display usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Buffer for storing sequences of command and data for the display. +// +//***************************************************************************** +static unsigned char g_pucBuffer[8]; + +//***************************************************************************** +// +// Define the SSD1329 128x96x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. Note that the controller support 128 rows while +// the RIT display only uses 96. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-63 on one side, 64-127 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-127 map to COM 127-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define RIT_INIT_REMAP 0x52 // app note says 0x51 +#define RIT_INIT_OFFSET 0x00 +static const unsigned char g_pucRIT128x96x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucRIT128x96x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD1329 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from RIT App Note for +// the P14201. Values used are from the RIT app note, except where noted. +// +//***************************************************************************** +static const unsigned char g_pucRIT128x96x4Init[] = +{ + // + // Unlock commands + // + 3, 0xFD, 0x12, 0xe3, + + // + // Display off + // + 2, 0xAE, 0xe3, + + // + // Icon off + // + 3, 0x94, 0, 0xe3, + + // + // Multiplex ratio + // + 3, 0xA8, 95, 0xe3, + + // + // Contrast + // + 3, 0x81, 0xb7, 0xe3, + + // + // Pre-charge current + // + 3, 0x82, 0x3f, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, RIT_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, RIT_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x11, 0xe3, + + // + // Frame frequency + // + 3, 0xB2, 0x23, 0xe3, + + // + // Front Clock Divider + // + 3, 0xB3, 0xe2, 0xe3, + + // + // Set gray scale table. App note uses default command: + // 2, 0xB7, 0xe3 + // This gray scale attempts some gamma correction to reduce the + // the brightness of the low levels. + // + 17, 0xB8, 1, 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 19, 22, 26, 30, 0xe3, + + // + // Second pre-charge period. App note uses value 0x04. + // + 3, 0xBB, 0x01, 0xe3, + + // + // Pre-charge voltage + // + 3, 0xBC, 0x3f, 0xe3, + + // + // Display ON + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, ulOLEDDC_PIN); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 127 }; + unsigned long ulRow, ulColumn; + + // + // Clear out the buffer used for sending bytes to the display. + *(unsigned long *)&g_pucBuffer[0] = 0; + *(unsigned long *)&g_pucBuffer[4] = 0; + + // + // Set the window to fill the entire display. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); + RITWriteCommand(pucCommand2, sizeof(pucCommand2)); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop through the rows + // + for(ulRow = 0; ulRow < 96; ulRow++) + { + // + // Loop through the columns. Each byte is two pixels, + // and the buffer hold 8 bytes, so 16 pixels are cleared + // at a time. + // + for(ulColumn = 0; ulColumn < 128; ulColumn += 8 * 2) + { + // + // Write 8 clearing bytes to the display, which will + // clear 16 pixels across. + // + RITWriteData(g_pucBuffer, sizeof(g_pucBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = 63; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + 7; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4VerticalInc, + sizeof(g_pucRIT128x96x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + g_pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + g_pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + g_pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + RITWriteData(g_pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (\e ulX) and the number of +//! columns (\e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 96); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = (ulX + ulWidth - 2) / 2; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + ulHeight - 1; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + RITWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the RIT driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the RIT driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD1329 controller on the panel. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + + /* Determine which board is being used. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + /* Ethernet is present, we must be using the LM3S8962 EK. */ + ulGPIOId = LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S8962_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_6; + ulOLEDEN_PIN = GPIO_PIN_7; + } + else + { + /* Ethernet is not present, we must be using the LM3S1968 EK. */ + ulGPIOId = LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S1968_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_2; + ulOLEDEN_PIN = GPIO_PIN_3; + } + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(ulGPIOId); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the GPIO port pin used as a D/Cn signal for OLED device, + // and the port pin used to enable power to the OLED panel. + // + GPIOPinTypeGPIOOutput(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN); + GPIOPadConfigSet(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + ulOLEDDC_PIN | ulOLEDEN_PIN); + + // + // Configure and enable the SSI0 port for master mode. + // + RIT128x96x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + RIT128x96x4Clear(); + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xe3 + }; + + // + // Put the display to sleep. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld new file mode 100644 index 0000000..3511144 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 1392 of the Stellaris Peripheral Driver Library. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c new file mode 100644 index 0000000..b987b2c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c @@ -0,0 +1,251 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1392 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vPortSVCHandler( void ); +extern void Timer0IntHandler( void ); +extern void vT2InterruptHandler( void ); +extern void vT3InterruptHandler( void ); +extern void vEMAC_ISR(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 120 +#endif +static unsigned long pulStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex-M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + vPortSVCHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + Timer0IntHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + vT2InterruptHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + vT3InterruptHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + 0, // Reserved + vEMAC_ISR, // Ethernet + IntDefaultHandler // Hibernate +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied main() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// A dummy printf function to satisfy the calls to printf from uip. This +// avoids pulling in the run-time library. +// +//***************************************************************************** +int +uipprintf(const char *fmt, ...) +{ + return(0); +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c new file mode 100644 index 0000000..7ee6d5e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c @@ -0,0 +1,176 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* High speed timer test as described in main.c. */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 0 ) + +/* Misc defines. */ +#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) +#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) + +/*-----------------------------------------------------------*/ + +/* Interrupt handler in which the jitter is measured. */ +void Timer0IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +volatile unsigned portLONG ulMaxJitter = 0UL; + +/* Counts the total number of times that the high frequency timer has 'ticked'. +This value is used by the run time stats function to work out what percentage +of CPU time each task is taking. */ +volatile unsigned portLONG ulHighFrequencyTimerTicks = 0UL; +/*-----------------------------------------------------------*/ + +void vSetupHighFrequencyTimer( void ) +{ +unsigned long ulFrequency; + + /* Timer zero is used to generate the interrupts, and timer 1 is used + to measure the jitter. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); + TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupt to be above the kernel - highest. */ + IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); + + /* Just used to measure time. */ + TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); + + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + + /* The rate at which the timer will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; + TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER0A ); + TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER0_BASE, TIMER_A ); + TimerEnable( TIMER1_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void Timer0IntHandler( void ) +{ +unsigned portLONG ulDifference; +volatile unsigned portLONG ulCurrentCount; +static unsigned portLONG ulMaxDifference = 0, ulLastCount = 0; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. */ + ulCurrentCount = timerTIMER_1_COUNT_VALUE; + + TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); + + if( ulCurrentCount < ulLastCount ) + { + /* How many times has timer 1 counted since the last interrupt? */ + ulDifference = ulLastCount - ulCurrentCount; + + /* Is this the largest difference we have measured yet? */ + if( ulDifference > ulMaxDifference ) + { + ulMaxDifference = ulDifference; + ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; + } + } + + ulLastCount = ulCurrentCount; + + /* Keep a count of the total number of 20KHz ticks. This is used by the + run time stats functionality to calculate how much CPU time is used by + each task. */ + ulHighFrequencyTimerTicks++; +} + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/Makefile.webserver b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/Makefile.webserver new file mode 100644 index 0000000..f38c47a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/clock-arch.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/clock-arch.h new file mode 100644 index 0000000..cde657b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c new file mode 100644 index 0000000..69e8ec6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c @@ -0,0 +1,313 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" + +/* Demo includes. */ +#include "emac.h" + +/* uIP includes. */ +#include "uip.h" + +/* Hardware library includes. */ +#include "hw_types.h" +#include "hw_memmap.h" +#include "hw_ints.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "interrupt.h" + +#define emacNUM_RX_BUFFERS 5 +#define emacFRAM_SIZE_BYTES 2 +#define macNEGOTIATE_DELAY 2000 +#define macWAIT_SEND_TIME ( 10 ) + +/* The task that handles the MAC peripheral. This is created at a high +priority and is effectively a deferred interrupt handler. The peripheral +handling is deferred to a task to prevent the entire FIFO having to be read +from within an ISR. */ +void vMACHandleTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used to wake the uIP task when data arrives. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +/* The semaphore used to wake the interrupt handler task. The peripheral +is processed at the task level to prevent the need to read the entire FIFO from +within the ISR itself. */ +xSemaphoreHandle xMACInterruptSemaphore = NULL; + +/* The buffer used by the uIP stack. In this case the pointer is used to +point to one of the Rx buffers. */ +unsigned portCHAR *uip_buf; + +/* Buffers into which Rx data is placed. */ +static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ]; + +/* The length of the data within each of the Rx buffers. */ +static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ]; + +/* Used to keep a track of the number of bytes to transmit. */ +static unsigned portLONG ulNextTxSpace; + +/*-----------------------------------------------------------*/ + +portBASE_TYPE vInitEMAC( void ) +{ +unsigned long ulTemp; +portBASE_TYPE xReturn; + + /* Ensure all interrupts are disabled. */ + EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); + + /* Clear any interrupts that were already pending. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Initialise the MAC and connect. */ + EthernetInit( ETH_BASE ); + EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); + EthernetEnable( ETH_BASE ); + + /* Mark each Rx buffer as empty. */ + for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) + { + ulRxLength[ ulTemp ] = 0; + } + + /* Create the queue and task used to defer the MAC processing to the + task level. */ + vSemaphoreCreateBinary( xMACInterruptSemaphore ); + xSemaphoreTake( xMACInterruptSemaphore, 0 ); + xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + vTaskDelay( macNEGOTIATE_DELAY ); + + /* We are only interested in Rx interrupts. */ + IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_ETH ); + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) +{ +static unsigned long ulNextRxBuffer = 0; +unsigned int iLen; + + iLen = ulRxLength[ ulNextRxBuffer ]; + + if( iLen != 0 ) + { + /* Leave room for the size at the start of the buffer. */ + uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + + ulRxLength[ ulNextRxBuffer ] = 0; + + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + return iLen; +} +/*-----------------------------------------------------------*/ + +void vInitialiseSend( void ) +{ + /* Set the index to the first byte to send - skipping over the size + bytes. */ + ulNextTxSpace = 2; +} +/*-----------------------------------------------------------*/ + +void vIncrementTxLength( unsigned portLONG ulLength ) +{ + ulNextTxSpace += ulLength; +} +/*-----------------------------------------------------------*/ + +void vSendBufferToMAC( void ) +{ +unsigned long *pulSource; +unsigned portSHORT * pus; +unsigned portLONG ulNextWord; + + /* Locate the data to be send. */ + pus = ( unsigned portSHORT * ) uip_buf; + + /* Add in the size of the data. */ + pus--; + *pus = ulNextTxSpace; + + /* Wait for data to be sent if there is no space immediately. */ + while( !EthernetSpaceAvail( ETH_BASE ) ) + { + vTaskDelay( macWAIT_SEND_TIME ); + } + + pulSource = ( unsigned portLONG * ) pus; + + for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) ) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; + pulSource++; + } + + /* Go. */ + HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR( void ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; +unsigned portLONG ulTemp; + + /* Clear the interrupt. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Was it an Rx interrupt? */ + if( ulTemp & ETH_INT_RX ) + { + xSemaphoreGiveFromISR( xMACInterruptSemaphore, &xHigherPriorityTaskWoken ); + EthernetIntDisable( ETH_BASE, ETH_INT_RX ); + } + + /* Switch to the uIP task. */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +void vMACHandleTask( void *pvParameters ) +{ +unsigned long ulLen = 0, i; +unsigned portLONG ulLength, ulInt; +unsigned long *pulBuffer; +static unsigned portLONG ulNextRxBuffer = 0; +portBASE_TYPE xSwitchRequired = pdFALSE; + + for( ;; ) + { + /* Wait for something to do. */ + xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); + + while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) + { + ulLength = HWREG( ETH_BASE + MAC_O_DATA ); + + /* Leave room at the start of the buffer for the size. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + *pulBuffer = ( ulLength >> 16 ); + + /* Get the size of the data. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); + ulLength &= 0xFFFF; + + if( ulLength > 4 ) + { + ulLength -= 4; + + if( ulLength >= UIP_BUFSIZE ) + { + /* The data won't fit in our buffer. Ensure we don't + try to write into the buffer. */ + ulLength = 0; + } + + /* Read out the data into our buffer. */ + for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) ) + { + *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); + pulBuffer++; + } + + /* Store the length of the data into the separate array. */ + ulRxLength[ ulNextRxBuffer ] = ulLength; + + /* Use the next buffer the next time through. */ + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + + /* Ensure the uIP task is not blocked as data has arrived. */ + xSemaphoreGive( xEMACSemaphore ); + } + } + + EthernetIntEnable( ETH_BASE, ETH_INT_RX ); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.h new file mode 100644 index 0000000..a49b598 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.h @@ -0,0 +1,322 @@ +/*---------------------------------------------------------------------------- + * LPC2378 Ethernet Definitions + *---------------------------------------------------------------------------- + * Name: EMAC.H + * Purpose: Philips LPC2378 EMAC hardware definitions + *---------------------------------------------------------------------------- + * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#ifndef __EMAC_H +#define __EMAC_H + +/* MAC address definition. The MAC address must be unique on the network. */ +#define emacETHADDR0 0 +#define emacETHADDR1 0xbd +#define emacETHADDR2 0x33 +#define emacETHADDR3 0x02 +#define emacETHADDR4 0x64 +#define emacETHADDR5 0x24 + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x7FE00000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#undef SUPP_SPEED /* Remove compiler warning. */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#undef MCMD_READ /* Remove compiler warning. */ +#define MCMD_READ 0x00000001 /* MII Read */ +#undef MCMD_SCAN /* Remove compiler warning. */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#undef MIND_BUSY /* Remove compiler warning. */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +// prototypes +portBASE_TYPE vInitEMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void vIncrementTxLength(unsigned long ulLength); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void vInitialiseSend(void); +unsigned int Rdy4Tx(void); +void vSendBufferToMAC(void); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings new file mode 100644 index 0000000..0d3c30c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.c new file mode 100644 index 0000000..ef7a41c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.h new file mode 100644 index 0000000..acbe7e1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.c new file mode 100644 index 0000000..5a5ce9b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.c @@ -0,0 +1,293 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(run, "run-time", run_time ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &run, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus; +extern unsigned long uxParTestGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + if( uxParTestGetLED( 0 ) ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, + "LED"\ + "

"\ + "", + pcStatus ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskGetRunTimeStats( signed char *pcWriteBuffer ); +static unsigned short +generate_runtime_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskGetRunTimeStats( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(run_time(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_runtime_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.h new file mode 100644 index 0000000..7ae9283 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.c new file mode 100644 index 0000000..dc4aef0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.h new file mode 100644 index 0000000..b594eea --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/404.html b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/404.html new file mode 100644 index 0000000..43e7f4c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.html b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.html new file mode 100644 index 0000000..4937dc6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml new file mode 100644 index 0000000..29d242c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml new file mode 100644 index 0000000..fd0697d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". + + +

+

+%! led-io +

+ +

+

+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/runtime.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/runtime.shtml new file mode 100644 index 0000000..67cae46 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/runtime.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Run-time statistics

+Page will refresh every 2 seconds.

+

Task            Abs Time      % Time
****************************************

+%! run-time
+
+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml new file mode 100644 index 0000000..d95a693 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+ +
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml new file mode 100644 index 0000000..4105367 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.c new file mode 100644 index 0000000..7348902 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.c @@ -0,0 +1,557 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, + 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, + 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, + 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, 0x65, 0x6e, + 0x74, 0x65, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, + 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, + 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 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0x72, 0x74, 0x6f, 0x73, 0x2e, 0x6f, 0x72, 0x67, + 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, + 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, 0x6f, 0x6d, 0x65, + 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, + 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, + 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6f, 0x2e, + 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x49, 0x4f, 0x3c, + 0x2f, 0x61, 0x3e, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, + 0x3e, 0xa, 0x3c, 0x68, 0x72, 0x3e, 0xa, 0x3c, 0x62, 0x72, + 0x3e, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, + 0x6f, 0x72, 0x6b, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, + 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, + 0xa, 0x3c, 0x70, 0x3e, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, + 0x65, 0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, + 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, + 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, + 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, + 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, + 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, + 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, + 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, + 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, + 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, 0x21, + 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, 0x65, + 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xa, 0x3c, 0x2f, 0x70, + 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, + 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, 0x3c, + 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, + 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_runtime_shtml[] = {{file_io_shtml, data_runtime_shtml, data_runtime_shtml + 15, sizeof(data_runtime_shtml) - 15}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_runtime_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 7 diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.h new file mode 100644 index 0000000..52d35c2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.c new file mode 100644 index 0000000..644cf16 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.h new file mode 100644 index 0000000..7f7a666 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makefsdata b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makefsdata new file mode 100644 index 0000000..8d2715a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makestrings b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makestrings new file mode 100644 index 0000000..8a13c6d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c new file mode 100644 index 0000000..6315c9c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c @@ -0,0 +1,338 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +#include "lcd_message.h" + +/* uip includes. */ +#include "hw_types.h" + +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "hw_memmap.h" +#include "lmi_flash.h" +#include "sysctl.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" + +/*-----------------------------------------------------------*/ + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 19 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} + + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR )( void ); + + /* Enable/Reset the Ethernet Controller */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); + SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + while( vInitEMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + prvSetMACAddress(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + vInitialiseSend(); + vIncrementTxLength( uip_len ); + vSendBufferToMAC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +unsigned portLONG ulUser0, ulUser1; +unsigned char pucMACArray[8]; +struct uip_eth_addr xAddr; + + /* Get the device MAC address from flash */ + FlashUserGet(&ulUser0, &ulUser1); + + /* Convert the MAC address from flash into sequence of bytes. */ + pucMACArray[0] = ((ulUser0 >> 0) & 0xff); + pucMACArray[1] = ((ulUser0 >> 8) & 0xff); + pucMACArray[2] = ((ulUser0 >> 16) & 0xff); + pucMACArray[3] = ((ulUser1 >> 0) & 0xff); + pucMACArray[4] = ((ulUser1 >> 8) & 0xff); + pucMACArray[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the MAC address. */ + EthernetMACAddrSet(ETH_BASE, pucMACArray); + + xAddr.addr[ 0 ] = pucMACArray[0]; + xAddr.addr[ 1 ] = pucMACArray[1]; + xAddr.addr[ 2 ] = pucMACArray[2]; + xAddr.addr[ 3 ] = pucMACArray[3]; + xAddr.addr[ 4 ] = pucMACArray[4]; + xAddr.addr[ 5 ] = pucMACArray[5]; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static portCHAR cMessageForDisplay[ 32 ]; +extern xQueueHandle xOLEDQueue; +xOLEDMessage xOLEDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 0, 1 ); + } + else + { + vParTestSetLED( 0, 0 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xOLEDMessage.pcMessage = cMessageForDisplay; + xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uip-conf.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uip-conf.h new file mode 100644 index 0000000..664077d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1500 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#define UIP_CONF_EXTERNAL_BUFFER + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/webserver.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/webserver.h new file mode 100644 index 0000000..1acb290 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg new file mode 100644 index 0000000..8f2b3ed --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg @@ -0,0 +1,28 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface ft2232 +ft2232_device_desc "Stellaris Evaluation Board A" +ft2232_layout evb_lm3s811 +ft2232_vid_pid 0x0403 0xbcd9 +jtag_speed 40 +#LM3S811 Evaluation Board has only srst +reset_config srst_only separate + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup attach +#target +#target arm7tdmi +target cortex_m3 little run_and_halt 0 +# 4k working area at base of ram +working_area 0 0x20000800 0x1200 nobackup +#target_script 0 reset ../doc/scripts/evb_lm3s811_test.script + +#flash configuration +flash bank stellaris 0 0 0 0 0 diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg new file mode 100644 index 0000000..28ffaea --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg @@ -0,0 +1,34 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface ft2232 +ft2232_device_desc "Stellaris Evaluation Board A" +ft2232_layout evb_lm3s811 +ft2232_vid_pid 0x0403 0xbcd9 +jtag_speed 40 +#LM3S811 Evaluation Board has only srst +reset_config srst_only separate + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset +#target +#target arm7tdmi +target cortex_m3 little run_and_init 0 +# 4k working area at base of ram +working_area 0 0x20000800 0x1200 nobackup +#target_script 0 reset ../doc/scripts/evb_lm3s811_test.script + +target_script 0 reset program.script + + +#flash configuration +flash bank stellaris 0 0 0 0 0 + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/program.script b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/program.script new file mode 100644 index 0000000..314624b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Eclipse/program.script @@ -0,0 +1,17 @@ +halt +sleep 200 +wait_halt +flash probe 0 +#sleep 500 +flash info 0 +#sleep 500 +#flash protect 0 0 31 off +#sleep 500 +flash erase 0 0 255 +sleep 200 +flash write 0 ./RTOSDemo/RTOSDemo.bin 0 +sleep 200 +reset run +shutdown + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Backup of RTOSDemo.ewd b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Backup of RTOSDemo.ewd new file mode 100644 index 0000000..1d3a442 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Backup of RTOSDemo.ewd @@ -0,0 +1,586 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Backup of RTOSDemo.ewp b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Backup of RTOSDemo.ewp new file mode 100644 index 0000000..a0a8e38 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Backup of RTOSDemo.ewp @@ -0,0 +1,947 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo files + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\QPeek.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\timertest.c + + + + Library files + + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\IAR\driverlib.r79 + + + $PROJ_DIR$\osram128x64x4.c + + + $PROJ_DIR$\rit128x96x4.c + + + + Scheduler files + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System files + + $PROJ_DIR$\startup_ewarm.c + + + + uIP files + + $PROJ_DIR$\webserver\emac.c + + + $PROJ_DIR$\webserver\http-strings.c + + + $PROJ_DIR$\webserver\httpd-cgi.c + + + $PROJ_DIR$\webserver\httpd-fs.c + + + $PROJ_DIR$\webserver\httpd.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + + + $PROJ_DIR$\webserver\uIP_Task.c + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Exe/RTOSDemo.out b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Exe/RTOSDemo.out new file mode 100644 index 0000000..51ee890 Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Exe/RTOSDemo.out differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Exe/RTOSDemo.sim b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Exe/RTOSDemo.sim new file mode 100644 index 0000000..640164d Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Exe/RTOSDemo.sim differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/BlockQ.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/BlockQ.pbi new file mode 100644 index 0000000..dcca4c1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/BlockQ.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 16s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/GenQTest.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/GenQTest.pbi new file mode 100644 index 0000000..f520d85 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/GenQTest.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 17s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\GenQTest.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\GenQTest.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/ParTest.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/ParTest.pbi new file mode 100644 index 0000000..70657dc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/ParTest.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 18s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ParTest\ParTest.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ParTest\ParTest.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/PollQ.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/PollQ.pbi new file mode 100644 index 0000000..03ca0a5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/PollQ.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 19s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\PollQ.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\PollQ.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/QPeek.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/QPeek.pbi new file mode 100644 index 0000000..63930bc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/QPeek.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 19s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\QPeek.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\QPeek.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/RTOSDemo.pbd b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/RTOSDemo.pbd new file mode 100644 index 0000000..d4563ba --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/RTOSDemo.pbd @@ -0,0 +1,32 @@ +This is an internal working file generated by the Source Browser. +08:43 51s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\BlockQ.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\GenQTest.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ParTest.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\PollQ.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\QPeek.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\blocktim.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\death.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\emac.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\flash.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\heap_2.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\http-strings.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\httpd-cgi.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\httpd-fs.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\httpd.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\integer.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\list.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\main.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\osram128x64x4.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\port.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\psock.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\queue.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\rit128x96x4.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\semtest.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\startup_ewarm.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\tasks.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\timer.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\timertest.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\uIP_Task.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\uip.pbi +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\uip_arp.pbi diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/blocktim.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/blocktim.pbi new file mode 100644 index 0000000..f9c643e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/blocktim.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 16s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\blocktim.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\blocktim.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/death.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/death.pbi new file mode 100644 index 0000000..6a62956 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/death.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 17s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\death.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\death.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/emac.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/emac.pbi new file mode 100644 index 0000000..08372c0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/emac.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 39s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\emac.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\emac.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/flash.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/flash.pbi new file mode 100644 index 0000000..d2e6e1b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/flash.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 17s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\flash.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\flash.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/heap_2.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/heap_2.pbi new file mode 100644 index 0000000..ae068e3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/heap_2.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 20s +C:\home\dwilson\dev\FreeRTOS\Source\portable\MemMang\heap_2.c +C:\home\dwilson\dev\FreeRTOS\Source\portable\MemMang\heap_2.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/http-strings.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/http-strings.pbi new file mode 100644 index 0000000..5733b96 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/http-strings.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 39s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\http-strings.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\http-strings.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd-cgi.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd-cgi.pbi new file mode 100644 index 0000000..73bd264 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd-cgi.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 39s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\httpd-cgi.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\httpd-cgi.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd-fs.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd-fs.pbi new file mode 100644 index 0000000..bb1e976 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd-fs.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 40s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\httpd-fs.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\httpd-fs.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd.pbi new file mode 100644 index 0000000..9bc502d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/httpd.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 40s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\httpd.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\httpd.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/integer.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/integer.pbi new file mode 100644 index 0000000..56ecedd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/integer.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 18s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\integer.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\integer.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/list.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/list.pbi new file mode 100644 index 0000000..77b5077 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/list.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 21s +C:\home\dwilson\dev\FreeRTOS\Source\list.c +C:\home\dwilson\dev\FreeRTOS\Source\list.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/main.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/main.pbi new file mode 100644 index 0000000..b3e83de --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/main.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 18s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\main.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\main.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/osram128x64x4.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/osram128x64x4.pbi new file mode 100644 index 0000000..d86afb3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/osram128x64x4.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 20s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\osram128x64x4.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\osram128x64x4.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/port.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/port.pbi new file mode 100644 index 0000000..e102f0e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/port.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 37s +C:\home\dwilson\dev\FreeRTOS\Source\portable\IAR\ARM_CM3\port.c +C:\home\dwilson\dev\FreeRTOS\Source\portable\IAR\ARM_CM3\port.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/psock.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/psock.pbi new file mode 100644 index 0000000..8f09fb1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/psock.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 40s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\psock.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\psock.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/queue.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/queue.pbi new file mode 100644 index 0000000..dac592b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/queue.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 38s +C:\home\dwilson\dev\FreeRTOS\Source\queue.c +C:\home\dwilson\dev\FreeRTOS\Source\queue.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/rit128x96x4.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/rit128x96x4.pbi new file mode 100644 index 0000000..54087a1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/rit128x96x4.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 20s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\rit128x96x4.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\rit128x96x4.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/semtest.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/semtest.pbi new file mode 100644 index 0000000..3c27b78 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/semtest.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 19s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\semtest.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\Minimal\semtest.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/startup_ewarm.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/startup_ewarm.pbi new file mode 100644 index 0000000..e88c578 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/startup_ewarm.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 51s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\startup_ewarm.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\startup_ewarm.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/tasks.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/tasks.pbi new file mode 100644 index 0000000..00ddacc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/tasks.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 38s +C:\home\dwilson\dev\FreeRTOS\Source\tasks.c +C:\home\dwilson\dev\FreeRTOS\Source\tasks.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timer.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timer.pbi new file mode 100644 index 0000000..a7a0a22 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timer.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 40s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\timer.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\timer.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timertest.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timertest.pbi new file mode 100644 index 0000000..a6ce4bc --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/timertest.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 19s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\timertest.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\timertest.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uIP_Task.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uIP_Task.pbi new file mode 100644 index 0000000..5b785e1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uIP_Task.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 41s +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\uIP_Task.c +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\uIP_Task.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip.pbi new file mode 100644 index 0000000..21ebc05 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 41s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\uip.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\uip.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip_arp.pbi b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip_arp.pbi new file mode 100644 index 0000000..b717d61 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/uip_arp.pbi @@ -0,0 +1,38 @@ +This is an internal working file generated by the Source Browser. +08:43 41s +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c +C:\home\dwilson\dev\FreeRTOS\Demo\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c +-D +IAR_ARMCM3_LM +-D +PACK_STRUCT_END= +--diag_suppress +pa082,pe513,pe167,pe550,pe144,pe191,pe177,pa039,pa050 +-o +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ +--no_unroll +--no_inline +--no_tbaa +--no_clustering +--no_scheduling +--debug +--endian=little +--cpu=Cortex-M3 +-e +--fpu=None +--dlib_config +C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\INC\c\DLib_Config_Normal.h +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\drivers\LuminaryMicro\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\common\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\..\source\include\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\ +-I +C:\home\dwilson\dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\..\Common\ethernet\uIP\uip-1.0\uip\ +-Om +--use_c++_inline diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h new file mode 100644 index 0000000..84f5fa3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h @@ -0,0 +1,148 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 50000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 1 + +#define configMAX_PRIORITIES ( 5UL ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) +#define configQUEUE_REGISTRY_SIZE 10 + +/* Timer related defines. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_pcTaskGetTaskName 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +#define configKERNEL_INTERRUPT_PRIORITY ( 7 << 5 ) /* Priority 7, or 255 as only the top three bits are implemented. This is the lowest priority. */ +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << 5 ) /* Priority 5, or 160 as only the top three bits are implemented. */ + +/* Use the Cortex-M3 optimised task selection rather than the generic C code +version. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + +#ifdef __ICCARM__ + void vAssertCalled( const char *pcFile, unsigned long ulLine ); + #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); +#endif + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.c new file mode 100644 index 0000000..5d360cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.c @@ -0,0 +1,133 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +#define tmrTIMER_2_FREQUENCY ( 2000UL ) +#define tmrTIMER_3_FREQUENCY ( 2001UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ +unsigned long ulFrequency; + + /* Timer 2 and 3 are utilised for this test. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER2 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER3 ); + TimerConfigure( TIMER2_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER3_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + IntPrioritySet( INT_TIMER2A, configMAX_SYSCALL_INTERRUPT_PRIORITY + ( 1 << 5 ) ); /* Shift left 5 as only the top 3 bits are implemented. */ + IntPrioritySet( INT_TIMER3A, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + + /* The rate at which the timers will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY; + TimerLoadSet( TIMER2_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER2A ); + TimerIntEnable( TIMER2_BASE, TIMER_TIMA_TIMEOUT ); + + /* The rate at which the timers will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_3_FREQUENCY; + TimerLoadSet( TIMER3_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER3A ); + TimerIntEnable( TIMER3_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER2_BASE, TIMER_A ); + TimerEnable( TIMER3_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void vT2InterruptHandler( void ) +{ + TimerIntClear( TIMER2_BASE, TIMER_TIMA_TIMEOUT ); + portEND_SWITCHING_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +void vT3InterruptHandler( void ) +{ + TimerIntClear( TIMER3_BASE, TIMER_TIMA_TIMEOUT ); + portEND_SWITCHING_ISR( xSecondTimerHandler() ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.h new file mode 100644 index 0000000..83edd5d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf new file mode 100644 index 0000000..575329d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// enet_lwip.icf - Linker configuration file for enet_lwip. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0003ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x2000ffff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c new file mode 100644 index 0000000..f7b26ef --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c @@ -0,0 +1,113 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Library includes. */ +#include "hw_types.h" +#include "gpio.h" +#include "hw_memmap.h" + + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); + GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2.bak b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2.bak new file mode 100644 index 0000000..cbc6fdb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2.bak @@ -0,0 +1,138 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' + +Group (Demo_Source) +Group (Libraries) +Group (RTOS_Source) +Group (uIP_Source) + +File 1,1,<..\Common\Minimal\BlockQ.c> +File 1,1,<..\Common\Minimal\blocktim.c> +File 1,1,<..\Common\Minimal\death.c> +File 1,1,<..\Common\Minimal\integer.c> +File 1,1,<.\main.c> +File 1,1,<.\ParTest\ParTest.c> +File 1,1,<..\Common\Minimal\PollQ.c> +File 1,1,<..\Common\Minimal\semtest.c> +File 1,2,<.\startup_rvmdk.S> +File 1,1,<.\timertest.c> +File 1,5,<.\FreeRTOSConfig.h> +File 1,1,<..\Common\Minimal\GenQTest.c> +File 1,1,<..\Common\Minimal\QPeek.c> +File 1,1,<.\IntQueueTimer.c> +File 1,1,<..\Common\Minimal\IntQueue.c> +File 1,1,<..\Common\Minimal\recmutex.c> +File 2,1,<.\rit128x96x4.c> +File 2,1,<.\osram128x64x4.c> +File 2,4,<..\Common\drivers\LuminaryMicro\Keil\driverlib.lib> +File 2,1,<.\formike128x128x16.c> +File 2,4,<..\Common\drivers\LuminaryMicro\Keil\grlib.lib> +File 3,1,<..\..\Source\tasks.c> +File 3,1,<..\..\Source\list.c> +File 3,1,<..\..\Source\queue.c> +File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +File 3,1,<..\..\Source\portable\MemMang\heap_2.c> +File 4,1,<.\webserver\uIP_Task.c> +File 4,1,<.\webserver\emac.c> +File 4,1,<.\webserver\httpd.c> +File 4,1,<.\webserver\httpd-cgi.c> +File 4,1,<.\webserver\httpd-fs.c> +File 4,1,<.\webserver\http-strings.c> +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c> +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c> +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c> +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c> + + +Options 1,0,0 // Target 'FreeRTOS_Demo' + Device (LM3S8962) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) + DevID (4285) + Rgf (LM3Sxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\rvmdk\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\rvmdk\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 1 + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } + OCMADSIROM { 1,0,0,0,0,0,0,4,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 5,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC (--diag_suppress 191,550,513,167,177,144) + ADSCDEFN (RVDS_ARMCM3_LM3S102, "PACK_STRUCT_END=","ALIGN_STRUCT_END=") + ADSCUDEF () + ADSCINCD (.;.\..\Common\drivers\LuminaryMicro;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;..\Common\ethernet\uIP\uip-1.0\uip;.\webserver) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S8962)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S8962) + OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + FLASH1 { 1,0,0,0,1,0,0,0,3,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\lmidk-agdi.dll) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep new file mode 100644 index 0000000..68371b3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep @@ -0,0 +1,990 @@ + + + + 2 + 864588464 + + Debug + + $TOOLKIT_DIR$\inc\c\stdio.h + $TOOLKIT_DIR$\inc\c\ystdio.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\Debug\Obj\main.o + $PROJ_DIR$\Debug\Obj\uip_arp.pbi + $PROJ_DIR$\Debug\Obj\blocktim.o + $PROJ_DIR$\LuminaryDrivers\hw_types.h + $PROJ_DIR$\Debug\Obj\death.o + $PROJ_DIR$\LuminaryDrivers\ssi.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_sysctl.h + $PROJ_DIR$\Debug\Obj\QPeek.pbi + $PROJ_DIR$\Debug\Obj\psock.pbi + $PROJ_DIR$\Debug\Obj\port.o + $PROJ_DIR$\Debug\Obj\pdc.pbi + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\timer.h + $PROJ_DIR$\Debug\Obj\PollQ.pbi + $PROJ_DIR$\Debug\Obj\uip.r79 + $PROJ_DIR$\Debug\Obj\psock.r79 + $PROJ_DIR$\Debug\Obj\uIP_Task.r79 + $PROJ_DIR$\Debug\Obj\list.r79 + $PROJ_DIR$\Debug\Obj\timer.pbi + $PROJ_DIR$\Debug\Obj\startup_ewarm.pbi + $PROJ_DIR$\..\Common\include\flash.h + $PROJ_DIR$\Debug\Obj\uip.pbi + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.h + $PROJ_DIR$\webserver\webserver.h + $PROJ_DIR$\Debug\Obj\ParTest.r79 + $PROJ_DIR$\Debug\Obj\portasm.r79 + $PROJ_DIR$\Debug\Obj\death.r79 + $PROJ_DIR$\Debug\Obj\heap_2.r79 + $PROJ_DIR$\..\Common\include\semtest.h + $PROJ_DIR$\Debug\Obj\httpd-cgi.r79 + $PROJ_DIR$\Debug\Obj\integer.pbi + $PROJ_DIR$\..\Common\include\death.h + $PROJ_DIR$\Debug\Obj\rit128x96x4.pbi + $PROJ_DIR$\LuminaryDrivers\pdc.c + $PROJ_DIR$\Debug\Obj\httpd-cgi.pbi + $PROJ_DIR$\..\Common\include\integer.h + $PROJ_DIR$\..\..\Source\include\portable.h + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.h + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\pt.h + $PROJ_DIR$\LuminaryDrivers\gpio.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\lmi_flash.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_ssi.h + $PROJ_DIR$\ParTest\ParTest.c + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\clock.h + $PROJ_DIR$\LuminaryDrivers\sysctl.h + $PROJ_DIR$\webserver\httpd.h + $PROJ_DIR$\Debug\Obj\flash.r79 + $PROJ_DIR$\webserver\httpd-fsdata.h + $PROJ_DIR$\Debug\Obj\uip_arp.r79 + $PROJ_DIR$\Debug\Obj\main.r79 + $PROJ_DIR$\..\Common\include\blocktim.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\lmi_timer.h + $PROJ_DIR$\..\..\Source\include\croutine.h + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uipopt.h + $PROJ_DIR$\Debug\Obj\osram128x64x4.pbi + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_memmap.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\rit128x96x4.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\ethernet.h + $PROJ_DIR$\Debug\Obj\death.pbi + $PROJ_DIR$\..\..\Source\include\projdefs.h + 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$PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\IntQueueTimer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\QPeek.c + + + $PROJ_DIR$\..\Common\Minimal\QueueSet.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\timertest.c + + + + Library files + + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\IAR\driverlib.a + + + $PROJ_DIR$\formike128x128x16.c + + + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\IAR\grlib.a + + + $PROJ_DIR$\osram128x64x4.c + + + $PROJ_DIR$\rit128x96x4.c + + + + Scheduler files + + $PROJ_DIR$\..\..\Source\croutine.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + System files + + $PROJ_DIR$\startup_ewarm.c + + + + uIP files + + $PROJ_DIR$\webserver\emac.c + + + $PROJ_DIR$\webserver\http-strings.c + + + $PROJ_DIR$\webserver\httpd-cgi.c + + + $PROJ_DIR$\webserver\httpd-fs.c + + + $PROJ_DIR$\webserver\httpd.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + + + $PROJ_DIR$\webserver\uIP_Task.c + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww new file mode 100644 index 0000000..239a938 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.opt.bak b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.opt.bak new file mode 100644 index 0000000..6a29b7a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.opt.bak @@ -0,0 +1,79 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Demo_Source),1,0,0 +GRPOPT 2,(Libraries),0,0,0 +GRPOPT 3,(RTOS_Source),1,0,0 +GRPOPT 4,(uIP_Source),0,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 1,2,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c> +OPTFFF 1,3,1,0,0,0,0,0,<..\Common\Minimal\death.c> +OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,5,1,0,0,216,228,0,<.\main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,110,0,0,0,115,0,0,0,248,3,0,0,22,2,0,0 } +OPTFFF 1,6,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 1,9,2,0,0,0,0,0,<.\startup_rvmdk.S> +OPTFFF 1,10,1,0,0,0,0,0,<.\timertest.c> +OPTFFF 1,11,5,922746880,0,0,0,0,<.\FreeRTOSConfig.h> +OPTFFF 1,12,1,0,0,0,0,0,<..\Common\Minimal\GenQTest.c> +OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\QPeek.c> +OPTFFF 1,14,1,721420288,0,83,83,0,<.\IntQueueTimer.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,44,0,0,0,46,0,0,0,171,3,0,0,193,1,0,0 } +OPTFFF 1,15,1,33554434,0,628,653,0,<..\Common\Minimal\IntQueue.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,66,0,0,0,69,0,0,0,193,3,0,0,216,1,0,0 } +OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\recmutex.c> +OPTFFF 2,17,1,0,0,0,0,0,<.\rit128x96x4.c> +OPTFFF 2,18,1,0,0,0,0,0,<.\osram128x64x4.c> +OPTFFF 2,19,4,0,0,0,0,0,<..\Common\drivers\LuminaryMicro\Keil\driverlib.lib> +OPTFFF 2,20,1,0,0,0,0,0,<.\formike128x128x16.c> +OPTFFF 2,21,4,0,0,0,0,0,<..\Common\drivers\LuminaryMicro\Keil\grlib.lib> +OPTFFF 3,22,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 3,23,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 3,24,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 3,25,1,0,0,122,122,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,22,0,0,0,23,0,0,0,173,4,0,0,170,1,0,0 } +OPTFFF 3,26,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> +OPTFFF 4,27,1,822083584,0,0,0,0,<.\webserver\uIP_Task.c> +OPTFFF 4,28,1,0,0,0,0,0,<.\webserver\emac.c> +OPTFFF 4,29,1,0,0,0,0,0,<.\webserver\httpd.c> +OPTFFF 4,30,1,0,0,0,0,0,<.\webserver\httpd-cgi.c> +OPTFFF 4,31,1,0,0,0,0,0,<.\webserver\httpd-fs.c> +OPTFFF 4,32,1,0,0,0,0,0,<.\webserver\http-strings.c> +OPTFFF 4,33,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c> +OPTFFF 4,34,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c> +OPTFFF 4,35,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c> +OPTFFF 4,36,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c> + + +TARGOPT 1, (FreeRTOS_Demo) + ADSCLK=8000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\rvmdk\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 255 + OPTBL 0,(Data Sheet) + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S8962)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S8962) + OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + OPTKEY 0,(UL2CM3)(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000) + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)() + OPTKEY 0,(lmidk-agdi)(-B0 -O1792) + OPTMM 1,2,(0) + OPTDF 0x84 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvgui.a0190789 b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvgui.a0190789 new file mode 100644 index 0000000..9bd96d7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvgui.a0190789 @@ -0,0 +1,2646 @@ + + + + 1.1 + +
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+ + + + 0 + 1920 + 1080 + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvopt b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvopt new file mode 100644 index 0000000..e4db295 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvopt @@ -0,0 +1,800 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + FreeRTOS_Demo + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\LM3S8962.PDF + + + + SARMCM3.DLL + + DLM.DLL + -pLM3S8962 + SARMCM3.DLL + + TLM.DLL + -pLM3S8962 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 5 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + UL2CM3 + -UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + lmidk-agdi + -U063107FEA -O1536 -S3 -FO29 + + + + + 1 + 2 + 0 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Demo_Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\BlockQ.c + BlockQ.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\blocktim.c + blocktim.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\death.c + death.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\integer.c + integer.c + + + 1 + 5 + 1 + 0 + 0 + 33 + 0 + 97 + 101 + 0 + .\main.c + main.c + + 44 + 0 + 1 + + -1 + -1 + + + -4 + -24 + + + 115 + 110 + 1016 + 534 + + + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\ParTest\ParTest.c + ParTest.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\PollQ.c + PollQ.c + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\semtest.c + semtest.c + + + 1 + 9 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_rvmdk.S + startup_rvmdk.S + + + 1 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\timertest.c + timertest.c + + + 1 + 11 + 5 + 0 + 0 + 55 + 0 + 0 + 0 + 0 + .\FreeRTOSConfig.h + FreeRTOSConfig.h + + + 1 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\GenQTest.c + GenQTest.c + + + 1 + 13 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\QPeek.c + QPeek.c + + + 1 + 14 + 1 + 0 + 0 + 43 + 0 + 83 + 83 + 0 + .\IntQueueTimer.c + IntQueueTimer.c + + 44 + 0 + 1 + + -1 + -1 + + + -4 + -24 + + + 46 + 44 + 939 + 449 + + + + + 1 + 15 + 1 + 0 + 1 + 2 + 0 + 628 + 653 + 0 + ..\Common\Minimal\IntQueue.c + IntQueue.c + + 44 + 2 + 3 + + -1 + -1 + + + -4 + -24 + + + 69 + 66 + 961 + 472 + + + + + 1 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\recmutex.c + recmutex.c + + + + + Libraries + 1 + 0 + 0 + + 2 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\rit128x96x4.c + rit128x96x4.c + + + 2 + 18 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\drivers\LuminaryMicro\Keil\driverlib.lib + driverlib.lib + + + 2 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\formike128x128x16.c + formike128x128x16.c + + + 2 + 20 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\drivers\LuminaryMicro\Keil\grlib.lib + grlib.lib + + + + + RTOS_Source + 1 + 0 + 0 + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\tasks.c + tasks.c + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\list.c + list.c + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\queue.c + queue.c + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\portable\RVDS\ARM_CM3\port.c + port.c + + + 3 + 25 + 1 + 0 + 0 + 36 + 0 + 33 + 33 + 0 + ..\..\Source\portable\MemMang\heap_2.c + heap_2.c + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\osram128x64x4.c + osram128x64x4.c + + + + + uIP_Source + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 49 + 0 + 0 + 0 + 0 + .\webserver\uIP_Task.c + uIP_Task.c + + + 4 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\emac.c + emac.c + + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\httpd.c + httpd.c + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\httpd-cgi.c + httpd-cgi.c + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\httpd-fs.c + httpd-fs.c + + + 4 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\http-strings.c + http-strings.c + + + 4 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + uip_arp.c + + + 4 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\psock.c + psock.c + + + 4 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\timer.c + timer.c + + + 4 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\uip.c + uip.c + + + + + 1 + 0 + + 100 + 1 + + + .\main.c + 33 + 97 + 101 + + + ..\..\Source\portable\MemMang\heap_2.c + 36 + 33 + 33 + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvproj b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvproj new file mode 100644 index 0000000..0764111 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.uvproj @@ -0,0 +1,600 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + FreeRTOS_Demo + 0x4 + ARM-ADS + + + LM3S8962 + Luminary Micro + IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000) + 4285 + LM3Sxxx.H + + + + + + + + + + + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk\ + RTOSDemo + 1 + 0 + 0 + 1 + 1 + .\rvmdk\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\rvmdk\RTOSDemo.bin .\rvmdk\RTOSDemo.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DLM.DLL + -pLM3S8962 + SARMCM3.DLL + + TLM.DLL + -pLM3S8962 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 4 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + BIN\lmidk-agdi.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress 191,550,513,167,177,144 + RVDS_ARMCM3_LM3S102, "PACK_STRUCT_END=","ALIGN_STRUCT_END=" + + .;.\..\Common\drivers\LuminaryMicro;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;..\Common\ethernet\uIP\uip-1.0\uip;.\webserver + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + --entry Reset_Handler + + + + + + + + Demo_Source + + + BlockQ.c + 1 + ..\Common\Minimal\BlockQ.c + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + death.c + 1 + ..\Common\Minimal\death.c + + + integer.c + 1 + ..\Common\Minimal\integer.c + + + main.c + 1 + .\main.c + + + ParTest.c + 1 + .\ParTest\ParTest.c + + + PollQ.c + 1 + ..\Common\Minimal\PollQ.c + + + semtest.c + 1 + ..\Common\Minimal\semtest.c + + + startup_rvmdk.S + 2 + .\startup_rvmdk.S + + + timertest.c + 1 + .\timertest.c + + + FreeRTOSConfig.h + 5 + .\FreeRTOSConfig.h + + + GenQTest.c + 1 + ..\Common\Minimal\GenQTest.c + + + QPeek.c + 1 + ..\Common\Minimal\QPeek.c + + + IntQueueTimer.c + 1 + .\IntQueueTimer.c + + + IntQueue.c + 1 + ..\Common\Minimal\IntQueue.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + QueueSet.c + 1 + ..\Common\Minimal\QueueSet.c + + + + + Libraries + + + rit128x96x4.c + 1 + .\rit128x96x4.c + + + osram128x64x4.c + 1 + .\osram128x64x4.c + + + driverlib.lib + 4 + ..\Common\drivers\LuminaryMicro\Keil\driverlib.lib + + + formike128x128x16.c + 1 + .\formike128x128x16.c + + + grlib.lib + 4 + ..\Common\drivers\LuminaryMicro\Keil\grlib.lib + + + + + RTOS_Source + + + tasks.c + 1 + ..\..\Source\tasks.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM3\port.c + + + heap_2.c + 1 + ..\..\Source\portable\MemMang\heap_2.c + + + + + uIP_Source + + + uIP_Task.c + 1 + .\webserver\uIP_Task.c + + + emac.c + 1 + .\webserver\emac.c + + + httpd.c + 1 + .\webserver\httpd.c + + + httpd-cgi.c + 1 + .\webserver\httpd-cgi.c + + + httpd-fs.c + 1 + .\webserver\httpd-fs.c + + + http-strings.c + 1 + .\webserver\http-strings.c + + + uip_arp.c + 1 + ..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + + + psock.c + 1 + ..\Common\ethernet\uIP\uip-1.0\uip\psock.c + + + timer.c + 1 + ..\Common\ethernet\uIP\uip-1.0\uip\timer.c + + + uip.c + 1 + ..\Common\ethernet\uIP\uip-1.0\uip\uip.c + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.xcl b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.xcl new file mode 100644 index 0000000..9bca99f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.xcl @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// webserver-lwip.xcl - Linker script for EW-ARM. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +// +// Set the CPU type to ARM. +// +-carm + +// +// Define the size of flash and SRAM. +// +-DROMSTART=00000000 +-DROMEND=00040000 +-DRAMSTART=20000000 +-DRAMEND=20010000 + + + +// +// Define the sections to place into flash, and the order to place them. +// +-Z(CODE)INTVEC=ROMSTART-ROMEND +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)CODE=ROMSTART-ROMEND +-Z(CONST)CODE_ID=ROMSTART-ROMEND +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + +// +// Define the sections to place into SRAM, and the order to place them. +// +-Z(DATA)VTABLE=RAMSTART-RAMEND +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND +-Z(DATA)CODE_I=RAMSTART-RAMEND diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_FreeRTOS_Demo.dep b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_FreeRTOS_Demo.dep new file mode 100644 index 0000000..b72b03d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_FreeRTOS_Demo.dep @@ -0,0 +1,471 @@ +Dependencies for Project 'RTOSDemo', Target 'FreeRTOS_Demo': (DO NOT MODIFY !) +F (..\Common\Minimal\BlockQ.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\blockq.o" --omf_browse ".\rvmdk\blockq.crf" --depend ".\rvmdk\blockq.d") +I (C:\Keil\ARM\RV31\INC\stdlib.h)(0x4D4C44E4) +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\..\Source\include\queue.h)(0x4E78C6B7) +I (..\Common\include\BlockQ.h)(0x4E78C6B7) +F (..\Common\Minimal\blocktim.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\blocktim.o" --omf_browse ".\rvmdk\blocktim.crf" --depend ".\rvmdk\blocktim.d") +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\..\Source\include\queue.h)(0x4E78C6B7) +I (..\Common\include\blocktim.h)(0x4E78C6B7) +F (..\Common\Minimal\death.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\death.o" --omf_browse ".\rvmdk\death.crf" --depend ".\rvmdk\death.d") +I (C:\Keil\ARM\RV31\INC\stdlib.h)(0x4D4C44E4) +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\Common\include\death.h)(0x4E78C6B7) +F (..\Common\Minimal\integer.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\integer.o" --omf_browse ".\rvmdk\integer.crf" --depend ".\rvmdk\integer.d") +I (C:\Keil\ARM\RV31\INC\stdlib.h)(0x4D4C44E4) +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\Common\include\integer.h)(0x4E78C6B7) +F (.\main.c)(0x4ED7964B)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\main.o" --omf_browse ".\rvmdk\main.crf" --depend ".\rvmdk\main.d") +I (C:\Keil\ARM\RV31\INC\stdio.h)(0x4D46C1D6) +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\..\Source\include\queue.h)(0x4E78C6B7) +I (..\..\Source\include\semphr.h)(0x4E78C6B7) +I (.\..\Common\drivers\LuminaryMicro\hw_memmap.h)(0x4A8A85D4) +I (.\..\Common\drivers\LuminaryMicro\hw_types.h)(0x4A8A85D4) +I (.\..\Common\drivers\LuminaryMicro\hw_sysctl.h)(0x4D4D7ED3) +I (.\..\Common\drivers\LuminaryMicro\sysctl.h)(0x4D4D7ED3) +I (.\..\Common\drivers\LuminaryMicro\gpio.h)(0x4A8A85D4) +I (.\..\Common\drivers\LuminaryMicro\grlib.h)(0x4A8A85D4) +I (.\..\Common\drivers\LuminaryMicro\rit128x96x4.h)(0x4A8A85D4) +I (osram128x64x4.h)(0x4A8A84A4) +I (formike128x128x16.h)(0x4A8A84A4) +I (..\Common\include\BlockQ.h)(0x4E78C6B7) +I (..\Common\include\death.h)(0x4E78C6B7) +I (..\Common\include\integer.h)(0x4E78C6B7) +I (..\Common\include\blocktim.h)(0x4E78C6B7) +I (..\Common\include\flash.h)(0x4E78C6B7) +I (..\Common\include\partest.h)(0x4E78C6B7) +I (..\Common\include\semtest.h)(0x4E78C6B7) +I (..\Common\include\PollQ.h)(0x4E78C6B7) +I (lcd_message.h)(0x4A8A84A4) +I (bitmap.h)(0x4A8A84A4) +I (..\Common\include\GenQTest.h)(0x4E78C6B7) +I (..\Common\include\QPeek.h)(0x4E78C6B7) +I (..\Common\include\recmutex.h)(0x4E78C6B7) +I (..\Common\include\IntQueue.h)(0x4E78C6B7) +F (.\ParTest\ParTest.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\partest.o" --omf_browse ".\rvmdk\partest.crf" --depend ".\rvmdk\partest.d") +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\Common\include\partest.h)(0x4E78C6B7) +I (.\..\Common\drivers\LuminaryMicro\hw_types.h)(0x4A8A85D4) +I (.\..\Common\drivers\LuminaryMicro\gpio.h)(0x4A8A85D4) +I (.\..\Common\drivers\LuminaryMicro\hw_memmap.h)(0x4A8A85D4) +F (..\Common\Minimal\PollQ.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\pollq.o" --omf_browse ".\rvmdk\pollq.crf" --depend ".\rvmdk\pollq.d") +I (C:\Keil\ARM\RV31\INC\stdlib.h)(0x4D4C44E4) +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\..\Source\include\queue.h)(0x4E78C6B7) +I (..\Common\include\PollQ.h)(0x4E78C6B7) +F (..\Common\Minimal\semtest.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\semtest.o" --omf_browse ".\rvmdk\semtest.crf" --depend ".\rvmdk\semtest.d") +I (C:\Keil\ARM\RV31\INC\stdlib.h)(0x4D4C44E4) +I (..\..\Source\include\FreeRTOS.h)(0x4E78C6B7) +I (C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\..\Source\include\task.h)(0x4E78C6B7) +I (..\..\Source\include\list.h)(0x4E78C6B7) +I (..\..\Source\include\semphr.h)(0x4E78C6B7) +I (..\..\Source\include\queue.h)(0x4E78C6B7) +I (..\Common\include\semtest.h)(0x4E78C6B7) +F (.\startup_rvmdk.S)(0x4A8A84A4)(--cpu Cortex-M3 -g --apcs=interwork -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -o ".\rvmdk\startup_rvmdk.o" --depend ".\rvmdk\startup_rvmdk.d") +F (.\timertest.c)(0x4E78C6B6)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro 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(C:\Keil\ARM\RV31\INC\stddef.h)(0x4D4262DE) +I (..\..\Source\include\projdefs.h)(0x4E78C6B7) +I (.\FreeRTOSConfig.h)(0x4E78C6B7) +I (..\..\Source\include\portable.h)(0x4E78C6B7) +I (..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h)(0x4E78C6B7) +I (..\..\Source\include\mpu_wrappers.h)(0x4E78C6B7) +I (..\Common\ethernet\uIP\uip-1.0\uip\timer.h)(0x4A8A85F4) +F (..\Common\ethernet\uIP\uip-1.0\uip\uip.c)(0x4A8A85F4)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\uip.o" --omf_browse ".\rvmdk\uip.crf" --depend ".\rvmdk\uip.d") +I (..\Common\ethernet\uIP\uip-1.0\uip\uip.h)(0x4A8A85F4) +I (..\Common\ethernet\uIP\uip-1.0\uip\uipopt.h)(0x4A8A85F4) +I (.\webserver\uip-conf.h)(0x4A8A84A2) +I (C:\Keil\ARM\RV31\INC\stdint.h)(0x4D46C1D4) +I (.\webserver\webserver.h)(0x4A8A84A2) +I (.\webserver\httpd.h)(0x4A8A84A2) +I (..\Common\ethernet\uIP\uip-1.0\uip\psock.h)(0x4A8A85F4) +I (..\Common\ethernet\uIP\uip-1.0\uip\pt.h)(0x4A8A85F4) +I (..\Common\ethernet\uIP\uip-1.0\uip\lc.h)(0x4A8A85F4) +I (..\Common\ethernet\uIP\uip-1.0\uip\lc-switch.h)(0x4A8A85F4) +I (.\webserver\httpd-fs.h)(0x4A8A84A2) +I (..\Common\ethernet\uIP\uip-1.0\uip\uip_arch.h)(0x4A8A85F4) +I (C:\Keil\ARM\RV31\INC\string.h)(0x4D46C1D6) diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_uvopt.bak b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_uvopt.bak new file mode 100644 index 0000000..fd8e2b8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo_uvopt.bak @@ -0,0 +1,823 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + FreeRTOS_Demo + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\LM3S8962.PDF + + + + SARMCM3.DLL + + DLM.DLL + -pLM3S8962 + SARMCM3.DLL + + TLM.DLL + -pLM3S8962 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 5 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + DLGUARM + + + 0 + UL2CM3 + -UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + lmidk-agdi + -U063107FEA -O1536 -S3 -FO29 + + + + + 1 + 2 + 0 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Demo_Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\BlockQ.c + BlockQ.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\blocktim.c + blocktim.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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IntQueueTimer.c + + 44 + 0 + 1 + + -1 + -1 + + + -4 + -24 + + + 46 + 44 + 939 + 449 + + + + + 1 + 15 + 1 + 0 + 1 + 2 + 0 + 628 + 653 + 0 + ..\Common\Minimal\IntQueue.c + IntQueue.c + + 44 + 2 + 3 + + -1 + -1 + + + -4 + -24 + + + 69 + 66 + 961 + 472 + + + + + 1 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\recmutex.c + recmutex.c + + + + + Libraries + 1 + 0 + 0 + + 2 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\rit128x96x4.c + rit128x96x4.c + + + 2 + 19 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\drivers\LuminaryMicro\Keil\driverlib.lib + driverlib.lib + + + 2 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\formike128x128x16.c + formike128x128x16.c + + + 2 + 21 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\drivers\LuminaryMicro\Keil\grlib.lib + grlib.lib + + + + + RTOS_Source + 1 + 0 + 0 + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\tasks.c + tasks.c + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\list.c + list.c + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\queue.c + queue.c + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 122 + 122 + 0 + ..\..\Source\portable\RVDS\ARM_CM3\port.c + port.c + + 44 + 0 + 1 + + -1 + -1 + + + -4 + -24 + + + 23 + 22 + 1197 + 426 + + + + + 3 + 26 + 1 + 0 + 0 + 36 + 0 + 1 + 18 + 0 + ..\..\Source\portable\MemMang\heap_2.c + heap_2.c + + + 3 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\osram128x64x4.c + osram128x64x4.c + + + + + uIP_Source + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 49 + 0 + 0 + 0 + 0 + .\webserver\uIP_Task.c + uIP_Task.c + + + 4 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\emac.c + emac.c + + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\httpd.c + httpd.c + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\httpd-cgi.c + httpd-cgi.c + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\httpd-fs.c + httpd-fs.c + + + 4 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\webserver\http-strings.c + http-strings.c + + + 4 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + uip_arp.c + + + 4 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\psock.c + psock.c + + + 4 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\timer.c + timer.c + + + 4 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\ethernet\uIP\uip-1.0\uip\uip.c + uip.c + + + + + 1 + 0 + + 100 + 1 + + + .\main.c + 33 + 97 + 101 + + + ..\..\Source\portable\MemMang\heap_2.c + 36 + 1 + 18 + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h new file mode 100644 index 0000000..29f813f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h @@ -0,0 +1,336 @@ +#ifndef BITMAP_H +#define BITMAP_H + +#define bmpBITMAP_HEIGHT 50 +#define bmpBITMAP_WIDTH 128 + +const unsigned char pucBasicBitmap[] = +{ +0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.c new file mode 100644 index 0000000..188099a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.c @@ -0,0 +1,902 @@ +//***************************************************************************** +// +// formike128x128x16.c - Display driver for the Formike Electronic +// KWH015C04-F01 CSTN panel with an ST7637 controller. +// +// Copyright (c) 2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3s3748_api +//! @{ +// +//***************************************************************************** + +#include "hw_gpio.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "sysctl.h" +#include "rom.h" +#include "grlib.h" +#include "formike128x128x16.h" +#include + +//***************************************************************************** +// +// Defines for the pins that are used to communicate with the ST7637. +// +//***************************************************************************** +#define LCD_A0_BASE GPIO_PORTB_BASE +#define LCD_A0_PIN GPIO_PIN_2 +#define LCD_WR_BASE GPIO_PORTC_BASE +#define LCD_WR_PIN GPIO_PIN_4 +#define LCD_RD_BASE GPIO_PORTC_BASE +#define LCD_RD_PIN GPIO_PIN_5 +#define LCD_BL_BASE GPIO_PORTF_BASE +#define LCD_BL_PIN GPIO_PIN_1 +#define LCD_DATA_BASE GPIO_PORTG_BASE + +//***************************************************************************** +// +// Translates a 24-bit RGB color to a display driver-specific color. +// +// \param c is the 24-bit RGB color. The least-significant byte is the blue +// channel, the next byte is the green channel, and the third byte is the red +// channel. +// +// This macro translates a 24-bit RGB color into a value that can be written +// into the display's frame buffer in order to reproduce that color, or the +// closest possible approximation of that color. +// +// \return Returns the display-driver specific color. +// +//***************************************************************************** +#define DPYCOLORTRANSLATE(c) ((((c) & 0x00ff0000) >> 19) | \ + ((((c) & 0x0000ff00) >> 5) & 0x000007e0) | \ + ((((c) & 0x000000ff) << 8) & 0x0000f800)) + +//***************************************************************************** +// +// Writes a data word to the ST7637. +// +//***************************************************************************** +static void +WriteData(unsigned char ucData) +{ + // + // Write the data to the data bus. + // + HWREG(LCD_DATA_BASE + GPIO_O_DATA + (0xff << 2)) = ucData; + + // + // Assert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = 0; + + // + // Deassert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = LCD_WR_PIN; +} + +//***************************************************************************** +// +// Writes a command to the ST7637. +// +//***************************************************************************** +static void +WriteCommand(unsigned char ucData) +{ + // + // Write the command to the data bus. + // + HWREG(LCD_DATA_BASE + GPIO_O_DATA + (0xff << 2)) = ucData; + + // + // Set the A0 signal low, indicating a command. + // + HWREG(LCD_A0_BASE + GPIO_O_DATA + (LCD_A0_PIN << 2)) = 0; + + // + // Assert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = 0; + + // + // Deassert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = LCD_WR_PIN; + + // + // Set the A0 signal high, indicating that following writes are data. + // + HWREG(LCD_A0_BASE + GPIO_O_DATA + (LCD_A0_PIN << 2)) = LCD_A0_PIN; +} + +//***************************************************************************** +// +//! Initializes the display driver. +//! +//! This function initializes the ST7637 display controller on the panel, +//! preparing it to display data. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16Init(void) +{ + unsigned long ulClockMS, ulCount; + + // + // Get the value to pass to SysCtlDelay() in order to delay for 1 ms. + // + ulClockMS = SysCtlClockGet() / (3 * 1000); + + // + // Enable the GPIO peripherals used to interface to the ST7637. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); + + // + // Configure the pins that connect to the LCD as GPIO outputs. + // + GPIOPinTypeGPIOOutput(LCD_A0_BASE, LCD_A0_PIN); + GPIOPinTypeGPIOOutput(LCD_WR_BASE, LCD_WR_PIN); + GPIOPinTypeGPIOOutput(LCD_RD_BASE, LCD_RD_PIN); + GPIOPinTypeGPIOOutput(LCD_BL_BASE, LCD_BL_PIN); + GPIOPinTypeGPIOOutput(LCD_DATA_BASE, 0xff); + + // + // Set the LCD control pins to their default values. + // + GPIOPinWrite(LCD_A0_BASE, LCD_A0_PIN, LCD_A0_PIN); + GPIOPinWrite(LCD_WR_BASE, LCD_WR_PIN | LCD_RD_PIN, + LCD_WR_PIN | LCD_RD_PIN); + GPIOPinWrite(LCD_BL_BASE, LCD_BL_PIN, 0); + GPIOPinWrite(LCD_DATA_BASE, 0xff, 0x00); + + // + // Perform a software reset of the ST7637. + // + WriteCommand(0x01); + + // + // Delay for 120ms. + // + SysCtlDelay(ulClockMS * 120); + + // + // Disable auto-load of mask rom data. + // + WriteCommand(0xD7); + WriteData(0xBF); + + // + // Set the OTP control mode to read. + // + WriteCommand(0xE0); + WriteData(0x00); + + // + // Delay for 10ms. + // + SysCtlDelay(ulClockMS * 10); + + // + // Start the OTP read. + // + WriteCommand(0xE3); + + // + // Delay for 20ms. + // + SysCtlDelay(ulClockMS * 20); + + // + // Cancel the OTP read (it should have finished by now). + // + WriteCommand(0xE1); + + // + // Turn off the display. + // + WriteCommand(0x28); + + // + // Exit sleep mode. + // + WriteCommand(0x11); + + // + // Delay for 50ms. + // + SysCtlDelay(ulClockMS * 50); + + // + // Program the LCD supply voltage V0 to 14V. + // + WriteCommand(0xC0); + WriteData(0x04); + WriteData(0x01); + + // + // Select an LCD bias voltage ratio of 1/12. + // + WriteCommand(0xC3); + WriteData(0x00); + + // + // Enable the x8 booster circuit. + // + WriteCommand(0xC4); + WriteData(0x07); + + // + // Invert the column scan direction for the panel. + // + WriteCommand(0xB7); + WriteData(0xC0); + + // + // Select 16bpp, 5-6-5 data input mode. + // + WriteCommand(0x3A); + WriteData(0x05); + + // + // Select the memory scanning direction. The scanning mode does not matter + // for this driver since the row/column selects will constrain the writes + // to the desired area of the display. + // + WriteCommand(0x36); + WriteData(0x00); + + // + // Turn on the display. + // + WriteCommand(0x29); + + // + // Clear the contents of the display buffer. + // + WriteCommand(0x2A); + WriteData(0x00); + WriteData(0x7F); + WriteCommand(0x2B); + WriteData(0x01); + WriteData(0x80); + WriteCommand(0x2c); + for(ulCount = 0; ulCount < (128 * 128); ulCount++) + { + WriteData(0x00); + WriteData(0x00); + } + + // + // Enable normal operation of the LCD. + // + WriteCommand(0x13); +} + +//***************************************************************************** +// +//! Turns on the backlight. +//! +//! This function turns on the backlight on the display. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16BacklightOn(void) +{ + // + // Assert the signal that turns on the backlight. + // + HWREG(LCD_BL_BASE + GPIO_O_DATA + (LCD_BL_PIN << 2)) = LCD_BL_PIN; +} + +//***************************************************************************** +// +//! Turns off the backlight. +//! +//! This function turns off the backlight on the display. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16BacklightOff(void) +{ + // + // Deassert the signal that turns on the backlight. + // + HWREG(LCD_BL_BASE + GPIO_O_DATA + (LCD_BL_PIN << 2)) = 0; +} + +//***************************************************************************** +// +//! Draws a pixel on the screen. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the pixel. +//! \param lY is the Y coordinate of the pixel. +//! \param ulValue is the color of the pixel. +//! +//! This function sets the given pixel to a particular color. The coordinates +//! of the pixel are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16PixelDraw(void *pvDisplayData, long lX, long lY, + unsigned long ulValue) +{ + // + // Set the X address of the display cursor. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the pixel value. + // + WriteCommand(0x2c); + WriteData(ulValue >> 8); + WriteData(ulValue); +} + +//***************************************************************************** +// +//! Draws a horizontal sequence of pixels on the screen. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the first pixel. +//! \param lY is the Y coordinate of the first pixel. +//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1 +//! or 4 bit per pixel formats. +//! \param lCount is the number of pixels to draw. +//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8. +//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel +//! formats, the most significant bit(s) represent the left-most pixel. +//! \param pucPalette is a pointer to the palette used to draw the pixels. +//! +//! This function draws a horizontal sequence of pixels on the screen, using +//! the supplied palette. For 1 bit per pixel format, the palette contains +//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette +//! contains 24-bit RGB values that must be translated before being written to +//! the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16PixelDrawMultiple(void *pvDisplayData, long lX, long lY, + long lX0, long lCount, long lBPP, + const unsigned char *pucData, + const unsigned char *pucPalette) +{ + unsigned long ulByte; + + // + // Set the extent of the line along the X axis. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX + lCount - 1); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Determine how to interpret the pixel data based on the number of bits + // per pixel. + // + switch(lBPP) + { + // + // The pixel data is in 1 bit per pixel format. + // + case 1: + { + // + // Loop while there are more pixels to draw. + // + while(lCount) + { + // + // Get the next byte of image data. + // + ulByte = *pucData++; + + // + // Loop through the pixels in this byte of image data. + // + for(; (lX0 < 8) && lCount; lX0++, lCount--) + { + // + // Draw this pixel in the appropriate color. + // + lBPP = ((unsigned long *)pucPalette)[(ulByte >> + (7 - lX0)) & 1]; + WriteData(lBPP >> 8); + WriteData(lBPP); + } + + // + // Start at the beginning of the next byte of image data. + // + lX0 = 0; + } + + // + // The image data has been drawn. + // + break; + } + + // + // The pixel data is in 4 bit per pixel format. + // + case 4: + { + // + // Loop while there are more pixels to draw. "Duff's device" is + // used to jump into the middle of the loop if the first nibble of + // the pixel data should not be used. Duff's device makes use of + // the fact that a case statement is legal anywhere within a + // sub-block of a switch statement. See + // http://en.wikipedia.org/wiki/Duff's_device for detailed + // information about Duff's device. + // + switch(lX0 & 1) + { + case 0: + while(lCount) + { + // + // Get the upper nibble of the next byte of pixel data + // and extract the corresponding entry from the + // palette. + // + ulByte = (*pucData >> 4) * 3; + ulByte = (*(unsigned long *)(pucPalette + ulByte) & + 0x00ffffff); + + // + // Translate this palette entry and write it to the + // screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + + // + // Decrement the count of pixels to draw. + // + lCount--; + + // + // See if there is another pixel to draw. + // + if(lCount) + { + case 1: + // + // Get the lower nibble of the next byte of pixel + // data and extract the corresponding entry from + // the palette. + // + ulByte = (*pucData++ & 15) * 3; + ulByte = (*(unsigned long *)(pucPalette + ulByte) & + 0x00ffffff); + + // + // Translate this palette entry and write it to the + // screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + + // + // Decrement the count of pixels to draw. + // + lCount--; + } + } + } + + // + // The image data has been drawn. + // + break; + } + + // + // The pixel data is in 8 bit per pixel format. + // + case 8: + { + // + // Loop while there are more pixels to draw. + // + while(lCount--) + { + // + // Get the next byte of pixel data and extract the + // corresponding entry from the palette. + // + ulByte = *pucData++ * 3; + ulByte = *(unsigned long *)(pucPalette + ulByte) & 0x00ffffff; + + // + // Translate this palette entry and write it to the screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + } + + // + // The image data has been drawn. + // + break; + } + } +} + +//***************************************************************************** +// +//! Flushes any cached drawing operations. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! +//! This functions flushes any cached drawing operations to the display. This +//! is useful when a local frame buffer is used for drawing operations, and the +//! flush would copy the local frame buffer to the display. For the ST7637 +//! driver, the flush is a no operation. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16Flush(void *pvDisplayData) +{ + // + // There is nothing to be done. + // +} + +//***************************************************************************** +// +//! Draws a horizontal line. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX1 is the X coordinate of the start of the line. +//! \param lX2 is the X coordinate of the end of the line. +//! \param lY is the Y coordinate of the line. +//! \param ulValue is the color of the line. +//! +//! This function draws a horizontal line on the display. The coordinates of +//! the line are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16LineDrawH(void *pvDisplayData, long lX1, long lX2, long lY, + unsigned long ulValue) +{ + // + // Set the extent of the line along the X axis. + // + WriteCommand(0x2a); + WriteData(lX1); + WriteData(lX2); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels of this horizontal line. + // + while(lX1++ <= lX2) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Draws a vertical line. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the line. +//! \param lY1 is the Y coordinate of the start of the line. +//! \param lY2 is the Y coordinate of the end of the line. +//! \param ulValue is the color of the line. +//! +//! This function draws a vertical line on the display. The coordinates of the +//! line are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16LineDrawV(void *pvDisplayData, long lX, long lY1, long lY2, + unsigned long ulValue) +{ + // + // Set the X address of the display cursor. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX); + + // + // Set the extent of the line along the Y axis. + // + WriteCommand(0x2b); + WriteData(lY1 + 1); + WriteData(lY2 + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels of this vertical line. + // + while(lY1++ <= lY2) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Fills a rectangle. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param pRect is a pointer to the structure describing the rectangle. +//! \param ulValue is the color of the rectangle. +//! +//! This function fills a rectangle on the display. The coordinates of the +//! rectangle are assumed to be within the extents of the display, and the +//! rectangle specification is fully inclusive (i.e. both sXMin and sXMax are +//! drawn, along with sYMin and sYMax). +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16RectFill(void *pvDisplayData, const tRectangle *pRect, + unsigned long ulValue) +{ + long lCount; + + // + // Set the extent of the rectangle along the X axis. + // + WriteCommand(0x2a); + WriteData(pRect->sXMin); + WriteData(pRect->sXMax); + + // + // Set the extent of the rectangle along the Y axis. + // + WriteCommand(0x2b); + WriteData(pRect->sYMin + 1); + WriteData(pRect->sYMax + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels in this rectangle. + // + for(lCount = ((pRect->sXMax - pRect->sXMin + 1) * + (pRect->sYMax - pRect->sYMin + 1)); lCount > 0; lCount--) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Translates a 24-bit RGB color to a display driver-specific color. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param ulValue is the 24-bit RGB color. The least-significant byte is the +//! blue channel, the next byte is the green channel, and the third byte is the +//! red channel. +//! +//! This function translates a 24-bit RGB color into a value that can be +//! written into the display's frame buffer in order to reproduce that color, +//! or the closest possible approximation of that color. +//! +//! \return Returns the display-driver specific color. +// +//***************************************************************************** +static unsigned long +Formike128x128x16ColorTranslate(void *pvDisplayData, unsigned long ulValue) +{ + // + // Translate from a 24-bit RGB color to a 5-6-5 RGB color. + // + return(DPYCOLORTRANSLATE(ulValue)); +} + +//***************************************************************************** +// +//! The display structure that describes the driver for the Formike Electronic +//! KWH015C04-F01 CSTN panel with an ST7637 controller. +// +//***************************************************************************** +const tDisplay g_sFormike128x128x16 = +{ + sizeof(tDisplay), + 0, + 128, + 128, + Formike128x128x16PixelDraw, + Formike128x128x16PixelDrawMultiple, + Formike128x128x16LineDrawH, + Formike128x128x16LineDrawV, + Formike128x128x16RectFill, + Formike128x128x16ColorTranslate, + Formike128x128x16Flush +}; + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + + + + + + + + + + + + + + + +/* FreeRTOS.org demo wrappers. These are required so the prototypes for the +functions are the same as for the display drivers used by other evaluation +kits. */ + +static tContext sContext; + +void vFormike128x128x16Clear( void ) +{ +const tRectangle xRectangle = { 0, 0, 127, 127 }; + + GrContextForegroundSet( &sContext, ClrBlack ); + GrRectFill( &sContext, &xRectangle ); + GrContextForegroundSet(&sContext, ClrWhite); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16StringDraw( const char *pcString, unsigned long lX, unsigned long lY, unsigned char ucColor ) +{ + GrContextForegroundSet(&sContext, ClrWhite); + GrStringDraw( &sContext, pcString, strlen( pcString ), lX, lY, false ); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16Init( unsigned long ul ) +{ +tRectangle rectScreen; + + ( void ) ul; + + Formike128x128x16Init(); + Formike128x128x16BacklightOn(); + GrContextInit(&sContext, &g_sFormike128x128x16); + GrContextFontSet(&sContext, &g_sFontCmss12); + rectScreen.sXMin = 0; + + /* Fill the screen with a black rectangle. */ + rectScreen.sYMin = 0; + rectScreen.sXMax = g_sFormike128x128x16.usWidth - 1; + rectScreen.sYMax = g_sFormike128x128x16.usHeight - 1; + GrContextForegroundSet(&sContext, ClrBlack); + GrRectFill(&sContext, &rectScreen); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16ImageDraw( const unsigned char *pucImage, unsigned long ulX, unsigned long ulY, unsigned long ulWidth, unsigned long ulHeight ) +{ + GrImageDraw( &sContext, pucImage, ( long ) ulX, ( long ) ulY); + +} + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.h new file mode 100644 index 0000000..feaec75 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/formike128x128x16.h @@ -0,0 +1,51 @@ +//***************************************************************************** +// +// formike128x128x16.h - Prototypes for the Formike Electronic KWH015C04-F01 +// display driver. +// +// Copyright (c) 2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FORMIKE128X128X16_H__ +#define __FORMIKE128X128X16_H__ + +//***************************************************************************** +// +// Prototypes for the globals exported by this driver. +// +//***************************************************************************** +extern void Formike128x128x16Init(void); +extern void Formike128x128x16BacklightOn(void); +extern void Formike128x128x16BacklightOff(void); +extern const tDisplay g_sFormike128x128x16; + +/* FreeRTOS.org demo wrappers. These are required so the prototypes for the +functions are the same as for the display drivers used by other evaluation +kits. */ +void vFormike128x128x16Clear( void ); +void vFormike128x128x16StringDraw( const char *pcString, unsigned long lX, unsigned long lY, unsigned char ucColor ); +void vFormike128x128x16Init( unsigned long ul ); +void vFormike128x128x16ImageDraw( const unsigned char *pucImage, unsigned long ulX, unsigned long ulY, unsigned long ulWidth, unsigned long ulHeight ); + +#endif // __FORMIKE128X128X16_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h new file mode 100644 index 0000000..adfc18b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h @@ -0,0 +1,9 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +typedef struct +{ + signed char *pcMessage; +} xOLEDMessage; + +#endif /* LCD_MESSAGE_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c new file mode 100644 index 0000000..437675f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c @@ -0,0 +1,496 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the OLED display by the 'OLED' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the OLED send the message on a queue to the OLED task instead of + * accessing the OLED themselves. The OLED task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" hook - This only executes every five seconds from the tick hook. + * Its main function is to check that all the standard demo tasks are still + * operational. Should any unexpected behaviour within a demo task be discovered + * the tick hook will write an error to the OLED (via the OLED task). If all the + * demo tasks are executing with their expected behaviour then the check task + * writes PASS to the OLED (again via the OLED task), as described above. + * + * "uIP" task - This is the task that handles the uIP stack. All TCP/IP + * processing is performed in this task. + */ + + + + +/************************************************************************* + * Please ensure to read http://www.freertos.org/portlm3sx965.html + * which provides information on configuring and running this demo for the + * various Luminary Micro EKs. + *************************************************************************/ + +/* Set the following option to 1 to include the WEB server in the build. By +default the WEB server is excluded to keep the compiled code size under the 32K +limit imposed by the KickStart version of the IAR compiler. The graphics +libraries take up a lot of ROM space, hence including the graphics libraries +and the TCP/IP stack together cannot be accommodated with the 32K size limit. */ +#define mainINCLUDE_WEB_SERVER 0 + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Hardware library includes. */ +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_sysctl.h" +#include "sysctl.h" +#include "gpio.h" +#include "grlib.h" +#include "rit128x96x4.h" +#include "osram128x64x4.h" +#include "formike128x128x16.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "PollQ.h" +#include "lcd_message.h" +#include "bitmap.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "IntQueue.h" +#include "QueueSet.h" + +/*-----------------------------------------------------------*/ + +/* The time between cycles of the 'check' functionality (defined within the +tick hook. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* Size of the stack allocated to the uIP task. */ +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The OLED task uses the sprintf function so requires a little more stack too. */ +#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainOLED_QUEUE_SIZE ( 3 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The period of the system clock in nano seconds. This is used to calculate +the jitter time in nano seconds. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Constants used when writing strings to the display. */ +#define mainCHARACTER_HEIGHT ( 9 ) +#define mainMAX_ROWS_128 ( mainCHARACTER_HEIGHT * 14 ) +#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) +#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) +#define mainFULL_SCALE ( 15 ) +#define ulSSI_FREQUENCY ( 3500000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The display is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the display directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vOLEDTask( void *pvParameters ); + +/* + * Configure the hardware for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Configures the high frequency timers - those used to measure the timing + * jitter while the real time kernel is executing. + */ +extern void vSetupHighFrequencyTimer( void ); + +/* + * Hook functions that can get called by the kernel. + */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName ); +void vApplicationTickHook( void ); + + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the OLED task. */ +xQueueHandle xOLEDQueue; + +/* The welcome text. */ +const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; + +/*-----------------------------------------------------------*/ + + +/************************************************************************* + * Please ensure to read http://www.freertos.org/portlm3sx965.html + * which provides information on configuring and running this demo for the + * various Luminary Micro EKs. + *************************************************************************/ +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by the OLED task. Messages for display on the OLED + are received via this queue. */ + xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartInterruptQueueTasks(); + vStartRecursiveMutexTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartQueuePeekTasks(); + vStartQueueSetTasks(); + + /* Exclude some tasks if using the kickstart version to ensure we stay within + the 32K code size limit. */ + #if mainINCLUDE_WEB_SERVER != 0 + { + /* Create the uIP task if running on a processor that includes a MAC and + PHY. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + } + } + #endif + + + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Configure the high frequency interrupt used to measure the interrupt + jitter time. */ + vSetupHighFrequencyTimer(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void prvSetupHardware( void ) +{ + /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is + a workaround to allow the PLL to operate reliably. */ + if( DEVICE_IS_REVA2 ) + { + SysCtlLDOSet( SYSCTL_LDO_2_75V ); + } + + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); + + /* Enable Port F for Ethernet LEDs + LED0 Bit 3 Output + LED1 Bit 2 Output */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); + GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); + GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static xOLEDMessage xMessage = { "PASS" }; +static unsigned portLONG ulTicksSinceLastDisplay = 0; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Called from every tick interrupt. Have enough ticks passed to make it + time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN CREATE"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH"; + } + else if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN INT QUEUE"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN REC MUTEX"; + } + else if( xAreQueueSetTasksStillRunning() != pdPASS ) + { + xMessage.pcMessage = "ERROR IN Q SET"; + } + + configASSERT( strcmp( ( const char * ) xMessage.pcMessage, "PASS" ) == 0 ); + + /* Send the message to the OLED gatekeeper for display. */ + xHigherPriorityTaskWoken = pdFALSE; + xQueueSendFromISR( xOLEDQueue, &xMessage, &xHigherPriorityTaskWoken ); + } + + /* Write to a queue that is in use as part of the queue set demo to + demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); +} +/*-----------------------------------------------------------*/ + +void vOLEDTask( void *pvParameters ) +{ +xOLEDMessage xMessage; +unsigned portLONG ulY, ulMaxY; +static portCHAR cMessage[ mainMAX_MSG_LEN ]; +extern volatile unsigned portLONG ulMaxJitter; +const unsigned portCHAR *pucImage; + +/* Functions to access the OLED. The one used depends on the dev kit +being used. */ +void ( *vOLEDInit )( unsigned portLONG ) = NULL; +void ( *vOLEDStringDraw )( const portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portCHAR ) = NULL; +void ( *vOLEDImageDraw )( const unsigned portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portLONG, unsigned portLONG ) = NULL; +void ( *vOLEDClear )( void ) = NULL; + + /* Map the OLED access functions to the driver functions that are appropriate + for the evaluation kit being used. */ + switch( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) + { + case SYSCTL_DID1_PRTNO_6965 : + case SYSCTL_DID1_PRTNO_2965 : vOLEDInit = OSRAM128x64x4Init; + vOLEDStringDraw = OSRAM128x64x4StringDraw; + vOLEDImageDraw = OSRAM128x64x4ImageDraw; + vOLEDClear = OSRAM128x64x4Clear; + ulMaxY = mainMAX_ROWS_64; + pucImage = pucBasicBitmap; + break; + + case SYSCTL_DID1_PRTNO_1968 : + case SYSCTL_DID1_PRTNO_8962 : vOLEDInit = RIT128x96x4Init; + vOLEDStringDraw = RIT128x96x4StringDraw; + vOLEDImageDraw = RIT128x96x4ImageDraw; + vOLEDClear = RIT128x96x4Clear; + ulMaxY = mainMAX_ROWS_96; + pucImage = pucBasicBitmap; + break; + + default : vOLEDInit = vFormike128x128x16Init; + vOLEDStringDraw = vFormike128x128x16StringDraw; + vOLEDImageDraw = vFormike128x128x16ImageDraw; + vOLEDClear = vFormike128x128x16Clear; + ulMaxY = mainMAX_ROWS_128; + pucImage = pucGrLibBitmap; + break; + + } + + ulY = ulMaxY; + + /* Initialise the OLED and display a startup message. */ + vOLEDInit( ulSSI_FREQUENCY ); + vOLEDStringDraw( "POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); + vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); + + /* Write the message on the next available row. */ + ulY += mainCHARACTER_HEIGHT; + if( ulY >= ulMaxY ) + { + ulY = mainCHARACTER_HEIGHT; + vOLEDClear(); + vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); + } + + /* Display the message along with the maximum jitter time from the + high priority time test. */ + sprintf( cMessage, "%s [%uns]", xMessage.pcMessage, ulMaxJitter * mainNS_PER_CLOCK ); + vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName ) +{ + ( void ) pxTask; + ( void ) pcTaskName; + + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char *pcFile, unsigned long ulLine ) +{ +volatile unsigned long ulSetTo1InDebuggerToExit = 0; + + taskENTER_CRITICAL(); + { + while( ulSetTo1InDebuggerToExit == 0 ) + { + /* Nothing do do here. Set the loop variable to a non zero value in + the debugger to step out of this function to the point that caused + the assertion. */ + ( void ) pcFile; + ( void ) ulLine; + } + } + taskEXIT_CRITICAL(); +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c new file mode 100644 index 0000000..3353a82 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sx965_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "osram128x64x4.h" + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for OSRAM usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-39 on one side, 40-79 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define OSRAM_INIT_REMAP 0x52 +#define OSRAM_INIT_OFFSET 0x4C +static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from OSRAM App Note AN018. +// +//***************************************************************************** +static const unsigned char g_pucOSRAM128x64x4Init[] = +{ + // + // Column Address + // + 4, 0x15, 0, 63, 0xe3, + + // + // Row Address + // + 4, 0x75, 0, 63, 0xe3, + + // + // Contrast Control + // + 3, 0x81, 50, 0xe3, + + // + // Half Current Range + // + 2, 0x85, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Multiplex Ratio + // + 3, 0xA8, 63, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x22, 0xe3, + + // + // Row Period + // + 3, 0xB2, 70, 0xe3, + + // + // Display Clock Divide + // + 3, 0xB3, 0xF1, 0xe3, + + // + // VSL + // + 3, 0xBF, 0x0D, 0xe3, + + // + // VCOMH + // + 3, 0xBE, 0x02, 0xe3, + + // + // VP + // + 3, 0xBC, 0x10, 0xe3, + + // + // Gamma + // + 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, + + // + // Set DC-DC + 3, 0xAD, 0x03, 0xe3, + + // + // Display ON/OFF + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; + unsigned long ulRow, ulColumn; + static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; + + // + // Set the window to fill the entire display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); + OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // In vertical address increment mode, loop through each column, filling + // each row with 0. + // + for(ulColumn = 0; ulColumn < (128/2); ulColumn++) + { + // + // 8 rows (bytes) per row of text. + // + for(ulRow = 0; ulRow < 80; ulRow += 8) + { + OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + static unsigned char pucBuffer[8]; + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = 63; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + 7; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + OSRAMWriteData(pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (/e ulX) and the number of +//! columns (/e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+--3------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by` +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + static unsigned char pucBuffer[8]; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 64); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = (ulX + ulWidth - 2) / 2; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + ulHeight - 1; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, + sizeof(g_pucOSRAM128x64x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + OSRAMWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the OSRAM driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the OSRAM driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); + +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD0323 controller on the panel. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the PC7 pin as a D/Cn signal for OLED device. + // + GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD); + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Configure and enable the SSI0 port for master mode. + // + OSRAM128x64x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + OSRAM128x64x4Clear(); + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xAD, 0x02 + }; + + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h new file mode 100644 index 0000000..2ba7cb9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical +// OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM128X64X4_H__ +#define __OSRAM128X64X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAM128x64x4Clear(void); +extern void OSRAM128x64x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAM128x64x4Init(unsigned long ulFrequency); +extern void OSRAM128x64x4Enable(unsigned long ulFrequency); +extern void OSRAM128x64x4Disable(void); +extern void OSRAM128x64x4DisplayOn(void); +extern void OSRAM128x64x4DisplayOff(void); + +//***************************************************************************** +// +// The following macro(s) map old names for the OSRAM functions to the new +// names. In new code, the new names should be used in favor of the old names. +// +//***************************************************************************** +#ifndef DEPRECATED +#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable +#endif + +#endif // __OSRAM128X64X4_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c new file mode 100644 index 0000000..cff38d5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c @@ -0,0 +1,981 @@ +//***************************************************************************** +// +// rit128x96x4.c - Driver for the RIT 128x96x4 graphical OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1504-conf of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sLM3S8962_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "rit128x96x4.h" + +//***************************************************************************** +// +// Macros that define the peripheral, port, and pin used for the OLEDDC +// panel control signal. +// +//***************************************************************************** + +unsigned long ulGPIOId = 0, ulGPIOBase = 0, ulOLEDDC_PIN = 0, ulOLEDEN_PIN = 0; + +#define LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOA +#define LM3S8962_GPIO_OLEDDC_BASE GPIO_PORTA_BASE +#define LM3S8962_GPIO_OLEDDC_PIN GPIO_PIN_6 +#define LM3S8962_GPIO_OLEDEN_PIN GPIO_PIN_7 + +#define LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOH +#define LM3S1968_GPIO_OLEDDC_BASE GPIO_PORTH_BASE +#define LM3S1968_GPIO_OLEDDC_PIN GPIO_PIN_2 +#define LM3S1968_GPIO_OLEDEN_PIN GPIO_PIN_3 + + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for display usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Buffer for storing sequences of command and data for the display. +// +//***************************************************************************** +static unsigned char g_pucBuffer[8]; + +//***************************************************************************** +// +// Define the SSD1329 128x96x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. Note that the controller support 128 rows while +// the RIT display only uses 96. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-63 on one side, 64-127 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-127 map to COM 127-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define RIT_INIT_REMAP 0x52 // app note says 0x51 +#define RIT_INIT_OFFSET 0x00 +static const unsigned char g_pucRIT128x96x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucRIT128x96x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD1329 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from RIT App Note for +// the P14201. Values used are from the RIT app note, except where noted. +// +//***************************************************************************** +static const unsigned char g_pucRIT128x96x4Init[] = +{ + // + // Unlock commands + // + 3, 0xFD, 0x12, 0xe3, + + // + // Display off + // + 2, 0xAE, 0xe3, + + // + // Icon off + // + 3, 0x94, 0, 0xe3, + + // + // Multiplex ratio + // + 3, 0xA8, 95, 0xe3, + + // + // Contrast + // + 3, 0x81, 0xb7, 0xe3, + + // + // Pre-charge current + // + 3, 0x82, 0x3f, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, RIT_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, RIT_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x11, 0xe3, + + // + // Frame frequency + // + 3, 0xB2, 0x23, 0xe3, + + // + // Front Clock Divider + // + 3, 0xB3, 0xe2, 0xe3, + + // + // Set gray scale table. App note uses default command: + // 2, 0xB7, 0xe3 + // This gray scale attempts some gamma correction to reduce the + // the brightness of the low levels. + // + 17, 0xB8, 1, 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 19, 22, 26, 30, 0xe3, + + // + // Second pre-charge period. App note uses value 0x04. + // + 3, 0xBB, 0x01, 0xe3, + + // + // Pre-charge voltage + // + 3, 0xBC, 0x3f, 0xe3, + + // + // Display ON + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, ulOLEDDC_PIN); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 127 }; + unsigned long ulRow, ulColumn; + + // + // Clear out the buffer used for sending bytes to the display. + *(unsigned long *)&g_pucBuffer[0] = 0; + *(unsigned long *)&g_pucBuffer[4] = 0; + + // + // Set the window to fill the entire display. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); + RITWriteCommand(pucCommand2, sizeof(pucCommand2)); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop through the rows + // + for(ulRow = 0; ulRow < 96; ulRow++) + { + // + // Loop through the columns. Each byte is two pixels, + // and the buffer hold 8 bytes, so 16 pixels are cleared + // at a time. + // + for(ulColumn = 0; ulColumn < 128; ulColumn += 8 * 2) + { + // + // Write 8 clearing bytes to the display, which will + // clear 16 pixels across. + // + RITWriteData(g_pucBuffer, sizeof(g_pucBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = 63; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + 7; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4VerticalInc, + sizeof(g_pucRIT128x96x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + g_pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + g_pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + g_pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + RITWriteData(g_pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (\e ulX) and the number of +//! columns (\e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 96); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = (ulX + ulWidth - 2) / 2; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + ulHeight - 1; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + RITWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the RIT driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the RIT driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD1329 controller on the panel. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + + /* Determine which board is being used. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + /* Ethernet is present, we must be using the LM3S8962 EK. */ + ulGPIOId = LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S8962_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_6; + ulOLEDEN_PIN = GPIO_PIN_7; + } + else + { + /* Ethernet is not present, we must be using the LM3S1968 EK. */ + ulGPIOId = LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S1968_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_2; + ulOLEDEN_PIN = GPIO_PIN_3; + } + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(ulGPIOId); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the GPIO port pin used as a D/Cn signal for OLED device, + // and the port pin used to enable power to the OLED panel. + // + GPIOPinTypeGPIOOutput(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN); + GPIOPadConfigSet(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + ulOLEDDC_PIN | ulOLEDEN_PIN); + + // + // Configure and enable the SSI0 port for master mode. + // + RIT128x96x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + RIT128x96x4Clear(); + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xe3 + }; + + // + // Put the display to sleep. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/ExtDll.iex b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/ExtDll.iex new file mode 100644 index 0000000..b661f48 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.axf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.axf new file mode 100644 index 0000000..ffc1c9d Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.axf differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.bin b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.bin new file mode 100644 index 0000000..c89d6f3 Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.bin differ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.lnp b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.lnp new file mode 100644 index 0000000..1baf87c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.lnp @@ -0,0 +1,3 @@ +--cpu Cortex-M3 ".\rvmdk\blockq.o" ".\rvmdk\blocktim.o" ".\rvmdk\death.o" ".\rvmdk\integer.o" ".\rvmdk\main.o" ".\rvmdk\partest.o" ".\rvmdk\pollq.o" ".\rvmdk\semtest.o" ".\rvmdk\startup_rvmdk.o" ".\rvmdk\timertest.o" ".\rvmdk\genqtest.o" ".\rvmdk\qpeek.o" ".\rvmdk\intqueuetimer.o" ".\rvmdk\intqueue.o" ".\rvmdk\recmutex.o" ".\rvmdk\rit128x96x4.o" "..\Common\drivers\LuminaryMicro\Keil\driverlib.lib" ".\rvmdk\formike128x128x16.o" "..\Common\drivers\LuminaryMicro\Keil\grlib.lib" ".\rvmdk\tasks.o" ".\rvmdk\list.o" ".\rvmdk\queue.o" ".\rvmdk\port.o" ".\rvmdk\heap_2.o" ".\rvmdk\osram128x64x4.o" ".\rvmdk\uip_task.o" ".\rvmdk\emac.o" ".\rvmdk\httpd.o" ".\rvmdk\httpd-cgi.o" ".\rvmdk\httpd-fs.o" ".\rvmdk\http-strings.o" ".\rvmdk\uip_arp.o" ".\rvmdk\psock.o" ".\rvmdk\timer.o" ".\rvmdk\uip.o" --strict --scatter ".\rvmdk\RTOSDemo.sct" +--entry Reset_Handler --autoat --summary_stderr --info summarysizes --info sizes --info totals + --list ".\rvmdk\RTOSDemo.map" -o ".\rvmdk\RTOSDemo.axf" \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.map b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.map new file mode 100644 index 0000000..ecd7484 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.map @@ -0,0 +1,133 @@ +ARM Linker, 4.1 [Build 713] [Standard] + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 684 82 0 24 0 13516 blockq.o + 1148 114 0 32 0 3117 blocktim.o + 356 62 0 20 0 3078 death.o + 72 8 0 24 0 2827 emac.o + 1598 80 48 0 28 10418 formike128x128x16.o + 1400 154 0 32 0 4030 genqtest.o + 300 32 0 24 24000 3375 heap_2.o + 178 20 0 4 0 2556 integer.o + 2216 288 0 84 400 11284 intqueue.o + 200 26 0 0 0 1398 intqueuetimer.o + 160 0 0 0 0 2769 list.o + 956 340 4933 12 25 23214 main.o + 888 86 571 25 0 5912 osram128x64x4.o + 40 4 0 0 0 425 partest.o + 360 62 0 12 0 2481 pollq.o + 352 40 0 4 0 4285 port.o + 984 166 0 24 0 3821 qpeek.o + 1438 6 0 0 80 12145 queue.o + 776 166 0 48 0 3122 recmutex.o + 1036 122 571 25 0 6352 rit128x96x4.o + 576 86 0 18 0 3080 semtest.o + 276 256 0 0 2048 456 startup_rvmdk.o + 3028 436 20 80 250 22209 tasks.o + 196 32 0 12 0 1272 timertest.o + + ---------------------------------------------------------------------- + 19228 2668 6180 512 26840 147142 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 10 0 5 8 9 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 44 6 0 0 0 84 __2sprintf.o + 58 0 0 0 0 0 __dczerorl.o + 8 0 0 0 0 68 __main.o + 284 0 0 0 0 156 __printf_wp.o + 52 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 44 0 0 0 0 108 _printf_char.o + 48 6 0 0 0 96 _printf_char_common.o + 120 18 0 0 0 92 _printf_dec.o + 180 0 0 0 0 88 _printf_intcommon.o + 0 0 0 0 0 0 _printf_percent.o + 4 0 0 0 0 0 _printf_percent_end.o + 6 0 0 0 0 0 _printf_s.o + 82 0 0 0 0 80 _printf_str.o + 6 0 0 0 0 0 _printf_u.o + 10 0 0 0 0 68 _sputc.o + 16 0 0 0 0 68 aeabi_memset.o + 12 0 0 0 0 72 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 6 0 0 0 0 0 libinit.o + 2 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 84 0 0 0 0 76 memcmp.o + 8 4 0 0 0 68 rt_fp_status_addr_intlibspace.o + 68 0 0 0 0 68 rt_memclr.o + 78 0 0 0 0 80 rt_memclr_w.o + 138 0 0 0 0 68 rt_memcpy_v6.o + 100 0 0 0 0 80 rt_memcpy_w.o + 0 0 0 0 0 0 rtentry.o + 12 0 0 0 0 0 rtentry2.o + 6 0 0 0 0 0 rtentry4.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 62 0 0 0 0 76 strlen.o + 86 0 0 0 0 76 strncpy.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 28 0 0 0 0 5171 ethernet.o + 278 0 0 0 0 3540 gpio.o + 144 4 96 0 0 1943 interrupt.o + 138 0 0 0 0 3529 ssi.o + 690 70 156 0 0 4940 sysctl.o + 72 0 0 0 0 2700 timer.o + 14 0 0 0 0 76 fpinit.o + 32 0 0 0 0 14114 context.o + 0 0 1500 0 0 14171 fontcmss12.o + 744 6 0 0 32 16318 image.o + 88 0 0 0 0 1366 line.o + 172 0 0 0 0 920 rectangle.o + 678 0 0 0 0 1899 string.o + + ---------------------------------------------------------------------- + 4872 130 1752 0 128 72695 Library Totals + 24 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 1770 50 0 0 96 2008 c_w.l + 1350 74 252 0 0 21823 driverlib.lib + 14 0 0 0 0 76 fz_ws.l + 1714 6 1500 0 32 48788 grlib.lib + + ---------------------------------------------------------------------- + 4872 130 1752 0 128 72695 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 24100 2798 7932 512 26968 209283 Grand Totals + 24100 2798 7932 28 26968 209283 ELF Image Totals (compressed) + 24100 2798 7932 28 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 32032 ( 31.28kB) + Total RW Size (RW Data + ZI Data) 27480 ( 26.84kB) + Total ROM Size (Code + RO Data + RW Data) 32060 ( 31.31kB) + +============================================================================== + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.plg b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.plg new file mode 100644 index 0000000..ebc3ee6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.plg @@ -0,0 +1,9 @@ + + +
+
µVision Build Log

+
Project:

+C:\home\dwilson\dev\CCS5ws\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\RTOSDemo.uvproj
+Project File Date:  12/01/2011
+
+
Output:

diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.sct b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.sct
new file mode 100644
index 0000000..79a39c7
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.tra b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.tra
new file mode 100644
index 0000000..d81e4f6
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/RTOSDemo.tra
@@ -0,0 +1,52 @@
+*** Creating Trace Output File '.\rvmdk\RTOSDemo.tra' Ok.
+### Preparing for ADS-LD.
+### Creating ADS-LD Command Line
+### List of Objects: adding '".\rvmdk\blockq.o"'
+### List of Objects: adding '".\rvmdk\blocktim.o"'
+### List of Objects: adding '".\rvmdk\death.o"'
+### List of Objects: adding '".\rvmdk\integer.o"'
+### List of Objects: adding '".\rvmdk\main.o"'
+### List of Objects: adding '".\rvmdk\partest.o"'
+### List of Objects: adding '".\rvmdk\pollq.o"'
+### List of Objects: adding '".\rvmdk\semtest.o"'
+### List of Objects: adding '".\rvmdk\startup_rvmdk.o"'
+### List of Objects: adding '".\rvmdk\timertest.o"'
+### List of Objects: adding '".\rvmdk\genqtest.o"'
+### List of Objects: adding '".\rvmdk\qpeek.o"'
+### List of Objects: adding '".\rvmdk\intqueuetimer.o"'
+### List of Objects: adding '".\rvmdk\intqueue.o"'
+### List of Objects: adding '".\rvmdk\recmutex.o"'
+### List of Objects: adding '".\rvmdk\rit128x96x4.o"'
+### List of Objects: adding '"..\Common\drivers\LuminaryMicro\Keil\driverlib.lib"'
+### List of Objects: adding '".\rvmdk\formike128x128x16.o"'
+### List of Objects: adding '"..\Common\drivers\LuminaryMicro\Keil\grlib.lib"'
+### List of Objects: adding '".\rvmdk\tasks.o"'
+### List of Objects: adding '".\rvmdk\list.o"'
+### List of Objects: adding '".\rvmdk\queue.o"'
+### List of Objects: adding '".\rvmdk\port.o"'
+### List of Objects: adding '".\rvmdk\heap_2.o"'
+### List of Objects: adding '".\rvmdk\osram128x64x4.o"'
+### List of Objects: adding '".\rvmdk\uip_task.o"'
+### List of Objects: adding '".\rvmdk\emac.o"'
+### List of Objects: adding '".\rvmdk\httpd.o"'
+### List of Objects: adding '".\rvmdk\httpd-cgi.o"'
+### List of Objects: adding '".\rvmdk\httpd-fs.o"'
+### List of Objects: adding '".\rvmdk\http-strings.o"'
+### List of Objects: adding '".\rvmdk\uip_arp.o"'
+### List of Objects: adding '".\rvmdk\psock.o"'
+### List of Objects: adding '".\rvmdk\timer.o"'
+### List of Objects: adding '".\rvmdk\uip.o"'
+### ADS-LD Command completed:
+--cpu Cortex-M3 ".\rvmdk\blockq.o" ".\rvmdk\blocktim.o" ".\rvmdk\death.o" ".\rvmdk\integer.o" ".\rvmdk\main.o" ".\rvmdk\partest.o" ".\rvmdk\pollq.o" ".\rvmdk\semtest.o" ".\rvmdk\startup_rvmdk.o" ".\rvmdk\timertest.o" ".\rvmdk\genqtest.o" ".\rvmdk\qpeek.o" ".\rvmdk\intqueuetimer.o" ".\rvmdk\intqueue.o" ".\rvmdk\recmutex.o" ".\rvmdk\rit128x96x4.o" "..\Common\drivers\LuminaryMicro\Keil\driverlib.lib" ".\rvmdk\formike128x128x16.o" "..\Common\drivers\LuminaryMicro\Keil\grlib.lib" ".\rvmdk\tasks.o" ".\rvmdk\list.o" ".\rvmdk\queue.o" ".\rvmdk\port.o" ".\rvmdk\heap_2.o" ".\rvmdk\osram128x64x4.o" ".\rvmdk\uip_task.o" ".\rvmdk\emac.o" ".\rvmdk\httpd.o" ".\rvmdk\httpd-cgi.o" ".\rvmdk\httpd-fs.o" ".\rvmdk\http-strings.o" ".\rvmdk\uip_arp.o" ".\rvmdk\psock.o" ".\rvmdk\timer.o" ".\rvmdk\uip.o" --strict --scatter ".\rvmdk\RTOSDemo.sct" 

+--entry Reset_Handler --autoat --summary_stderr --info summarysizes --info sizes --info totals 

+ --list ".\rvmdk\RTOSDemo.map" -o ".\rvmdk\RTOSDemo.axf"### Preparing Environment (PrepEnvAds)
+### ADS-LD Output File: '.\rvmdk\RTOSDemo.axf'
+### ADS-LD Command File: '.\rvmdk\RTOSDemo.lnp'
+### Checking for dirty Components...
+### Creating CmdFile '.\rvmdk\RTOSDemo.lnp', Handle=0x000004F8
+### Writing '.lnp' file
+### ADS-LD Command file '.\rvmdk\RTOSDemo.lnp' is ready.
+### ADS-LD: About to start ADS-LD Thread.
+### ADS-LD: executed with 0 errors
+### Updating obj list
+### LDADS_file() completed.
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blockq.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blockq.crf
new file mode 100644
index 0000000..5196cca
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blockq.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blocktim.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blocktim.crf
new file mode 100644
index 0000000..3b63b91
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/blocktim.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/death.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/death.crf
new file mode 100644
index 0000000..73c2fbe
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/death.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.__i
new file mode 100644
index 0000000..704405c
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\emac.o" --omf_browse ".\rvmdk\emac.crf" --depend ".\rvmdk\emac.d" "webserver\emac.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.crf
new file mode 100644
index 0000000..93bf01d
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/emac.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/formike128x128x16.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/formike128x128x16.__i
new file mode 100644
index 0000000..1243fe1
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/formike128x128x16.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\formike128x128x16.o" --omf_browse ".\rvmdk\formike128x128x16.crf" --depend ".\rvmdk\formike128x128x16.d" "formike128x128x16.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/formike128x128x16.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/formike128x128x16.crf
new file mode 100644
index 0000000..e23bd97
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/formike128x128x16.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/genqtest.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/genqtest.crf
new file mode 100644
index 0000000..d3cc151
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/genqtest.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.__i
new file mode 100644
index 0000000..3160c8c
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\heap_2.o" --omf_browse ".\rvmdk\heap_2.crf" --depend ".\rvmdk\heap_2.d" "..\..\Source\portable\MemMang\heap_2.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.crf
new file mode 100644
index 0000000..bb4eba2
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/heap_2.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/http-strings.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/http-strings.__i
new file mode 100644
index 0000000..6a9a268
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/http-strings.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\http-strings.o" --omf_browse ".\rvmdk\http-strings.crf" --depend ".\rvmdk\http-strings.d" "webserver\http-strings.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/http-strings.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/http-strings.crf
new file mode 100644
index 0000000..cd74580
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/http-strings.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.__i
new file mode 100644
index 0000000..c8b71ef
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\httpd-cgi.o" --omf_browse ".\rvmdk\httpd-cgi.crf" --depend ".\rvmdk\httpd-cgi.d" "webserver\httpd-cgi.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.crf
new file mode 100644
index 0000000..2482816
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-cgi.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.__i
new file mode 100644
index 0000000..62de74e
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\httpd-fs.o" --omf_browse ".\rvmdk\httpd-fs.crf" --depend ".\rvmdk\httpd-fs.d" "webserver\httpd-fs.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.crf
new file mode 100644
index 0000000..6f28e6c
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd-fs.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.__i
new file mode 100644
index 0000000..7ac8d3d
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\httpd.o" --omf_browse ".\rvmdk\httpd.crf" --depend ".\rvmdk\httpd.d" "webserver\httpd.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.crf
new file mode 100644
index 0000000..d47ea2e
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/httpd.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/integer.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/integer.crf
new file mode 100644
index 0000000..97e0e74
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/integer.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueue.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueue.crf
new file mode 100644
index 0000000..2094ca1
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueue.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueuetimer.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueuetimer.crf
new file mode 100644
index 0000000..79f0384
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/intqueuetimer.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.__i
new file mode 100644
index 0000000..662962b
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\list.o" --omf_browse ".\rvmdk\list.crf" --depend ".\rvmdk\list.d" "..\..\Source\list.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.crf
new file mode 100644
index 0000000..ba9fff8
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/list.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.__i
new file mode 100644
index 0000000..7c1cff3
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\main.o" --omf_browse ".\rvmdk\main.crf" --depend ".\rvmdk\main.d" "main.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.crf
new file mode 100644
index 0000000..c7fa24c
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/main.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/osram128x64x4.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/osram128x64x4.__i
new file mode 100644
index 0000000..a07efc6
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/osram128x64x4.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\osram128x64x4.o" --omf_browse ".\rvmdk\osram128x64x4.crf" --depend ".\rvmdk\osram128x64x4.d" "osram128x64x4.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/osram128x64x4.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/osram128x64x4.crf
new file mode 100644
index 0000000..b1c5ac2
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/osram128x64x4.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/partest.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/partest.crf
new file mode 100644
index 0000000..db9ffc8
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/partest.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/pollq.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/pollq.crf
new file mode 100644
index 0000000..8ee4d5a
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/pollq.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.__i
new file mode 100644
index 0000000..84ad890
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\port.o" --omf_browse ".\rvmdk\port.crf" --depend ".\rvmdk\port.d" "..\..\Source\portable\RVDS\ARM_CM3\port.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.crf
new file mode 100644
index 0000000..8fd5549
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/port.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.__i
new file mode 100644
index 0000000..81742f7
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\psock.o" --omf_browse ".\rvmdk\psock.crf" --depend ".\rvmdk\psock.d" "..\Common\ethernet\uIP\uip-1.0\uip\psock.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.crf
new file mode 100644
index 0000000..c5ef03e
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/psock.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/qpeek.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/qpeek.crf
new file mode 100644
index 0000000..953808e
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/qpeek.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.__i
new file mode 100644
index 0000000..7256e84
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\queue.o" --omf_browse ".\rvmdk\queue.crf" --depend ".\rvmdk\queue.d" "..\..\Source\queue.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.crf
new file mode 100644
index 0000000..83bc6be
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/queue.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/recmutex.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/recmutex.crf
new file mode 100644
index 0000000..8905d60
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/recmutex.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/rit128x96x4.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/rit128x96x4.crf
new file mode 100644
index 0000000..8d1bf1e
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/rit128x96x4.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/semtest.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/semtest.crf
new file mode 100644
index 0000000..f38f94b
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/semtest.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.__i
new file mode 100644
index 0000000..d05cd48
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\tasks.o" --omf_browse ".\rvmdk\tasks.crf" --depend ".\rvmdk\tasks.d" "..\..\Source\tasks.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.crf
new file mode 100644
index 0000000..dca898f
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/tasks.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.__i
new file mode 100644
index 0000000..30e1462
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\timer.o" --omf_browse ".\rvmdk\timer.crf" --depend ".\rvmdk\timer.d" "..\Common\ethernet\uIP\uip-1.0\uip\timer.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.crf
new file mode 100644
index 0000000..e3c960b
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timer.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timertest.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timertest.crf
new file mode 100644
index 0000000..9b17f93
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/timertest.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.__i
new file mode 100644
index 0000000..3c6f379
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\uip.o" --omf_browse ".\rvmdk\uip.crf" --depend ".\rvmdk\uip.d" "..\Common\ethernet\uIP\uip-1.0\uip\uip.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.crf
new file mode 100644
index 0000000..27f3a59
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.__i
new file mode 100644
index 0000000..f3ec4a5
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\uip_arp.o" --omf_browse ".\rvmdk\uip_arp.crf" --depend ".\rvmdk\uip_arp.d" "..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.crf
new file mode 100644
index 0000000..f2abf22
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_arp.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.__i b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.__i
new file mode 100644
index 0000000..b546891
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -I. -I.\..\Common\drivers\LuminaryMicro -I..\..\Source\portable\RVDS\ARM_CM3 -I..\..\Source\include -I..\Common\include -I..\Common\ethernet\uIP\uip-1.0\uip -I.\webserver --diag_suppress 191,550,513,167,177,144 -I "C:\Keil\ARM\CMSIS\Include" -I "C:\Keil\ARM\INC\Luminary" -DRVDS_ARMCM3_LM3S102 -DPACK_STRUCT_END= -DALIGN_STRUCT_END= -o ".\rvmdk\uip_task.o" --omf_browse ".\rvmdk\uip_task.crf" --depend ".\rvmdk\uip_task.d" "webserver\uIP_Task.c"
\ No newline at end of file
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.crf b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.crf
new file mode 100644
index 0000000..2d0d0b7
Binary files /dev/null and b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rvmdk/uip_task.crf differ
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat
new file mode 100644
index 0000000..9d325f6
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat
@@ -0,0 +1,24 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armlmiftdi.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\TexasInstruments\FlashLM3Sx8xx.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\TexasInstruments\LM3S6965.ddf" "--drv_verify_download" "--semihosting=none" "--device=LM3S6965" "--lmiftdi_speed=500" 
+
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt
new file mode 100644
index 0000000..81fb875
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt
@@ -0,0 +1,80 @@
+
+
+
+  
+    
+      201622
+      
+        20
+        1006
+        268
+        67
+      
+      
+        
+          
+          
+          
+          
+        164272727
+      
+      
+        
+          
+          
+          
+          
+        200
+        
+        
+      10Disassembly_I05002000
+    200100100100100
+    
+      
+      
+    
+        
+          
+            TabID-10465-12018
+            Debug Log
+            Debug-Log
+            
+          
+          
+            TabID-9942-12028
+            Build
+            Build
+            
+          
+        TabID-31294-227BreakpointsBreakpoints
+        
+      0
+        
+          
+            TabID-21213-12021
+            Workspace
+            Workspace
+            
+              
+            RTOSDemoRTOSDemo/Demo filesRTOSDemo/System filesRTOSDemo/uIP files
+          
+        
+        
+      0
+    
+      
+      
+      
+      
+    TextEditor$WS_DIR$\main.c00000457110051100500100000010000001
+    
+      
+      
+      
+      
+      
+    iaridepm.enu1debuggergui.enu1-2-2740238-2-2240200142857203666142857755601-2-21981682-2-216842001002381203666142857203666
+  
+
+
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni
new file mode 100644
index 0000000..b77749e
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni
@@ -0,0 +1,61 @@
+[CodeCoverage]
+Enabled=_ 0
+[DisAssemblyWindow]
+NumStates=_ 1
+State 1=_ 1
+[Profiling]
+Enabled=0
+[StackPlugin]
+Enabled=1
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnHow=0
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[Stack]
+FillEnabled=0
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnLogOnly=1
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[LMIFTDIDriver]
+LMI_ResetMode=0x00000000
+[DebugChecksum]
+Checksum=-1311150949
+[Exceptions]
+StopOnUncaught=_ 0
+StopOnThrow=_ 0
+[CallStack]
+ShowArgs=0
+[Disassembly]
+MixedMode=1
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[CallStackLog]
+Enabled=0
+[DriverProfiling]
+Enabled=0
+Mode=0
+Graph=0
+Symbiont=0
+Exclusions=
+[Disassemble mode]
+mode=1
+[Breakpoints]
+Bp0=_ "STD_CODE" "{$PROJ_DIR$\main.c}.489.3" 1 0 0 0 "" 0 ""
+Count=1
+[Aliases]
+Count=0
+SuppressDialog=0
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt
new file mode 100644
index 0000000..c5db75f
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt
@@ -0,0 +1,49 @@
+
+
+
+  
+    
+  RTOSDemo/Debug
+  
+    
+      
+        
+          
+          
+          
+          
+        241272727
+      
+    4826882619100726867
+    
+      
+    
+        
+          
+            TabID-18883-22024
+            Workspace
+            Workspace
+            
+              
+            RTOSDemoRTOSDemo/Demo filesRTOSDemo/Scheduler files
+          
+        
+        
+      0TabID-29040-7360Find in FilesFind-in-FilesTabID-19024-10413BuildBuildTabID-19202-19100Debug LogDebug-Log1
+    
+      
+      
+      
+      
+    TextEditor$WS_DIR$\main.c00000443110051100500100000010000001
+    
+      
+      
+      
+      
+      
+    iaridepm.enu1-2-2719315-2-2200200119048203666188690734216-2-22191682-2-216842211002381225051119048203666
+  
+
+
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c
new file mode 100644
index 0000000..dfb51d9
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c
@@ -0,0 +1,219 @@
+//*****************************************************************************
+//
+// startup_ewarm.c - Boot code for Stellaris.
+//
+// Copyright (c) 2006-2007 Luminary Micro, Inc.  All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 100 of the Stellaris Ethernet
+// Applications Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Enable the IAR extensions for this source file.
+//
+//*****************************************************************************
+#pragma language=extended
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+static void NmiSR(void);
+static void FaultISR(void);
+static void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// External declaration for the interrupt handler used by the application.
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern void __iar_program_start(void);
+extern void xPortPendSVHandler(void);
+extern void xPortSysTickHandler(void);
+extern void vPortSVCHandler(void);
+extern void vT2InterruptHandler( void );
+extern void vT3InterruptHandler( void );
+extern void vEMAC_ISR( void );
+extern void Timer0IntHandler( void );
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+#ifndef STACK_SIZE
+#define STACK_SIZE                              120
+#endif
+static unsigned long pulStack[STACK_SIZE] @ ".noinit";
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table.  The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+    void (*pfnHandler)(void);
+    unsigned long ulPtr;
+}
+uVectorEntry;
+
+//*****************************************************************************
+//
+// The minimal vector table for a Cortex-M3.  Note that the proper constructs
+// must be placed on this to ensure that it ends up at physical address
+// 0x0000.0000.
+//
+//*****************************************************************************
+__root const uVectorEntry __vector_table[] @ ".intvec" =
+{
+    { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },
+                                            // The initial stack pointer
+    __iar_program_start,                    // The reset handler
+    NmiSR,                                  // The NMI handler
+    FaultISR,                               // The hard fault handler
+    IntDefaultHandler,                      // The MPU fault handler
+    IntDefaultHandler,                      // The bus fault handler
+    IntDefaultHandler,                      // The usage fault handler
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    vPortSVCHandler,                        // SVCall handler
+    IntDefaultHandler,                      // Debug monitor handler
+    0,                                      // Reserved
+    xPortPendSVHandler,                     // The PendSV handler
+    xPortSysTickHandler,                    // The SysTick handler
+    IntDefaultHandler,                      // GPIO Port A
+    IntDefaultHandler,                      // GPIO Port B
+    IntDefaultHandler,                      // GPIO Port C
+    IntDefaultHandler,                      // GPIO Port D
+    IntDefaultHandler,                      // GPIO Port E
+    IntDefaultHandler,                      // UART0 Rx and Tx
+    IntDefaultHandler,                      // UART1 Rx and Tx
+    IntDefaultHandler,                      // SSI Rx and Tx
+    IntDefaultHandler,                      // I2C Master and Slave
+    IntDefaultHandler,                      // PWM Fault
+    IntDefaultHandler,                      // PWM Generator 0
+    IntDefaultHandler,                      // PWM Generator 1
+    IntDefaultHandler,                      // PWM Generator 2
+    IntDefaultHandler,                      // Quadrature Encoder
+    IntDefaultHandler,                      // ADC Sequence 0
+    IntDefaultHandler,                      // ADC Sequence 1
+    IntDefaultHandler,                      // ADC Sequence 2
+    IntDefaultHandler,                      // ADC Sequence 3
+    IntDefaultHandler,                      // Watchdog timer
+    Timer0IntHandler,                       // Timer 0 subtimer A
+    IntDefaultHandler,                      // Timer 0 subtimer B
+    IntDefaultHandler,                      // Timer 1 subtimer A
+    IntDefaultHandler,                      // Timer 1 subtimer B
+    vT2InterruptHandler,                      // Timer 2 subtimer A
+    IntDefaultHandler,                      // Timer 2 subtimer B
+    IntDefaultHandler,                      // Analog Comparator 0
+    IntDefaultHandler,                      // Analog Comparator 1
+    IntDefaultHandler,                      // Analog Comparator 2
+    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
+    IntDefaultHandler,                      // FLASH Control
+    IntDefaultHandler,                      // GPIO Port F
+    IntDefaultHandler,                      // GPIO Port G
+    IntDefaultHandler,                      // GPIO Port H
+    IntDefaultHandler,                      // UART2 Rx and Tx
+    IntDefaultHandler,                      // SSI1 Rx and Tx
+    vT3InterruptHandler,                    // Timer 3 subtimer A
+    IntDefaultHandler,                      // Timer 3 subtimer B
+    IntDefaultHandler,                      // I2C1 Master and Slave
+    IntDefaultHandler,                      // Quadrature Encoder 1
+    IntDefaultHandler,                      // CAN0
+    IntDefaultHandler,                      // CAN1
+    IntDefaultHandler,                      // CAN2
+    vEMAC_ISR,                     			// Ethernet
+    IntDefaultHandler,                      // Hibernate
+    IntDefaultHandler,                      // USB0
+    IntDefaultHandler,                      // PWM Generator 3
+    IntDefaultHandler,                      // uDMA Software Transfer
+    IntDefaultHandler                       // uDMA Error
+};
+
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI.  This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+static void
+NmiSR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+FaultISR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S
new file mode 100644
index 0000000..b7077b1
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S
@@ -0,0 +1,251 @@
+; <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;
+; startup_rvmdk.S - Startup code for use with Keil's uVision.
+;
+; Copyright (c) 2007 Luminary Micro, Inc.  All rights reserved.
+; 
+; Software License Agreement
+; 
+; Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+; exclusively on LMI's microcontroller products.
+; 
+; The software is owned by LMI and/or its suppliers, and is protected under
+; applicable copyright laws.  All rights are reserved.  Any use in violation
+; of the foregoing restrictions may subject the user to criminal sanctions
+; under applicable laws, as well as to civil liability for the breach of the
+; terms and conditions of this license.
+; 
+; THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; 
+; This is part of revision 1408 of the Stellaris Peripheral Driver Library.
+;
+;******************************************************************************
+
+;******************************************************************************
+;
+;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+;******************************************************************************
+Stack   EQU     0x00000800
+
+;******************************************************************************
+;
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+;******************************************************************************
+Heap    EQU     0x00000000
+
+;******************************************************************************
+;
+; Allocate space for the stack.
+;
+;******************************************************************************
+        AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+        SPACE   Stack
+__initial_sp
+
+;******************************************************************************
+;
+; Allocate space for the heap.
+;
+;******************************************************************************
+        AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+        SPACE   Heap
+__heap_limit
+
+;******************************************************************************
+;
+; Indicate that the code in this file preserves 8-byte alignment of the stack.
+;
+;******************************************************************************
+        PRESERVE8
+
+;******************************************************************************
+;
+; Place code into the reset code section.
+;
+;******************************************************************************
+        AREA    RESET, CODE, READONLY
+        THUMB
+
+;******************************************************************************
+;
+; The vector table.
+;
+;******************************************************************************
+        EXPORT  __Vectors
+__Vectors
+        DCD     StackMem + Stack            ; Top of Stack
+        DCD     Reset_Handler               ; Reset Handler
+        DCD     NmiSR                       ; NMI Handler
+        DCD     FaultISR                    ; Hard Fault Handler
+        DCD     IntDefaultHandler           ; MPU Fault Handler
+        DCD     IntDefaultHandler           ; Bus Fault Handler
+        DCD     IntDefaultHandler           ; Usage Fault Handler
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+        DCD     0                           ; Reserved
+		EXTERN 	vPortSVCHandler
+        DCD     vPortSVCHandler           	; SVCall Handler
+        DCD     IntDefaultHandler           ; Debug Monitor Handler
+        DCD     0                           ; Reserved
+		EXTERN  xPortPendSVHandler
+        DCD     xPortPendSVHandler          ; PendSV Handler
+        EXTERN  xPortSysTickHandler
+        DCD     xPortSysTickHandler         ; SysTick Handler
+        DCD     IntDefaultHandler           ; GPIO Port A
+        DCD     IntDefaultHandler           ; GPIO Port B
+        DCD     IntDefaultHandler           ; GPIO Port C
+        DCD     IntDefaultHandler           ; GPIO Port D
+        DCD     IntDefaultHandler           ; GPIO Port E
+        DCD     IntDefaultHandler           ; UART0
+        DCD     IntDefaultHandler           ; UART1
+        DCD     IntDefaultHandler           ; SSI
+        DCD     IntDefaultHandler           ; I2C
+        DCD     IntDefaultHandler           ; PWM Fault
+        DCD     IntDefaultHandler           ; PWM Generator 0
+        DCD     IntDefaultHandler           ; PWM Generator 1
+        DCD     IntDefaultHandler           ; PWM Generator 2
+        DCD     IntDefaultHandler           ; Quadrature Encoder
+        DCD     IntDefaultHandler           ; ADC Sequence 0
+        DCD     IntDefaultHandler           ; ADC Sequence 1
+        DCD     IntDefaultHandler           ; ADC Sequence 2
+        DCD     IntDefaultHandler           ; ADC Sequence 3
+        DCD     IntDefaultHandler           ; Watchdog
+        EXTERN  Timer0IntHandler
+        DCD     Timer0IntHandler            ; Timer 0A
+        DCD     IntDefaultHandler           ; Timer 0B
+        DCD     IntDefaultHandler           ; Timer 1A
+        DCD     IntDefaultHandler           ; Timer 1B
+		EXTERN  vT2InterruptHandler
+        DCD     vT2InterruptHandler         ; Timer 2A
+        DCD     IntDefaultHandler           ; Timer 2B
+        DCD     IntDefaultHandler           ; Comp 0
+        DCD     IntDefaultHandler           ; Comp 1
+        DCD     IntDefaultHandler           ; Comp 2
+        DCD     IntDefaultHandler           ; System Control
+        DCD     IntDefaultHandler           ; Flash Control
+        DCD     IntDefaultHandler           ; GPIO Port F
+        DCD     IntDefaultHandler           ; GPIO Port G
+        DCD     IntDefaultHandler           ; GPIO Port H
+        DCD     IntDefaultHandler           ; UART2 Rx and Tx
+        DCD     IntDefaultHandler           ; SSI1 Rx and Tx
+		EXTERN  vT3InterruptHandler
+        DCD     vT3InterruptHandler         ; Timer 3 subtimer A
+        DCD     IntDefaultHandler           ; Timer 3 subtimer B
+        DCD     IntDefaultHandler           ; I2C1 Master and Slave
+        DCD     IntDefaultHandler           ; Quadrature Encoder 1
+        DCD     IntDefaultHandler           ; CAN0
+        DCD     IntDefaultHandler           ; CAN1
+        DCD     0                           ; Reserved
+        EXTERN  vEMAC_ISR
+        DCD     vEMAC_ISR                   ; Ethernet
+        DCD     IntDefaultHandler           ; Hibernate
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor first starts execution
+; following a reset event.
+;
+;******************************************************************************
+        EXPORT  Reset_Handler
+Reset_Handler
+        ;
+        ; Call the C library enty point that handles startup.  This will copy
+        ; the .data section initializers from flash to SRAM and zero fill the
+        ; .bss section.  It will then call __rt_entry, which will be either the
+        ; C library version or the one supplied here depending on the
+        ; configured startup type.
+        ;
+        IMPORT  __main
+        B       __main
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor receives a NMI.  This
+; simply enters an infinite loop, preserving the system state for examination
+; by a debugger.
+;
+;******************************************************************************
+NmiSR
+        B       NmiSR
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor receives a fault
+; interrupt.  This simply enters an infinite loop, preserving the system state
+; for examination by a debugger.
+;
+;******************************************************************************
+FaultISR
+        B       FaultISR
+
+;******************************************************************************
+;
+; This is the code that gets called when the processor receives an unexpected
+; interrupt.  This simply enters an infinite loop, preserving the system state
+; for examination by a debugger.
+;
+;******************************************************************************
+IntDefaultHandler
+        B       IntDefaultHandler
+
+;******************************************************************************
+;
+; Make sure the end of this section is aligned.
+;
+;******************************************************************************
+        ALIGN
+
+;******************************************************************************
+;
+; Some code in the normal code section for initializing the heap and stack.
+;
+;******************************************************************************
+        AREA    |.text|, CODE, READONLY
+
+;******************************************************************************
+;
+; The function expected of the C library startup code for defining the stack
+; and heap memory locations.  For the C library version of the startup code,
+; provide this function so that the C library initialization code can find out
+; the location of the stack and heap.
+;
+;******************************************************************************
+    IF :DEF: __MICROLIB
+        EXPORT  __initial_sp
+        EXPORT  __heap_base
+        EXPORT  __heap_limit
+    ELSE
+        IMPORT  __use_two_region_memory
+        EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+        LDR     R0, =HeapMem
+        LDR     R1, =(StackMem + Stack)
+        LDR     R2, =(HeapMem + Heap)
+        LDR     R3, =StackMem
+        BX      LR
+    ENDIF
+
+;******************************************************************************
+;
+; Make sure the end of this section is aligned.
+;
+;******************************************************************************
+        ALIGN
+
+;******************************************************************************
+;
+; Tell the assembler that we're done.
+;
+;******************************************************************************
+        END
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c
new file mode 100644
index 0000000..9c65f38
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c
@@ -0,0 +1,170 @@
+/*
+    FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. 
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* High speed timer test as described in main.c. */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Library includes. */
+#include "hw_ints.h"
+#include "hw_memmap.h"
+#include "hw_types.h"
+#include "interrupt.h"
+#include "sysctl.h"
+#include "lmi_timer.h"
+#include "hw_timer.h"
+
+/* The set frequency of the interrupt.  Deviations from this are measured as
+the jitter. */
+#define timerINTERRUPT_FREQUENCY		( 20000UL )
+
+/* The expected time between each of the timer interrupts - if the jitter was
+zero. */
+#define timerEXPECTED_DIFFERENCE_VALUE	( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )
+
+/* The highest available interrupt priority. */
+#define timerHIGHEST_PRIORITY			( 0 )
+
+/* Misc defines. */
+#define timerMAX_32BIT_VALUE			( 0xffffffffUL )
+#define timerTIMER_1_COUNT_VALUE		( * ( ( volatile unsigned long * ) ( ( unsigned portLONG ) TIMER1_BASE + 0x48UL ) ) )
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt handler in which the jitter is measured. */
+void Timer0IntHandler( void );
+
+/* Stores the value of the maximum recorded jitter between interrupts. */
+volatile unsigned portLONG ulMaxJitter = 0;
+
+/*-----------------------------------------------------------*/
+
+void vSetupHighFrequencyTimer( void )
+{
+unsigned long ulFrequency;
+
+	/* Timer zero is used to generate the interrupts, and timer 1 is used
+	to measure the jitter. */
+	SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );
+    SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );
+    TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );
+    TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );
+	
+	/* Set the timer interrupt to be above the kernel - highest. */
+	IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );
+
+	/* Just used to measure time. */
+    TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );
+	
+	/* Ensure interrupts do not start until the scheduler is running. */
+	portDISABLE_INTERRUPTS();
+	
+	/* The rate at which the timer will interrupt. */
+	ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY;	
+    TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );
+    IntEnable( INT_TIMER0A );
+    TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );
+
+	/* Enable both timers. */	
+    TimerEnable( TIMER0_BASE, TIMER_A );
+    TimerEnable( TIMER1_BASE, TIMER_A );
+}
+/*-----------------------------------------------------------*/
+
+void Timer0IntHandler( void )
+{
+unsigned portLONG ulDifference;
+volatile unsigned portLONG ulCurrentCount;
+static unsigned portLONG ulMaxDifference = 0, ulLastCount = 0;
+
+	/* We use the timer 1 counter value to measure the clock cycles between
+	the timer 0 interrupts. */
+	ulCurrentCount = timerTIMER_1_COUNT_VALUE;
+
+	TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );
+
+	if( ulCurrentCount < ulLastCount )
+	{	
+		/* How many times has timer 1 counted since the last interrupt? */
+		ulDifference = 	ulLastCount - ulCurrentCount;
+	
+		/* Is this the largest difference we have measured yet? */
+		if( ulDifference > ulMaxDifference )
+		{
+			ulMaxDifference = ulDifference;
+			ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;
+		}
+	}
+	
+	ulLastCount = ulCurrentCount;
+}
+
+
+
+
+
+
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/Makefile.webserver b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/Makefile.webserver
new file mode 100644
index 0000000..f38c47a
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/Makefile.webserver
@@ -0,0 +1 @@
+APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/clock-arch.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/clock-arch.h
new file mode 100644
index 0000000..cde657b
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/clock-arch.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $
+ */
+
+#ifndef __CLOCK_ARCH_H__
+#define __CLOCK_ARCH_H__
+
+#include "FreeRTOS.h"
+
+typedef unsigned long clock_time_t;
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ
+
+#endif /* __CLOCK_ARCH_H__ */
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c
new file mode 100644
index 0000000..8570d66
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c
@@ -0,0 +1,318 @@
+/*
+    FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. 
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* Demo includes. */
+#include "emac.h"
+
+/* uIP includes. */
+#include "uip.h"
+
+/* Hardware library includes. */
+#include "hw_types.h"
+#include "hw_memmap.h"
+#include "hw_ints.h"
+#include "hw_ethernet.h"
+#include "ethernet.h"
+#include "interrupt.h"
+
+#define emacNUM_RX_BUFFERS		5
+#define emacFRAM_SIZE_BYTES 	2
+#define macNEGOTIATE_DELAY 		2000
+#define macWAIT_SEND_TIME		( 10 )
+
+/* The task that handles the MAC peripheral.  This is created at a high
+priority and is effectively a deferred interrupt handler.  The peripheral
+handling is deferred to a task to prevent the entire FIFO having to be read
+from within an ISR. */
+void vMACHandleTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The semaphore used to wake the uIP task when data arrives. */
+xSemaphoreHandle xEMACSemaphore = NULL;
+
+/* The semaphore used to wake the interrupt handler task.  The peripheral
+is processed at the task level to prevent the need to read the entire FIFO from
+within the ISR itself. */
+xSemaphoreHandle xMACInterruptSemaphore = NULL;
+
+/* The buffer used by the uIP stack.  In this case the pointer is used to
+point to one of the Rx buffers. */
+unsigned portCHAR *uip_buf;
+
+/* Buffers into which Rx data is placed. */
+static union
+{
+	unsigned portLONG ulJustForAlignment;
+	unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ];
+} uxRxBuffers;
+
+/* The length of the data within each of the Rx buffers. */
+static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ];
+
+/* Used to keep a track of the number of bytes to transmit. */
+static unsigned portLONG ulNextTxSpace;
+
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE vInitEMAC( void )
+{
+unsigned long ulTemp;
+portBASE_TYPE xReturn;
+
+	/* Ensure all interrupts are disabled. */
+	EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
+
+	/* Clear any interrupts that were already pending. */
+    ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
+    EthernetIntClear( ETH_BASE, ulTemp );
+
+	/* Initialise the MAC and connect. */
+    EthernetInit( ETH_BASE );
+    EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );
+    EthernetEnable( ETH_BASE );
+
+	/* Mark each Rx buffer as empty. */
+	for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )
+	{
+		ulRxLength[ ulTemp ] = 0;
+	}
+	
+	/* Create the queue and task used to defer the MAC processing to the
+	task level. */
+	vSemaphoreCreateBinary( xMACInterruptSemaphore );
+	xSemaphoreTake( xMACInterruptSemaphore, 0 );
+	xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
+	vTaskDelay( macNEGOTIATE_DELAY );
+	
+	/* We are only interested in Rx interrupts. */
+	IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );
+    IntEnable( INT_ETH );
+    EthernetIntEnable(ETH_BASE, ETH_INT_RX);
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
+{
+static unsigned long ulNextRxBuffer = 0;
+unsigned int iLen;
+
+	iLen = ulRxLength[ ulNextRxBuffer ];
+
+	if( iLen != 0 )
+	{
+		/* Leave room for the size at the start of the buffer. */
+		uip_buf = &( uxRxBuffers.ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
+		
+		ulRxLength[ ulNextRxBuffer ] = 0;
+		
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+    return iLen;
+}
+/*-----------------------------------------------------------*/
+
+void vInitialiseSend( void )
+{
+	/* Set the index to the first byte to send - skipping over the size
+	bytes. */
+	ulNextTxSpace = 2;
+}
+/*-----------------------------------------------------------*/
+
+void vIncrementTxLength( unsigned portLONG ulLength )
+{
+	ulNextTxSpace += ulLength;
+}
+/*-----------------------------------------------------------*/
+
+void vSendBufferToMAC( void )
+{
+unsigned long *pulSource;
+unsigned portSHORT * pus;
+unsigned portLONG ulNextWord;
+
+	/* Locate the data to be send. */
+	pus = ( unsigned portSHORT * ) uip_buf;
+
+	/* Add in the size of the data. */
+	pus--;
+	*pus = ulNextTxSpace;
+
+	/* Wait for data to be sent if there is no space immediately. */
+    while( !EthernetSpaceAvail( ETH_BASE ) )
+    {
+		vTaskDelay( macWAIT_SEND_TIME );
+    }
+	
+	pulSource = ( unsigned portLONG * ) pus;	
+	
+	for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) )
+	{
+       	HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;
+		pulSource++;
+	}
+
+	/* Go. */
+    HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;
+}
+/*-----------------------------------------------------------*/
+
+void vEMAC_ISR( void )
+{
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+unsigned portLONG ulTemp;
+
+	/* Clear the interrupt. */
+	ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
+	EthernetIntClear( ETH_BASE, ulTemp );
+		
+	/* Was it an Rx interrupt? */
+	if( ulTemp & ETH_INT_RX )
+	{
+		xSemaphoreGiveFromISR( xMACInterruptSemaphore, &xHigherPriorityTaskWoken );
+		EthernetIntDisable( ETH_BASE, ETH_INT_RX );
+	}
+		
+    /* Switch to the uIP task. */
+	portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
+}
+/*-----------------------------------------------------------*/
+
+void vMACHandleTask( void *pvParameters )
+{
+unsigned long i, ulInt;
+unsigned portLONG ulLength;
+unsigned long *pulBuffer;
+static unsigned portLONG ulNextRxBuffer = 0;
+
+	for( ;; )
+	{
+		/* Wait for something to do. */
+		xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );
+		
+		while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )
+		{		
+			ulLength = HWREG( ETH_BASE + MAC_O_DATA );
+			
+			/* Leave room at the start of the buffer for the size. */
+			pulBuffer = ( unsigned long * ) &( uxRxBuffers.ucRxBuffers[ ulNextRxBuffer ][ 2 ] );			
+			*pulBuffer = ( ulLength >> 16 );
+
+			/* Get the size of the data. */			
+			pulBuffer = ( unsigned long * ) &( uxRxBuffers.ucRxBuffers[ ulNextRxBuffer ][ 4 ] );			
+			ulLength &= 0xFFFF;
+			
+			if( ulLength > 4 )
+			{
+				ulLength -= 4;
+				
+				if( ulLength >= UIP_BUFSIZE )
+				{
+					/* The data won't fit in our buffer.  Ensure we don't
+					try to write into the buffer. */
+					ulLength = 0;
+				}
+
+				/* Read out the data into our buffer. */
+				for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) )
+				{
+					*pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );
+					pulBuffer++;
+				}
+				
+				/* Store the length of the data into the separate array. */
+				ulRxLength[ ulNextRxBuffer ] = ulLength;
+				
+				/* Use the next buffer the next time through. */
+				ulNextRxBuffer++;
+				if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
+				{
+					ulNextRxBuffer = 0;
+				}
+		
+				/* Ensure the uIP task is not blocked as data has arrived. */
+				xSemaphoreGive( xEMACSemaphore );
+			}
+		}
+		
+		EthernetIntEnable( ETH_BASE, ETH_INT_RX );
+		
+		( void ) ulInt;
+	}
+}
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h
new file mode 100644
index 0000000..a49b598
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h
@@ -0,0 +1,322 @@
+/*----------------------------------------------------------------------------
+ *      LPC2378 Ethernet Definitions
+ *----------------------------------------------------------------------------
+ *      Name:    EMAC.H
+ *      Purpose: Philips LPC2378 EMAC hardware definitions
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+#ifndef __EMAC_H
+#define __EMAC_H
+
+/* MAC address definition.  The MAC address must be unique on the network. */
+#define emacETHADDR0 0
+#define emacETHADDR1 0xbd
+#define emacETHADDR2 0x33
+#define emacETHADDR3 0x02
+#define emacETHADDR4 0x64
+#define emacETHADDR5 0x24
+
+
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG         2           /* Num.of TX Fragments 2*1536= 3.0kB */
+#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
+
+#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
+
+/* EMAC variables located in 16K Ethernet SRAM */
+#define RX_DESC_BASE        0x7FE00000
+#define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
+#define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
+#define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
+#define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)
+#define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)
+
+/* RX and TX descriptor and status definitions. */
+#define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
+#define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
+#define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
+#define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
+#define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
+#define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
+#define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
+#define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)
+#define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
+#undef  MAC2_NO_BACKOFF /* Remove compiler warning. */
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF            0x00000012  /* Recommended value                 */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF            0x0000370F  /* Default value                     */
+
+/* PHY Support Register */
+#undef SUPP_SPEED   /* Remove compiler warning. */
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
+#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
+#define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
+
+/* MII Management Command Register */
+#undef MCMD_READ   /* Remove compiler warning. */
+#define MCMD_READ           0x00000001  /* MII Read                          */
+#undef MCMD_SCAN /* Remove compiler warning. */
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
+
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
+
+/* MII Management Indicators Register */
+#undef MIND_BUSY   /* Remove compiler warning. */
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
+
+/* Command Register */
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
+
+/* Status Register */
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
+
+/* Power Down Register */
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
+
+/* RX Status Information Word */
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS         0x10        /* Status Register                   */
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
+
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
+
+#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
+#define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
+
+// prototypes
+portBASE_TYPE  vInitEMAC(void);
+unsigned short ReadFrameBE_EMAC(void);
+void           vIncrementTxLength(unsigned long ulLength);
+void           CopyFromFrame_EMAC(void *Dest, unsigned short Size);
+void           DummyReadFrame_EMAC(unsigned short Size);
+unsigned short StartReadFrame(void);
+void           EndReadFrame(void);
+unsigned int   CheckFrameReceived(void);
+void           vInitialiseSend(void);
+unsigned int   Rdy4Tx(void);
+void           vSendBufferToMAC(void);
+void vEMACWaitForInput( void );
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer );
+
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings
new file mode 100644
index 0000000..0d3c30c
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings
@@ -0,0 +1,35 @@
+http_http "http://"
+http_200 "200 "
+http_301 "301 "
+http_302 "302 "
+http_get "GET "
+http_10 "HTTP/1.0"
+http_11 "HTTP/1.1"
+http_content_type "content-type: "
+http_texthtml "text/html"
+http_location "location: "
+http_host "host: "
+http_crnl "\r\n"
+http_index_html "/index.html"
+http_404_html "/404.html"
+http_referer "Referer:"
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"
+http_content_type_plain "Content-type: text/plain\r\n\r\n"
+http_content_type_html "Content-type: text/html\r\n\r\n"
+http_content_type_css  "Content-type: text/css\r\n\r\n"
+http_content_type_text "Content-type: text/text\r\n\r\n"
+http_content_type_png  "Content-type: image/png\r\n\r\n"
+http_content_type_gif  "Content-type: image/gif\r\n\r\n"
+http_content_type_jpg  "Content-type: image/jpeg\r\n\r\n"
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"
+http_html ".html"
+http_shtml ".shtml"
+http_htm ".htm"
+http_css ".css"
+http_png ".png"
+http_gif ".gif"
+http_jpg ".jpg"
+http_text ".txt"
+http_txt ".txt"
+
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.c
new file mode 100644
index 0000000..ef7a41c
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.c
@@ -0,0 +1,102 @@
+const char http_http[8] = 
+/* "http://" */
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };
+const char http_200[5] = 
+/* "200 " */
+{0x32, 0x30, 0x30, 0x20, };
+const char http_301[5] = 
+/* "301 " */
+{0x33, 0x30, 0x31, 0x20, };
+const char http_302[5] = 
+/* "302 " */
+{0x33, 0x30, 0x32, 0x20, };
+const char http_get[5] = 
+/* "GET " */
+{0x47, 0x45, 0x54, 0x20, };
+const char http_10[9] = 
+/* "HTTP/1.0" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };
+const char http_11[9] = 
+/* "HTTP/1.1" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };
+const char http_content_type[15] = 
+/* "content-type: " */
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };
+const char http_texthtml[10] = 
+/* "text/html" */
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_location[11] = 
+/* "location: " */
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };
+const char http_host[7] = 
+/* "host: " */
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };
+const char http_crnl[3] = 
+/* "\r\n" */
+{0xd, 0xa, };
+const char http_index_html[12] = 
+/* "/index.html" */
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_404_html[10] = 
+/* "/404.html" */
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_referer[9] = 
+/* "Referer:" */
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };
+const char http_header_200[84] = 
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };
+const char http_header_404[91] = 
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };
+const char http_content_type_plain[29] = 
+/* "Content-type: text/plain\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_html[28] = 
+/* "Content-type: text/html\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_css [27] = 
+/* "Content-type: text/css\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_text[28] = 
+/* "Content-type: text/text\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_png [28] = 
+/* "Content-type: image/png\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_gif [28] = 
+/* "Content-type: image/gif\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_jpg [29] = 
+/* "Content-type: image/jpeg\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_binary[43] = 
+/* "Content-type: application/octet-stream\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };
+const char http_html[6] = 
+/* ".html" */
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_shtml[7] = 
+/* ".shtml" */
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_htm[5] = 
+/* ".htm" */
+{0x2e, 0x68, 0x74, 0x6d, };
+const char http_css[5] = 
+/* ".css" */
+{0x2e, 0x63, 0x73, 0x73, };
+const char http_png[5] = 
+/* ".png" */
+{0x2e, 0x70, 0x6e, 0x67, };
+const char http_gif[5] = 
+/* ".gif" */
+{0x2e, 0x67, 0x69, 0x66, };
+const char http_jpg[5] = 
+/* ".jpg" */
+{0x2e, 0x6a, 0x70, 0x67, };
+const char http_text[5] = 
+/* ".txt" */
+{0x2e, 0x74, 0x78, 0x74, };
+const char http_txt[5] = 
+/* ".txt" */
+{0x2e, 0x74, 0x78, 0x74, };
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.h
new file mode 100644
index 0000000..acbe7e1
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.h
@@ -0,0 +1,34 @@
+extern const char http_http[8];
+extern const char http_200[5];
+extern const char http_301[5];
+extern const char http_302[5];
+extern const char http_get[5];
+extern const char http_10[9];
+extern const char http_11[9];
+extern const char http_content_type[15];
+extern const char http_texthtml[10];
+extern const char http_location[11];
+extern const char http_host[7];
+extern const char http_crnl[3];
+extern const char http_index_html[12];
+extern const char http_404_html[10];
+extern const char http_referer[9];
+extern const char http_header_200[84];
+extern const char http_header_404[91];
+extern const char http_content_type_plain[29];
+extern const char http_content_type_html[28];
+extern const char http_content_type_css [27];
+extern const char http_content_type_text[28];
+extern const char http_content_type_png [28];
+extern const char http_content_type_gif [28];
+extern const char http_content_type_jpg [29];
+extern const char http_content_type_binary[43];
+extern const char http_html[6];
+extern const char http_shtml[7];
+extern const char http_htm[5];
+extern const char http_css[5];
+extern const char http_png[5];
+extern const char http_gif[5];
+extern const char http_jpg[5];
+extern const char http_text[5];
+extern const char http_txt[5];
diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c
new file mode 100644
index 0000000..803b771
--- /dev/null
+++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c
@@ -0,0 +1,269 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ *         Web server script interface
+ * \author
+ *         Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2006, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "psock.h"
+#include "httpd.h"
+#include "httpd-cgi.h"
+#include "httpd-fs.h"
+
+#include 
+#include 
+
+HTTPD_CGI_CALL(file, "file-stats", file_stats);
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);
+HTTPD_CGI_CALL(net, "net-stats", net_stats);
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );
+HTTPD_CGI_CALL(io, "led-io", led_io );
+
+
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL };
+
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))
+{
+  PSOCK_BEGIN(&s->sout);
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+httpd_cgifunction
+httpd_cgi(char *name)
+{
+  const struct httpd_cgi_call **f;
+
+  /* Find the matching name in the table, return the function. */
+  for(f = calls; *f != NULL; ++f) {
+    if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {
+      return (*f)->function;
+    }
+  }
+  return nullfunction;
+}
+/*---------------------------------------------------------------------------*/
+static unsigned short
+generate_file_stats(void *arg)
+{
+  char *f = (char *)arg;
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))
+{
+  PSOCK_BEGIN(&s->sout);
+
+  PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);
+
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+static const char closed[] =   /*  "CLOSED",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,
+ 0x44,  0};
+static const char syn_sent[] = /*  "SYN-SENT",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,
+ 0x54,  0};
+static const char established[] = /*  "ESTABLISHED",*/
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,
+ 0x45, 0x44, 0};
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x31, 0};
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x32, 0};
+static const char closing[] = /*  "CLOSING",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x49,
+ 0x4e, 0x47, 0};
+static const char time_wait[] = /*  "TIME-WAIT,"*/
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,
+ 0x49, 0x54, 0};
+static const char last_ack[] = /*  "LAST-ACK"*/
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,
+ 0x4b, 0};
+
+static const char *states[] = {
+  closed,
+  syn_rcvd,
+  syn_sent,
+  established,
+  fin_wait_1,
+  fin_wait_2,
+  closing,
+  time_wait,
+  last_ack};
+
+
+static unsigned short
+generate_tcp_stats(void *arg)
+{
+  struct uip_conn *conn;
+  struct httpd_state *s = (struct httpd_state *)arg;
+
+  conn = &uip_conns[s->count];
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,
+		 "
\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus; +extern unsigned long uxParTestGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + if( uxParTestGetLED( 0 ) ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, + "LED"\ + "

"\ + "", + pcStatus ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h new file mode 100644 index 0000000..7ae9283 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c new file mode 100644 index 0000000..dc4aef0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h new file mode 100644 index 0000000..b594eea --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/404.html b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/404.html new file mode 100644 index 0000000..43e7f4c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.html b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.html new file mode 100644 index 0000000..1d3bbee --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.shtml new file mode 100644 index 0000000..1923ea7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/io.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/io.shtml new file mode 100644 index 0000000..07554bb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". + + +

+
+%! led-io +

+ + +

+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/stats.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/stats.shtml new file mode 100644 index 0000000..d762f40 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/tcp.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/tcp.shtml new file mode 100644 index 0000000..654d61f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.c new file mode 100644 index 0000000..a7fcfab --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.c @@ -0,0 +1,470 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 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0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, + 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, + 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, + 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, + 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, + 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, + 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, + 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, + 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, + 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, + 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, + 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, + 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, + 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, + 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, + 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, + 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, + 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, + 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, + 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, + 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, + 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, + 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, + 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, + 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, + 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, + 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, + 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, + 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, + 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, + 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, + 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, + 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, + 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, + 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, 0x3c, + 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, + 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, + 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, 0x3c, + 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, + 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, + 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, + 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, + 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, + 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, + 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, + 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, + 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, + 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, + 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, + 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, + 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, + 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 6 diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.h new file mode 100644 index 0000000..52d35c2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c new file mode 100644 index 0000000..644cf16 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h new file mode 100644 index 0000000..7f7a666 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata new file mode 100644 index 0000000..8d2715a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings new file mode 100644 index 0000000..8a13c6d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c new file mode 100644 index 0000000..6859049 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c @@ -0,0 +1,349 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "hw_types.h" +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "hw_memmap.h" +#include "lmi_flash.h" +#include "sysctl.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" +#include "lcd_message.h" + +struct timer { + clock_time_t start; + clock_time_t interval; +}; + + +/*-----------------------------------------------------------*/ + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 19 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +/* Define clock functions here to avoid header file name clash between uIP +and the Luminary Micro driver library. */ +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +extern void timer_set(struct timer *t, clock_time_t interval); +extern int timer_expired(struct timer *t); +extern void timer_reset(struct timer *t); + + + + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR )( void ); + + /* Enable/Reset the Ethernet Controller */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); + SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + while( vInitEMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + prvSetMACAddress(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + vInitialiseSend(); + vIncrementTxLength( uip_len ); + vSendBufferToMAC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +unsigned portLONG ulUser0, ulUser1; +unsigned char pucMACArray[8]; +struct uip_eth_addr xAddr; + + /* Get the device MAC address from flash */ + FlashUserGet(&ulUser0, &ulUser1); + + /* Convert the MAC address from flash into sequence of bytes. */ + pucMACArray[0] = ((ulUser0 >> 0) & 0xff); + pucMACArray[1] = ((ulUser0 >> 8) & 0xff); + pucMACArray[2] = ((ulUser0 >> 16) & 0xff); + pucMACArray[3] = ((ulUser1 >> 0) & 0xff); + pucMACArray[4] = ((ulUser1 >> 8) & 0xff); + pucMACArray[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the MAC address. */ + EthernetMACAddrSet(ETH_BASE, pucMACArray); + + xAddr.addr[ 0 ] = pucMACArray[0]; + xAddr.addr[ 1 ] = pucMACArray[1]; + xAddr.addr[ 2 ] = pucMACArray[2]; + xAddr.addr[ 3 ] = pucMACArray[3]; + xAddr.addr[ 4 ] = pucMACArray[4]; + xAddr.addr[ 5 ] = pucMACArray[5]; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static portCHAR cMessageForDisplay[ 32 ]; +extern xQueueHandle xOLEDQueue; +xOLEDMessage xOLEDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 0, 1 ); + } + else + { + vParTestSetLED( 0, 0 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xOLEDMessage.pcMessage = ( signed portCHAR * ) cMessageForDisplay; + xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h new file mode 100644 index 0000000..455540d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#define UIP_CONF_EXTERNAL_BUFFER + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h new file mode 100644 index 0000000..1acb290 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/FreeRTOSConfig.h new file mode 100644 index 0000000..c65a929 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/FreeRTOSConfig.h @@ -0,0 +1,150 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 50000000UL ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 10 +#define configGENERATE_RUN_TIME_STATS 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 1 + +#define configMAX_PRIORITIES ( 5UL ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer related constants. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +#define configKERNEL_INTERRUPT_PRIORITY ( ( unsigned char ) 7 << ( unsigned char ) 5 ) /* Priority 7, or 255 as only the top three bits are implemented. This is the lowest priority. */ +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( ( unsigned char ) 5 << ( unsigned char ) 5 ) /* Priority 5, or 160 as only the top three bits are implemented. */ + +extern volatile unsigned long ulHighFrequencyTimerTicks; +/* There is already a high frequency timer running - just reset its count back +to zero. */ +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() ( ulHighFrequencyTimerTicks = 0UL ) +#define portGET_RUN_TIME_COUNTER_VALUE() ulHighFrequencyTimerTicks + +/* Use Cortex-M3 optimised task selection rather than the generic C code +version. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + +/* Disable interrupts and sit in a null loop if assert is called. */ +#define configASSERT( x ) if( ( ( x ) == 0 ) ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.c new file mode 100644 index 0000000..5d360cb --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.c @@ -0,0 +1,133 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +#define tmrTIMER_2_FREQUENCY ( 2000UL ) +#define tmrTIMER_3_FREQUENCY ( 2001UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ +unsigned long ulFrequency; + + /* Timer 2 and 3 are utilised for this test. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER2 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER3 ); + TimerConfigure( TIMER2_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER3_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + IntPrioritySet( INT_TIMER2A, configMAX_SYSCALL_INTERRUPT_PRIORITY + ( 1 << 5 ) ); /* Shift left 5 as only the top 3 bits are implemented. */ + IntPrioritySet( INT_TIMER3A, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + + /* The rate at which the timers will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY; + TimerLoadSet( TIMER2_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER2A ); + TimerIntEnable( TIMER2_BASE, TIMER_TIMA_TIMEOUT ); + + /* The rate at which the timers will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_3_FREQUENCY; + TimerLoadSet( TIMER3_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER3A ); + TimerIntEnable( TIMER3_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER2_BASE, TIMER_A ); + TimerEnable( TIMER3_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void vT2InterruptHandler( void ) +{ + TimerIntClear( TIMER2_BASE, TIMER_TIMA_TIMEOUT ); + portEND_SWITCHING_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +void vT3InterruptHandler( void ) +{ + TimerIntClear( TIMER3_BASE, TIMER_TIMA_TIMEOUT ); + portEND_SWITCHING_ISR( xSecondTimerHandler() ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.h new file mode 100644 index 0000000..83edd5d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/IntQueueTimer.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Startup.s b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Startup.s new file mode 100644 index 0000000..53ce62b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Startup.s @@ -0,0 +1,199 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions + * ------------------------ + * + * STARTUP_FROM_RESET + * + * If defined, the program will startup from power-on/reset. If not defined + * the program will just loop endlessly from power-on/reset. + * + * This definition is not defined by default on this target because the + * debugger is unable to reset this target and maintain control of it over the + * JTAG interface. The advantage of doing this is that it allows the debugger + * to reset the CPU and run programs from a known reset CPU state on each run. + * It also acts as a safety net if you accidently download a program in FLASH + * that crashes and prevents the debugger from taking control over JTAG + * rendering the target unusable over JTAG. The obvious disadvantage of doing + * this is that your application will not startup without the debugger. + * + * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst + * you are developing and only define STARTUP_FROM_RESET when development is + * complete. + * + *****************************************************************************/ + +.extern xPortPendSVHandler +.extern xPortSysTickHandler +.extern vPortSVCHandler +.extern Timer0IntHandler +.extern vT2InterruptHandler +.extern vT3InterruptHandler +.extern vEMAC_ISR + + +.global reset_handler + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word reset_handler +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word Nmi_ISR + .word Fault_ISR + .word MPU_Fault_ISR + .word 0 /* Populate if using Bus fault */ + .word 0 /* Populate if using Usage fault */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word vPortSVCHandler + .word 0 /* Populate if using a debug monitor */ + .word 0 /* Reserved */ + .word xPortPendSVHandler + .word xPortSysTickHandler + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word UART0_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_Timer_ISR + .word Timer0IntHandler + .word Timer0B_ISR + .word Timer1A_ISR + .word Timer1B_ISR + .word vT2InterruptHandler + .word Timer2B_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + .word GPIO_Port_F_ISR + .word GPIO_Port_G_ISR + .word GPIO_Port_H_ISR + .word UART2_ISR + .word SSI1_ISR + .word vT3InterruptHandler + .word Timer3B_ISR + .word I2C1_ISR + .word QEI1_ISR + .word CAN0_ISR + .word CAN1_ISR + .word CAN2_ISR + .word vEMAC_ISR + .word HIBERNATE_ISR + .word USB0_ISR + .word PWM_Generator_3_ISR + .word uDMA_Software_Transfer_ISR + .word uDMA_Error_ISR +_vectors_end: + + .section .init, "ax" + .thumb_func + +reset_handler: +#ifdef __RAM_BUILD + /* If this is a RAM build, configure vector table offset register to point + to the RAM vector table. */ + ldr r0, =0xE000ED08 + ldr r1, =_vectors + str r1, [r0] +#endif + b _start + +DEFAULT_ISR_HANDLER Nmi_ISR +DEFAULT_ISR_HANDLER Fault_ISR +DEFAULT_ISR_HANDLER MPU_Fault_ISR +DEFAULT_ISR_HANDLER SVCall_ISR +DEFAULT_ISR_HANDLER SysTick_ISR +DEFAULT_ISR_HANDLER PendSV_ISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_Timer_ISR +DEFAULT_ISR_HANDLER Timer0A_ISR +DEFAULT_ISR_HANDLER Timer0B_ISR +DEFAULT_ISR_HANDLER Timer1A_ISR +DEFAULT_ISR_HANDLER Timer1B_ISR +DEFAULT_ISR_HANDLER Timer2A_ISR +DEFAULT_ISR_HANDLER Timer2B_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR +DEFAULT_ISR_HANDLER GPIO_Port_F_ISR +DEFAULT_ISR_HANDLER GPIO_Port_G_ISR +DEFAULT_ISR_HANDLER GPIO_Port_H_ISR +DEFAULT_ISR_HANDLER UART2_ISR +DEFAULT_ISR_HANDLER SSI1_ISR +DEFAULT_ISR_HANDLER Timer3A_ISR +DEFAULT_ISR_HANDLER Timer3B_ISR +DEFAULT_ISR_HANDLER I2C1_ISR +DEFAULT_ISR_HANDLER QEI1_ISR +DEFAULT_ISR_HANDLER CAN0_ISR +DEFAULT_ISR_HANDLER CAN1_ISR +DEFAULT_ISR_HANDLER CAN2_ISR +DEFAULT_ISR_HANDLER ETHERNET_ISR +DEFAULT_ISR_HANDLER HIBERNATE_ISR +DEFAULT_ISR_HANDLER USB0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_3_ISR +DEFAULT_ISR_HANDLER uDMA_Software_Transfer_ISR +DEFAULT_ISR_HANDLER uDMA_Error_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Target.js b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Target.js new file mode 100644 index 0000000..55a9c2c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/LM3S_Target.js @@ -0,0 +1,28 @@ +/****************************************************************************** + Target Script for LM3S. + + Copyright (c) 2006 Rowley Associates Limited. + + This file may be distributed under the terms of the License Agreement + provided with this software. + + THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE + WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + ******************************************************************************/ + +function Reset() +{ + TargetInterface.resetAndStop(1000); +} + +function RAMReset() +{ + Reset(); +} + +function FLASHReset() +{ + Reset(); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/ParTest/ParTest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/ParTest/ParTest.c new file mode 100644 index 0000000..f7b26ef --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/ParTest/ParTest.c @@ -0,0 +1,113 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Library includes. */ +#include "hw_types.h" +#include "gpio.h" +#include "hw_memmap.h" + + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); + GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzp b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzp new file mode 100644 index 0000000..a8fc86c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzp @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzs b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzs new file mode 100644 index 0000000..4d744e7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/RTOSDemo.hzs @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/bitmap.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/bitmap.h new file mode 100644 index 0000000..29f813f --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/bitmap.h @@ -0,0 +1,336 @@ +#ifndef BITMAP_H +#define BITMAP_H + +#define bmpBITMAP_HEIGHT 50 +#define bmpBITMAP_WIDTH 128 + +const unsigned char pucBasicBitmap[] = +{ +0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/formike128x128x16.c new file mode 100644 index 0000000..87ff5fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/formike128x128x16.c @@ -0,0 +1,902 @@ +//***************************************************************************** +// +// formike128x128x16.c - Display driver for the Formike Electronic +// KWH015C04-F01 CSTN panel with an ST7637 controller. +// +// Copyright (c) 2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3s3748_api +//! @{ +// +//***************************************************************************** + +#include "hw_gpio.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "sysctl.h" +#include "rom.h" +#include "grlib.h" +#include "formike128x128x16.h" +#include + +//***************************************************************************** +// +// Defines for the pins that are used to communicate with the ST7637. +// +//***************************************************************************** +#define LCD_A0_BASE GPIO_PORTB_BASE +#define LCD_A0_PIN GPIO_PIN_2 +#define LCD_WR_BASE GPIO_PORTC_BASE +#define LCD_WR_PIN GPIO_PIN_4 +#define LCD_RD_BASE GPIO_PORTC_BASE +#define LCD_RD_PIN GPIO_PIN_5 +#define LCD_BL_BASE GPIO_PORTF_BASE +#define LCD_BL_PIN GPIO_PIN_1 +#define LCD_DATA_BASE GPIO_PORTG_BASE + +//***************************************************************************** +// +// Translates a 24-bit RGB color to a display driver-specific color. +// +// \param c is the 24-bit RGB color. The least-significant byte is the blue +// channel, the next byte is the green channel, and the third byte is the red +// channel. +// +// This macro translates a 24-bit RGB color into a value that can be written +// into the display's frame buffer in order to reproduce that color, or the +// closest possible approximation of that color. +// +// \return Returns the display-driver specific color. +// +//***************************************************************************** +#define DPYCOLORTRANSLATE(c) ((((c) & 0x00ff0000) >> 19) | \ + ((((c) & 0x0000ff00) >> 5) & 0x000007e0) | \ + ((((c) & 0x000000ff) << 8) & 0x0000f800)) + +//***************************************************************************** +// +// Writes a data word to the ST7637. +// +//***************************************************************************** +static void +WriteData(unsigned char ucData) +{ + // + // Write the data to the data bus. + // + HWREG(LCD_DATA_BASE + GPIO_O_DATA + (0xff << 2)) = ucData; + + // + // Assert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = 0; + + // + // Deassert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = LCD_WR_PIN; +} + +//***************************************************************************** +// +// Writes a command to the ST7637. +// +//***************************************************************************** +static void +WriteCommand(unsigned char ucData) +{ + // + // Write the command to the data bus. + // + HWREG(LCD_DATA_BASE + GPIO_O_DATA + (0xff << 2)) = ucData; + + // + // Set the A0 signal low, indicating a command. + // + HWREG(LCD_A0_BASE + GPIO_O_DATA + (LCD_A0_PIN << 2)) = 0; + + // + // Assert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = 0; + + // + // Deassert the write enable signal. + // + HWREG(LCD_WR_BASE + GPIO_O_DATA + (LCD_WR_PIN << 2)) = LCD_WR_PIN; + + // + // Set the A0 signal high, indicating that following writes are data. + // + HWREG(LCD_A0_BASE + GPIO_O_DATA + (LCD_A0_PIN << 2)) = LCD_A0_PIN; +} + +//***************************************************************************** +// +//! Initializes the display driver. +//! +//! This function initializes the ST7637 display controller on the panel, +//! preparing it to display data. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16Init(void) +{ + unsigned long ulClockMS, ulCount; + + // + // Get the value to pass to SysCtlDelay() in order to delay for 1 ms. + // + ulClockMS = SysCtlClockGet() / (3 * 1000); + + // + // Enable the GPIO peripherals used to interface to the ST7637. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); + + // + // Configure the pins that connect to the LCD as GPIO outputs. + // + GPIOPinTypeGPIOOutput(LCD_A0_BASE, LCD_A0_PIN); + GPIOPinTypeGPIOOutput(LCD_WR_BASE, LCD_WR_PIN); + GPIOPinTypeGPIOOutput(LCD_RD_BASE, LCD_RD_PIN); + GPIOPinTypeGPIOOutput(LCD_BL_BASE, LCD_BL_PIN); + GPIOPinTypeGPIOOutput(LCD_DATA_BASE, 0xff); + + // + // Set the LCD control pins to their default values. + // + GPIOPinWrite(LCD_A0_BASE, LCD_A0_PIN, LCD_A0_PIN); + GPIOPinWrite(LCD_WR_BASE, LCD_WR_PIN | LCD_RD_PIN, + LCD_WR_PIN | LCD_RD_PIN); + GPIOPinWrite(LCD_BL_BASE, LCD_BL_PIN, 0); + GPIOPinWrite(LCD_DATA_BASE, 0xff, 0x00); + + // + // Perform a software reset of the ST7637. + // + WriteCommand(0x01); + + // + // Delay for 120ms. + // + SysCtlDelay(ulClockMS * 120); + + // + // Disable auto-load of mask rom data. + // + WriteCommand(0xD7); + WriteData(0xBF); + + // + // Set the OTP control mode to read. + // + WriteCommand(0xE0); + WriteData(0x00); + + // + // Delay for 10ms. + // + SysCtlDelay(ulClockMS * 10); + + // + // Start the OTP read. + // + WriteCommand(0xE3); + + // + // Delay for 20ms. + // + SysCtlDelay(ulClockMS * 20); + + // + // Cancel the OTP read (it should have finished by now). + // + WriteCommand(0xE1); + + // + // Turn off the display. + // + WriteCommand(0x28); + + // + // Exit sleep mode. + // + WriteCommand(0x11); + + // + // Delay for 50ms. + // + SysCtlDelay(ulClockMS * 50); + + // + // Program the LCD supply voltage V0 to 14V. + // + WriteCommand(0xC0); + WriteData(0x04); + WriteData(0x01); + + // + // Select an LCD bias voltage ratio of 1/12. + // + WriteCommand(0xC3); + WriteData(0x00); + + // + // Enable the x8 booster circuit. + // + WriteCommand(0xC4); + WriteData(0x07); + + // + // Invert the column scan direction for the panel. + // + WriteCommand(0xB7); + WriteData(0xC0); + + // + // Select 16bpp, 5-6-5 data input mode. + // + WriteCommand(0x3A); + WriteData(0x05); + + // + // Select the memory scanning direction. The scanning mode does not matter + // for this driver since the row/column selects will constrain the writes + // to the desired area of the display. + // + WriteCommand(0x36); + WriteData(0x00); + + // + // Turn on the display. + // + WriteCommand(0x29); + + // + // Clear the contents of the display buffer. + // + WriteCommand(0x2A); + WriteData(0x00); + WriteData(0x7F); + WriteCommand(0x2B); + WriteData(0x01); + WriteData(0x80); + WriteCommand(0x2c); + for(ulCount = 0; ulCount < (128 * 128); ulCount++) + { + WriteData(0x00); + WriteData(0x00); + } + + // + // Enable normal operation of the LCD. + // + WriteCommand(0x13); +} + +//***************************************************************************** +// +//! Turns on the backlight. +//! +//! This function turns on the backlight on the display. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16BacklightOn(void) +{ + // + // Assert the signal that turns on the backlight. + // + HWREG(LCD_BL_BASE + GPIO_O_DATA + (LCD_BL_PIN << 2)) = LCD_BL_PIN; +} + +//***************************************************************************** +// +//! Turns off the backlight. +//! +//! This function turns off the backlight on the display. +//! +//! \return None. +// +//***************************************************************************** +void +Formike128x128x16BacklightOff(void) +{ + // + // Deassert the signal that turns on the backlight. + // + HWREG(LCD_BL_BASE + GPIO_O_DATA + (LCD_BL_PIN << 2)) = 0; +} + +//***************************************************************************** +// +//! Draws a pixel on the screen. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the pixel. +//! \param lY is the Y coordinate of the pixel. +//! \param ulValue is the color of the pixel. +//! +//! This function sets the given pixel to a particular color. The coordinates +//! of the pixel are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16PixelDraw(void *pvDisplayData, long lX, long lY, + unsigned long ulValue) +{ + // + // Set the X address of the display cursor. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the pixel value. + // + WriteCommand(0x2c); + WriteData(ulValue >> 8); + WriteData(ulValue); +} + +//***************************************************************************** +// +//! Draws a horizontal sequence of pixels on the screen. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the first pixel. +//! \param lY is the Y coordinate of the first pixel. +//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1 +//! or 4 bit per pixel formats. +//! \param lCount is the number of pixels to draw. +//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8. +//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel +//! formats, the most significant bit(s) represent the left-most pixel. +//! \param pucPalette is a pointer to the palette used to draw the pixels. +//! +//! This function draws a horizontal sequence of pixels on the screen, using +//! the supplied palette. For 1 bit per pixel format, the palette contains +//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette +//! contains 24-bit RGB values that must be translated before being written to +//! the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16PixelDrawMultiple(void *pvDisplayData, long lX, long lY, + long lX0, long lCount, long lBPP, + const unsigned char *pucData, + const unsigned char *pucPalette) +{ + unsigned long ulByte; + + // + // Set the extent of the line along the X axis. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX + lCount - 1); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Determine how to interpret the pixel data based on the number of bits + // per pixel. + // + switch(lBPP) + { + // + // The pixel data is in 1 bit per pixel format. + // + case 1: + { + // + // Loop while there are more pixels to draw. + // + while(lCount) + { + // + // Get the next byte of image data. + // + ulByte = *pucData++; + + // + // Loop through the pixels in this byte of image data. + // + for(; (lX0 < 8) && lCount; lX0++, lCount--) + { + // + // Draw this pixel in the appropriate color. + // + lBPP = ((unsigned long *)pucPalette)[(ulByte >> + (7 - lX0)) & 1]; + WriteData(lBPP >> 8); + WriteData(lBPP); + } + + // + // Start at the beginning of the next byte of image data. + // + lX0 = 0; + } + + // + // The image data has been drawn. + // + break; + } + + // + // The pixel data is in 4 bit per pixel format. + // + case 4: + { + // + // Loop while there are more pixels to draw. "Duff's device" is + // used to jump into the middle of the loop if the first nibble of + // the pixel data should not be used. Duff's device makes use of + // the fact that a case statement is legal anywhere within a + // sub-block of a switch statement. See + // http://en.wikipedia.org/wiki/Duff's_device for detailed + // information about Duff's device. + // + switch(lX0 & 1) + { + case 0: + while(lCount) + { + // + // Get the upper nibble of the next byte of pixel data + // and extract the corresponding entry from the + // palette. + // + ulByte = (*pucData >> 4) * 3; + ulByte = (*(unsigned long *)(pucPalette + ulByte) & + 0x00ffffff); + + // + // Translate this palette entry and write it to the + // screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + + // + // Decrement the count of pixels to draw. + // + lCount--; + + // + // See if there is another pixel to draw. + // + if(lCount) + { + case 1: + // + // Get the lower nibble of the next byte of pixel + // data and extract the corresponding entry from + // the palette. + // + ulByte = (*pucData++ & 15) * 3; + ulByte = (*(unsigned long *)(pucPalette + ulByte) & + 0x00ffffff); + + // + // Translate this palette entry and write it to the + // screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + + // + // Decrement the count of pixels to draw. + // + lCount--; + } + } + } + + // + // The image data has been drawn. + // + break; + } + + // + // The pixel data is in 8 bit per pixel format. + // + case 8: + { + // + // Loop while there are more pixels to draw. + // + while(lCount--) + { + // + // Get the next byte of pixel data and extract the + // corresponding entry from the palette. + // + ulByte = *pucData++ * 3; + ulByte = *(unsigned long *)(pucPalette + ulByte) & 0x00ffffff; + + // + // Translate this palette entry and write it to the screen. + // + ulByte = DPYCOLORTRANSLATE(ulByte); + WriteData(ulByte >> 8); + WriteData(ulByte); + } + + // + // The image data has been drawn. + // + break; + } + } +} + +//***************************************************************************** +// +//! Flushes any cached drawing operations. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! +//! This functions flushes any cached drawing operations to the display. This +//! is useful when a local frame buffer is used for drawing operations, and the +//! flush would copy the local frame buffer to the display. For the ST7637 +//! driver, the flush is a no operation. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16Flush(void *pvDisplayData) +{ + // + // There is nothing to be done. + // +} + +//***************************************************************************** +// +//! Draws a horizontal line. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX1 is the X coordinate of the start of the line. +//! \param lX2 is the X coordinate of the end of the line. +//! \param lY is the Y coordinate of the line. +//! \param ulValue is the color of the line. +//! +//! This function draws a horizontal line on the display. The coordinates of +//! the line are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16LineDrawH(void *pvDisplayData, long lX1, long lX2, long lY, + unsigned long ulValue) +{ + // + // Set the extent of the line along the X axis. + // + WriteCommand(0x2a); + WriteData(lX1); + WriteData(lX2); + + // + // Set the Y address of the display cursor. + // + WriteCommand(0x2b); + WriteData(lY + 1); + WriteData(lY + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels of this horizontal line. + // + while(lX1++ <= lX2) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Draws a vertical line. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param lX is the X coordinate of the line. +//! \param lY1 is the Y coordinate of the start of the line. +//! \param lY2 is the Y coordinate of the end of the line. +//! \param ulValue is the color of the line. +//! +//! This function draws a vertical line on the display. The coordinates of the +//! line are assumed to be within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16LineDrawV(void *pvDisplayData, long lX, long lY1, long lY2, + unsigned long ulValue) +{ + // + // Set the X address of the display cursor. + // + WriteCommand(0x2a); + WriteData(lX); + WriteData(lX); + + // + // Set the extent of the line along the Y axis. + // + WriteCommand(0x2b); + WriteData(lY1 + 1); + WriteData(lY2 + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels of this vertical line. + // + while(lY1++ <= lY2) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Fills a rectangle. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param pRect is a pointer to the structure describing the rectangle. +//! \param ulValue is the color of the rectangle. +//! +//! This function fills a rectangle on the display. The coordinates of the +//! rectangle are assumed to be within the extents of the display, and the +//! rectangle specification is fully inclusive (i.e. both sXMin and sXMax are +//! drawn, along with sYMin and sYMax). +//! +//! \return None. +// +//***************************************************************************** +static void +Formike128x128x16RectFill(void *pvDisplayData, const tRectangle *pRect, + unsigned long ulValue) +{ + long lCount; + + // + // Set the extent of the rectangle along the X axis. + // + WriteCommand(0x2a); + WriteData(pRect->sXMin); + WriteData(pRect->sXMax); + + // + // Set the extent of the rectangle along the Y axis. + // + WriteCommand(0x2b); + WriteData(pRect->sYMin + 1); + WriteData(pRect->sYMax + 1); + + // + // Write the data RAM write command. + // + WriteCommand(0x2c); + + // + // Loop through the pixels in this rectangle. + // + for(lCount = ((pRect->sXMax - pRect->sXMin + 1) * + (pRect->sYMax - pRect->sYMin + 1)); lCount > 0; lCount--) + { + // + // Write the pixel value. + // + WriteData(ulValue >> 8); + WriteData(ulValue); + } +} + +//***************************************************************************** +// +//! Translates a 24-bit RGB color to a display driver-specific color. +//! +//! \param pvDisplayData is a pointer to the driver-specific data for this +//! display driver. +//! \param ulValue is the 24-bit RGB color. The least-significant byte is the +//! blue channel, the next byte is the green channel, and the third byte is the +//! red channel. +//! +//! This function translates a 24-bit RGB color into a value that can be +//! written into the display's frame buffer in order to reproduce that color, +//! or the closest possible approximation of that color. +//! +//! \return Returns the display-driver specific color. +// +//***************************************************************************** +static unsigned long +Formike128x128x16ColorTranslate(void *pvDisplayData, unsigned long ulValue) +{ + // + // Translate from a 24-bit RGB color to a 5-6-5 RGB color. + // + return(DPYCOLORTRANSLATE(ulValue)); +} + +//***************************************************************************** +// +//! The display structure that describes the driver for the Formike Electronic +//! KWH015C04-F01 CSTN panel with an ST7637 controller. +// +//***************************************************************************** +const tDisplay g_sFormike128x128x16 = +{ + sizeof(tDisplay), + 0, + 128, + 128, + Formike128x128x16PixelDraw, + Formike128x128x16PixelDrawMultiple, + Formike128x128x16LineDrawH, + Formike128x128x16LineDrawV, + Formike128x128x16RectFill, + Formike128x128x16ColorTranslate, + Formike128x128x16Flush +}; + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + + + + + + + + + + + + + + + +/* FreeRTOS.org demo wrappers. These are required so the prototypes for the +functions are the same as for the display drivers used by other evaluation +kits. */ + +static tContext sContext; + +void vFormike128x128x16Clear( void ) +{ +const tRectangle xRectangle = { 0, 0, 127, 127 }; + + GrContextForegroundSet( &sContext, ClrBlack ); + GrRectFill( &sContext, &xRectangle ); + GrContextForegroundSet(&sContext, ClrWhite); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16StringDraw( const char *pcString, unsigned long lX, unsigned long lY, unsigned char ucColor ) +{ + GrContextForegroundSet(&sContext, ClrWhite); + GrStringDraw( &sContext, pcString, strlen( pcString ), lX, lY, false ); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16Init( unsigned long ul ) +{ +tRectangle rectScreen; +const unsigned char *pcAppName = "www.FreeRTOS.org"; + + ( void ) ul; + + Formike128x128x16Init(); + Formike128x128x16BacklightOn(); + GrContextInit(&sContext, &g_sFormike128x128x16); + GrContextFontSet(&sContext, &g_sFontCmss12); + rectScreen.sXMin = 0; + + /* Fill the screen with a black rectangle. */ + rectScreen.sYMin = 0; + rectScreen.sXMax = g_sFormike128x128x16.usWidth - 1; + rectScreen.sYMax = g_sFormike128x128x16.usHeight - 1; + GrContextForegroundSet(&sContext, ClrBlack); + GrRectFill(&sContext, &rectScreen); +} +/*-----------------------------------------------------------*/ + +void vFormike128x128x16ImageDraw( const unsigned char *pucImage, unsigned long ulX, unsigned long ulY, unsigned long ulWidth, unsigned long ulHeight ) +{ + GrImageDraw( &sContext, pucImage, ( long ) ulX, ( long ) ulY); +} + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/formike128x128x16.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/formike128x128x16.h new file mode 100644 index 0000000..feaec75 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/formike128x128x16.h @@ -0,0 +1,51 @@ +//***************************************************************************** +// +// formike128x128x16.h - Prototypes for the Formike Electronic KWH015C04-F01 +// display driver. +// +// Copyright (c) 2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FORMIKE128X128X16_H__ +#define __FORMIKE128X128X16_H__ + +//***************************************************************************** +// +// Prototypes for the globals exported by this driver. +// +//***************************************************************************** +extern void Formike128x128x16Init(void); +extern void Formike128x128x16BacklightOn(void); +extern void Formike128x128x16BacklightOff(void); +extern const tDisplay g_sFormike128x128x16; + +/* FreeRTOS.org demo wrappers. These are required so the prototypes for the +functions are the same as for the display drivers used by other evaluation +kits. */ +void vFormike128x128x16Clear( void ); +void vFormike128x128x16StringDraw( const char *pcString, unsigned long lX, unsigned long lY, unsigned char ucColor ); +void vFormike128x128x16Init( unsigned long ul ); +void vFormike128x128x16ImageDraw( const unsigned char *pucImage, unsigned long ulX, unsigned long ulY, unsigned long ulWidth, unsigned long ulHeight ); + +#endif // __FORMIKE128X128X16_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/lcd_message.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/lcd_message.h new file mode 100644 index 0000000..ced7a1d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/lcd_message.h @@ -0,0 +1,9 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +typedef struct +{ + char *pcMessage; +} xOLEDMessage; + +#endif /* LCD_MESSAGE_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/main.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/main.c new file mode 100644 index 0000000..09c9414 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/main.c @@ -0,0 +1,483 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the OLED display by the 'OLED' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the OLED send the message on a queue to the OLED task instead of + * accessing the OLED themselves. The OLED task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" hook - This only executes every five seconds from the tick hook. + * Its main function is to check that all the standard demo tasks are still + * operational. Should any unexpected behaviour within a demo task be discovered + * the tick hook will write an error to the OLED (via the OLED task). If all the + * demo tasks are executing with their expected behaviour then the check task + * writes PASS to the OLED (again via the OLED task), as described above. + * + * "uIP" task - This is the task that handles the uIP stack. All TCP/IP + * processing is performed in this task. + */ + + + + +/************************************************************************* + * Please ensure to read http://www.freertos.org/portLM3Sxxxx_Eclipse.html + * which provides information on configuring and running this demo for the + * various Luminary Micro EKs. + *************************************************************************/ + + + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Hardware library includes. */ +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_sysctl.h" +#include "sysctl.h" +#include "gpio.h" +#include "grlib.h" +#include "rit128x96x4.h" +#include "osram128x64x4.h" +#include "formike128x128x16.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "PollQ.h" +#include "lcd_message.h" +#include "bitmap.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "IntQueue.h" +#include "QueueSet.h" + +/*-----------------------------------------------------------*/ + +/* The time between cycles of the 'check' functionality (defined within the +tick hook. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* Size of the stack allocated to the uIP task. */ +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The OLED task uses the sprintf function so requires a little more stack too. */ +#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainOLED_QUEUE_SIZE ( 3 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The period of the system clock in nano seconds. This is used to calculate +the jitter time in nano seconds. */ +#define mainNS_PER_CLOCK ( ( unsigned long ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Constants used when writing strings to the display. */ +#define mainCHARACTER_HEIGHT ( 9 ) +#define mainMAX_ROWS_128 ( mainCHARACTER_HEIGHT * 14 ) +#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) +#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) +#define mainFULL_SCALE ( 15 ) +#define ulSSI_FREQUENCY ( 3500000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The display is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the display directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vOLEDTask( void *pvParameters ); + +/* + * Configure the hardware for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Configures the high frequency timers - those used to measure the timing + * jitter while the real time kernel is executing. + */ +extern void vSetupHighFrequencyTimer( void ); + +/* + * The idle hook is used to run a test of the scheduler context switch + * mechanism. + */ +void vApplicationIdleHook( void ) __attribute__((naked)); +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the OLED task. */ +xQueueHandle xOLEDQueue; + +/* The welcome text. */ +const char * const pcWelcomeMessage = " www.FreeRTOS.org"; + +/* Variables used to detect the test in the idle hook failing. */ +unsigned long ulIdleError = pdFALSE; + +/*-----------------------------------------------------------*/ + +/************************************************************************* + * Please ensure to read http://www.freertos.org/portLM3Sxxxx_Eclipse.html + * which provides information on configuring and running this demo for the + * various Luminary Micro EKs. + *************************************************************************/ +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by the OLED task. Messages for display on the OLED + are received via this queue. */ + xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); + + /* Create the uIP task if running on a processor that includes a MAC and + PHY. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + } + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartInterruptQueueTasks(); + vStartQueueSetTasks(); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vOLEDTask, ( signed char * ) "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Configure the high frequency interrupt used to measure the interrupt + jitter time. */ + vSetupHighFrequencyTimer(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +void prvSetupHardware( void ) +{ + /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is + a workaround to allow the PLL to operate reliably. */ + if( DEVICE_IS_REVA2 ) + { + SysCtlLDOSet( SYSCTL_LDO_2_75V ); + } + + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); + + /* Enable Port F for Ethernet LEDs + LED0 Bit 3 Output + LED1 Bit 2 Output */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); + GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); + GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static xOLEDMessage xMessage = { "PASS" }; +static unsigned long ulTicksSinceLastDisplay = 0; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Called from every tick interrupt. Have enough ticks passed to make it + time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN CREATE"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN REC MUTEX"; + } + else if( ulIdleError != pdFALSE ) + { + xMessage.pcMessage = "ERROR IN HOOK"; + } + else if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN INT QUEUE"; + } + else if( xAreQueueSetTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN QUEUE SET"; + } + + /* Send the message to the OLED gatekeeper for display. */ + xHigherPriorityTaskWoken = pdFALSE; + xQueueSendFromISR( xOLEDQueue, &xMessage, &xHigherPriorityTaskWoken ); + } + + /* Exercise the queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); +} +/*-----------------------------------------------------------*/ + +void vOLEDTask( void *pvParameters ) +{ +xOLEDMessage xMessage; +unsigned long ulY, ulMaxY; +static char cMessage[ mainMAX_MSG_LEN ]; +extern volatile unsigned long ulMaxJitter; +unsigned portBASE_TYPE uxUnusedStackOnEntry; +const unsigned char *pucImage; + +/* Functions to access the OLED. The one used depends on the dev kit +being used. */ +void ( *vOLEDInit )( unsigned long ) = NULL; +void ( *vOLEDStringDraw )( const char *, unsigned long, unsigned long, unsigned char ) = NULL; +void ( *vOLEDImageDraw )( const unsigned char *, unsigned long, unsigned long, unsigned long, unsigned long ) = NULL; +void ( *vOLEDClear )( void ) = NULL; + + /* Just for demo purposes. */ + uxUnusedStackOnEntry = uxTaskGetStackHighWaterMark( NULL ); + + /* Map the OLED access functions to the driver functions that are appropriate + for the evaluation kit being used. */ + switch( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) + { + case SYSCTL_DID1_PRTNO_6965 : + case SYSCTL_DID1_PRTNO_2965 : vOLEDInit = OSRAM128x64x4Init; + vOLEDStringDraw = OSRAM128x64x4StringDraw; + vOLEDImageDraw = OSRAM128x64x4ImageDraw; + vOLEDClear = OSRAM128x64x4Clear; + ulMaxY = mainMAX_ROWS_64; + pucImage = pucBasicBitmap; + break; + + case SYSCTL_DID1_PRTNO_1968 : + case SYSCTL_DID1_PRTNO_8962 : vOLEDInit = RIT128x96x4Init; + vOLEDStringDraw = RIT128x96x4StringDraw; + vOLEDImageDraw = RIT128x96x4ImageDraw; + vOLEDClear = RIT128x96x4Clear; + ulMaxY = mainMAX_ROWS_96; + pucImage = pucBasicBitmap; + break; + + default : vOLEDInit = vFormike128x128x16Init; + vOLEDStringDraw = vFormike128x128x16StringDraw; + vOLEDImageDraw = vFormike128x128x16ImageDraw; + vOLEDClear = vFormike128x128x16Clear; + ulMaxY = mainMAX_ROWS_128; + pucImage = pucGrLibBitmap; + break; + } + + ulY = ulMaxY; + + /* Initialise the OLED and display a startup message. */ + vOLEDInit( ulSSI_FREQUENCY ); + vOLEDStringDraw( "POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); + vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); + + /* Write the message on the next available row. */ + ulY += mainCHARACTER_HEIGHT; + if( ulY >= ulMaxY ) + { + ulY = mainCHARACTER_HEIGHT; + vOLEDClear(); + vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); + } + + /* Display the message along with the maximum jitter time from the + high priority time test. */ + sprintf( cMessage, "%s [%uns]", xMessage.pcMessage, ulMaxJitter * mainNS_PER_CLOCK ); + vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* Just to keep the linker happy. */ +void __error__( char *pcFilename, unsigned long ulLine ) +{ + for( ;; ); +} + +int uipprintf( const char *fmt, ... ) +{ + return( 0 ); +} diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.c new file mode 100644 index 0000000..3353a82 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.c @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sx965_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "osram128x64x4.h" + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for OSRAM usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-39 on one side, 40-79 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define OSRAM_INIT_REMAP 0x52 +#define OSRAM_INIT_OFFSET 0x4C +static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from OSRAM App Note AN018. +// +//***************************************************************************** +static const unsigned char g_pucOSRAM128x64x4Init[] = +{ + // + // Column Address + // + 4, 0x15, 0, 63, 0xe3, + + // + // Row Address + // + 4, 0x75, 0, 63, 0xe3, + + // + // Contrast Control + // + 3, 0x81, 50, 0xe3, + + // + // Half Current Range + // + 2, 0x85, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Multiplex Ratio + // + 3, 0xA8, 63, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x22, 0xe3, + + // + // Row Period + // + 3, 0xB2, 70, 0xe3, + + // + // Display Clock Divide + // + 3, 0xB3, 0xF1, 0xe3, + + // + // VSL + // + 3, 0xBF, 0x0D, 0xe3, + + // + // VCOMH + // + 3, 0xBE, 0x02, 0xe3, + + // + // VP + // + 3, 0xBC, 0x10, 0xe3, + + // + // Gamma + // + 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, + + // + // Set DC-DC + 3, 0xAD, 0x03, 0xe3, + + // + // Display ON/OFF + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; + unsigned long ulRow, ulColumn; + static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; + + // + // Set the window to fill the entire display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); + OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // In vertical address increment mode, loop through each column, filling + // each row with 0. + // + for(ulColumn = 0; ulColumn < (128/2); ulColumn++) + { + // + // 8 rows (bytes) per row of text. + // + for(ulRow = 0; ulRow < 80; ulRow += 8) + { + OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + static unsigned char pucBuffer[8]; + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = 63; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + 7; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + OSRAMWriteData(pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (/e ulX) and the number of +//! columns (/e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+--3------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by` +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + static unsigned char pucBuffer[8]; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 64); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = (ulX + ulWidth - 2) / 2; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + ulHeight - 1; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, + sizeof(g_pucOSRAM128x64x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + OSRAMWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the OSRAM driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the OSRAM driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); + +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD0323 controller on the panel. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the PC7 pin as a D/Cn signal for OLED device. + // + GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD); + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Configure and enable the SSI0 port for master mode. + // + OSRAM128x64x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + OSRAM128x64x4Clear(); + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xAD, 0x02 + }; + + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.h new file mode 100644 index 0000000..2ba7cb9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/osram128x64x4.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical +// OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM128X64X4_H__ +#define __OSRAM128X64X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAM128x64x4Clear(void); +extern void OSRAM128x64x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAM128x64x4Init(unsigned long ulFrequency); +extern void OSRAM128x64x4Enable(unsigned long ulFrequency); +extern void OSRAM128x64x4Disable(void); +extern void OSRAM128x64x4DisplayOn(void); +extern void OSRAM128x64x4DisplayOff(void); + +//***************************************************************************** +// +// The following macro(s) map old names for the OSRAM functions to the new +// names. In new code, the new names should be used in favor of the old names. +// +//***************************************************************************** +#ifndef DEPRECATED +#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable +#endif + +#endif // __OSRAM128X64X4_H__ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_end.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_end.h new file mode 100644 index 0000000..621c9fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_end.h @@ -0,0 +1,2 @@ +/* Note used by this port of uIP, but required for compilation. */ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_start.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_start.h new file mode 100644 index 0000000..621c9fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/pack_struct_start.h @@ -0,0 +1,2 @@ +/* Note used by this port of uIP, but required for compilation. */ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/rit128x96x4.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/rit128x96x4.c new file mode 100644 index 0000000..cff38d5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/rit128x96x4.c @@ -0,0 +1,981 @@ +//***************************************************************************** +// +// rit128x96x4.c - Driver for the RIT 128x96x4 graphical OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1504-conf of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sLM3S8962_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "rit128x96x4.h" + +//***************************************************************************** +// +// Macros that define the peripheral, port, and pin used for the OLEDDC +// panel control signal. +// +//***************************************************************************** + +unsigned long ulGPIOId = 0, ulGPIOBase = 0, ulOLEDDC_PIN = 0, ulOLEDEN_PIN = 0; + +#define LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOA +#define LM3S8962_GPIO_OLEDDC_BASE GPIO_PORTA_BASE +#define LM3S8962_GPIO_OLEDDC_PIN GPIO_PIN_6 +#define LM3S8962_GPIO_OLEDEN_PIN GPIO_PIN_7 + +#define LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOH +#define LM3S1968_GPIO_OLEDDC_BASE GPIO_PORTH_BASE +#define LM3S1968_GPIO_OLEDDC_PIN GPIO_PIN_2 +#define LM3S1968_GPIO_OLEDEN_PIN GPIO_PIN_3 + + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for display usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Buffer for storing sequences of command and data for the display. +// +//***************************************************************************** +static unsigned char g_pucBuffer[8]; + +//***************************************************************************** +// +// Define the SSD1329 128x96x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. Note that the controller support 128 rows while +// the RIT display only uses 96. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-63 on one side, 64-127 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-127 map to COM 127-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define RIT_INIT_REMAP 0x52 // app note says 0x51 +#define RIT_INIT_OFFSET 0x00 +static const unsigned char g_pucRIT128x96x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucRIT128x96x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD1329 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from RIT App Note for +// the P14201. Values used are from the RIT app note, except where noted. +// +//***************************************************************************** +static const unsigned char g_pucRIT128x96x4Init[] = +{ + // + // Unlock commands + // + 3, 0xFD, 0x12, 0xe3, + + // + // Display off + // + 2, 0xAE, 0xe3, + + // + // Icon off + // + 3, 0x94, 0, 0xe3, + + // + // Multiplex ratio + // + 3, 0xA8, 95, 0xe3, + + // + // Contrast + // + 3, 0x81, 0xb7, 0xe3, + + // + // Pre-charge current + // + 3, 0x82, 0x3f, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, RIT_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, RIT_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x11, 0xe3, + + // + // Frame frequency + // + 3, 0xB2, 0x23, 0xe3, + + // + // Front Clock Divider + // + 3, 0xB3, 0xe2, 0xe3, + + // + // Set gray scale table. App note uses default command: + // 2, 0xB7, 0xe3 + // This gray scale attempts some gamma correction to reduce the + // the brightness of the low levels. + // + 17, 0xB8, 1, 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 19, 22, 26, 30, 0xe3, + + // + // Second pre-charge period. App note uses value 0x04. + // + 3, 0xBB, 0x01, 0xe3, + + // + // Pre-charge voltage + // + 3, 0xBC, 0x3f, 0xe3, + + // + // Display ON + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, ulOLEDDC_PIN); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 127 }; + unsigned long ulRow, ulColumn; + + // + // Clear out the buffer used for sending bytes to the display. + *(unsigned long *)&g_pucBuffer[0] = 0; + *(unsigned long *)&g_pucBuffer[4] = 0; + + // + // Set the window to fill the entire display. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); + RITWriteCommand(pucCommand2, sizeof(pucCommand2)); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop through the rows + // + for(ulRow = 0; ulRow < 96; ulRow++) + { + // + // Loop through the columns. Each byte is two pixels, + // and the buffer hold 8 bytes, so 16 pixels are cleared + // at a time. + // + for(ulColumn = 0; ulColumn < 128; ulColumn += 8 * 2) + { + // + // Write 8 clearing bytes to the display, which will + // clear 16 pixels across. + // + RITWriteData(g_pucBuffer, sizeof(g_pucBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = 63; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + 7; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4VerticalInc, + sizeof(g_pucRIT128x96x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + g_pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + g_pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + g_pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + RITWriteData(g_pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (\e ulX) and the number of +//! columns (\e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 96); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = (ulX + ulWidth - 2) / 2; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + ulHeight - 1; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + RITWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the RIT driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the RIT driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD1329 controller on the panel. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + + /* Determine which board is being used. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + /* Ethernet is present, we must be using the LM3S8962 EK. */ + ulGPIOId = LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S8962_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_6; + ulOLEDEN_PIN = GPIO_PIN_7; + } + else + { + /* Ethernet is not present, we must be using the LM3S1968 EK. */ + ulGPIOId = LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S1968_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_2; + ulOLEDEN_PIN = GPIO_PIN_3; + } + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(ulGPIOId); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the GPIO port pin used as a D/Cn signal for OLED device, + // and the port pin used to enable power to the OLED panel. + // + GPIOPinTypeGPIOOutput(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN); + GPIOPadConfigSet(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + ulOLEDDC_PIN | ulOLEDEN_PIN); + + // + // Configure and enable the SSI0 port for master mode. + // + RIT128x96x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + RIT128x96x4Clear(); + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xe3 + }; + + // + // Put the display to sleep. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/thumb_crt0.s b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/thumb_crt0.s new file mode 100644 index 0000000..4c4b71d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/thumb_crt0.s @@ -0,0 +1,227 @@ +/***************************************************************************** + * Copyright (c) 2009 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions + * ------------------------ + * APP_ENTRY_POINT + * + * Defines the application entry point function, if undefined this setting + * defaults to "main". + * + * USE_PROCESS_STACK + * + * If defined, thread mode will be configured to use the process stack if + * the size of the process stack is greater than zero bytes in length. + * + * INITIALIZE_STACK + * + * If defined, the contents of the stack will be initialized to a the + * value 0xCC. + * + * FULL_LIBRARY + * + * If defined then + * - argc, argv are setup by the debug_getargs. + * - the exit symbol is defined and executes on return from main. + * - the exit symbol calls destructors, atexit functions and then debug_exit. + * + * If not defined then + * - argc and argv are zero. + * - no exit symbol, code loops on return from main. + *****************************************************************************/ + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + + .global _start + .syntax unified + .extern APP_ENTRY_POINT +#ifdef FULL_LIBRARY + .global exit +#endif + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + +_start: +#ifdef __RAM_BUILD + ldr r1, =__stack_end__ + mov sp, r1 +#endif +#ifdef INITIALIZE_STACK + mov r2, #0xCC + ldr r0, =__stack_start__ +#ifndef __RAM_BUILD + mov r1, sp +#endif + bl memory_set +#endif + +#ifdef USE_PROCESS_STACK + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f + msr psp, r1 + mov r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + mov r2, #0xCC + bl memory_set +#endif +1: +#endif + /* Copy initialised memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl memory_set + + /* Initialise the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + mov r0, #0 + mov lr, r0 + mov r12, sp + +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + mov r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + mov r0, #0 + mov r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + +#ifdef FULL_LIBRARY + .thumb_func +exit: + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + add r0, r0, #1 + b memory_set +1: + bx lr + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/timertest.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/timertest.c new file mode 100644 index 0000000..7fcc85e --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/timertest.c @@ -0,0 +1,176 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* High speed timer test as described in main.c. */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 0 ) + +/* Misc defines. */ +#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) +#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) + +/*-----------------------------------------------------------*/ + +/* Interrupt handler in which the jitter is measured. */ +void Timer0IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +volatile unsigned long ulMaxJitter = 0UL; + +/* Counts the total number of times that the high frequency timer has 'ticked'. +This value is used by the run time stats function to work out what percentage +of CPU time each task is taking. */ +volatile unsigned long ulHighFrequencyTimerTicks = 0UL; +/*-----------------------------------------------------------*/ + +void vSetupHighFrequencyTimer( void ) +{ +unsigned long ulFrequency; + + /* Timer zero is used to generate the interrupts, and timer 1 is used + to measure the jitter. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); + TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupt to be above the kernel - highest. */ + IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); + + /* Just used to measure time. */ + TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); + + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + + /* The rate at which the timer will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; + TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER0A ); + TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER0_BASE, TIMER_A ); + TimerEnable( TIMER1_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void Timer0IntHandler( void ) +{ +unsigned long ulDifference; +volatile unsigned long ulCurrentCount; +static unsigned long ulMaxDifference = 0, ulLastCount = 0; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. */ + ulCurrentCount = timerTIMER_1_COUNT_VALUE; + + TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); + + if( ulCurrentCount < ulLastCount ) + { + /* How many times has timer 1 counted since the last interrupt? */ + ulDifference = ulLastCount - ulCurrentCount; + + /* Is this the largest difference we have measured yet? */ + if( ulDifference > ulMaxDifference ) + { + ulMaxDifference = ulDifference; + ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; + } + } + + ulLastCount = ulCurrentCount; + + /* Keep a count of the total number of 20KHz ticks. This is used by the + run time stats functionality to calculate how much CPU time is used by + each task. */ + ulHighFrequencyTimerTicks++; +} + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/Makefile.webserver b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/Makefile.webserver new file mode 100644 index 0000000..f38c47a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/clock-arch.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/clock-arch.h new file mode 100644 index 0000000..cde657b --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/emac.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/emac.c new file mode 100644 index 0000000..60e17de --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/emac.c @@ -0,0 +1,312 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" + +/* Demo includes. */ +#include "emac.h" + +/* uIP includes. */ +#include "uip.h" + +/* Hardware library includes. */ +#include "hw_types.h" +#include "hw_memmap.h" +#include "hw_ints.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "interrupt.h" + +#define emacNUM_RX_BUFFERS 5 +#define emacFRAM_SIZE_BYTES 2 +#define macNEGOTIATE_DELAY 2000 +#define macWAIT_SEND_TIME ( 10 ) + +/* The task that handles the MAC peripheral. This is created at a high +priority and is effectively a deferred interrupt handler. The peripheral +handling is deferred to a task to prevent the entire FIFO having to be read +from within an ISR. */ +void vMACHandleTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used to wake the uIP task when data arrives. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +/* The semaphore used to wake the interrupt handler task. The peripheral +is processed at the task level to prevent the need to read the entire FIFO from +within the ISR itself. */ +xSemaphoreHandle xMACInterruptSemaphore = NULL; + +/* The buffer used by the uIP stack. In this case the pointer is used to +point to one of the Rx buffers. */ +unsigned char *uip_buf; + +/* Buffers into which Rx data is placed. */ +static unsigned char ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ] __attribute__((aligned(4))); + +/* The length of the data within each of the Rx buffers. */ +static unsigned long ulRxLength[ emacNUM_RX_BUFFERS ]; + +/* Used to keep a track of the number of bytes to transmit. */ +static unsigned long ulNextTxSpace; + +/*-----------------------------------------------------------*/ + +portBASE_TYPE vInitEMAC( void ) +{ +unsigned long ulTemp; +portBASE_TYPE xReturn; + + /* Ensure all interrupts are disabled. */ + EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); + + /* Clear any interrupts that were already pending. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Initialise the MAC and connect. */ + EthernetInit( ETH_BASE ); + EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); + EthernetEnable( ETH_BASE ); + + /* Mark each Rx buffer as empty. */ + for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) + { + ulRxLength[ ulTemp ] = 0; + } + + /* Create the queue and task used to defer the MAC processing to the + task level. */ + vSemaphoreCreateBinary( xMACInterruptSemaphore ); + xSemaphoreTake( xMACInterruptSemaphore, 0 ); + xReturn = xTaskCreate( vMACHandleTask, ( signed char * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + vTaskDelay( macNEGOTIATE_DELAY ); + + /* We are only interested in Rx interrupts. */ + IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_ETH ); + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) +{ +static unsigned long ulNextRxBuffer = 0; +unsigned int iLen; + + iLen = ulRxLength[ ulNextRxBuffer ]; + + if( iLen != 0 ) + { + /* Leave room for the size at the start of the buffer. */ + uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + + ulRxLength[ ulNextRxBuffer ] = 0; + + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + return iLen; +} +/*-----------------------------------------------------------*/ + +void vInitialiseSend( void ) +{ + /* Set the index to the first byte to send - skipping over the size + bytes. */ + ulNextTxSpace = 2; +} +/*-----------------------------------------------------------*/ + +void vIncrementTxLength( unsigned long ulLength ) +{ + ulNextTxSpace += ulLength; +} +/*-----------------------------------------------------------*/ + +void vSendBufferToMAC( void ) +{ +unsigned long *pulSource; +unsigned short * pus; +unsigned long ulNextWord; + + /* Locate the data to be send. */ + pus = ( unsigned short * ) uip_buf; + + /* Add in the size of the data. */ + pus--; + *pus = ulNextTxSpace; + + /* Wait for data to be sent if there is no space immediately. */ + while( !EthernetSpaceAvail( ETH_BASE ) ) + { + vTaskDelay( macWAIT_SEND_TIME ); + } + + pulSource = ( unsigned long * ) pus; + + for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned long ) ) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; + pulSource++; + } + + /* Go. */ + HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR( void ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; +unsigned long ulTemp; + + /* Clear the interrupt. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Was it an Rx interrupt? */ + if( ulTemp & ETH_INT_RX ) + { + xSemaphoreGiveFromISR( xMACInterruptSemaphore, &xHigherPriorityTaskWoken ); + EthernetIntDisable( ETH_BASE, ETH_INT_RX ); + } + + /* Switch to the uIP task. */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +void vMACHandleTask( void *pvParameters ) +{ +unsigned long i; +unsigned long ulLength, ulInt; +unsigned long *pulBuffer; +static unsigned long ulNextRxBuffer = 0; + + for( ;; ) + { + /* Wait for something to do. */ + xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); + + while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) + { + ulLength = HWREG( ETH_BASE + MAC_O_DATA ); + + /* Leave room at the start of the buffer for the size. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + *pulBuffer = ( ulLength >> 16 ); + + /* Get the size of the data. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); + ulLength &= 0xFFFF; + + if( ulLength > 4 ) + { + ulLength -= 4; + + if( ulLength >= UIP_BUFSIZE ) + { + /* The data won't fit in our buffer. Ensure we don't + try to write into the buffer. */ + ulLength = 0; + } + + /* Read out the data into our buffer. */ + for( i = 0; i < ulLength; i += sizeof( unsigned long ) ) + { + *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); + pulBuffer++; + } + + /* Store the length of the data into the separate array. */ + ulRxLength[ ulNextRxBuffer ] = ulLength; + + /* Use the next buffer the next time through. */ + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + + /* Ensure the uIP task is not blocked as data has arrived. */ + xSemaphoreGive( xEMACSemaphore ); + } + } + + EthernetIntEnable( ETH_BASE, ETH_INT_RX ); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/emac.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/emac.h new file mode 100644 index 0000000..a49b598 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/emac.h @@ -0,0 +1,322 @@ +/*---------------------------------------------------------------------------- + * LPC2378 Ethernet Definitions + *---------------------------------------------------------------------------- + * Name: EMAC.H + * Purpose: Philips LPC2378 EMAC hardware definitions + *---------------------------------------------------------------------------- + * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#ifndef __EMAC_H +#define __EMAC_H + +/* MAC address definition. The MAC address must be unique on the network. */ +#define emacETHADDR0 0 +#define emacETHADDR1 0xbd +#define emacETHADDR2 0x33 +#define emacETHADDR3 0x02 +#define emacETHADDR4 0x64 +#define emacETHADDR5 0x24 + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x7FE00000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#undef SUPP_SPEED /* Remove compiler warning. */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#undef MCMD_READ /* Remove compiler warning. */ +#define MCMD_READ 0x00000001 /* MII Read */ +#undef MCMD_SCAN /* Remove compiler warning. */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#undef MIND_BUSY /* Remove compiler warning. */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +// prototypes +portBASE_TYPE vInitEMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void vIncrementTxLength(unsigned long ulLength); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void vInitialiseSend(void); +unsigned int Rdy4Tx(void); +void vSendBufferToMAC(void); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings new file mode 100644 index 0000000..0d3c30c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings.c new file mode 100644 index 0000000..ef7a41c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings.h new file mode 100644 index 0000000..acbe7e1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-cgi.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-cgi.c new file mode 100644 index 0000000..1bf08e2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-cgi.c @@ -0,0 +1,293 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(run, "run-time", run_time ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &run, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus; +extern unsigned long uxParTestGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + if( uxParTestGetLED( 0 ) ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, + "LED"\ + "

"\ + "", + pcStatus ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskGetRunTimeStats( signed char *pcWriteBuffer ); +static unsigned short +generate_runtime_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskGetRunTimeStats( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(run_time(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_runtime_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-cgi.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-cgi.h new file mode 100644 index 0000000..7ae9283 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs.c new file mode 100644 index 0000000..dc4aef0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs.h new file mode 100644 index 0000000..b594eea --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/404.html b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/404.html new file mode 100644 index 0000000..43e7f4c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/index.html b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/index.html new file mode 100644 index 0000000..4937dc6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/index.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/index.shtml new file mode 100644 index 0000000..29d242c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/io.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/io.shtml new file mode 100644 index 0000000..fd0697d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". + + +

+
+%! led-io +

+ + +

+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/runtime.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/runtime.shtml new file mode 100644 index 0000000..67cae46 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/runtime.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Run-time statistics

+Page will refresh every 2 seconds.

+

Task            Abs Time      % Time
****************************************

+%! run-time
+
+ + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/stats.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/stats.shtml new file mode 100644 index 0000000..d95a693 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/tcp.shtml b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/tcp.shtml new file mode 100644 index 0000000..4105367 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Task Stats | Run Time Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fsdata.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fsdata.c new file mode 100644 index 0000000..7348902 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fsdata.c @@ -0,0 +1,557 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, + 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, + 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, + 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, 0x65, 0x6e, + 0x74, 0x65, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, + 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, + 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, + 0xa, 0x20, 0x20, 0x20, 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0x73, 0x2e, 0x6f, 0x72, 0x67, + 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, + 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, 0x6f, 0x6d, 0x65, + 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, + 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, + 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6f, 0x2e, + 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x49, 0x4f, 0x3c, + 0x2f, 0x61, 0x3e, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, + 0x3e, 0xa, 0x3c, 0x68, 0x72, 0x3e, 0xa, 0x3c, 0x62, 0x72, + 0x3e, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, + 0x6f, 0x72, 0x6b, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, + 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, + 0xa, 0x3c, 0x70, 0x3e, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, + 0x65, 0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, + 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, + 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, + 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, + 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, + 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, + 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, + 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, + 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, + 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, 0x21, + 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, 0x65, + 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xa, 0x3c, 0x2f, 0x70, + 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, + 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, 0x3c, + 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, + 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_runtime_shtml[] = {{file_io_shtml, data_runtime_shtml, data_runtime_shtml + 15, sizeof(data_runtime_shtml) - 15}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_runtime_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 7 diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fsdata.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fsdata.h new file mode 100644 index 0000000..52d35c2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd.c new file mode 100644 index 0000000..644cf16 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd.h new file mode 100644 index 0000000..7f7a666 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/makefsdata b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/makefsdata new file mode 100644 index 0000000..8d2715a --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/makestrings b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/makestrings new file mode 100644 index 0000000..8a13c6d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/uIP_Task.c b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/uIP_Task.c new file mode 100644 index 0000000..366e9c2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/uIP_Task.c @@ -0,0 +1,349 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +#include "lcd_message.h" + +/* uip includes. */ +#include "hw_types.h" + +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "hw_memmap.h" +#include "lmi_flash.h" +#include "sysctl.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" + +/*-----------------------------------------------------------*/ + +/* IP address configuration. */ +#define uipIP_ADDR0 192 +#define uipIP_ADDR1 168 +#define uipIP_ADDR2 0 +#define uipIP_ADDR3 201 + +/* Netmask configuration. */ +#define uipNETMASK_0 255 +#define uipNETMASK_1 255 +#define uipNETMASK_2 255 +#define uipNETMASK_3 0 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} + + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR )( void ); + + /* Enable/Reset the Ethernet Controller */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); + SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + uip_ipaddr( xIPAddr, uipNETMASK_0, uipNETMASK_1, uipNETMASK_2, uipNETMASK_3 ); + uip_setnetmask( xIPAddr ); + httpd_init(); + + while( vInitEMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + prvSetMACAddress(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + vInitialiseSend(); + vIncrementTxLength( uip_len ); + vSendBufferToMAC(); + vInitialiseSend(); + vIncrementTxLength( uip_len ); + vSendBufferToMAC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +unsigned long ulUser0, ulUser1; +unsigned char pucMACArray[8]; +struct uip_eth_addr xAddr; + + /* Get the device MAC address from flash */ + FlashUserGet(&ulUser0, &ulUser1); + + /* Convert the MAC address from flash into sequence of bytes. */ + pucMACArray[0] = ((ulUser0 >> 0) & 0xff); + pucMACArray[1] = ((ulUser0 >> 8) & 0xff); + pucMACArray[2] = ((ulUser0 >> 16) & 0xff); + pucMACArray[3] = ((ulUser1 >> 0) & 0xff); + pucMACArray[4] = ((ulUser1 >> 8) & 0xff); + pucMACArray[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the MAC address. */ + EthernetMACAddrSet(ETH_BASE, pucMACArray); + + xAddr.addr[ 0 ] = pucMACArray[0]; + xAddr.addr[ 1 ] = pucMACArray[1]; + xAddr.addr[ 2 ] = pucMACArray[2]; + xAddr.addr[ 3 ] = pucMACArray[3]; + xAddr.addr[ 4 ] = pucMACArray[4]; + xAddr.addr[ 5 ] = pucMACArray[5]; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( char *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static char cMessageForDisplay[ 32 ]; +extern xQueueHandle xOLEDQueue; +xOLEDMessage xOLEDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 0, 1 ); + } + else + { + vParTestSetLED( 0, 0 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xOLEDMessage.pcMessage = cMessageForDisplay; + xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); + } +} + diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/uip-conf.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/uip-conf.h new file mode 100644 index 0000000..664077d --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1500 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#define UIP_CONF_EXTERNAL_BUFFER + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/webserver.h b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/webserver.h new file mode 100644 index 0000000..1acb290 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_LM3Sxxxx_Rowley/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/FreeRTOSConfig.h b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/FreeRTOSConfig.h new file mode 100644 index 0000000..51898d3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/FreeRTOSConfig.h @@ -0,0 +1,127 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 50000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2560 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 0 +#define configUSE_COUNTING_SEMAPHORES 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_RECURSIVE_MUTEXES 0 +#define configQUEUE_REGISTRY_SIZE 0 +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_MALLOC_FAILED_HOOK 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 + +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 +#endif +#define configUNUSED_PRIO_BITS ( ( unsigned char ) ( 8 - configPRIO_BITS ) ) + +#define configKERNEL_INTERRUPT_PRIORITY ( ( unsigned char ) 7 << configUNUSED_PRIO_BITS ) /* Priority 7, or 255 as only the top three bits are implemented. This is the lowest priority. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( ( unsigned char ) 5 << configUNUSED_PRIO_BITS ) /* Priority 5, or 160 as only the top three bits are implemented. */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/LM3S_Startup.s b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/LM3S_Startup.s new file mode 100644 index 0000000..cbf6ecf --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/LM3S_Startup.s @@ -0,0 +1,196 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions + * ------------------------ + * + * STARTUP_FROM_RESET + * + * If defined, the program will startup from power-on/reset. If not defined + * the program will just loop endlessly from power-on/reset. + * + * This definition is not defined by default on this target because the + * debugger is unable to reset this target and maintain control of it over the + * JTAG interface. The advantage of doing this is that it allows the debugger + * to reset the CPU and run programs from a known reset CPU state on each run. + * It also acts as a safety net if you accidently download a program in FLASH + * that crashes and prevents the debugger from taking control over JTAG + * rendering the target unusable over JTAG. The obvious disadvantage of doing + * this is that your application will not startup without the debugger. + * + * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst + * you are developing and only define STARTUP_FROM_RESET when development is + * complete. + * + *****************************************************************************/ + +.extern xPortPendSVHandler +.extern xPortSysTickHandler +.extern vPortSVCHandler + +.global reset_handler + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word reset_handler +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word Nmi_ISR + .word Fault_ISR + .word MPU_Fault_ISR + .word 0 /* Populate if using Bus fault */ + .word 0 /* Populate if using Usage fault */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word vPortSVCHandler + .word 0 /* Populate if using a debug monitor */ + .word 0 /* Reserved */ + .word xPortPendSVHandler + .word xPortSysTickHandler + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word UART0_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_Timer_ISR + .word Timer0A_ISR + .word Timer0B_ISR + .word Timer1A_ISR + .word Timer1B_ISR + .word Timer2A_ISR + .word Timer2B_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + .word GPIO_Port_F_ISR + .word GPIO_Port_G_ISR + .word GPIO_Port_H_ISR + .word UART2_ISR + .word SSI1_ISR + .word Timer3A_ISR + .word Timer3B_ISR + .word I2C1_ISR + .word QEI1_ISR + .word CAN0_ISR + .word CAN1_ISR + .word CAN2_ISR + .word EMAC_ISR + .word HIBERNATE_ISR + .word USB0_ISR + .word PWM_Generator_3_ISR + .word uDMA_Software_Transfer_ISR + .word uDMA_Error_ISR +_vectors_end: + + .section .init, "ax" + .thumb_func + +reset_handler: +#ifdef __RAM_BUILD + /* If this is a RAM build, configure vector table offset register to point + to the RAM vector table. */ + ldr r0, =0xE000ED08 + ldr r1, =_vectors + str r1, [r0] +#endif + b _start + +DEFAULT_ISR_HANDLER Nmi_ISR +/*DEFAULT_ISR_HANDLER Fault_ISR*/ +/*DEFAULT_ISR_HANDLER MPU_Fault_ISR*/ +DEFAULT_ISR_HANDLER SVCall_ISR +DEFAULT_ISR_HANDLER SysTick_ISR +DEFAULT_ISR_HANDLER PendSV_ISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_Timer_ISR +DEFAULT_ISR_HANDLER Timer0A_ISR +DEFAULT_ISR_HANDLER Timer0B_ISR +DEFAULT_ISR_HANDLER Timer1A_ISR +DEFAULT_ISR_HANDLER Timer1B_ISR +DEFAULT_ISR_HANDLER Timer2A_ISR +DEFAULT_ISR_HANDLER Timer2B_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR +DEFAULT_ISR_HANDLER GPIO_Port_F_ISR +DEFAULT_ISR_HANDLER GPIO_Port_G_ISR +DEFAULT_ISR_HANDLER GPIO_Port_H_ISR +DEFAULT_ISR_HANDLER UART2_ISR +DEFAULT_ISR_HANDLER SSI1_ISR +DEFAULT_ISR_HANDLER Timer3A_ISR +DEFAULT_ISR_HANDLER Timer3B_ISR +DEFAULT_ISR_HANDLER I2C1_ISR +DEFAULT_ISR_HANDLER QEI1_ISR +DEFAULT_ISR_HANDLER CAN0_ISR +DEFAULT_ISR_HANDLER CAN1_ISR +DEFAULT_ISR_HANDLER CAN2_ISR +DEFAULT_ISR_HANDLER ETHERNET_ISR +DEFAULT_ISR_HANDLER HIBERNATE_ISR +DEFAULT_ISR_HANDLER USB0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_3_ISR +DEFAULT_ISR_HANDLER uDMA_Software_Transfer_ISR +DEFAULT_ISR_HANDLER uDMA_Error_ISR +DEFAULT_ISR_HANDLER EMAC_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ + diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/LM3S_Target.js b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/LM3S_Target.js new file mode 100644 index 0000000..55a9c2c --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/LM3S_Target.js @@ -0,0 +1,28 @@ +/****************************************************************************** + Target Script for LM3S. + + Copyright (c) 2006 Rowley Associates Limited. + + This file may be distributed under the terms of the License Agreement + provided with this software. + + THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE + WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + ******************************************************************************/ + +function Reset() +{ + TargetInterface.resetAndStop(1000); +} + +function RAMReset() +{ + Reset(); +} + +function FLASHReset() +{ + Reset(); +} + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/RTOSDemo.hzp b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/RTOSDemo.hzp new file mode 100644 index 0000000..fab3463 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/RTOSDemo.hzp @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/RTOSDemo.hzs b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/RTOSDemo.hzs new file mode 100644 index 0000000..93cb286 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/RTOSDemo.hzs @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/flash_placement.xml b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/flash_placement.xml new file mode 100644 index 0000000..1a5c7a5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/flash_placement.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/main.c b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/main.c new file mode 100644 index 0000000..749b7e1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/main.c @@ -0,0 +1,1006 @@ +/* + FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong? * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, training, latest information, + license and contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool. + + Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell + the code with commercial support, indemnification, and middleware, under + the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also + provide a safety engineered and independently SIL3 certified version under + the SafeRTOS brand: http://www.SafeRTOS.com. +*/ + + +/* + * This file demonstrates the use of FreeRTOS-MPU. It creates tasks in both + * User mode and Privileged mode, and using both the original xTaskCreate() and + * the new xTaskCreateRestricted() API functions. The purpose of each created + * task is documented in the comments above the task function prototype (in + * this file), with the task behaviour demonstrated and documented within the + * task function itself. In addition a queue is used to demonstrate passing + * data between protected/restricted tasks as well as passing data between an + * interrupt and a protected/restricted task. + */ + + + +/* Standard includes. */ +#include +#include <__cross_studio_io.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Hardware library includes. */ +#include "hw_types.h" +#include "hw_sysctl.h" +#include "sysctl.h" + +/*-----------------------------------------------------------*/ + +/* Misc constants. */ +#define mainDONT_BLOCK ( 0 ) + +/* Definitions for the messages that can be sent to the check task. */ +#define mainREG_TEST_1_STILL_EXECUTING ( 0 ) +#define mainREG_TEST_2_STILL_EXECUTING ( 1 ) +#define mainPRINT_SYSTEM_STATUS ( 2 ) + +/* GCC specifics. */ +#define mainALIGN_TO( x ) __attribute__((aligned(x))) + + +/*-----------------------------------------------------------*/ +/* Prototypes for functions that implement tasks. -----------*/ +/*-----------------------------------------------------------*/ + +/* + * Prototype for the reg test tasks. Amongst other things, these fill the CPU + * registers with known values before checking that the registers still contain + * the expected values. Each of the two tasks use different values so an error + * in the context switch mechanism can be caught. Both reg test tasks execute + * at the idle priority so will get preempted regularly. Each task repeatedly + * sends a message on a queue so long as it remains functioning correctly. If + * an error is detected within the task the task is simply deleted. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); + +/* + * Prototype for the check task. The check task demonstrates various features + * of the MPU before entering a loop where it waits for messages to arrive on a + * queue. + * + * Two types of messages can be processes: + * + * 1) "I'm Alive" messages sent from the reg test tasks, indicating that the + * task is still operational. + * + * 2) "Print Status commands" sent periodically by the tick hook function (and + * therefore from within an interrupt) which command the check task to write + * either pass or fail to the terminal, depending on the status of the reg + * test tasks. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Prototype for a task created in User mode using the original vTaskCreate() + * API function. The task demonstrates the characteristics of such a task, + * before simply deleting itself. + */ +static void prvOldStyleUserModeTask( void *pvParameters ); + +/* + * Prototype for a task created in Privileged mode using the original + * vTaskCreate() API function. The task demonstrates the characteristics of + * such a task, before simply deleting itself. + */ +static void prvOldStylePrivilegedModeTask( void *pvParameters ); + + +/*-----------------------------------------------------------*/ +/* Prototypes for other misc functions. --------------------*/ +/*-----------------------------------------------------------*/ + +/* + * Just configures any clocks and IO necessary. + */ +static void prvSetupHardware( void ); + +/* + * Simply deletes the calling task. The function is provided only because it + * is simpler to call from asm code than the normal vTaskDelete() API function. + * It has the noinline attribute because it is called from asm code. + */ +static void prvDeleteMe( void ) __attribute__((noinline)); + +/* + * Used by both reg test tasks to send messages to the check task. The message + * just lets the check task know that the task is still functioning correctly. + * If a reg test task detects an error it will delete itself, and in so doing + * prevent itself from sending any more 'I'm Alive' messages to the check task. + */ +static void prvSendImAlive( xQueueHandle xHandle, unsigned long ulTaskNumber ); + +/* + * The check task is created with access to three memory regions (plus its + * stack). Each memory region is configured with different parameters and + * prvTestMemoryRegions() demonstrates what can and cannot be accessed for each + * region. prvTestMemoryRegions() also demonstrates a task that was created + * as a privileged task settings its own privilege level down to that of a user + * task. + */ +static void prvTestMemoryRegions( void ); + +/*-----------------------------------------------------------*/ + +/* The handle of the queue used to communicate between tasks and between tasks +and interrupts. Note that this is a file scope variable that falls outside of +any MPU region. As such other techniques have to be used to allow the tasks +to gain access to the queue. See the comments in the tasks themselves for +further information. */ +static xQueueHandle xFileScopeCheckQueue = NULL; + + +/*-----------------------------------------------------------*/ +/* Data used by the 'check' task. ---------------------------*/ +/*-----------------------------------------------------------*/ + +/* Define the constants used to allocate the check task stack. Note that the +stack size is defined in words, not bytes. */ +#define mainCHECK_TASK_STACK_SIZE_WORDS 128 +#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + +/* Declare the stack that will be used by the check task. The kernel will + automatically create an MPU region for the stack. The stack alignment must + match its size, so if 128 words are reserved for the stack then it must be + aligned to ( 128 * 4 ) bytes. */ +static portSTACK_TYPE xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainCHECK_TASK_STACK_ALIGNMENT ); + +/* Declare three arrays - an MPU region will be created for each array +using the xTaskParameters structure below. THIS IS JUST TO DEMONSTRATE THE +MPU FUNCTIONALITY, the data is not used by the check tasks primary function +of monitoring the reg test tasks and printing out status information. + +Note that the arrays allocate slightly more RAM than is actually assigned to +the MPU region. This is to permit writes off the end of the array to be +detected even when the arrays are placed in adjacent memory locations (with no +gaps between them). The align size must be a power of two. */ +#define mainREAD_WRITE_ARRAY_SIZE 130 +#define mainREAD_WRITE_ALIGN_SIZE 128 +char cReadWriteArray[ mainREAD_WRITE_ARRAY_SIZE ] mainALIGN_TO( mainREAD_WRITE_ALIGN_SIZE ); + +#define mainREAD_ONLY_ARRAY_SIZE 260 +#define mainREAD_ONLY_ALIGN_SIZE 256 +char cReadOnlyArray[ mainREAD_ONLY_ARRAY_SIZE ] mainALIGN_TO( mainREAD_ONLY_ALIGN_SIZE ); + +#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 +#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 +char cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] mainALIGN_TO( mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ); + +/* Fill in a xTaskParameters structure to define the check task - this is the +structure passed to the xTaskCreateRestricted() function. */ +static const xTaskParameters xCheckTaskParameters = +{ + prvCheckTask, /* pvTaskCode - the function that implements the task. */ + ( signed char * ) "Check", /* pcName */ + mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ + ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT,/* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ + xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + + /* xRegions - In this case the xRegions array is used to create MPU regions + for all three of the arrays declared directly above. Each MPU region is + created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE + MPU FUNCTIONALITY, the data is not used by the check tasks primary function + of monitoring the reg test tasks and printing out status information.*/ + { + /* Base address Length Parameters */ + { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, + { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, + { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } + } +}; + +/* Three MPU regions are defined for use by the 'check' task when the task is +created. These are only used to demonstrate the MPU features and are not +actually necessary for the check task to fulfill its primary purpose. Instead +the MPU regions are replaced with those defined by xAltRegions prior to the +check task receiving any data on the queue or printing any messages to the +debug console. The region configured by xAltRegions just gives the check task +access to the debug variables that form part of the Rowley library, and are +accessed within the debug_printf() function. */ +extern unsigned long dbgCntrlWord_mempoll; +static const xMemoryRegion xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] = +{ + /* Base address Length Parameters */ + { ( void * ) &dbgCntrlWord_mempoll, 32, portMPU_REGION_READ_WRITE }, + { 0, 0, 0 }, + { 0, 0, 0 } +}; + + + +/*-----------------------------------------------------------*/ +/* Data used by the 'reg test' tasks. -----------------------*/ +/*-----------------------------------------------------------*/ + +/* Define the constants used to allocate the reg test task stacks. Note that +that stack size is defined in words, not bytes. */ +#define mainREG_TEST_STACK_SIZE_WORDS 128 +#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + +/* Declare the stacks that will be used by the reg test tasks. The kernel will +automatically create an MPU region for the stack. The stack alignment must +match its size, so if 128 words are reserved for the stack then it must be +aligned to ( 128 * 4 ) bytes. */ +static portSTACK_TYPE xRegTest1Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); +static portSTACK_TYPE xRegTest2Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); + +/* Fill in a xTaskParameters structure per reg test task to define the tasks. */ +static const xTaskParameters xRegTest1Parameters = +{ + prvRegTest1Task, /* pvTaskCode - the function that implements the task. */ + ( signed char * ) "RegTest1", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) 0x12345678, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ + xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } +}; +/*-----------------------------------------------------------*/ + +static xTaskParameters xRegTest2Parameters = +{ + prvRegTest2Task, /* pvTaskCode - the function that implements the task. */ + ( signed char * ) "RegTest2", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + tskIDLE_PRIORITY, /* uxPriority */ + xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } +}; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used to pass "I'm alive" messages to the check task. */ + xFileScopeCheckQueue = xQueueCreate( 1, sizeof( unsigned long ) ); + + /* One check task uses the task parameter to receive the queue handle. + This allows the file scope variable to be accessed from within the task. + The pvParameters member of xRegTest2Parameters can only be set after the + queue has been created so is set here. */ + xRegTest2Parameters.pvParameters = xFileScopeCheckQueue; + + /* Create the three test tasks. Handles to the created tasks are not + required, hence the second parameter is NULL. */ + xTaskCreateRestricted( &xRegTest1Parameters, NULL ); + xTaskCreateRestricted( &xRegTest2Parameters, NULL ); + xTaskCreateRestricted( &xCheckTaskParameters, NULL ); + + /* Create the tasks that are created using the original xTaskCreate() API + function. */ + xTaskCreate( prvOldStyleUserModeTask, /* The function that implements the task. */ + ( signed char * ) "Task1", /* Text name for the task. */ + 100, /* Stack depth in words. */ + NULL, /* Task parameters. */ + 3, /* Priority and mode (user in this case). */ + NULL /* Handle. */ + ); + + xTaskCreate( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ + ( signed char * ) "Task2", /* Text name for the task. */ + 100, /* Stack depth in words. */ + NULL, /* Task parameters. */ + ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ + NULL /* Handle. */ + ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +/* This task is created in privileged mode so can access the file scope +queue variable. Take a stack copy of this before the task is set into user +mode. Once that task is in user mode the file scope queue variable will no +longer be accessible but the stack copy will. */ +xQueueHandle xQueue = xFileScopeCheckQueue; +long lMessage; +unsigned long ulStillAliveCounts[ 2 ] = { 0 }; +const char *pcStatusMessage = "PASS\r\n"; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* Print out the amount of free heap space so configTOTAL_HEAP_SIZE can be + tuned. The heap size is set to be very small in this example and will need + to be increased before many more tasks, queues or semaphores can be + created. */ + debug_printf( "There are %d bytes of unused heap space.\r\n", xPortGetFreeHeapSize() ); + + /* Demonstrate how the various memory regions can and can't be accessed. + The task privilege level is set down to user mode within this function. */ + prvTestMemoryRegions(); + + /* Change the memory regions allocated to this task to those initially + set up for demonstration purposes to those actually required by the task. */ + vTaskAllocateMPURegions( NULL, xAltRegions ); + + /* This loop performs the main function of the task, which is blocking + on a message queue then processing each message as it arrives. */ + for( ;; ) + { + /* Wait for the next message to arrive. */ + xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); + + switch( lMessage ) + { + case mainREG_TEST_1_STILL_EXECUTING : + /* Message from task 1, so task 1 must still be executing. */ + ( ulStillAliveCounts[ 0 ] )++; + break; + + case mainREG_TEST_2_STILL_EXECUTING : + /* Message from task 2, so task 2 must still be executing. */ + ( ulStillAliveCounts[ 1 ] )++; + break; + + case mainPRINT_SYSTEM_STATUS : + /* Message from tick hook, time to print out the system + status. If messages has stopped arriving from either reg + test task then the status must be set to fail. */ + if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) ) + { + /* One or both of the test tasks are no longer sending + 'still alive' messages. */ + pcStatusMessage = "FAIL\r\n"; + } + + /* Print a pass/fail message to the terminal. This will be + visible in the CrossWorks IDE. */ + debug_printf( pcStatusMessage ); + + /* Reset the count of 'still alive' messages. */ + memset( ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); + break; + + default : + /* Something unexpected happened. Delete this task so the + error is apparent (no output will be displayed). */ + prvDeleteMe(); + break; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvTestMemoryRegions( void ) +{ +long l; +char cTemp; + + /* The check task (from which this function is called) is created in the + Privileged mode. The privileged array can be both read from and written + to while this task is privileged. */ + cPrivilegedOnlyAccessArray[ 0 ] = 'a'; + if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + apparent (no output will be displayed). */ + prvDeleteMe(); + } + + /* Writing off the end of the RAM allocated to this task will *NOT* cause a + protection fault because the task is still executing in a privileged mode. + Uncomment the following to test. */ + /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ + + /* Now set the task into user mode. */ + portSWITCH_TO_USER_MODE(); + + /* Accessing the privileged only array will now cause a fault. Uncomment + the following line to test. */ + /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ + + /* The read/write array can still be successfully read and written. */ + for( l = 0; l < mainREAD_WRITE_ALIGN_SIZE; l++ ) + { + cReadWriteArray[ l ] = 'a'; + if( cReadWriteArray[ l ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + apparent (no output will be displayed). */ + prvDeleteMe(); + } + } + + /* But attempting to read or write off the end of the RAM allocated to this + task will cause a fault. Uncomment either of the following two lines to + test. */ + /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ + /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ + + /* The read only array can be successfully read... */ + for( l = 0; l < mainREAD_ONLY_ALIGN_SIZE; l++ ) + { + cTemp = cReadOnlyArray[ l ]; + } + + /* ...but cannot be written. Uncomment the following line to test. */ + /* cReadOnlyArray[ 0 ] = 'a'; */ + + /* Writing to the first and last locations in the stack array should not + cause a protection fault. Note that doing this will cause the kernel to + detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than + 1. */ + xCheckTaskStack[ 0 ] = 0; + xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; + + /* Writing off either end of the stack array should cause a protection + fault, uncomment either of the following two lines to test. */ + /* xCheckTaskStack[ -1 ] = 0; */ + /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ + + ( void ) cTemp; +} +/*-----------------------------------------------------------*/ + +static void prvRegTest1Task( void *pvParameters ) +{ +/* This task is created in privileged mode so can access the file scope +queue variable. Take a stack copy of this before the task is set into user +mode. Once this task is in user mode the file scope queue variable will no +longer be accessible but the stack copy will. */ +xQueueHandle xQueue = xFileScopeCheckQueue; + + /* Now the queue handle has been obtained the task can switch to user + mode. This is just one method of passing a handle into a protected + task, the other reg test task uses the task parameter instead. */ + portSWITCH_TO_USER_MODE(); + + /* First check that the parameter value is as expected. */ + if( pvParameters != ( void * ) 0x12345678 ) + { + /* Error detected. Delete the task so it stops communicating with + the check task. */ + prvDeleteMe(); + } + + + for( ;; ) + { + /* This task tests the kernel context switch mechanism by reading and + writing directly to registers - which requires the test to be written + in assembly code. */ + __asm volatile + ( + " MOV R4, #104 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */ + " MOV R5, #105 \n" + " MOV R6, #106 \n" + " MOV R8, #108 \n" + " MOV R9, #109 \n" + " MOV R10, #110 \n" + " MOV R11, #111 \n" + "reg1loop: \n" + " MOV R0, #100 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */ + " MOV R1, #101 \n" + " MOV R2, #102 \n" + " MOV R3, #103 \n" + " MOV R12, #112 \n" + " SVC #1 \n" /* Yield just to increase test coverage. */ + " CMP R0, #100 \n" /* Check all the registers still contain their expected values. */ + " BNE prvDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task. */ + " CMP R1, #101 \n" + " BNE prvDeleteMe \n" + " CMP R2, #102 \n" + " BNE prvDeleteMe \n" + " CMP R3, #103 \n" + " BNE prvDeleteMe \n" + " CMP R4, #104 \n" + " BNE prvDeleteMe \n" + " CMP R5, #105 \n" + " BNE prvDeleteMe \n" + " CMP R6, #106 \n" + " BNE prvDeleteMe \n" + " CMP R8, #108 \n" + " BNE prvDeleteMe \n" + " CMP R9, #109 \n" + " BNE prvDeleteMe \n" + " CMP R10, #110 \n" + " BNE prvDeleteMe \n" + " CMP R11, #111 \n" + " BNE prvDeleteMe \n" + " CMP R12, #112 \n" + " BNE prvDeleteMe \n" + :::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12" + ); + + /* Send mainREG_TEST_1_STILL_EXECUTING to the check task to indicate that this + task is still functioning. */ + prvSendImAlive( xQueue, mainREG_TEST_1_STILL_EXECUTING ); + + /* Go back to check all the register values again. */ + __asm volatile( " B reg1loop " ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTest2Task( void *pvParameters ) +{ +/* The queue handle is passed in as the task parameter. This is one method of +passing data into a protected task, the other reg test task uses a different +method. */ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; + + for( ;; ) + { + /* This task tests the kernel context switch mechanism by reading and + writing directly to registers - which requires the test to be written + in assembly code. */ + __asm volatile + ( + " MOV R4, #4 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */ + " MOV R5, #5 \n" + " MOV R6, #6 \n" + " MOV R8, #8 \n" /* Frame pointer is omitted as it must not be changed. */ + " MOV R9, #9 \n" + " MOV R10, 10 \n" + " MOV R11, #11 \n" + "reg2loop: \n" + " MOV R0, #13 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */ + " MOV R1, #1 \n" + " MOV R2, #2 \n" + " MOV R3, #3 \n" + " MOV R12, #12 \n" + " CMP R0, #13 \n" /* Check all the registers still contain their expected values. */ + " BNE prvDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task */ + " CMP R1, #1 \n" + " BNE prvDeleteMe \n" + " CMP R2, #2 \n" + " BNE prvDeleteMe \n" + " CMP R3, #3 \n" + " BNE prvDeleteMe \n" + " CMP R4, #4 \n" + " BNE prvDeleteMe \n" + " CMP R5, #5 \n" + " BNE prvDeleteMe \n" + " CMP R6, #6 \n" + " BNE prvDeleteMe \n" + " CMP R8, #8 \n" + " BNE prvDeleteMe \n" + " CMP R9, #9 \n" + " BNE prvDeleteMe \n" + " CMP R10, #10 \n" + " BNE prvDeleteMe \n" + " CMP R11, #11 \n" + " BNE prvDeleteMe \n" + " CMP R12, #12 \n" + " BNE prvDeleteMe \n" + :::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12" + ); + + /* Send mainREG_TEST_2_STILL_EXECUTING to the check task to indicate that this + task is still functioning. */ + prvSendImAlive( xQueue, mainREG_TEST_2_STILL_EXECUTING ); + + /* Go back to check all the register values again. */ + __asm volatile( " B reg2loop " ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +extern unsigned long __SRAM_segment_end__[]; +extern unsigned long __privileged_data_start__[]; +extern unsigned long __privileged_data_end__[]; +extern unsigned long __FLASH_segment_start__[]; +extern unsigned long __FLASH_segment_end__[]; +volatile unsigned long *pul; +volatile unsigned long ulReadData; + + /* The idle task, and therefore this function, run in Supervisor mode and + can therefore access all memory. Try reading from corners of flash and + RAM to ensure a memory fault does not occur. + + Start with the edges of the privileged data area. */ + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Next the standard SRAM area. */ + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* And the standard Flash area - the start of which is marked for + privileged access only. */ + pul = __FLASH_segment_start__; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading off the end of Flash or SRAM space should cause a fault. + Uncomment one of the following two pairs of lines to test. */ + + /* pul = __FLASH_segment_end__ + 4; + ulReadData = *pul; */ + + /* pul = __SRAM_segment_end__ + 1; + ulReadData = *pul; */ + + ( void ) ulReadData; +} +/*-----------------------------------------------------------*/ + +static void prvOldStyleUserModeTask( void *pvParameters ) +{ +extern unsigned long __privileged_data_start__[]; +extern unsigned long __privileged_data_end__[]; +extern unsigned long __SRAM_segment_end__[]; +extern unsigned long __privileged_functions_end__[]; +extern unsigned long __FLASH_segment_start__[]; +extern unsigned long __FLASH_segment_end__[]; +const volatile unsigned long *pulStandardPeripheralRegister = ( volatile unsigned long * ) 0x400FC0C4; /* PCONP */ +volatile unsigned long *pul; +volatile unsigned long ulReadData; + +/* The following lines are commented out to prevent the unused variable +compiler warnings when the tests that use the variable are also commented out. +extern unsigned long __privileged_functions_start__[]; +const volatile unsigned long *pulSystemPeripheralRegister = ( volatile unsigned long * ) 0xe000e014; */ + + ( void ) pvParameters; + + /* This task is created in User mode using the original xTaskCreate() API + function. It should have access to all Flash and RAM except that marked + as Privileged access only. Reading from the start and end of the non- + privileged RAM should not cause a problem (the privileged RAM is the first + block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + should not be a problem (the privileged Flash is the first block at the + bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Standard peripherals are accessible. */ + ulReadData = *pulStandardPeripheralRegister; + + /* System peripherals are not accessible. Uncomment the following line + to test. Also uncomment the declaration of pulSystemPeripheralRegister + at the top of this function. */ + /* ulReadData = *pulSystemPeripheralRegister; */ + + /* Reading from anywhere inside the privileged Flash or RAM should cause a + fault. This can be tested by uncommenting any of the following pairs of + lines. Also uncomment the declaration of __privileged_functions_start__ + at the top of this function. */ + + /* pul = __privileged_functions_start__; + ulReadData = *pul; */ + + /* pul = __privileged_functions_end__ - 1; + ulReadData = *pul; */ + + /* pul = __privileged_data_start__; + ulReadData = *pul; */ + + /* pul = __privileged_data_end__ - 1; + ulReadData = *pul; */ + + /* Must not just run off the end of a task function, so delete this task. + Note that because this task was created using xTaskCreate() the stack was + allocated dynamically and I have not included any code to free it again. */ + vTaskDelete( NULL ); + + ( void ) ulReadData; +} +/*-----------------------------------------------------------*/ + +static void prvOldStylePrivilegedModeTask( void *pvParameters ) +{ +extern unsigned long __privileged_data_start__[]; +extern unsigned long __privileged_data_end__[]; +extern unsigned long __SRAM_segment_end__[]; +extern unsigned long __privileged_functions_start__[]; +extern unsigned long __privileged_functions_end__[]; +extern unsigned long __FLASH_segment_start__[]; +extern unsigned long __FLASH_segment_end__[]; +volatile unsigned long *pul; +volatile unsigned long ulReadData; +const volatile unsigned long *pulSystemPeripheralRegister = ( volatile unsigned long * ) 0xe000e014; /* Systick */ +const volatile unsigned long *pulStandardPeripheralRegister = ( volatile unsigned long * ) 0x400FC0C4; /* PCONP */ + + ( void ) pvParameters; + + /* This task is created in Privileged mode using the original xTaskCreate() + API function. It should have access to all Flash and RAM including that + marked as Privileged access only. So reading from the start and end of the + non-privileged RAM should not cause a problem (the privileged RAM is the + first block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + should not be a problem (the privileged Flash is the first block at the + bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading from anywhere inside the privileged Flash or RAM should also + not be a problem. */ + pul = __privileged_functions_start__; + ulReadData = *pul; + pul = __privileged_functions_end__ - 1; + ulReadData = *pul; + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Finally, accessing both System and normal peripherals should both be + possible. */ + ulReadData = *pulSystemPeripheralRegister; + ulReadData = *pulStandardPeripheralRegister; + + /* Must not just run off the end of a task function, so delete this task. + Note that because this task was created using xTaskCreate() the stack was + allocated dynamically and I have not included any code to free it again. */ + vTaskDelete( NULL ); + + ( void ) ulReadData; +} +/*-----------------------------------------------------------*/ + +static void prvDeleteMe( void ) +{ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvSendImAlive( xQueueHandle xHandle, unsigned long ulTaskNumber ) +{ + if( xHandle != NULL ) + { + xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is + a workaround to allow the PLL to operate reliably. */ + if( DEVICE_IS_REVA2 ) + { + SysCtlLDOSet( SYSCTL_LDO_2_75V ); + } + + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static unsigned long ulCallCount; +const unsigned long ulCallsBetweenSends = 5000 / portTICK_RATE_MS; +const unsigned long ulMessage = mainPRINT_SYSTEM_STATUS; +portBASE_TYPE xDummy; + + /* If configUSE_TICK_HOOK is set to 1 then this function will get called + from each RTOS tick. It is called from the tick interrupt and therefore + will be executing in the privileged state. */ + + ulCallCount++; + + /* Is it time to print out the pass/fail message again? */ + if( ulCallCount >= ulCallsBetweenSends ) + { + ulCallCount = 0; + + /* Send a message to the check task to command it to check that all + the tasks are still running then print out the status. + + This is running in an ISR so has to use the "FromISR" version of + xQueueSend(). Because it is in an ISR it is running with privileges + so can access xFileScopeCheckQueue directly. */ + xQueueSendFromISR( xFileScopeCheckQueue, &ulMessage, &xDummy ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) +{ + /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this + function will automatically get called if a task overflows its stack. */ + ( void ) pxTask; + ( void ) pcTaskName; + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will + be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() + is called automatically when a task, queue or semaphore is created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* Just to keep the linker happy. */ +void __error__( char *pcFilename, unsigned long ulLine ) +{ + ( void ) pcFilename; + ( void ) ulLine; + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* Just to keep the linker happy. */ +int uipprintf( const char *fmt, ... ) +{ + ( void ) fmt; + return( 0 ); +} +/*-----------------------------------------------------------*/ + +void hard_fault_handler(unsigned int * hardfault_args) +{ +volatile unsigned int stacked_r0; +volatile unsigned int stacked_r1; +volatile unsigned int stacked_r2; +volatile unsigned int stacked_r3; +volatile unsigned int stacked_r12; +volatile unsigned int stacked_lr; +volatile unsigned int stacked_pc; +volatile unsigned int stacked_psr; + + stacked_r0 = ((unsigned long) hardfault_args[0]); + stacked_r1 = ((unsigned long) hardfault_args[1]); + stacked_r2 = ((unsigned long) hardfault_args[2]); + stacked_r3 = ((unsigned long) hardfault_args[3]); + + stacked_r12 = ((unsigned long) hardfault_args[4]); + stacked_lr = ((unsigned long) hardfault_args[5]); + stacked_pc = ((unsigned long) hardfault_args[6]); + stacked_psr = ((unsigned long) hardfault_args[7]); + + /* Inspect stacked_pc to locate the offending instruction. */ + for( ;; ); + + ( void ) stacked_psr; + ( void ) stacked_pc; + ( void ) stacked_lr; + ( void ) stacked_r12; + ( void ) stacked_r0; + ( void ) stacked_r1; + ( void ) stacked_r2; + ( void ) stacked_r3; +} +/*-----------------------------------------------------------*/ + +void Fault_ISR( void ) __attribute__((naked)); +void Fault_ISR( void ) +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, [r0, #24] \n" + " ldr r2, handler_address_const \n" + " bx r2 \n" + " handler_address_const: .word hard_fault_handler \n" + ); +} +/*-----------------------------------------------------------*/ + +void MPU_Fault_ISR( void ) __attribute__((naked)); +void MPU_Fault_ISR( void ) +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, [r0, #24] \n" + " ldr r2, handler_address_const \n" + " bx r2 \n" + " handler2_address_const: .word hard_fault_handler \n" + ); +} +/*-----------------------------------------------------------*/ \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/thumb_crt0.s b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/thumb_crt0.s new file mode 100644 index 0000000..10fc4cd --- /dev/null +++ b/third_party/FreeRTOS/Demo/CORTEX_MPU_LM3Sxxxx_Rowley/thumb_crt0.s @@ -0,0 +1,233 @@ +/***************************************************************************** + * Copyright (c) 2009 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions + * ------------------------ + * APP_ENTRY_POINT + * + * Defines the application entry point function, if undefined this setting + * defaults to "main". + * + * USE_PROCESS_STACK + * + * If defined, thread mode will be configured to use the process stack if + * the size of the process stack is greater than zero bytes in length. + * + * INITIALIZE_STACK + * + * If defined, the contents of the stack will be initialized to a the + * value 0xCC. + * + * FULL_LIBRARY + * + * If defined then + * - argc, argv are setup by the debug_getargs. + * - the exit symbol is defined and executes on return from main. + * - the exit symbol calls destructors, atexit functions and then debug_exit. + * + * If not defined then + * - argc and argv are zero. + * - no exit symbol, code loops on return from main. + *****************************************************************************/ + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + + .global _start + .syntax unified + .extern APP_ENTRY_POINT +#ifdef FULL_LIBRARY + .global exit +#endif + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + +_start: +#ifdef __RAM_BUILD + ldr r1, =__stack_end__ + mov sp, r1 +#endif +#ifdef INITIALIZE_STACK + mov r2, #0xCC + ldr r0, =__stack_start__ +#ifndef __RAM_BUILD + mov r1, sp +#endif + bl memory_set +#endif + +#ifdef USE_PROCESS_STACK + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f + msr psp, r1 + mov r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + mov r2, #0xCC + bl memory_set +#endif +1: +#endif + /* Copy initialised memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl memory_set + + /* Zero the privileged data. */ + ldr r0, =__privileged_data_start__ + ldr r1, =__privileged_data_end__ + mov r2, #0 + bl memory_set + + /* Initialise the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + mov r0, #0 + mov lr, r0 + mov r12, sp + +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + mov r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + mov r0, #0 + mov r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + +#ifdef FULL_LIBRARY + .thumb_func +exit: + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + add r0, r0, #1 + b memory_set +1: + bx lr + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/00index_e.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/00index_e.html new file mode 100644 index 0000000..478093c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/00index_e.html @@ -0,0 +1,101 @@ + + + + + + + +ELM - FAT File System Module + + + +

FAT File System Module

+
+ +
+layer +

FatFs is a generic FAT file system module for small embedded systems. The FatFs is written in compliance with ANSI C and completely separated from the disk I/O layer. Therefore it is independent of hardware architecture. It can be incorporated into low cost microcontrollers, such as AVR, 8051, PIC, ARM, Z80 and etc..., without any change. Petit FatFs module is also available here.

+ +

Features

+
    +
  • Windows compatible FAT12/16/32 file system.
    • +
  • Platform independent. Easy to port.
    • +
  • Very small footprint for code and work area.
    • +
  • Various configuration options: +
      +
    • Multiple volumes (physical drives and partitions).
      • +
    • Multiple OEM code pages including DBCS.
      • +
    • Long file name (LFN) support in OEM code or Unicode.
      • +
    • RTOS support.
      • +
    • Multiple sector size support.
      • +
    • Read-only, minimized API, I/O buffer and etc...
      • +
    +
    • +
+
+ + +
+

Application Interface

+

FatFs module provides following functions to access the FAT volumes.

+ +
+ + +
+

Disk I/O Interface

+

Since the FatFs module is completely separated from disk I/O layer, it requires following functions to lower layer to read/write the physical disk and to get current time. The low level disk I/O module is not a part of FatFs module so that it must be provided by user. The sample drivers are also available in the resources.

+ +
+ + +
+

Resources

+

The FatFs module is a free software opened for education, research and development. You can use, modify and/or republish it for personal, non-profit use or commercial products without any restriction under your responsibility.

+ +
+ + + + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/00index_j.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/00index_j.html new file mode 100644 index 0000000..ea8e25c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/00index_j.html @@ -0,0 +1,102 @@ + + + + + + + +ELM - ”Ä—pFATƒtƒ@ƒCƒ‹ƒVƒXƒeƒ€Eƒ‚ƒWƒ…[ƒ‹ + + + +

FATƒtƒ@ƒCƒ‹ƒVƒXƒeƒ€Eƒ‚ƒWƒ…[ƒ‹

+
+ +
+layer +

FatFs‚ͬ‹K–Í‚È‘g‚Ýž‚݃VƒXƒeƒ€Œü‚¯‚̔ėpFATƒtƒ@ƒCƒ‹ƒVƒXƒeƒ€Eƒ‚ƒWƒ…[ƒ‹‚Å‚·BANSI C€‹’‚Ńn[ƒhƒEƒFƒAEƒA[ƒLƒeƒNƒ`ƒƒ‚ɂ͈ˑ¶‚µ‚È‚¢‚Ì‚ÅA•K—v‚ȃ[ƒNEƒGƒŠƒA‚ªŠm•Û‚Å‚«‚ê‚ÎA8051, PIC, AVR, SH, Z80, H8, ARM‚ȂLjÀ‰¿‚ȃ}ƒCƒRƒ“‚Å‚àŽg—p‰Â”\‚Å‚·BFatFs‚ðƒVƒ…ƒŠƒ“ƒN‚µ‚½‚Õ‚¿FatFs‚à‚ ‚è‚Ü‚·B

+

FatFsƒ‚ƒWƒ…[ƒ‹‚Ì“Á’¥

+
    +
  • WindowsŒÝŠ· FAT12/16/32ƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€
    • +
  • ƒvƒ‰ƒbƒgƒtƒH[ƒ€”ñˆË‘¶
    • +
  • ƒRƒ“ƒpƒNƒg‚ȃR[ƒhEƒTƒCƒY‚ÆRAMŽg—p—Ê
    • +
  • ‘½‚­‚Ì\¬ƒIƒvƒVƒ‡ƒ“: +
      +
    • •¡”‚̃{ƒŠƒ…[ƒ€(•¨—ƒhƒ‰ƒCƒuE‹æ‰æ)
      • +
    • DBCS‚ðŠÜ‚Þ•¡”‚ÌOEMƒR[ƒhEƒy[ƒW
      • +
    • ’·‚¢ƒtƒ@ƒCƒ‹–¼(LFN)‘Ήž (Unicode API‚à‘I‘ð‰Â)
      • +
    • ƒ}ƒ‹ƒ`ƒ^ƒXƒN‘Ήž
      • +
    • ƒ}ƒ‹ƒ`EƒZƒNƒ^EƒTƒCƒY‘Ήž
      • +
    • ƒŠ[ƒhEƒIƒ“ƒŠ[Aˆê•”API‚ÌíœAƒoƒbƒtƒ@\¬A‚»‚Ì‘¼c
      • +
    +
    • +
+
+ + +
+

ãˆÊƒŒƒCƒ„I/F

+

FatFsƒ‚ƒWƒ…[ƒ‹‚ÍAŽŸ‚̃tƒ@ƒCƒ‹‘€ìŠÖ”‚ð’ñ‹Ÿ‚µ‚Ä‚¢‚Ü‚·B

+
    +
  • f_mount - ƒ[ƒNƒGƒŠƒA‚Ì“o˜^Eíœ
    • +
  • f_open - ƒtƒ@ƒCƒ‹‚̃I[ƒvƒ“Eì¬
    • +
  • f_close - ƒtƒ@ƒCƒ‹‚̃Nƒ[ƒY
    • +
  • f_read - ƒtƒ@ƒCƒ‹‚Ì“Ç‚Ýž‚Ý
    • +
  • f_write - ƒtƒ@ƒCƒ‹‚Ì‘‚«ž‚Ý
    • +
  • f_lseek - R/Wƒ|ƒCƒ“ƒ^‚̈ړ®, ƒtƒ@ƒCƒ‹EƒTƒCƒY‚ÌŠg’£
    • +
  • f_truncate - ƒtƒ@ƒCƒ‹EƒTƒCƒY‚ÌØ‚è‹l‚ß
    • +
  • f_sync - ƒLƒƒƒbƒVƒ…‚³‚ꂽƒf[ƒ^‚̃tƒ‰ƒbƒVƒ…
    • +
  • f_opendir - ƒfƒBƒŒƒNƒgƒŠ‚̃I[ƒvƒ“
    • +
  • f_readdir - ƒfƒBƒŒƒNƒgƒŠ‚Ì“Ç‚Ýo‚µ
    • +
  • f_getfree - ƒfƒBƒXƒN‹ó‚«—̈æ‚̎擾
    • +
  • f_stat - ƒtƒ@ƒCƒ‹EƒXƒe[ƒ^ƒX‚̎擾
    • +
  • f_mkdir - ƒfƒBƒŒƒNƒgƒŠ‚Ìì¬
    • +
  • f_unlink - ƒtƒ@ƒCƒ‹/ƒfƒBƒŒƒNƒgƒŠ‚Ìíœ
    • +
  • f_chmod - ƒtƒ@ƒCƒ‹/ƒfƒBƒŒƒNƒgƒŠ‚Ì‘®«‚Ì•ÏX
    • +
  • f_utime - ƒtƒ@ƒCƒ‹/ƒfƒBƒŒƒNƒgƒŠ‚̃^ƒCƒ€ƒXƒ^ƒ“ƒv‚Ì•ÏX
    • +
  • f_rename - ƒtƒ@ƒCƒ‹/ƒfƒBƒŒƒNƒgƒŠ‚Ì–¼‘O•ÏXEˆÚ“®
    • +
  • f_mkfs - ƒfƒBƒXƒN‚̃tƒH[ƒ}ƒbƒg
    • +
  • f_chdir - ƒJƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚Ì•ÏX
    • +
  • f_chdrive - ƒJƒŒƒ“ƒgEƒhƒ‰ƒCƒu‚Ì•ÏX
    • +
  • f_forward - ƒtƒ@ƒCƒ‹Eƒf[ƒ^‚ðƒXƒgƒŠ[ƒ€ŠÖ”‚É’¼Ú“]‘—‚·‚é
    • +
  • f_gets - •¶Žš—ñ‚Ì“Ç‚Ýž‚Ý
    • +
  • f_putc - •¶Žš‚Ì‘‚«ž‚Ý
    • +
  • f_puts - •¶Žš—ñ‚Ì‘‚«ž‚Ý
    • +
  • f_printf - ‘Ž®‰»•¶Žš—ñ‚Ì‘‚«ž‚Ý
    • +
+
+ + +
+

‰ºˆÊƒŒƒCƒ„I/F

+

FatFsƒ‚ƒWƒ…[ƒ‹‚ÍA•¨—ƒhƒ‰ƒCƒu“™‚ւ̃AƒNƒZƒX‚Ì‚½‚ßA‰ºˆÊƒŒƒCƒ„‚ÉŽŸ‚̃Cƒ“ƒ^[ƒtƒF[ƒX‚ð—v‹‚µ‚Ü‚·B‚»‚ꂼ‚ê‚Ì‹L˜^ƒƒfƒBƒA‚ɑΉž‚µ‚½ƒfƒBƒXƒNI/Oƒ‚ƒWƒ…[ƒ‹‚ÍAƒ†[ƒU‚É‚æ‚Á‚Ä—pˆÓ‚³‚ê‚é•K—v‚ª‚ ‚è‚Ü‚·BŽ‘—¿‚Ƀhƒ‰ƒCƒo‚ðŠÜ‚ÞƒTƒ“ƒvƒ‹EƒvƒƒWƒFƒNƒg‚ ‚èB

+
    +
  • disk_initialize - ƒfƒBƒXƒNEƒhƒ‰ƒCƒu‚̉Šú‰»
    • +
  • disk_status - ƒfƒBƒXƒNEƒhƒ‰ƒCƒu‚Ìó‘Ԏ擾
    • +
  • disk_read - ƒfƒBƒXƒN‚©‚ç‚Ì“Ç‚Ýž‚Ý
    • +
  • disk_write - ƒfƒBƒXƒN‚Ö‚Ì‘‚«ž‚Ý
    • +
  • disk_ioctl - ‚»‚Ì‘¼‚̃hƒ‰ƒCƒu§Œä
    • +
  • get_fattime - “ú•tEŽž‚̎擾
    • +
+
+ + +
+

Ž‘—¿

+

FatFsƒ‚ƒWƒ…[ƒ‹‚̓tƒŠ[Eƒ\ƒtƒgƒEƒFƒA‚Æ‚µ‚Ä‹³ˆçEŒ¤‹†EŠJ”­—p‚ÉŒöŠJ‚µ‚Ä‚¢‚Ü‚·B‚ǂ̂悤‚È—˜—p–Ú“IiŒÂlE”ñ¤—pE¤—pj‚Å‚àŽg—pE‰ü•ÏE”z•z‚ɂ‚¢‚Ĉê؂̧ŒÀ‚Í‚ ‚è‚Ü‚¹‚ñ‚ªA‘S‚Ä—˜—pŽÒ‚ÌÓ”C‚̉º‚Å‚Ì—˜—p‚Æ‚µ‚Ü‚·B

+ +
+ + +
+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/css_e.css b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/css_e.css new file mode 100644 index 0000000..b462e31 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/css_e.css @@ -0,0 +1,56 @@ +* {margin: 0; padding: 0; border-width: 0;} +body {margin: 8px; background-color: #e0ffff; font-color: black; font-family: serif; line-height: 133%; max-width: 1024px;} +a:link {color: blue;} +a:visited {color: darkmagenta;} +a:hover {background-color: #a0ffff;} +a:active {color: darkmagenta; position: relative; top: 1px; left: 1px;} +abbr {border-width: 1px;} + +p {margin: 0 0 0.3em 1em;} +em {font-style: normal; font-weight: bold; margin: 0 0.1em;} +pre em {font-style: italic; font-weight: normal;} +strong {} +pre {margin: 0.5em 1em; padding: 0.5em; line-height: 1.2em; background-color: white;} +tt {margin: 0 0.2em;} +ol {margin: 0 2.5em;} +ul {margin: 0 2em;} +dl {margin: 0 1em;} +dt {font-family: monospace;} +dl.par dt {margin: 0.5em 0 0 0 ; font-style: italic; } +dl.ret dt {margin: 0.5em 0 0 0 ; font-weight: bold;} +dd {margin: 0 2em;} +hr {border-width: 1px; margin: 1em;} +div.abst {font-family: sans-serif;} +div.para {clear: both; font-family: serif;} +.equ {text-indent: 0; margin: 1em 2em 1em;} +.indent {margin-left: 2em;} +.rset {float: right; margin: 0 0 0.5em 0.5em;} +.lset {float: left; margin: 0 0.5em 0.5em 0.5em;} +ul.flat li {list-style-type: none; margin: 0;} +a.imglnk img {border: 1px solid;} +.iequ {white-space: nowrap; font-weight: bold;} +.clr {clear: both;} +.it {font-style: italic;} +.mfd {font-size: 0.7em; padding: 0 1px; border: 1px solid; white-space : nowrap} + +h1 {line-height: 1em; font-size: 2em; font-family: sans-serif; padding: 0.3em 0 0.3em;} +p.hdd {float: right; text-align: right; margin-top: 0.5em;} +hr.hds {clear: both; margin-bottom: 1em;} + +h2 {font-size: 1.5em; font-family: sans-serif; margin: 0 0 0.5em;} +h3 {font-size: 1.5em; font-family: sans-serif; margin: 1.5em 0 0.5em;} +h4 {font-size: 1.2em; font-family: sans-serif; margin: 1em 0 0.2em;} +h5 {font-size: 1em; font-family: sans-serif; margin: 0.5em 0 0em;} +small {font-size: 80%;} +.indent {margin-left: 2em;} + +/* Tables */ +table {margin: 0.5em 1em; border-collapse: collapse; border-style: solid; border-width: 2px; border-color: black; } +th {background-color: white; border-style: solid; border-width: 1px 1px 2px; border-color: black; padding: 0 3px; vertical-align: top; white-space: nowrap;} +td {background-color: white; border-style: solid; border-width: 1px; border-color: black; padding: 0 3px; vertical-align: top; line-height: 1.3em;} +table.lst td:first-child {font-family: monospace;} +table.lst2 td {font-family: monospace;} +table caption {font-family: sans-serif; font-weight: bold;} +tr.lst3 td { border-width: 2px 1px 1px; } + +p.foot {clear: both; text-indent: 0; margin: 1em 0.5em 1em;} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/css_j.css b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/css_j.css new file mode 100644 index 0000000..7a73e5a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/css_j.css @@ -0,0 +1,59 @@ +@charset "Shift_JIS"; +/* Common style sheet for Tech Notes */ + +* {margin: 0; padding: 0; border-width: 0;} +body {margin: 8px; background-color: #e0ffff; font-color: black; font-family:"‚l‚r ‚o–¾’©", serif; line-height: 150%; letter-spacing: 1px; max-width: 1024px;} +a:link {color: blue;} +a:visited {color: darkmagenta;} +a:hover {background-color: #a0ffff;} +a:active {color: darkmagenta; position: relative; top: 1px; left: 1px;} +abbr {border-width: 1px;} + +p {text-indent: 1em; margin: 0 0 0.3em 0.5em;} +em {font-style: normal; font-weight: bold; margin: 0 0.1em;} +pre em {font-style: italic; font-weight: normal;} +strong {} +pre {margin: 0.5em 1em; padding: 0.5em; line-height: 1.2em; letter-spacing: 0; background-color: white;} +tt {margin: 0 0.2em; letter-spacing: 0;} +ol {margin: 0 2.5em;} +ul {margin: 0 2em;} +dl {margin: 0 1em;} +dt {font-family: monospace;} +dl.par dt {margin: 0.5em 0 0 0 ; font-style: italic; letter-spacing: 0;} +dl.ret dt {margin: 0.5em 0 0 0 ; font-family: monospace; letter-spacing: 0; font-weight: bold;} +dd {margin: 0 2em;} +hr {border-width: 1px; margin: 1em;} +div.abst {font-family: "‚l‚r ‚oƒSƒVƒbƒN",sans-serif;} +div.para {clear: both; font-family: "‚l‚r ‚o–¾’©",serif;} +.equ {text-indent: 0; margin: 1em 2em 1em;} +.indent {margin-left: 2em;} +.rset {float: right; margin: 0 0 0.5em 0.5em;} +.lset {float: left; margin: 0 0.5em 0.5em 0.5em;} +ul.flat li {list-style-type: none; margin: 0;} +a.imglnk img {border: 1px solid;} +.iequ {white-space: nowrap; font-weight: bold;} +.clr {clear: both;} +.it {font-style: italic;} +.mfd {font-size: 0.7em; padding: 0 1px; border: 1px solid; white-space : nowrap} + +h1 {line-height: 1em; font-size: 2em; font-family: sans-serif; padding: 0.3em 0 0.3em;} +p.hdd {float: right; text-align: right; margin-top: 0.5em;} +hr.hds {clear: both; margin-bottom: 1em;} + +h2 {font-size: 1.5em; font-family: "‚l‚r ‚oƒSƒVƒbƒN",sans-serif; margin: 0 0 0.5em;} +h3 {font-size: 1.5em; font-family: "‚l‚r ‚oƒSƒVƒbƒN",sans-serif; margin: 1.5em 0 0.5em;} +h4 {font-size: 1.2em; font-family: "‚l‚r ‚oƒSƒVƒbƒN",sans-serif; margin: 1em 0 0.2em;} +h5 {font-size: 1em; font-family: "‚l‚r ‚oƒSƒVƒbƒN",sans-serif; margin: 0.5em 0 0em;} +small {font-size: 80%;} +.indent {margin-left: 2em;} + +/* Tables */ +table {margin: 0.5em 1em; border-collapse: collapse; border-style: solid; border-width: 2px; border-color: black; letter-spacing: 0;} +th {background-color: white; border-style: solid; border-width: 1px 1px 2px; border-color: black; padding: 0 3px; vertical-align: top;} +td {background-color: white; border-style: solid; border-width: 1px; border-color: black; padding: 0 3px; vertical-align: top; line-height: 1.3em;} +table.lst td:first-child {font-family: monospace; white-space: nowrap;} +table.lst2 td {font-family: monospace; white-space: nowrap;} +table caption {font-family: sans-serif; font-weight: bold;} +tr.lst3 td { border-width: 2px 1px 1px; } + +p.foot {clear: both; text-indent: 0; margin: 1em 0.5em 1em;} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/appnote.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/appnote.html new file mode 100644 index 0000000..ff37d64 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/appnote.html @@ -0,0 +1,189 @@ + + + + + + + +FatFs Module Application Note + + + +

FatFs Module Application Note

+
+ +
+

Considerations on porting to various platform

+

The FatFs module is assuming following terms on portability.

+
    +
  • ANSI C
    +The FatFs module is a middleware that written in ANSI C. There is no platform dependence, so long as the compiler is in compliance with ANSI C.
    • +
  • Size of integer types
    +The FatFs module assumes that size of char/short/long are 8/16/32-bit and int is 16 or 32 bit. These correspondence are defined in integer.h. This will not be a problem on most compilers. When any conflict with existing definitions is occured, you must resolve it with care.
    • +
+
+ +
+

Memory Usage (R0.07e)

+
LocalRemoteStateRetransmissionsTimerFlags
+ + + + + + + + + + +
AVRH8/300HPICTLCS-870/CV850ESSH2ARM7TDMIx86
CompilerWinAVR(gcc)CH38C30(gcc)CC870CCA850SHCWinARM(gcc)VC6
_WORD_ACCESS10011001
text (Full, R/W)1219410559109241522976868727105647342
text (Min, R/W)79886903710899604884565165444764
text (Full, R/O)55324753502067603462377746243316
text (Min, R/O)40403631373650832556290732842510
bssD*2 + 2D*4 + 2D*2 + 2D*2 + 2D*4 + 2D*4 + 2D*4 + 2D*4 + 2
Work area
(_FS_TINY == 0)		D*560 +
F*544		D*560 +
F*550		D*560 +
F*544		D*560 +
F*550		D*560 +
F*550		D*560 +
F*550		D*560 +
F*550
Work area
(_FS_TINY == 1)		D*560 +
F*32		D*560 +
F*36		D*560 +
F*32		D*560 +
F*32		D*560 +
F*36		D*560 +
F*36		D*560 +
F*36		D*560 +
F*36
+

These are the memory usage on some target systems with following condition. The memory sizes are in unit of byte, D means number of volumes and F means number of open files. All samples are optimezed in code size.

+
+_FS_READONLY     0 (R/W), 1 (R/O)
+_FS_MINIMIZE     0 (Full function), 3 (Minimized function)
+_USE_STRFUNC     0 (Disable string functions)
+_USE_MKFS        0 (Disable f_mkfs function)
+_USE_FORWARD     0 (Disable f_forward function)
+_CODE_PAGE       932 (Japanese Shift-JIS)
+_USE_LFN         0 (Disable LFN)
+_LFN_UNICODE     0 (Disable Unicode API)
+_MAX_SS          512 (Single sector size)
+_FS_RPATH        0 (Disable relative path)
+_MULTI_PARTITION 0 (Single partition per drive)
+_FS_REENTRANT    0 (Disable reentrancy)
+
+ + +
+

Module Size Reduction

+

Follwing table shows which function is removed by configuration options for the module size reduction.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function_FS_MINIMIZE_FS_READONLY_USE_STRFUNC_FS_RPATH_USE_MKFS_USE_FORWARD
12310000
f_mount
f_open
f_close
f_read
f_writex
f_syncx
f_lseekx
f_opendirxx
f_readdirxx
f_statxxx
f_getfreexxxx
f_truncatexxxx
f_unlinkxxxx
f_mkdirxxxx
f_chmodxxxx
f_utimexxxx
f_renamexxxx
f_chdirx
f_chdrivex
f_mkfsxx
f_forwardx
f_putcxx
f_putsxx
f_printfxx
f_getsx
+
+ +
+

Long File Name

+

The FatFs module supports long file name (LFN) from revision 0.07. The two different file names, SFN and LFN, of a file is transparent in the file functions except for f_readdir function. To enable LFN feature, set _USE_LFN to 1 or 2, and add a Unicode code conversion function ff_convert and ff_wtoupper to the project. This function is available in cc*.c. The LFN feature requiers a certain working buffer in addition. The buffer size can be configured by _MAX_LFN corresponding to the available memory size. The size of long file name will reach up to 255 characters so that the _MAX_LFN should be set to 255 for full featured LFN operation. When the size of working buffer is insufficient for the given file name, the file function will fail with FR_INVALID_NAME. When enable the LFN feature with re-entrant feature, _USE_LFN must be set to 2. In this case, the file funciton allocates the working buffer on the stack. The working buffer occupies (_MAX_LFN + 1) * 2 bytes so that the caller's stack must be a sufficient size considering the working buffer.

+ + + + + + + + +
LFN cfg on ARM7
Code pageROM size [bytes]
SBCS+3721
932(Shift-JIS)+62609
936(GBK)+177797
949(Korean)+139857
950(Big5)+111497
+

When the LFN feature is enabled, the module size will be increased depends on the selected code page. Right table shows the difference in module size when LFN is enabled with some code pages. We are the Japanese, Chinese and Korean have tens of thousands of characters. Unfortunately, it requires a huge OEM-Unicode bidirectional conversion table and the module size will be drastically increased that shown in the table. As the result, the FatFs with LFN will not able to be implemented to most 8-bit microcontrollers including AVR. This is the reason why I had not been interested in implementing the LFN feature for a long time :-)

+

Note that the LFN feature on the FAT file system is a patent of Microsoft Corporation. When enable it on the commercial products, a license from Microsoft may be required depends on the final destination.

+
+ +
+

Re-entrancy

+

The file operations to the different volume can always work simultaneously regardless of re-entrancy setting. The re-entrancy to the same volume can be enabled with _FS_REENTRANT option. In this case, also the OS dependent synchronization object control functions, ff_cre_syncobj, ff_del_syncobj, ff_req_grant and ff_rel_grant must be added to the project. The sample code with documentation is available in syncobj.c.

+

When a file function is called while the volume is in use by any other task, the access is blocked until the task leaves file function. If wait time exceeded a period defined by _TIMEOUT, the file function will abort with FR_TIMEOUT. The timeout feature might not be supported on some RTOS.

+

There is an exception on f_mount and f_mkfs function. These functions are not re-entrant to the same volume. When use these functions, all other task must close the corresponding file on the volume and avoid to access the volume.

+

Note that this section describes on the re-entrancy of the FatFs module itself. There is no assumtion on the re-entrancy of low level disk I/O module.

+
+ +
+

Duplicated file access

+

FatFs module does not support the shareing controls of duplicated file access. It is permitted when open method to the file is only read mode. The duplicated open in write mode to a file is always prohibited and open file must not be renamed, deleted, otherwise the FAT structure on the volume can be collapted.

+
+ +
+

Performance effective file access

+

For good performance on reading/writing files on the small embedded system, application programmer should consider what process is done in the FatFs module. The file data on the disk is transferred in following sequence by f_read function.

+

Figure 1. Sector miss-aligned read (short)
+ +

+

Figure 2. Sector miss-aligned read (long)
+ +

+

Figure 3. Sector aligned read
+ +

+

The file I/O buffer means a sector buffer to read/write a partial data on the sector. The sector buffer is either file private sector buffer on each file object or shared sector buffer on the file system object. The buffer configuration option _FS_TINY determins which sector buffer is used for the file data transfer. When tiny buffer (1) is selected, data memory consumption is reduced 512 bytes each file object. In this case, FatFs module uses only a sector buffer on the file system object for file data transfer and FAT/directory access. The disadvantage of the tiny buffer configuration is: the FAT data cached in the sector buffer will be lost by file data transfer and it must be reloaded at every cluster boundary. However it will be suitable for most application from view point of the decent performance and low memory comsumption.

+

Figure 1 shows that partial sector data is transferred via the file I/O buffer. On long data transfer shown in Figure 2, middle of transfer data that covers one or more sector is transferred to application buffer directly. Figure 3 shows that the case of entier transfer data is aligned to the sector boundary. In this case, file I/O buffer is not used. On the direct transfer, the maximum extent of sectors are read with disk_read function at a time but the multi sector transfer never across the cluster boundary even if it is contiguous.

+

Therefore taking effort to sector aligned read/write accesss avoids buffered data transfer and the read/write performance will be improved. Besides the effect, cached FAT data will not be flushed by file data transfer on the tiny configuration so that it can achieve same performance as non tiny configuration with small memory footprint.

+
+ +
+

Critical Section

+

When write operation to the FAT file system is interrupted due to any accidental failure, such as sudden blackout, incorrect disk removal and unrecoverable disk error, the FAT structure can be collapted. Following images shows the critical section on the FatFs application.

+
+Figure 4. Long critical section
+fig.4 +
+
+Figure 5. Minimized critical section
+fig.5 +
+
+

An interruption in the red section can cause a cross link; as a result, the file/directory being changed may be lost. There is one or more possibility listed below when an interruption in the yellow section is occured.

+
    +
  • File data being rewrited is collapted.
    • +
  • A file being appended returns initial state.
    • +
  • A file created as new is gone.
    • +
  • A file created as new or in overwritten remains with length of zero.
    • +
  • Efficiency of disk use gets worse due to lost chain.
    • +
+

Each case does not affect the files that not in write mode open. To minimize risk of data loss, the critical section can be minimized like shown in Figure 5 by minimizing the time that file is opened in write mode or using f_sync function properly.

+
+ +
+

Unicode API

+

FatFs supports OEM code set on the API in default but FatFs can also switch the code set to Unicode. For more information, refer to the description in the file name.

+
+ + +
+

About FatFs License

+

This is a copy of the FatFs license document that included in the source codes.

+
/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.07e                    (C)ChaN, 2009
+/-----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following trems.
+/
+/  Copyright (C) 2009, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+

Therefore FatFs license is one of the BSD-style license but there is a big difference. Because FatFs is for embedded projects, the conditions for redistributions in binary form, such as embedded code, hex file and binary library, are not specified to increase its usability. The documentation of the distributions need not include about FatFs and its license document, and it may also. Of course FatFs is compatible with the projects under GNU GPL. When redistribute it with any modification, the license can also be changed to GNU GPL or BSD license.

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chdir.html new file mode 100644 index 0000000..b28c73a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chdir.html @@ -0,0 +1,87 @@ + + + + + + + +FatFs - f_chdir + + + + +
+

f_chdir

+

The f_chdir function changes the current directory of a drive.

+
+FRESULT f_chdir (
+  const XCHAR* Path /* Pointer to the path name */
+);
+
+
+ +
+

Parameters

+
+
Path
+
Pointer to the null-terminated string that specifies a directory to go.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The path name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_chdir function changes the current directory of the logical drive. The current directory of a drive is initialized to the root directory when the drive is auto-mounted. Note that the current directory is retained in the each file system object so that it also affects other tasks that using the drive.

+
+ + +
+

QuickInfo

+

Available when _FS_RPATH == 1.

+
+ + +
+

Example

+
+    // Change current direcoty of the current drive (dir1 under root dir)
+    f_chdir("/dir1");
+
+    // Change current direcoty of drive 2 (parent dir)
+    f_chdir("2:..");
+
+
+ +
+

See Also

+

f_chdrive

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chdrive.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chdrive.html new file mode 100644 index 0000000..c3b599e --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chdrive.html @@ -0,0 +1,61 @@ + + + + + + + +FatFs - f_chdrive + + + + +
+

f_chdrive

+

The f_chdrive function changes the current drive.

+
+FRESULT f_chdrive (
+  BYTE Drive /* Logical drive number */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the logical drive number to be set as the current drive.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
+
+ + +
+

Description

+

The f_chdrive function changes the current drive. The initial value of the current drive number is 0. Note that the current drive is retained in a static variable so that it also affects other tasks that using the file functions.

+
+ +
+

QuickInfo

+

Available when _FS_RPATH == 1.

+
+ + +
+

See Also

+

f_chdir

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chmod.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chmod.html new file mode 100644 index 0000000..d72e201 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/chmod.html @@ -0,0 +1,97 @@ + + + + + + + +FatFs - f_chmod + + + + +
+

f_chmod

+

The f_chmod function changes the attribute of a file or directory.

+
+FRESULT f_chmod (
+  const XCHAR* FileName, /* Pointer to the file or directory */
+  BYTE Attribute,        /* Attribute flags */
+  BYTE AttributeMask     /* Attribute masks */
+);
+
+
+ +
+

Parameters

+
+
FileName
+
Pointer to the null-terminated string that specifies a file or directory to be changed
+
Attribute
+
Attribute flags to be set in one or more combination of the following flags. The specified flags are set and others are cleard.
+ + + + + + +
AttributeDescription
AM_RDORead only
AM_ARCArchive
AM_SYSSystem
AM_HIDHidden
+
+
AttributeMask
+
Attribute mask that specifies which attribute is changed. The specified aattributes are set or cleard.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_FILE
+
Could not find the file.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The file name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_WRITE_PROTECTED
+
The medium is write protected.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_chmod function changes the attribute of a file or directory.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    // Set read-only flag, clear archive flag and others are retained.
+    f_chmod("file.txt", AR_RDO, AR_RDO | AR_ARC);
+
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/close.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/close.html new file mode 100644 index 0000000..e69fece --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/close.html @@ -0,0 +1,68 @@ + + + + + + + +FatFs - f_close + + + + +
+

f_close

+

The f_close function closes an open file.

+
+FRESULT f_close (
+  FIL* FileObject     /* Pointer to the file object structure */
+);
+
+
+ +
+

Parameter

+
+
FileObject
+
Pointer to the open file object structure to be closed.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The file object has been closed successfuly.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
+ + +
+

Description

+

The f_close function closes an open file object. If any data has been written to the file, the cached information of the file is written back to the disk. After the function succeeded, the file object is no longer valid and it can be discarded. If the file object has been opened in read-only mode, it may be discarded without closing process by this function.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_read, f_write, f_sync, FIL, FATFS

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dinit.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dinit.html new file mode 100644 index 0000000..5bf3870 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dinit.html @@ -0,0 +1,45 @@ + + + + + + + +FatFs - disk_initialize + + + + +
+

disk_initialize

+

The disk_initialize function initializes the disk drive.

+
+DSTATUS disk_initialize (
+  BYTE Drive           /* Physical drive number */
+);
+
+
+ +
+

Parameter

+
+
Drive
+
Specifies the physical drive number to initialize.
+
+
+ + +
+

Return Values

+

This function returns a disk status as the result. For details of the disk status, refer to the disk_status function.

+
+ +
+

Description

+

The disk_initialize function initializes a physical drive. When the function succeeded, STA_NOINIT flag in the return value is cleard.

+

This function is called from volume mount process in the FatFs module to manage the media change. Application program must not call this function while FatFs module is active, or FAT structure on the volume can be collapted. To re-initialize the file system, use f_mount function.

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dioctl.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dioctl.html new file mode 100644 index 0000000..cdd4f8c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dioctl.html @@ -0,0 +1,68 @@ + + + + + + + +FatFs - disk_ioctl + + + + +
+

disk_ioctl

+

The disk_ioctl function cntrols device specified features and miscellaneous functions other than disk read/write.

+
+DRESULT disk_ioctl (
+  BYTE Drive,      /* Drive number */
+  BYTE Command,    /* Control command code */
+  void* Buffer     /* Data transfer buffer */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the drive number (0-9).
+
Command
+
Specifies the command code.
+
Buffer
+
Pointer to the parameter buffer depends on the command code. When it is not used, specify a NULL pointer.
+
+
+ + +
+

Return Value

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
Any error occured.
+
RES_PARERR
+
Invalid command code.
+
RES_NOTRDY
+
The disk drive has not been initialized.
+
+
+ + +
+

Description

+

The FatFs module uses only device independent commands described below. Any device dependent function is not used.

+ + + + + + +
CommandDescription
CTRL_SYNCMake sure that the disk drive has finished pending write process. When the disk I/O module has a write back cache, flush the dirty sector immediately. This command is not required in read-only configuration.

+
GET_SECTOR_SIZEReturns sector size of the drive into the WORD variable pointed by Buffer. This command is not required in single sector size configuration, _MAX_SS is 512.
GET_SECTOR_COUNTReturns total sectors on the drive into the DWORD variable pointed by Buffer. This command is used in only f_mkfs function.
GET_BLOCK_SIZEReturns erase block size of the memory array in unit of sector into the DWORD variable pointed by Buffer. When the erase block size is unknown or magnetic disk device, return 1. This command is used in only f_mkfs function.
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dread.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dread.html new file mode 100644 index 0000000..f0f6a79 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dread.html @@ -0,0 +1,58 @@ + + + + + + + +FatFs - disk_read + + + + +
+

disk_read

+

The disk_read function reads sector(s) from the disk drive.

+
+DRESULT disk_read (
+  BYTE Drive,          /* Physical drive number */
+  BYTE* Buffer,        /* Pointer to the read data buffer */
+  DWORD SectorNumber,  /* Start sector number */
+  BYTE SectorCount     /* Number of sectros to read */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the physical drive number.
+
Buffer
+
Pointer to the byte array to store the read data. The buffer size of number of bytes to be read, sector size * sector count, is required. The memory address specified by upper layer may or may not be aligned to word boundary.
+
SectorNumber
+
Specifies the start sector number in logical block address (LBA).
+
SectorCount
+
Specifies number of sectors to read. The value can be 1 to 255.
+
+
+ + +
+

Return Value

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
Any hard error occured during the read operation and could not recover it.
+
RES_PARERR
+
Invalid parameter.
+
RES_NOTRDY
+
The disk drive has not been initialized.
+
+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dstat.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dstat.html new file mode 100644 index 0000000..6b3a247 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dstat.html @@ -0,0 +1,47 @@ + + + + + + + +FatFs - disk_status + + + + +
+

disk_status

+

The disk_status function returns the current disk status.

+
+DSTATUS disk_status (
+  BYTE Drive     /* Physical drive number */
+);
+
+
+ +
+

Parameter

+
+
Drive
+
Specifies the physical drive number to be confirmed.
+
+
+ + +
+

Return Values

+

The disk status is returned in combination of following flags.

+
+
STA_NOINIT
+
Indicates that the disk drive has not been initialized. This flag is set on: system reset, disk removal and disk_initialize function failed, and cleared on: disk_initialize function succeeded.
+
STA_NODISK
+
Indicates that no medium in the drive. This is always cleared on fixed disk drive.
+
STA_PROTECTED
+
Indicates that the medium is write protected. This is always cleared on the drive that does not support write protect notch. Not valid when STA_NODISK is set.
+
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dwrite.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dwrite.html new file mode 100644 index 0000000..2fac546 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/dwrite.html @@ -0,0 +1,66 @@ + + + + + + + +FatFs - disk_write + + + + +
+

disk_write

+

The disk_write writes sector(s) to the disk.

+
+DRESULT disk_write (
+  BYTE Drive,          /* Physical drive number */
+  const BYTE* Buffer,  /* Pointer to the write data (may be non aligned) */
+  DWORD SectorNumber,  /* Sector number to write */
+  BYTE SectorCount     /* Number of sectors to write */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the physical drive number.
+
Buffer
+
Pointer to the byte array to be written. The memory address specified by upper layer may or may not be aligned to word boundary.
+
SectorNumber
+
Specifies the start sector number in logical block address (LBA).
+
SectorCount
+
Specifies the number of sectors to write. The value can be 1 to 255.
+
+
+ + +
+

Return Values

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
Any hard error occured during the write operation and could not recover it.
+
RES_WRPRT
+
The medium is write protected.
+
RES_PARERR
+
Invalid parameter.
+
RES_NOTRDY
+
The disk drive has not been initialized.
+
+
+ + +
+

Description

+

This function is not required in read only configuration.

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/fattime.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/fattime.html new file mode 100644 index 0000000..7e15797 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/fattime.html @@ -0,0 +1,50 @@ + + + + + + + +FatFs - get_fattime + + + + +
+

get_fattime

+

The get_fattime function gets current time.

+
+DWORD get_fattime (void);
+
+
+ + +
+

Return Value

+

Currnet time is returned with packed into a DWORD value. The bit field is as follows:

+
+
bit31:25
+
Year from 1980 (0..127)
+
bit24:21
+
Month (1..12)
+
bit20:16
+
Day in month(1..31)
+
bit15:11
+
Hour (0..23)
+
bit10:5
+
Minute (0..59)
+
bit4:0
+
Second / 2 (0..29)
+
+
+ + +
+

Description

+

The get_fattime function must return any valid time even if the system does not support a real time clock. If a zero is returned, the file will not have a valid time. This fucntion is not required in read only configuration.

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/filename.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/filename.html new file mode 100644 index 0000000..00b8626 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/filename.html @@ -0,0 +1,68 @@ + + + + + + + +FatFs - Path Names + + + + +
+

Format of the path names

+

The path name format on the FatFs module is similer to the filename specs of DOS/Windos as follows:

+
+ "[drive#:][/]directory/file"
+
+

The FatFs module supports long file name (LFN) and 8.3 format file name (SFN). The LFN can be used when LFN feature is enabled (_USE_LFN > 0). The differences between DOS/Windows are directory separator and logical drive number. The sub directories are separated with a / or \. The logical drive is specified in a numeral with a colon. When the drive number is omitted, it is assumed as default drive (0 or current drive). Leading/embedded spaces in the given path name are valid as a part of the name on LFN configuration but they are recognized as end of the path name on non-LFN configuration.

+

In default configuration (_FS_RPATH == 0), it does not have a concept of current directory like OS oriented file system. All objects on the volume are always specified in full path name that follows from the root directory. Dot directory names are not allowed. Heading separator is ignored and it can be exist or omitted. The default drive number is fixed to 0.

+

When relative path feature is enabled (_FS_RPATH == 1), specified path is followed from the root directory if a heading separator is exist. If not, the path is followed from the current directory set with f_chdir function. Dot names are also allowed for the directory name. The default drive number is the current drive number set with f_chdrive function.

+ + + + + + + + + + + + + +
Path name_FS_RPATH == 0_FS_RPATH == 1
file.txtA file in the root directory on the drive 0A file in the current directory on the current drive
/file.txtA file in the root directory on the drive 0A file in the root directory on the current drive
The root directory on the drive 0The current directory on the current drive
2:The root directory on the drive 2The current directory on the drive 2
2:file.txtA file in the root directory on the drive 2A file in the current directory on the drive 2
2:/The root directory on the drive 2The root directory on the drive 2
../file.txtInvalid nameA file in the parent directory
.Invalid nameThis directory
..Invalid nameParent directory of the current directory
dir1/..Invalid nameThe current directory
/..Invalid nameInvalid name (Cannot use dot names at the root directory)
+
+ +


+
+

Unicode API

+

The path names are input/output in either OEM code (SBCS/DBCS) or Unicode depends on the configuration options. The type of arguments that specifies the file names are defined as XCHAR which is an alias of char in default. The code set of the file name string is the OEM code set specifid by _CODE_PAGE. When _LFN_UNICODE is set to 1 under LFN configuration, the type of the XCHAR is switched to unsigned short (wide character) to support Unicode. In this case, the LFN feature is fully supported and the Unicode specific characters, such as âœâ˜ªâœ¡â˜¸â˜­, can also be used for the path name.

+
+ +


+
+

Correspondence between logical and physical drives

+

The FatFs module has work areas that called file system object for each volume (logical drive). In default, the logical drive is bound to the physical drive that has same drive number, and the first partition is mounted. When _MULTI_PARTITION == 1 is specified in configuration option, each individual logical drive can be bound to any physical drive/partition. In this case, a drive number resolution table must be defined as follows:

+
+Example: Logical drive 0-2 are assigned to three pri-partitions on the physical drive 0 (fixed disk)
+         Logical drive 3 is assigned to physical drive 1 (removable disk)
+
+const PARTITION Drives[] = {
+    {0, 0},     /* Logical drive 0 ==> Physical drive 0, 1st partition */
+    {0, 1},     /* Logical drive 1 ==> Physical drive 0, 2nd partition */
+    {0, 2},     /* Logical drive 2 ==> Physical drive 0, 3rd partition */
+    {1, 0}      /* Logical drive 3 ==> Physical drive 1 */
+};
+
+

There are some considerations when use _MULTI_PARTITION configuration.

+
    +
  • Only pri-partition (0-3) can be mounted.
    • +
  • When the physical drive has no partition table (SFD format), the partition number is ignored.
    • +
  • The physical drive that has two or more logical drives must be a fixed drive.
    • +
+
+ + + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/forward.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/forward.html new file mode 100644 index 0000000..581e50e --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/forward.html @@ -0,0 +1,142 @@ + + + + + + + +FatFs - f_forward + + + + +
+

f_forward

+

The f_forward function reads the file data and forward it to the data streaming device.

+
+FRESULT f_forward (
+  FIL* FileObject,                 /* File object */
+  UINT (*Func)(const BYTE*,UINT),  /* Data streaming function */
+  UINT ByteToFwd,                  /* Number of bytes to forward */
+  UINT* ByteFwd                    /* Number of bytes forwarded */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object.
+
Func
+
Pointer to the user-defined data streaming function. For details, refer to the sample code.
+
ByteToFwd
+
Number of bytes to forward in range of UINT.
+
ByteFwd
+
Pointer to the UINT variable to return number of bytes forwarded.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_DENIED
+
The function denied due to the file has been opened in non-read mode.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
+ + +
+

Description

+

The f_forward function reads the data from the file and forward it to the outgoing stream without data buffer. This is suitable for small memory system because it does not require any data buffer at application module. The file pointer of the file object increases in number of bytes forwarded. In case of *ByteFwd < ByteToFwd without error, it means the requested bytes could not be transferred due to end of file or stream goes busy during data transfer.

+
+ + +
+

QuickInfo

+

Available when _USE_FORWARD == 1 and _FS_TINY == 1.

+
+ + +
+

Example (Audio playback)

+
+/*-----------------------------------------------------------------------*/
+/* Sample code of data transfer function to be called from f_forward     */
+/*-----------------------------------------------------------------------*/
+
+UINT out_stream (   /* Returns number of bytes sent or stream status */
+    const BYTE *p,  /* Pointer to the data block to be sent */
+    UINT btf        /* >0: Transfer call (Number of bytes to be sent). 0: Sense call */
+)
+{
+    UINT cnt = 0;
+
+
+    if (btf == 0) {     /* Sense call */
+        /* Return stream status (0: Busy, 1: Ready) */
+        /* When once it returned ready to sense call, it must accept a byte at least */
+        /* at subsequent transfer call, or f_forward will fail with FR_INT_ERROR. */
+        if (FIFO_READY) cnt = 1;
+    }
+    else {              /* Transfer call */
+        do {    /* Repeat while there is any data to be sent and the stream is ready */
+            FIFO_PORT = *p++;
+            cnt++;
+        } while (cnt < btf && FIFO_READY);
+    }
+
+    return cnt;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* Sample code using f_forward function                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT play_file (
+    char *fn        /* Pointer to the audio file name to be played */
+)
+{
+    FRESULT rc;
+    FIL fil;
+    UINT dmy;
+
+    /* Open the audio file in read only mode */
+    rc = f_open(&fil, fn, FA_READ);
+
+    /* Repeat until the file pointer reaches end of the file */
+    while (rc == FR_OK && fil.fptr < fil.fsize) {
+
+        /* any other processes... */
+
+        /* Fill output stream periodicaly or on-demand */
+        rc = f_forward(&fil, out_stream, 1000, &dmy);
+    }
+
+    /* The read-only file object may be discarded without close */
+    return rc;
+}
+
+
+ + +
+

See Also

+

f_open, fgets, f_write, f_close, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/getfree.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/getfree.html new file mode 100644 index 0000000..26ca344 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/getfree.html @@ -0,0 +1,101 @@ + + + + + + + +FatFs - f_getfree + + + + +
+

f_getfree

+

The f_getfree function gets number of the free clusters.

+
+FRESULT f_getfree (
+  const XCHAR* Path,        /* Root directory of the drive */
+  DWORD* Clusters,          /* Pointer to the variable to store number of free clusters */
+  FATFS** FileSystemObject  /* Pointer to pointer to file system object */
+);
+
+
+ +
+

Parameters

+
+
Path
+
Pinter to the null-terminated string that specifies the root directory of the logical drive.
+
Clusters
+
Pointer to the DWORD variable to store number of free clusters.
+
FileSystemObject
+
Pointer to pointer that to store a pointer to the corresponding file system object.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded. The *Clusters has number of free clusters and *FileSystemObject points the file system object.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT partition on the disk.
+
+
+ + +
+

Descriptions

+

The f_getfree function gets number of free clusters on the drive. The member csize in the file system object is refrecting number of sectors per cluster, so that the free space in unit of sector can be calcurated with this. When FSInfo structure on FAT32 volume is not in sync, this function can return an incorrect free cluster count.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    FATFS *fs;
+    DWORD fre_clust, fre_sect, tot_sect;
+
+
+    /* Get drive information and free clusters */
+    res = f_getfree("/", &fre_clust, &fs);
+    if (res) die(res);
+
+    /* Get total sectors and free sectors */
+    tot_sect = (fs->max_clust - 2) * fs->csize;
+    fre_sect = fre_clust * fs->csize;
+
+    /* Print free space in unit of KB (assuming 512B/sector) */
+    printf("%lu KB total drive space.\n"
+           "%lu KB available.\n",
+           fre_sect / 2, tot_sect / 2);
+
+
+ + +
+

See Also

+

FATFS

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/gets.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/gets.html new file mode 100644 index 0000000..1df618a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/gets.html @@ -0,0 +1,63 @@ + + + + + + + +FatFs - f_gets + + + + +
+

f_gets

+

The f_gets reads a string from the file.

+
+char* f_gets (
+  char* Str,        /* Read buffer */
+  int Size,         /* Size of the read buffer */
+  FIL* FileObject   /* File object */
+);
+
+
+ +
+

Parameters

+
+
Str
+
Pointer to read buffer to store the read string.
+
Size
+
Size of the read buffer.
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

When the function succeeded, Str will be returuned.

+
+ + +
+

Description

+

The f_gets() is a wrapper function of f_read(). The read operation continues until a '\n' is stored, reached end of file or buffer is filled with Size - 1 characters. The read string is terminated with a '\0'. When the file has reached end of the file or any error occured during read operation, f_gets() returns a NULL. The EOF and error status can be examined with f_eof() and f_error() macro.

+
+ + +
+

QuickInfo

+

Available when _USE_STRFUNC is 1 or 2. When it is set to 2, '\r's contained in the file are stripped out.

+
+ + +
+

See Also

+

f_open, f_read, f_putc, f_puts, f_printf, f_close, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/lseek.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/lseek.html new file mode 100644 index 0000000..3639f64 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/lseek.html @@ -0,0 +1,111 @@ + + + + + + + +FatFs - f_lseek + + + + +
+

f_lseek

+

The f_lseek function moves the file read/write pointer of an open file object. It can also be used to increase the file size (cluster pre-allocation).

+ +
+FRESULT f_lseek (
+  FIL* FileObject,   /* Pointer to the file object structure */
+  DWORD Offset       /* File offset in unit of byte */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object.
+
Offset
+
Number of bytes where from start of the file
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
+ + +
+

Description

+

The f_lseek function moves the file R/W pointer of an open file. The offset can be specified in only origin from top of the file. When an offset above the file size is specified in write mode, the file size is increased and the data in the expanded area is undefined. This is suitable to create a large file quickly, for fast write operation. After the f_lseek function succeeded, member fptr in the file object should be checked in order to make sure the R/W pointer has been moved correctry. In case of fptr is not the expected value, either of followings has been occured.

+
    +
  • End of file. The specified Offset was clipped at the file size because the file has been opened in read-only mode.
    • +
  • Disk full. There is insufficient free space on the volume to expand the file size.
    • +
+
+ + +
+

QuickInfo

+

Available when _FS_MINIMIZE <= 2.

+
+ + +
+

Example

+
+    /* Move to offset of 5000 from top of the file */
+    res = f_lseek(file, 5000);
+
+    /* Move to end of the file to append data */
+    res = f_lseek(file, file->fsize);
+
+    /* Forward 3000 bytes */
+    res = f_lseek(file, file->fptr + 3000);
+
+    /* Rewind 2000 bytes (take care on overflow) */
+    res = f_lseek(file, file->fptr - 2000);
+
+
+    /* Cluster pre-allocation (to prevent buffer overrun on streaming write) */
+
+    res = f_open(file, recfile, FA_CREATE_NEW | FA_WRITE); /* Create a file */
+
+    res = f_lseek(file, PRE_SIZE);         /* Pre-allocate clusters */
+    if (res || file->fptr != PRE_SIZE) ... /* Check if the file size has been increased correctly */
+
+    res = f_lseek(file, DATA_START);       /* Record data stream without cluster allocation delay */
+    ...
+
+    res = f_truncate(file);                /* Truncate unused area */
+    res = f_lseek(file, 0);                /* Put file header */
+    ...
+
+    res = f_close(file);
+
+
+ + +
+

See Also

+

f_open, f_truncate, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mkdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mkdir.html new file mode 100644 index 0000000..c76991d --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mkdir.html @@ -0,0 +1,89 @@ + + + + + + + +FatFs - f_mkdir + + + + +
+

f_mkdir

+

The f_mkdir function creates a new directory.

+
+FRESULT f_mkdir (
+  const XCHAR* DirName /* Pointer to the directory name */
+);
+
+
+ +
+

Parameter

+
+
DirName
+
Pointer to the null-terminated string that specifies the directory name to create.
+
+
+ + +
+

Return Value

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The path name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_DENIED
+
The directory cannot be created due to directory table or disk is full.
+
FR_EXIST
+
A file or directory that has same name is already existing.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_WRITE_PROTECTED
+
The medium is write protected.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_mkdir function creates a new directory.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    res = f_mkdir("sub1");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2/sub3");
+    if (res) die(res);
+
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mkfs.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mkfs.html new file mode 100644 index 0000000..dd860bb --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mkfs.html @@ -0,0 +1,78 @@ + + + + + + + +FatFs - f_mkfs + + + + +
+

f_mkfs

+

The f_mkfs fucntion creates a file system on the drive.

+
+FRESULT f_mkfs (
+  BYTE  Drive,            /* Logical drive number */
+  BYTE  PartitioningRule, /* Partitioning rule */
+  WORD  AllocSize         /* Size of the allocation unit */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Logical drive number (0-9) to be formatted.
+
PartitioningRule
+
When 0 is given, a partition table is created into the first sector on the drive and then the file system is created on the partition. This is called FDISK format and used for harddisk and memory card. When 1 is given, the file system starts from the first sector without partition table. This is often called super floppy disk (SFD) format and used for floppy disk and removable disk.
+
AllocSize
+
Specifies allocation unit size in number of bytes per cluster. The value must be 0 or power of 2 in range of from 512 to 32768. When 0 is specified, the cluster size is determined depends on the volume size. FAT64 (64KB/cluster on FAT16) cannot be created by this function.
+
+
+ +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The drive cannot work due to any reason.
+
FR_WRITE_PROTECTED
+
The drive is write protected.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_MKFS_ABORTED
+
The function aborted before start in format due to a reason as follows. +
    +
  • The disk size is too small.
    • +
  • Invalid parameter was given to any parameter.
    • +
  • Not allowable cluster size for this drive. This can occure when number of clusters becomes around 0xFF7 and 0xFFF7.
    • +
+
+
+
+ +
+

Description

+

The f_mkfs function creates a FAT file system on the drive. There are two partitioning rules, FDISK and SFD, for removable media. It can be selected with an argument. The FDISK format is recommended for the most case. This function currently does not support multiple partition, so that existing partitions on the physical dirve will be deleted and re-created a new partition occupies entire disk space.

+

The FAT sub-type, FAT12/FAT16/FAT32, is determined by number of clusters on the drive and nothing else, according to the FAT specification issued by Microsoft. Thus which FAT sub-type is selected, is depends on the volume size and the specified cluster size. The cluster size affects performance of the file system and large cluster increases the performance.

+
+ + +
+

QuickInfo

+

Available when _FS_READOLNY == 0 and _USE_MKFS == 1.

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mount.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mount.html new file mode 100644 index 0000000..aa80f3b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/mount.html @@ -0,0 +1,65 @@ + + + + + + + +FatFs - f_mount + + + + +
+

f_mount

+

The f_mount fucntion registers/unregisters a work area to the FatFs module.

+
+FRESULT f_mount (
+  BYTE  Drive,              /* Logical drive number */
+  FATFS*  FileSystemObject  /* Pointer to the work area */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Logical drive number (0-9) to register/unregister the work area.
+
FileSystemObject
+
Pointer to the work area (file system object) to be registered.
+
+
+ +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
+
+ + +
+

Description

+

The f_mount function registers/unregisters a work area to the FatFs module. The work area must be given to the each volume with this function prior to use any other file function. To unregister a work area, specify a NULL to the FileSystemObject, and then the work area can be discarded.

+

This function only initializes the given work area and registers its address to the internal table, any access to the disk I/O layer does not occure. The volume mount process is performed on first file access after f_mount function or media change.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

FATFS

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/open.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/open.html new file mode 100644 index 0000000..33d6d9c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/open.html @@ -0,0 +1,148 @@ + + + + + + + +FatFs - f_open + + + + +
+

f_open

+

The f_open function creates a file object to be used to access the file.

+
+FRESULT f_open (
+  FIL* FileObject,       /* Pointer to the blank file object structure */
+  const XCHAR* FileName, /* Pointer to the file neme */
+  BYTE ModeFlags         /* Mode flags */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the file object structure to be created.
+
FileName
+
Pointer to a null-terminated string that specifies the file name to create or open.
+
ModeFlags
+
Specifies the type of access and open method for the file. It is specified by a combination of following flags.
+ + + + + + + + +
ValueDescription
FA_READSpecifies read access to the object. Data can be read from the file.
Combine with FA_WRITE for read-write access.
FA_WRITESpecifies write access to the object. Data can be written to the file.
Combine with FA_READ for read-write access.
FA_OPEN_EXISTINGOpens the file. The function fails if the file is not existing. (Default)
FA_OPEN_ALWAYSOpens the file, if it is existing. If not, a new file is created.
FA_CREATE_NEWCreates a new file. The function fails if the file is already existing.
FA_CREATE_ALWAYSCreates a new file. If the file is existing, it is truncated and overwritten.
+
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded and the file object is valid.
+
FR_NO_FILE
+
Could not find the file.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The file name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_EXIST
+
The file is already existing.
+
FR_DENIED
+
The required access was denied due to one of the following reasons: +
  • Write mode open of a read-only file.
    • +
  • File cannot be created due to a read-only file or same name directory is existing.
    • +
  • File cannot be created due to the directory table or disk is full.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_WRITE_PROTECTED
+
Write mode open or creation under the medium is write protected.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

A file object is created when the function succeeded. The file object is used for subsequent read/write functions to refer to the file. When close an open file object, use f_close function. If the modified file is not closed, the file may be collapsed.

+

Before using any file function, a work area (file system object) must be given to the logical drive with f_mount function. All file functions can work after this procedure.

+
+ + +
+

QuickInfo

+

Always available. The mode flags, FA_WRITE, FA_CREATE_ALWAYS, FA_CREATE_NEW, FA_OPEN_ALWAYS, are not available when _FS_READONLY == 1.

+
+ + +
+

Example (File Copy)

+
+void main (void)
+{
+    FATFS fs[2];         /* Work area (file system object) for logical drives */
+    FIL fsrc, fdst;      /* file objects */
+    BYTE buffer[4096];   /* file copy buffer */
+    FRESULT res;         /* FatFs function common result code */
+    UINT br, bw;         /* File R/W count */
+
+
+    /* Register work area for logical drives */
+    f_mount(0, &fs[0]);
+    f_mount(1, &fs[1]);
+
+    /* Open source file on the drive 1 */
+    res = f_open(&fsrc, "1:srcfile.dat", FA_OPEN_EXISTING | FA_READ);
+    if (res) die(res);
+
+    /* Create destination file on the drive 0 */
+    res = f_open(&fdst, "0:dstfile.dat", FA_CREATE_ALWAYS | FA_WRITE);
+    if (res) die(res);
+
+    /* Copy source to destination */
+    for (;;) {
+        res = f_read(&fsrc, buffer, sizeof(buffer), &br);
+        if (res || br == 0) break;   /* error or eof */
+        res = f_write(&fdst, buffer, br, &bw);
+        if (res || bw < br) break;   /* error or disk full */
+    }
+
+    /* Close open files */
+    f_close(&fsrc);
+    f_close(&fdst);
+
+    /* Unregister work area prior to discard it */
+    f_mount(0, NULL);
+    f_mount(1, NULL);
+}
+
+
+ + +
+

See Also

+

f_read, f_write, f_close, FIL, FATFS

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/opendir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/opendir.html new file mode 100644 index 0000000..eb180f2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/opendir.html @@ -0,0 +1,79 @@ + + + + + + + +FatFs - f_opendir + + + + +
+

f_opendir

+

The f_opendir function opens a directory.

+
+FRESULT f_opendir (
+  DIR* DirObject,       /* Pointer to the blank directory object structure */
+  const XCHAR* DirName  /* Pointer to the directory name */
+);
+
+
+ +
+

Parameters

+
+
DirObject
+
Pointer to the blank directory object to be created.
+
DirName
+
Pinter to the null-terminated string that specifies the directory name to be opened.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded and the directory object is created. It is used for subsequent calls to read the directory entries.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The path name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_opendir function opens an exsisting directory and creates the directory object for subsequent calls. The directory object structure can be discarded at any time without any procedure.

+
+ + +
+

QuickInfo

+

Available when _FS_MINIMIZE <= 1.

+
+ + +
+

See Also

+

f_readdir, DIR

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/printf.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/printf.html new file mode 100644 index 0000000..a672662 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/printf.html @@ -0,0 +1,82 @@ + + + + + + + +FatFs - f_printf + + + + +
+

f_printf

+

The f_printf function writes formatted string to the file.

+
+int f_printf (
+  FIL* FileObject,     /* File object */
+  const char* Foramt,  /* Format stirng */
+  ...
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
Format
+
Pointer to the null-terminated format string.
+
...
+
Optional arguments.
+ +
+
+ + +
+

Return Values

+

When the function succeeded, number of characters written is returned. When the function failed due to disk full or any error, an EOF will be returned.

+
+ + +
+

Description

+

The f_printf() is a wrapper function of f_putc() and f_puts(). The format control directive is a sub-set of standard library shown as follos:

+
    +
  • Type: c s d u X
    • +
  • Size: l
    • +
  • Flag: 0
    • +
+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _USE_STRFUNC is 1 or 2. When it is set to 2, '\n's contained in the output are converted to "\r\n".

+
+ + +
+

Example

+
+    f_printf(&fil, "%6d", -200);         /* "  -200" */
+    f_printf(&fil, "%02u", 5);           /* "05" */
+    f_printf(&fil, "%ld", 12345678L);    /* "12345678" */
+    f_printf(&fil, "%08lX", 1194684UL);  /* "00123ABC" */
+    f_printf(&fil, "%s", "String");      /* "String" */
+    f_printf(&fil, "%c", 'a');           /* "a" */
+
+
+ + +
+

See Also

+

f_open, f_putc, f_puts, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/putc.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/putc.html new file mode 100644 index 0000000..374e677 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/putc.html @@ -0,0 +1,60 @@ + + + + + + + +FatFs - f_putc + + + + +
+

f_putc

+

The f_putc funciton puts a character to the file.

+
+int f_putc (
+  int Chr,          /* A character to put */
+  FIL* FileObject   /* File object */
+);
+
+
+ +
+

Parameters

+
+
Chr
+
A character to be put.
+
FileObject
+
Pointer to the open file object structuer.
+
+
+ + +
+

Return Values

+

When the character was written successfuly, the function returns the character. When the function failed due to disk full or any error, an EOF will be returned.

+
+ + +
+

Description

+

The f_putc() is a wrapper function of f_write().

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _USE_STRFUNC is 1 or 2. When it is set to 2, a '\n' is converted to "\r\n".

+
+ + +
+

See Also

+

f_open, f_puts, f_printf, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/puts.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/puts.html new file mode 100644 index 0000000..7aca04b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/puts.html @@ -0,0 +1,60 @@ + + + + + + + +FatFs - f_puts + + + + +
+

f_puts

+

The f_puts function writes a string to the file.

+
+int f_puts (
+  const char* Str,  /* String */
+  FIL* FileObject   /* File object */
+);
+
+
+ +
+

Parameters

+
+
Str
+
Pointer to the null terminated string to be written. The null character will not be written.
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Value

+

When the function succeeded, number of characters written that is not minus value is returned. When the function failed due to disk full or any error, an EOF will be returned.

+
+ + +
+

Description

+

The f_puts() is a wrapper function of f_putc().

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _USE_STRFUNC is 1 or 2. When it is set to 2, '\n's contained in the string are converted to "\r\n".

+
+ + +
+

See Also

+

f_open, f_putc, f_printf, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/read.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/read.html new file mode 100644 index 0000000..ef01573 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/read.html @@ -0,0 +1,79 @@ + + + + + + + +FatFs - f_read + + + + +
+

f_read

+

The f_read function reads data from a file.

+
+FRESULT f_read (
+  FIL* FileObject,    /* Pointer to the file object structure */
+  void* Buffer,       /* Pointer to the buffer to store read data */
+  UINT ByteToRead,    /* Number of bytes to read */
+  UINT* ByteRead      /* Pointer to the variable to return number of bytes read */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object.
+
Buffer
+
Pointer to the buffer to store read data
+
ByteToRead
+
Number of bytes to read in range of UINT.
+
ByteRead
+
Pointer to the UINT variable to return number of bytes read. The value is always valid after the function call regardless of the result.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_DENIED
+
The function denied due to the file has been opened in non-read mode.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
+ + +
+

Description

+

The file pointer of the file object increases in number of bytes read. After the function succeeded, *ByteRead should be checked to detect the end of file. In case of *ByteRead < ByteToRead, it means the R/W pointer reached end of the file during read operation.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, fgets, f_write, f_close, FIL

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/readdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/readdir.html new file mode 100644 index 0000000..b37193f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/readdir.html @@ -0,0 +1,119 @@ + + + + + + + +FatFs - f_readdir + + + + +
+

f_readdir

+

The f_readdir function reads directory entries.

+
+FRESULT f_readdir (
+  DIR* DirObject,    /* Pointer to the open directory object */
+  FILINFO* FileInfo  /* Pointer to the file information structure */
+);
+
+
+ +
+

Parameters

+
+
DirObject
+
Pointer to the open directory object.
+
FileInfo
+
Pointer to the file information structure to store the read item.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_INVALID_OBJECT
+
The directory object is invalid.
+
+
+ + +
+

Description

+

The f_readdir function reads directory entries in sequence. All items in the directory can be read by calling f_readdir function repeatedly. When all directory entries have been read and no item to read, the function returns a null string into f_name[] member without any error. When a null pointer is given to the FileInfo, the read index of the directory object will be rewinded.

+

When LFN feature is enabled, lfname and lfsize in the file information structure must be initialized with valid value prior to use the f_readdir function. The lfname is a pointer to the string buffer to return the long file name. The lfsize is the size of the string buffer in unit of character. If either the size of read buffer or LFN working buffer is insufficient for the LFN or the object has no LFN, a null string will be returned to the LFN read buffer. If the LFN contains any charactrer that cannot be converted to OEM code, a null string will be returned but this is not the case on Unicode API configuration. When lfname is a NULL, nothing of the LFN is returned. When the object has no LFN, any small capitals can be contained in the SFN.

+

When relative path feature is enabled (_FS_RPATH == 1), "." and ".." entries are not filtered out and it will appear in the read entries.

+
+ + +
+

QuickInfo

+

Available when _FS_MINIMIZE <= 1.

+
+ + +
+

Sample Code

+
+FRESULT scan_files (char* path)
+{
+    FRESULT res;
+    FILINFO fno;
+    DIR dir;
+    int i;
+    char *fn;
+#if _USE_LFN
+    static char lfn[_MAX_LFN * (_DF1S ? 2 : 1) + 1];
+    fno.lfname = lfn;
+    fno.lfsize = sizeof(lfn);
+#endif
+
+
+    res = f_opendir(&dir, path);
+    if (res == FR_OK) {
+        i = strlen(path);
+        for (;;) {
+            res = f_readdir(&dir, &fno);
+            if (res != FR_OK || fno.fname[0] == 0) break;
+            if (fno.fname[0] == '.') continue;
+#if _USE_LFN
+            fn = *fno.lfname ? fno.lfname : fno.fname;
+#else
+            fn = fno.fname;
+#endif
+            if (fno.fattrib & AM_DIR) {
+                sprintf(&path[i], "/%s", fn);
+                res = scan_files(path);
+                if (res != FR_OK) break;
+                path[i] = 0;
+            } else {
+                printf("%s/%s\n", path, fn);
+            }
+        }
+    }
+
+    return res;
+}
+
+
+ + +
+

See Also

+

f_opendir, f_stat, FILINFO, DIR

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/rename.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/rename.html new file mode 100644 index 0000000..4a2de3b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/rename.html @@ -0,0 +1,93 @@ + + + + + + + +FatFs - f_rename + + + + +
+

f_rename

+

Renames an object.

+
+FRESULT f_rename (
+  const XCHAR* OldName, /* Pointer to old object name */
+  const XCHAR* NewName  /* Pointer to new object name */
+);
+
+
+ +
+

Parameters

+
+
OldName
+
Pointer to a null-terminated string specifies the old object name to be renamed.
+
NewName
+
Pointer to a null-terminated string specifies the new object name without drive number.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_FILE
+
Could not find the old name.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The file name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_EXIST
+
The new name is colliding with an existing name.
+
FR_DENIED
+
The new name could not be created due to any reason.
+
FR_WRITE_PROTECTED
+
The medium is write protected.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

Renames an object and can also move it to other directory. The logical drive number is determined by old name, new name must not contain a logical drive number. Do not rename open objects.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    /* Rename an object */
+    f_rename("oldname.txt", "newname.txt");
+
+    /* Rename and move an object to other directory */
+    f_rename("oldname.txt", "dir1/newname.txt");
+
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sdir.html new file mode 100644 index 0000000..fe4f8ff --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sdir.html @@ -0,0 +1,36 @@ + + + + + + + +FatFs - DIR + + + + +
+

DIR

+

The DIR structure is used for the work area to read a directory by f_oepndir, f_readdir function. There is no member that can be changed by application.

+
+typedef struct _DIR_ {
+    FATFS*  fs;         /* Pointer to the owner file system object */
+    WORD    id;         /* Owner file system mount ID */
+    WORD    index;      /* Current read/write index number */
+    DWORD   sclust;     /* Table start cluster (0:Static table) */
+    DWORD   clust;      /* Current cluster */
+    DWORD   sect;       /* Current sector */
+    BYTE*   dir;        /* Pointer to the current SFN entry in the win[] */
+    BYTE*   fn;         /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+    WCHAR*  lfn;        /* Pointer to the LFN working buffer */
+    WORD    lfn_idx;    /* Last matched LFN index (0xFFFF:No LFN) */
+#endif
+} DIR;
+
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfatfs.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfatfs.html new file mode 100644 index 0000000..fb9dad8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfatfs.html @@ -0,0 +1,53 @@ + + + + + + + +FatFs - FATFS + + + + +
+

FATFS

+

The FATFS structure holds dynamic work area of individual logical drives. It is given by application program and registerd/unregisterd to the FatFs module with f_mount function. Following members are in standard configuration. There is no member that can be changed from the application program.

+
+typedef struct _FATFS_ {
+    BYTE    fs_type;    /* FAT sub type */
+    BYTE    drive;      /* Physical drive number */
+    BYTE    csize;      /* Number of sectors per cluster */
+    BYTE    n_fats;     /* Number of FAT copies */
+    BYTE    wflag;      /* win[] dirty flag (1:must be written back) */
+    BYTE    fsi_flag;   /* fsinfo dirty flag (1:must be written back) */
+    WORD    id;         /* File system mount ID */
+    WORD    n_rootdir;  /* Number of root directory entries (0 on FAT32) */
+#if _FS_REENTRANT
+    _SYNC_t sobj;       /* Identifier of sync object */
+#endif
+#if _MAX_SS != 512
+    WORD    s_size;     /* Sector size */
+#endif
+#if !_FS_READONLY
+    DWORD   last_clust; /* Last allocated cluster */
+    DWORD   free_clust; /* Number of free clusters */
+    DWORD   fsi_sector; /* fsinfo sector */
+#endif
+#if _FS_RPATH
+    DWORD   cdir;       /* Current directory (0:root)*/
+#endif
+    DWORD   sects_fat;  /* Sectors per fat */
+    DWORD   max_clust;  /* Maximum cluster# + 1. Number of clusters is max_clust - 2 */
+    DWORD   fatbase;    /* FAT start sector */
+    DWORD   dirbase;    /* Root directory start sector (Cluster# on FAT32) */
+    DWORD   database;   /* Data start sector */
+    DWORD   winsect;    /* Current sector appearing in the win[] */
+    BYTE    win[_MAX_SS];/* Disk access window for Directory/FAT */
+} FATFS;
+
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfile.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfile.html new file mode 100644 index 0000000..c6af008 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfile.html @@ -0,0 +1,42 @@ + + + + + + + +FatFs - FIL + + + + +
+

FIL

+

The FIL structure (file object) holds state of an open file. It is initialzed by f_open function and discarded by f_close function. There is no member that can be changed by the application program.

+ +
+typedef struct _FIL_ {
+    FATFS*  fs;         /* Pointer to the owner file system object */
+    WORD    id;         /* Owner file system mount ID */
+    BYTE    flag;       /* File status flags */
+    BYTE    csect;      /* Sector address in the cluster */
+    DWORD   fptr;       /* File R/W pointer */
+    DWORD   fsize;      /* File size */
+    DWORD   org_clust;  /* File start cluster */
+    DWORD   curr_clust; /* Current cluster */
+    DWORD   dsect;      /* Current data sector */
+#if !_FS_READONLY
+    DWORD   dir_sect;   /* Sector containing the directory entry */
+    BYTE*   dir_ptr;    /* Ponter to the directory entry in the window */
+#endif
+#if !_FS_TINY
+    BYTE    buf[_MAX_SS];/* File R/W buffer */
+#endif
+} FIL;
+
+ +
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfileinfo.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfileinfo.html new file mode 100644 index 0000000..ab3e887 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sfileinfo.html @@ -0,0 +1,69 @@ + + + + + + + +FatFs - FILINFO + + + + +
+

FILINFO

+

The FILINFO structure holds a file information returned by f_stat and f_readdir function.

+
+typedef struct _FILINFO_ {
+    DWORD fsize;      /* File size */
+    WORD  fdate;      /* Last modified date */
+    WORD  ftime;      /* Last modified time */
+    BYTE  fattrib;    /* Attribute */
+    char  fname[13];  /* Short file name (8.3 format) */
+#if _USE_LFN
+    XCHAR* lfname;    /* Pointer to the LFN buffer */
+    int   lfsize;     /* Size of LFN buffer [characters] */
+#endif
+} FILINFO;
+
+
+ +

Members

+
+
fsize
+
Indicates size of the file in unit of byte. This is always zero when it is a directory.
+
fdate
+
Indicates the date that the file was modified or the directory was created.
+
+
bit15:9
+
Year origin from 1980 (0..127)
+
bit8:5
+
Month (1..12)
+
bit4:0
+
Day (1..31)
+
+
+
ftime
+
Indicates the time that the file was modified or the directory was created.
+
+
bit15:11
+
Hour (0..23)
+
bit10:5
+
Minute (0..59)
+
bit4:0
+
Second / 2 (0..29)
+
+
+
fattrib
+
Indicates the file/directory attribute in combination of AM_DIR, AM_RDO, AM_HID, AM_SYS and AM_ARC.
+
fname[]
+
Indicates the file/directory name in 8.3 format null-terminated string. It is always returnd with upper case on non-LFN configuration but it can be returned with lower case on LFN configuration.
+
lfname
+
Pointer to the LFN buffer to store the read LFN. This member must be initialized by application prior to use this structure. Not available on non-LFN configuration.
+
lfsize
+
Size of the LFN buffer in unit of chars. This member must be initialized by application prior to use this structure. Not available on non-LFN configuration.
+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/stat.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/stat.html new file mode 100644 index 0000000..7f92754 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/stat.html @@ -0,0 +1,75 @@ + + + + + + + +FatFs - f_stat + + + + +
+

f_stat

+

The f_stat gets the file status.

+
+FRESULT f_stat (
+  const XCHAR* FileName,  /* Pointer to the file or directory name */
+  FILINFO* FileInfo       /* Pointer to the FILINFO structure */
+);
+
+
+ +
+

Parameters

+
+
FileName
+
Pointer to the null-terminated string that specifies the file or directory to get its information.
+
FileInfo
+
Pointer to the blank FILINFO structure to store the information.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_FILE
+
Could not find the file or directory.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The file name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_stat gets the information of a file or directory. For details of the infomation, refer to the FILINFO structure and f_readdir function. This function is not supported in minimization level of >= 1.

+
+ + +
+

References

+

f_opendir, f_readdir, FILINFO

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sync.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sync.html new file mode 100644 index 0000000..21b9953 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/sync.html @@ -0,0 +1,68 @@ + + + + + + + +FatFs - f_sync + + + + +
+

f_sync

+

The f_sync function flushes the cached information of a writing file.

+
+FRESULT f_sync (
+  FIL* FileObject     /* Pointer to the file object */
+);
+
+
+ +
+

Parameter

+
+
FileObject
+
Pointer to the open file object to be flushed.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
+ + +
+

Description

+

The f_sync function performs the same process as f_close function but the file is left opened and can continue read/write/seek operations to the file. This is suitable for the applications that open files for a long time in write mode, such as data logger. Performing f_sync of periodic or immediataly after f_write can minimize the risk of data loss due to a sudden blackout or an unintentional disk removal. However f_sync immediataly before f_close has no advantage because f_close performs f_sync in it. In other words, the differnce between those functions is that the file object is invalidated or not.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0.

+
+ + +
+

See Also

+

f_close

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/truncate.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/truncate.html new file mode 100644 index 0000000..cb6f0b0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/truncate.html @@ -0,0 +1,71 @@ + + + + + + + +FatFs - f_truncate + + + + +
+

f_truncate

+

The f_truncate function truncates the file size.

+
+FRESULT f_truncate (
+  FIL* FileObject     /* Pointer to the file object */
+);
+
+
+ +
+

Parameter

+
+
FileObject
+
Pointer to the open file object to be truncated.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_DENIED
+
The file has been opened in read-only mode.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
+ + +
+

Description

+

The f_truncate function truncates the file size to the current file R/W point. When the file R/W pointer is already pointing end of the file, this function has no effect.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/unlink.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/unlink.html new file mode 100644 index 0000000..8755680 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/unlink.html @@ -0,0 +1,78 @@ + + + + + + + +FatFs - f_unlink + + + + +
+

f_unlink

+

The f_unlink removes an object.

+
+FRESULT f_unlink (
+  const XCHAR* FileName  /* Pointer to the object name */
+);
+
+
+ +
+

Parameter

+
+
FileName
+
Pointer to the null-terminated string that specifies an object to be removed.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_FILE
+
Could not find the file or directory.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The path name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_DENIED
+
The function was denied due to either of following reasons: +
  • The object has read-only attribute
  • The directory is not empty.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_WRITE_PROTECTED
+
The medium is write protected.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_unlink function removes an object. Do not remove open objects and current directory.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/utime.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/utime.html new file mode 100644 index 0000000..9c596f5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/utime.html @@ -0,0 +1,83 @@ + + + + + + + +FatFs - f_utime + + + + +
+

f_utime

+

The f_utime function changes the timestamp of a file or directory.

+
+FRESULT f_utime (
+  const XCHAR* FileName,   /* Pointer to the file or directory path */
+  const FILINFO* TimeDate  /* Time and data to be set */
+);
+
+
+ +
+

Parameters

+
+
FileName
+
Pointer to the null-terminated string that specifies a file or directory to be changed.
+
TimeDate
+
Pointer to the file information structure that has a timestamp to be set in member fdate and ftime. Do not care any other members.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_NO_FILE
+
Could not find the file.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The file name is invalid.
+
FR_INVALID_DRIVE
+
The drive number is invalid.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_WRITE_PROTECTED
+
The medium is write protected.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_ENABLED
+
The logical drive has no work area.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the disk.
+
+
+ + +
+

Description

+

The f_utime function changes the timestamp of a file or directory

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

See Also

+

f_stat, FILINFO

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/write.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/write.html new file mode 100644 index 0000000..291c046 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/en/write.html @@ -0,0 +1,79 @@ + + + + + + + +FatFs - f_write + + + + +
+

f_write

+

The f_write writes data to a file.

+
+FRESULT f_write (
+  FIL* FileObject,     /* Pointer to the file object structure */
+  const void* Buffer,  /* Pointer to the data to be written */
+  UINT ByteToWrite,    /* Number of bytes to write */
+  UINT* ByteWritten    /* Pointer to the variable to return number of bytes written */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
Buffer
+
Pointer to the data to be written.
+
ByteToWrite
+
Specifies number of bytes to write in range of UINT.
+
ByteWritten
+
Pointer to the UINT variable to return the number of bytes written. The value is always valid after the function call regardless of the result.
+
+
+ + +
+

Return Values

+
+
FR_OK (0)
+
The function succeeded.
+
FR_DENIED
+
The function denied due to the file has been opened in non-write mode.
+
FR_DISK_ERR
+
The function failed due to an error in the disk function.
+
FR_INT_ERR
+
The function failed due to a wrong FAT structure or an internal error.
+
FR_NOT_READY
+
The disk drive cannot work due to no medium in the drive or any other reason.
+
FR_INVALID_OBJECT
+
The file object is invalid.
+
+
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+

Description

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The R/W pointer in the file object is increased in number of bytes written. After the function succeeded, *ByteWritten should be checked to detect the disk full. In case of *ByteWritten < ByteToWrite, it means the volume got full during the write operation.

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QuickInfo

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Available when _FS_READONLY == 0.

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See Also

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f_open, f_read, fputc, fputs, fprintf, f_close, FIL

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Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f1.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f1.png new file mode 100644 index 0000000..42cc271 Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f1.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f2.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f2.png new file mode 100644 index 0000000..8ef0ec2 Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f2.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f3.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f3.png new file mode 100644 index 0000000..9111bfc Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f3.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f4.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f4.png new file mode 100644 index 0000000..f9a6b46 Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f4.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f5.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f5.png new file mode 100644 index 0000000..b110b29 Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/f5.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/layers.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/layers.png new file mode 100644 index 0000000..d485d6b Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/layers.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/rwtest.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/rwtest.png new file mode 100644 index 0000000..a34bf06 Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/rwtest.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/rwtest2.png b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/rwtest2.png new file mode 100644 index 0000000..aeb38be Binary files /dev/null and b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/img/rwtest2.png differ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/appnote.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/appnote.html new file mode 100644 index 0000000..216872f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/appnote.html @@ -0,0 +1,194 @@ + + + + + + + +FatFsモジュール アプリケーション・ノート + + + +

FatFsモジュール アプリケーション・ノート

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+

ãƒãƒ¼ãƒ†ã‚£ãƒ³ã‚°ã®éš›ã«é…æ…®ã™ã¹ãã“ã¨

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FatFsモジュールã¯ç§»æ¤æ€§ã«é–¢ã—ã¦æ¬¡ã®ç‚¹ã‚’å‰æã¨ã—ã¦ã„ã¾ã™ã€‚

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    +
  • 処ç†ç³»ã¯ANSI C準拠ã§ã‚ã‚‹ã“ã¨ã€‚
    +FatFsモジュールã¯ANSI C準拠ã§è¨˜è¿°ã•ã‚Œã¦ã„ã‚‹ã®ã§ã€ANSI C準拠ã®ã‚³ãƒ³ãƒ‘イラãªã‚‰ç‰¹ã«å‡¦ç†ç³»ä¾å­˜ãªç‚¹ã¯ã‚ã‚Šã¾ã›ã‚“。
    • +
  • char/short/longã®ã‚µã‚¤ã‚ºã¯ã€ãã‚Œãžã‚Œ8/16/32ビットã§ã€intã¯16ã¾ãŸã¯32ビットã§ã‚ã‚‹ã“ã¨ã€‚
    +サイズを明示ã™ã‚‹æ•´æ•°ã®åž‹ãŒ integer.h 内ã§å®šç¾©ã•ã‚Œã¦ã„ã¾ã™ã€‚æ•´æ•°ã®åž‹ã¨ã‚µã‚¤ã‚ºã«é–¢ã—ã¦ã¯ã€ã¾ã£ã¨ã†ãªå‡¦ç†ç³»ãªã‚‰å•é¡Œãªã„ã¯ãšã§ã™ãŒã€æ—¢å­˜ã®å®šç¾©ã¨è¡çªã—ãŸå ´åˆã¯ãƒ¦ãƒ¼ã‚¶ã«ã‚ˆã£ã¦è§£æ±ºã•ã‚Œãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。
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+

ãƒ¡ãƒ¢ãƒªä½¿ç”¨é‡ (R0.07e)

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AVRH8/300HPICTLCS-870/CV850ESSH2ARM7TDMIx86
CompilerWinAVR(gcc)CH38C30(gcc)CC870CCA850SHCWinARM(gcc)VC6
_WORD_ACCESS10011001
text (Full, R/W)1219410559109241522976868727105647342
text (Min, R/W)79886903710899604884565165444764
text (Full, R/O)55324753502067603462377746243316
text (Min, R/O)40403631373650832556290732842510
bssD*2 + 2D*4 + 2D*2 + 2D*2 + 2D*4 + 2D*4 + 2D*4 + 2D*4 + 2
Work area
(_FS_TINY == 0)		D*560 +
F*544		D*560 +
F*550		D*560 +
F*544		D*560 +
F*550		D*560 +
F*550		D*560 +
F*550		D*560 +
F*550
Work area
(_FS_TINY == 1)		D*560 +
F*32		D*560 +
F*36		D*560 +
F*32		D*560 +
F*32		D*560 +
F*36		D*560 +
F*36		D*560 +
F*36		D*560 +
F*36
+

上ã®è¡¨ã«ã„ãã¤ã‹ã®ã‚¿ãƒ¼ã‚²ãƒƒãƒˆã«ãŠã‘るメモリ使用é‡ã®ä¾‹ã‚’示ã—ã¾ã™ã€‚テスト時ã®æ§‹æˆã‚ªãƒ—ションã¯æ¬¡ã®é€šã‚Šã§ã™ã€‚数値ã®å˜ä½ã¯ãƒã‚¤ãƒˆã§ã€Dã¯è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–æ•°ã€Fã¯åŒæ™‚オープン・ファイル数を示ã—ã¾ã™ã€‚コンパイラã®æœ€é©åŒ–オプションã¯ã‚³ãƒ¼ãƒ‰ãƒ»ã‚µã‚¤ã‚ºã¨ã—ã¦ã„ã¾ã™ã€‚

+
+_FS_READONLY     0 (R/W), 1 (R/O)
+_FS_MINIMIZE     0 (Full function), 3 (Minimized function)
+_USE_STRFUNC     0 (Disable string functions)
+_USE_MKFS        0 (Disable f_mkfs function)
+_USE_FORWARD     0 (Disable f_forward function)
+_CODE_PAGE       932 (Japanese Shift-JIS)
+_USE_LFN         0 (Disable LFN)
+_LFN_UNICODE     0 (Disable Unicode API)
+_MAX_SS          512 (Single sector size)
+_FS_RPATH        0 (Disable relative path)
+_MULTI_PARTITION 0 (Single partition per drive)
+_FS_REENTRANT    0 (Disable reentrancy)
+
+
+ +
+

モジュール・サイズã®ç¸®å°

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次ã®è¡¨ã¯æ§‹æˆã‚ªãƒ—ションã®è¨­å®šå€¤ã«ã‚ˆã‚Šã©ã®æ©Ÿèƒ½ãŒå‰Šé™¤ã•ã‚Œã‚‹ã‹ã‚’示ã—ã¾ã™ã€‚

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Function_FS_MINIMIZE_FS_READONLY_USE_STRFUNC_FS_RPATH_USE_MKFS_USE_FORWARD
12310000
f_mount
f_open
f_close
f_read
f_writex
f_syncx
f_lseekx
f_opendirxx
f_readdirxx
f_statxxx
f_getfreexxxx
f_truncatexxxx
f_unlinkxxxx
f_mkdirxxxx
f_chmodxxxx
f_utimexxxx
f_renamexxxx
f_chdirx
f_chdrivex
f_mkfsxx
f_forwardx
f_putcxx
f_putsxx
f_printfxx
f_getsx
+
+ +
+

é•·ã„ファイルå

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FatFsモジュールã¯R0.07ã‹ã‚‰é•·ã„ファイルå(LFN)をサãƒãƒ¼ãƒˆã—ã¾ã—ãŸã€‚ファイルã«ä»˜ã‘られãŸ2ã¤ã®ç•°ãªã‚‹åå‰(短ã„ファルåã¨é•·ã„ファイルå)ã¯ã€f_readdir関数を除ãファイルæ“作関数ã«ãŠã„ã¦é€éŽã§ã™ã€‚LFN機能を有効ã«ã™ã‚‹ã«ã¯ã€_USE_LFNã‚’1ã¾ãŸã¯2ã«è¨­å®šã—ã€Unicode変æ›é–¢æ•° ff_convert, ff_wtoupper をプロジェクトã«è¿½åŠ ã—ã¾ã™ã€‚ã“れらã®é–¢æ•°ã¯ã€cc*.cã«å«ã¾ã‚Œã¦ã„ã¾ã™ã€‚LFN機能ã¯ã€åŠ ãˆã¦ã‚る程度ã®ãƒ¯ãƒ¼ã‚¯ãƒ»ã‚¨ãƒªã‚¢(LFNæ“作ãƒãƒƒãƒ•ã‚¡)ã‚’å¿…è¦ã¨ã—ã¾ã™ã€‚ãƒãƒƒãƒ•ã‚¡é•·ã¯ä½¿ç”¨ã§ãるメモリã«å¿œã˜ã¦_MAX_LFNオプションã§æ§‹æˆã•ã‚Œã‚‹ã“ã¨ãŒã§ãã¾ã™ã€‚LFNã®é•·ã•ã¯æœ€å¤§255文字ã«é”ã™ã‚‹ã®ã§ã€LFN完全対応ã®ãŸã‚ã«ã¯_MAX_LFNã¯255ã«è¨­å®šã•ã‚Œã‚‹ã¹ãã§ã™ã€‚与ãˆã‚‰ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«åã«å¯¾ã—ã¦ãƒãƒƒãƒ•ã‚¡é•·ãŒä¸è¶³ã—ãŸå ´åˆã€ãƒ•ã‚¡ã‚¤ãƒ«é–¢æ•°ã¯FR_INVALID_NAMEã§å¤±æ•—ã—ã¾ã™ã€‚

+

LFN機能をリエントラント構æˆã§ä½¿ç”¨ã™ã‚‹å ´åˆã¯ã€_USE_LFNã¯2ã«è¨­å®šã•ã‚Œãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。ã“ã®å ´åˆã€ãƒ•ã‚¡ã‚¤ãƒ«é–¢æ•°ã¯ãƒãƒƒãƒ•ã‚¡ã‚’スタックã«ç¢ºä¿ã—ã¾ã™ã€‚ãƒãƒƒãƒ•ã‚¡ãƒ»ã‚µã‚¤ã‚ºã¯ã€(_MAX_LFN + 1) * 2ãƒã‚¤ãƒˆã«ãªã‚‹ã®ã§ã€å‘¼ã³å‡ºã—å´ã‚¹ã‚¿ãƒƒã‚¯ã®ã‚µã‚¤ã‚ºã¯ãれを考慮ã—ãŸå分ãªã‚µã‚¤ã‚ºã§ãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。

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LFN cfg on ARM7
コードページROMサイズ[bytes]
SBCS+3721
932(Shift-JIS)+62609
936(GBK)+177797
949(Korean)+139857
950(Big5)+111497
+

LFNを有効ã«ã™ã‚‹ã¨ã€é¸æŠžã•ã‚ŒãŸã‚³ãƒ¼ãƒ‰ãƒ»ãƒšãƒ¼ã‚¸ã«å¿œã˜ã¦ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚µã‚¤ã‚ºãŒå¢—大ã•ã‚Œã¾ã™ã€‚å³ã®è¡¨ã«å„コード・ページã«ãŠã‘ã‚‹LFNを有効ã«ã—ãŸã¨ãã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚µã‚¤ã‚ºã®é•ã„を示ã—ã¾ã™ã€‚ç§ãŸã¡æ—¥æœ¬äººã€ä¸­å›½äººãŠã‚ˆã³éŸ“国人ã¯æ•°ä¸‡ã®æ–‡å­—ã‚’æŒã¡ã¾ã™ã€‚ä¸å¹¸ãªã“ã¨ã«ã€ãã‚Œã¯å·¨å¤§ãªOEMï¼Unicode相互変æ›ãƒ†ãƒ¼ãƒ–ルをè¦æ±‚ã—ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚µã‚¤ã‚ºã¯åŠ‡çš„ã«å¢—大ã•ã‚Œã¾ã™ã€‚ãã®çµæžœã€LFNを有効ã«ã—ãŸFatFsモジュールã¯ã€AVRã‚’å«ã‚€æ®†ã©ã®8ビット・マイコンã«ã‚¤ãƒ³ãƒ—リメントã•ã‚Œã‚‹ã“ã¨ãŒã§ãã¾ã›ã‚“。ã“ã‚Œã¯é•·ã„é–“ç§ãŒLFNをインプリメントã™ã‚‹ã“ã¨ã«èˆˆå‘³ã‚’æŒã£ã¦ã“ãªã‹ã£ãŸç†ç”±ã§ã™ã€‚

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注: FATファイル・システム上ã®LFN機能ã¯ãƒžã‚¤ã‚¯ãƒ­ã‚½ãƒ•ãƒˆç¤¾ã®ç‰¹è¨±ã§ã™ã€‚商用製å“ã§ãれを有効ã«ã™ã‚‹ã¨ãã¯ã€æœ€çµ‚仕å‘地ã«ã‚ˆã£ã¦ã¯ãƒ©ã‚¤ã‚»ãƒ³ã‚¹ãŒå¿…è¦ã‹ã‚‚知れã¾ã›ã‚“。

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リエントランシー

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互ã„ã«ç•°ãªã‚‹ãƒœãƒªãƒ¥ãƒ¼ãƒ (è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–)ã«å¯¾ã™ã‚‹ãƒ•ã‚¡ã‚¤ãƒ«æ“作ã¯ã€å¸¸ã«åŒæ™‚平行ã«å‹•ä½œã§ãã¾ã™ã€‚åŒã˜ãƒœãƒªãƒ¥ãƒ¼ãƒ ã«å¯¾ã—ã¦ã¯ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã§ã¯ãƒªã‚¨ãƒ³ãƒˆãƒ©ãƒ³ãƒˆã§ã¯ã‚ã‚Šã¾ã›ã‚“ãŒã€_FS_REENTRANTオプションã§ãƒªã‚¨ãƒ³ãƒˆãƒ©ãƒ³ãƒˆã«ã™ã‚‹ã“ã¨ã‚‚ã§ãã¾ã™ã€‚ã“ã®å ´åˆã€OSä¾å­˜ã®åŒæœŸã‚ªãƒ–ジェクトæ“作関数 ff_cre_syncobj, ff_del_syncobj, ff_req_grant 㨠ff_rel_grant ã‚‚ã¾ãŸãƒ—ロジェクトã«è¿½åŠ ã•ã‚Œãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。サンプル・コードã¨è§£èª¬ã¯syncobj.cã«ã‚ã‚Šã¾ã™ã€‚

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ã‚るタスクãŒãƒœãƒªãƒ¥ãƒ¼ãƒ ã‚’使用中ã«ä»–ã®ã‚¿ã‚¹ã‚¯ã‹ã‚‰ãã®ãƒœãƒªãƒ¥ãƒ¼ãƒ ã«å¯¾ã™ã‚‹ãƒ•ã‚¡ã‚¤ãƒ«é–¢æ•°ãŒå‘¼ã³å‡ºã•ã‚Œã‚‹ã¨ã€ãã®ã‚¢ã‚¯ã‚»ã‚¹ã¯å…ˆã®ã‚¿ã‚¹ã‚¯ãŒãƒ•ã‚¡ã‚¤ãƒ«é–¢æ•°ã‚’抜ã‘ã‚‹ã¾ã§ãƒ–ロックã•ã‚Œã¾ã™ã€‚ã‚‚ã—ã€å¾…ã¡æ™‚é–“ãŒ_TIMEOUTã§æŒ‡å®šã•ã‚ŒãŸæœŸé–“を越ã™ã¨ã€ãã®é–¢æ•°ã¯FR_TIMEOUTã§ã‚¢ãƒœãƒ¼ãƒˆã—ã¾ã™ã€‚ã„ãã¤ã‹ã®RTOSã§ã¯ã‚¿ã‚¤ãƒ ã‚¢ã‚¦ãƒˆæ©Ÿèƒ½ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œãªã„ã‹ã‚‚知れã¾ã›ã‚“。

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ã²ã¨ã¤ã®ä¾‹å¤–ãŒf_mountã¨f_mkfs関数ã«ã‚ã‚Šã¾ã™ã€‚ã“れらã®é–¢æ•°ã¯åŒã˜ãƒœãƒªãƒ¥ãƒ¼ãƒ ã«å¯¾ã—ã¦ãƒªã‚¨ãƒ³ãƒˆãƒ©ãƒ³ãƒˆã§ã¯ã‚ã‚Šã¾ã›ã‚“。ã“れらã®é–¢æ•°ã‚’使用ã™ã‚‹ã¨ãã¯ã€ã‚¢ãƒ—リケーション・レベルã§æŽ’他制御ã—ãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。

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注: ã“ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã¯FatFsモジュールãれ自体ã®ãƒªã‚¨ãƒ³ãƒˆãƒ©ãƒ³ã‚·ãƒ¼ã«ã¤ã„ã¦èª¬æ˜Žã—ã¦ã„ã¾ã™ã€‚ディスクI/Oモジュールã®ãƒªã‚¨ãƒ³ãƒˆãƒ©ãƒ³ã‚·ãƒ¼ã«é–¢ã—ã¦ã¯ä½•ã®å‰æã‚‚ã‚ã‚Šã¾ã›ã‚“。

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+

多é‡ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ã‚¢ã‚¯ã‚»ã‚¹

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FatFsモジュールã§ã¯å¤šé‡ã‚¢ã‚¯ã‚»ã‚¹æ©Ÿèƒ½ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“。ファイルã«å¯¾ã™ã‚‹å¤šé‡ã‚¢ã‚¯ã‚»ã‚¹ã¯ã€ãã®ã‚¢ã‚¯ã‚»ã‚¹ãƒ»ãƒ¢ãƒ¼ãƒ‰ã«ã‚ˆã£ã¦åˆ¶é™ã•ã‚Œã¾ã™ã€‚一ã¤ã®ãƒ•ã‚¡ã‚¤ãƒ«ã«å¯¾ã™ã‚‹å¤šé‡ã‚ªãƒ¼ãƒ—ンã¯ã€ãれらãŒå…¨ã¦ãƒªãƒ¼ãƒ‰ãƒ»ãƒ¢ãƒ¼ãƒ‰ã®ã¨ãã«é™ã£ã¦è¨±å¯ã•ã‚Œã¾ã™ã€‚書ãè¾¼ã¿ãƒ¢ãƒ¼ãƒ‰ã‚’å«ã‚€å¤šé‡ã‚ªãƒ¼ãƒ—ンã€ã¾ãŸé–‹ã‹ã‚Œã¦ã„るファイルã«å¯¾ã™ã‚‹ãƒªãƒãƒ¼ãƒ ã‚„消去を行ã£ã¦ã¯ãªã‚Šã¾ã›ã‚“。ã•ã‚‚ãªã„ã¨ã€ãã®ãƒœãƒªãƒ¥ãƒ¼ãƒ ã®FAT構造ãŒç ´å£Šã•ã‚Œã‚‹å¯èƒ½æ€§ãŒã‚ã‚Šã¾ã™ã€‚

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+

効率的ãªãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ã‚¢ã‚¯ã‚»ã‚¹

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å°è¦æ¨¡ãªçµ„込システムã§ã®ãƒ•ã‚¡ã‚¤ãƒ«ã®èª­ã¿æ›¸ãã«ãŠã‘る効率ã®è‰¯ã„アクセスã®ãŸã‚ã€ã‚¢ãƒ—リケーション・プログラマã¯FatFsモジュールã®ä¸­ã§ã©ã®ã‚ˆã†ãªå‡¦ç†ãŒè¡Œã‚ã‚Œã¦ã„ã‚‹ã‹è€ƒæ…®ã™ã¹ãã§ã™ã€‚ディスク上ã®ãƒ‡ãƒ¼ã‚¿ã¯f_read関数ã«ã‚ˆã‚Šæ¬¡ã®ã‚·ãƒ¼ã‚±ãƒ³ã‚¹ã§è»¢é€ã•ã‚Œã¾ã™ã€‚

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図1. セクタ・ミスアラインド・リード (ショート)
+fig.1 +

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図2. セクタ・ミスアラインド・リード (ロング)
+fig.2 +

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図3. セクタ・アラインド・リード
+fig.3 +

+

ファイルI/Oãƒãƒƒãƒ•ã‚¡ã¯ã‚»ã‚¯ã‚¿ã®ä¸€éƒ¨ã®ãƒ‡ãƒ¼ã‚¿ã‚’読ã¿æ›¸ãã™ã‚‹ãŸã‚ã®ã‚»ã‚¯ã‚¿ãƒ»ãƒãƒƒãƒ•ã‚¡ã‚’æ„味ã—ã¾ã™ã€‚セクタ・ãƒãƒƒãƒ•ã‚¡ã¯ã€ãã‚Œãžã‚Œã®ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ã‚ªãƒ–ジェクト内ã®ãƒ—ライベート・セクタ・ãƒãƒƒãƒ•ã‚¡ã¾ãŸã¯ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ã‚·ã‚¹ãƒ†ãƒ ãƒ»ã‚ªãƒ–ジェクト内ã®å…±æœ‰ã‚»ã‚¯ã‚¿ãƒ»ãƒãƒƒãƒ•ã‚¡ã®ã©ã¡ã‚‰ã‹ã§ã™ã€‚ãƒãƒƒãƒ•ã‚¡æ§‹æˆã‚ªãƒ—ションã®_FS_TINYã¯ã€ãƒ‡ãƒ¼ã‚¿è»¢é€ã«ã©ã¡ã‚‰ã‚’使ã†ã‹ã‚’決定ã—ã¾ã™ã€‚タイニー・ãƒãƒƒãƒ•ã‚¡(1)ãŒé¸æŠžã•ã‚Œã‚‹ã¨ãƒ‡ãƒ¼ã‚¿ãƒ»ãƒ¡ãƒ¢ãƒªã®æ¶ˆè²»ã¯ãã‚Œãžã‚Œã®ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ã‚ªãƒ–ジェクトã§512ãƒã‚¤ãƒˆæ¸›å°‘ã•ã‚Œã¾ã™ã€‚ã“ã®å ´åˆã€FatFsモジュールã¯ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ãƒ‡ãƒ¼ã‚¿ã®è»¢é€ã¨FAT/ディレクトリ・アクセスã«ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ã‚·ã‚¹ãƒ†ãƒ ãƒ»ã‚ªãƒ–ジェクト内ã®ã‚»ã‚¯ã‚¿ãƒ»ãƒãƒƒãƒ•ã‚¡ã ã‘を使用ã—ã¾ã™ã€‚タイニー・ãƒãƒƒãƒ•ã‚¡ã®æ¬ ç‚¹ã¯ã€ã‚»ã‚¯ã‚¿ãƒ»ãƒãƒƒãƒ•ã‚¡ã«ã‚­ãƒ£ãƒƒã‚·ãƒ¥ã•ã‚ŒãŸFATデータãŒãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ãƒ‡ãƒ¼ã‚¿ã®è»¢é€ã«ã‚ˆã‚Šå¤±ã‚ã‚Œã€ã‚¯ãƒ©ã‚¹ã‚¿å¢ƒç•Œã®æ¯Žã«ãƒªãƒ­ãƒ¼ãƒ‰ã•ã‚Œãªã‘ã‚Œã°ãªã‚‰ãªã„ã“ã¨ã§ã™ã€‚ã§ã‚‚ã€æ‚ªããªã„性能ã¨å°‘ãªã„メモリ消費ã®è¦–点ã‹ã‚‰å¤šãã®ã‚¢ãƒ—リケーションã«é©ã™ã‚‹ã§ã—ょã†ã€‚

+

図1ã¯ã‚»ã‚¯ã‚¿ã®ä¸€éƒ¨ã®ãƒ‡ãƒ¼ã‚¿ãŒãƒ•ã‚¡ã‚¤ãƒ«I/Oãƒãƒƒãƒ•ã‚¡ã‚’経由ã§è»¢é€ã•ã‚Œã‚‹ã“ã¨ã‚’示ã—ã¾ã™ã€‚図2ã«ç¤ºã•ã‚Œã‚‹é•·ã„データã®è»¢é€ã§ã¯ã€è»¢é€ãƒ‡ãƒ¼ã‚¿ã®ä¸­é–“ã®1セクタã¾ãŸã¯ãれ以上ã®ã‚»ã‚¯ã‚¿ã«ã¾ãŸãŒã‚‹è»¢é€ãƒ‡ãƒ¼ã‚¿ãŒã‚¢ãƒ—リケーション・ãƒãƒƒãƒ•ã‚¡ã«ç›´æŽ¥è»¢é€ã•ã‚Œã¦ã„ã¾ã™ã€‚図3ã¯è»¢é€ãƒ‡ãƒ¼ã‚¿å…¨ä½“ãŒã‚»ã‚¯ã‚¿å¢ƒç•Œã«ã‚¢ãƒ©ã‚¤ãƒ¡ãƒ³ãƒˆã•ã‚Œã¦ã„ã‚‹å ´åˆã‚’示ã—ã¦ã„ã¾ã™ã€‚ã“ã®å ´åˆã€ãƒ•ã‚¡ã‚¤ãƒ«I/Oãƒãƒƒãƒ•ã‚¡ã¯ä½¿ç”¨ã•ã‚Œã¾ã›ã‚“。直接転é€ã«ãŠã„ã¦ã¯æœ€å¤§ã®ç¯„囲ã®ã‚»ã‚¯ã‚¿ãŒdisk_read関数ã§ä¸€åº¦ã«èª­ã¿è¾¼ã¾ã‚Œã¾ã™ãŒã€ã‚¯ãƒ©ã‚¹ã‚¿å¢ƒç•Œã‚’越ãˆã‚‹ãƒžãƒ«ãƒãƒ»ã‚»ã‚¯ã‚¿è»¢é€ã¯ãã‚ŒãŒéš£æŽ¥ã§ã‚ã£ã¦ã‚‚è¡Œã‚ã‚Œã¾ã›ã‚“。

+

ã“ã®ã‚ˆã†ã«ã€ã‚»ã‚¯ã‚¿ã«ã‚¢ãƒ©ã‚¤ãƒ¡ãƒ³ãƒˆã—ãŸãƒ•ã‚¡ã‚¤ãƒ«ã®èª­ã¿æ›¸ãã¸ã®é…æ…®ã¯ãƒãƒƒãƒ•ã‚¡çµŒç”±ã®ãƒ‡ãƒ¼ã‚¿è»¢é€ã‚’é¿ã‘ã€èª­ã¿æ›¸ã性能ã¯æ”¹å–„ã•ã‚Œã‚‹ã§ã—ょã†ã€‚ãã®åŠ¹æžœã«åŠ ãˆã€ã‚¿ã‚¤ãƒ‹ãƒ¼æ§‹æˆã§ã‚­ãƒ£ãƒƒã‚·ãƒ¥ã•ã‚ŒãŸFATデータãŒãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ãƒ‡ãƒ¼ã‚¿ã®è»¢é€ã«ã‚ˆã‚Šãƒ•ãƒ©ãƒƒã‚·ãƒ¥ã•ã‚Œãšã€éžã‚¿ã‚¤ãƒ‹ãƒ¼æ§‹æˆã¨åŒã˜æ€§èƒ½ã‚’å°ã•ãªãƒ¡ãƒ¢ãƒªãƒ»ãƒ•ãƒƒãƒˆãƒ—リントã§é”æˆã§ãã¾ã™ã€‚

+
+ +
+

クリãƒã‚«ãƒ«ãƒ»ã‚»ã‚¯ã‚·ãƒ§ãƒ³

+

ディスク上ã®FAT構造をæ“作ã—ã¦ã„る途中ã§ã€åœé›»ã€ä¸æ­£ãªãƒ¡ãƒ‡ã‚£ã‚¢ã®å–り外ã—ã€å›žå¾©ä¸èƒ½ãªãƒ‡ãƒ¼ã‚¿ãƒ»ã‚¨ãƒ©ãƒ¼ç­‰ã®éšœå®³ãŒç™ºç”Ÿã™ã‚‹ã¨ã€å‡¦ç†ãŒä¸­é€”åŠç«¯ãªçŠ¶æ…‹ã§ä¸­æ–­ã•ã‚Œã€ãã®çµæžœã¨ã—ã¦FAT構造ãŒç ´å£Šã•ã‚Œã‚‹å¯èƒ½æ€§ãŒã‚ã‚Šã¾ã™ã€‚次ã«FatFsモジュールã«ãŠã‘るクリãƒã‚«ãƒ«ãƒ»ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã¨ã€ãã®é–“ã®éšœå®³ã«ã‚ˆã‚Šèµ·ãã†ã‚‹ã‚¨ãƒ©ãƒ¼ã®çŠ¶æ…‹ã‚’示ã—ã¾ã™ã€‚

+
+図4. é•·ã„クリãƒã‚«ãƒ«ãƒ»ã‚»ã‚¯ã‚·ãƒ§ãƒ³
+fig.4 +
+
+図5. 最å°åŒ–ã—ãŸã‚¯ãƒªãƒã‚«ãƒ«ãƒ»ã‚»ã‚¯ã‚·ãƒ§ãƒ³
+fig.5 +
+
+

赤ã§ç¤ºã—ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ã‚’実行中ã«éšœå®³ãŒç™ºç”Ÿã—ãŸå ´åˆã€ã‚¯ãƒ­ã‚¹ãƒ»ãƒªãƒ³ã‚¯ãŒç™ºç”Ÿã—ã¦æ“作対象ã®ãƒ•ã‚¡ã‚¤ãƒ«ãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªãŒå¤±ã‚れるå¯èƒ½æ€§ãŒã‚ã‚Šã¾ã™ã€‚黄色ã§ç¤ºã—ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ã‚’実行中ã«éšœå®³ãŒç™ºç”Ÿã—ãŸå ´åˆã€ã¤ãŽã®ã†ã¡ã„ãšã‚Œã‹ã¾ãŸã¯è¤‡æ•°ã®çµæžœãŒç”Ÿã˜ã‚‹å¯èƒ½æ€§ãŒã‚ã‚Šã¾ã™ã€‚

+
    +
  • 書ãæ›ãˆä¸­ã®ãƒ•ã‚¡ã‚¤ãƒ«ã®ãƒ‡ãƒ¼ã‚¿ãŒç ´å£Šã•ã‚Œã‚‹ã€‚
    • +
  • 追記中ã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒã‚ªãƒ¼ãƒ—ンå‰ã®çŠ¶æ…‹ã«æˆ»ã‚‹ã€‚
    • +
  • æ–°è¦ã«ä½œæˆã•ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«ãŒæ¶ˆãˆã‚‹ã€‚
    • +
  • æ–°è¦ã¾ãŸã¯ä¸Šæ›¸ãã§ä½œæˆã•ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«ã®é•·ã•ãŒã‚¼ãƒ­ã«ãªã£ã¦æ®‹ã‚‹ã€‚
    • +
  • ロストãƒã‚§ãƒ¼ãƒ³ã®ç™ºç”Ÿã«ã‚ˆã‚Šãƒ‡ã‚£ã‚¹ã‚¯ã®åˆ©ç”¨åŠ¹çŽ‡ãŒæ‚ªåŒ–ã™ã‚‹ã€‚
    • +
+

ã„ãšã‚Œã‚‚書ãè¾¼ã¿ä¸­ã‚„æ“作対象ã§ãªã„ファイルã«ã¯å½±éŸ¿ã¯ã‚ã‚Šã¾ã›ã‚“。ã“れらã®ã‚¯ãƒªãƒã‚«ãƒ«ãƒ»ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã¯ã€ãƒ•ã‚¡ã‚¤ãƒ«ã‚’書ãè¾¼ã¿ãƒ¢ãƒ¼ãƒ‰ã§é–‹ã„ã¦ã„る時間を最å°é™ã«ã™ã‚‹ã‹ã€f_sync()ã‚’é©å®œä½¿ç”¨ã™ã‚‹ã“ã¨ã§å›³5ã®ã‚ˆã†ã«ãƒªã‚¹ã‚¯ã‚’最å°åŒ–ã™ã‚‹ã“ã¨ãŒã§ãã¾ã™ã€‚

+
+ +
+

日本語ファイルåã®å¤§æ–‡å­—変æ›

+

CP932(Shift_JIS)ã§ã‹ã¤éžLFN構æˆã®ã¨ãã¯ã€æ‹¡å¼µæ–‡å­—ã®å°æ–‡å­—(2ãƒã‚¤ãƒˆè‹±å­—・キリル文字・ギリシャ文字)ã«å¯¾ã—ã¦å¤§æ–‡å­—変æ›ã‚’è¡Œã‚ãšã€å°æ–‡å­—ã®ã¾ã¾SFNエントリã«è¨˜éŒ²ãƒ»æ¤œç´¢ã•ã‚Œã¾ã™ã€‚ã“ã‚Œã¯æ—¥æœ¬èªžMSDOSã¨åŒã˜ä»•æ§˜ã¨ãªã‚Šã¾ã™ã€‚ã“ã®ãŸã‚ã€å…¨è§’å°æ–‡å­—ã‚’å«ã‚€ãƒ•ã‚¡ã‚¤ãƒ«ã‚’作æˆã™ã‚‹ã¨ã€NTç³»Windowsã§ãã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’é–‹ã‘ãªããªã‚Šã¾ã™ã€‚LFN構æˆã§ã¯å¤§æ–‡å­—変æ›ã‚’è¡Œã„ã¾ã™(NTç³»Windows仕様)。

+
+ +
+

Unicode入出力ã¸ã®å¯¾å¿œ

+

ファイル関数ã®ãƒ•ã‚¡ã‚¤ãƒ«å入出力ã¯ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã§ã¯ OEMコードã§ã™ãŒã€ã“れをUnicodeã«åˆ‡ã‚Šæ›¿ãˆã‚‹ã“ã¨ã‚‚ã§ãã¾ã™ã€‚詳細ã¯ã€ãƒ•ã‚¡ã‚¤ãƒ«åã‚’å‚ç…§ã—ã¦ãã ã•ã„。

+
+ +
+

FatFsã®ãƒ©ã‚¤ã‚»ãƒ³ã‚¹ã«ã¤ã„ã¦

+

ソース・ファイルã®ãƒ˜ãƒƒãƒ€ã«ãƒ©ã‚¤ã‚»ãƒ³ã‚¹æ¡ä»¶ãŒè¨˜è¿°ã•ã‚Œã¦ã„ã‚‹ã®ã§ã€åˆ©ç”¨ã®éš›ã¯ãã‚Œã«å¾“ã†ã“ã¨ã€‚英語を読ã‚ãªã„æ–¹ã®ãŸã‚ã«ä»¥ä¸‹ã«æ—¥æœ¬èªžè¨³ã‚’示ã—ã¦ãŠãã¾ã™ã€‚

+
/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.07e                    (C)ChaN, 2009
+/-----------------------------------------------------------------------------/
+/ FatFsモジュールã¯ã€å°è¦æ¨¡ãªçµ„ã¿è¾¼ã¿ã‚·ã‚¹ãƒ†ãƒ å‘ã‘ã®æ±Žç”¨FATファイルシステム・
+/ モジュールã§ã™ã€‚ã“ã‚Œã¯ãƒ•ãƒªãƒ¼ãƒ»ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢ã¨ã—ã¦ã€æ•™è‚²ãƒ»ç ”究・開発ã®ãŸã‚ã«
+/ 以下ã®ãƒ©ã‚¤ã‚»ãƒ³ã‚¹ãƒ»ãƒãƒªã‚·ãƒ¼ã®ä¸‹ã§å…¬é–‹ã•ã‚Œã¦ã„ã¾ã™ã€‚
+/
+/  Copyright (C) 2009, ChaN, all right reserved.
+/
+/ * FatFsモジュールã¯ãƒ•ãƒªãƒ¼ãƒ»ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢ã§ã‚ã‚Šã€ã¾ãŸç„¡ä¿è¨¼ã§ã™ã€‚
+/ * 用途ã«åˆ¶é™ã¯ã‚ã‚Šã¾ã›ã‚“。ã‚ãªãŸã®è²¬ä»»ã®ä¸‹ã«ãŠã„ã¦ã€å€‹äººçš„・éžå–¶åˆ©çš„ãª
+/   ã‚‚ã®ã‹ã‚‰å•†ç”¨è£½å“ã®é–‹ç™ºã«åŠã¶ç›®çš„ã«ä½¿ç”¨ãƒ»æ”¹å¤‰ãƒ»å†é…布ã™ã‚‹ã“ã¨ãŒã§ãã¾ã™ã€‚
+/ * ソース・コードをå†é…布ã™ã‚‹ã¨ãã¯ã€ä¸Šè¨˜ã®è‘—作権表示をä¿æŒã—ãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。
+/
+/-----------------------------------------------------------------------------/
+

è¦ã™ã‚‹ã«FatFsã¯ã‚¿ãƒ€ã§è‡ªç”±ã«ä½¿ãˆã‚‹ã¨ã„ã†ã“ã¨ã§ã™ã€‚ソース・コードをå†é…布ã™ã‚‹ã¨ãã¯ã€ã“ã®ãƒ–ロックをãã®ã¾ã¾ä¿æŒã—ã¦ãŠãã“ã¨ã€‚ã“ã®ã‚ˆã†ã«FatFsã¯BSDライクãªãƒ©ã‚¤ã‚»ãƒ³ã‚¹ã¨ã—ã¦ã„ã¾ã™ãŒã€ä¸€ã¤å¤§ããªé•ã„ãŒã‚ã‚Šã¾ã™ã€‚特ã«çµ„ã¿è¾¼ã¿ç”¨é€”ã§ã®åˆ©ç”¨ä¾¡å€¤ã‚’高ã‚ã‚‹ãŸã‚ã€ãƒã‚¤ãƒŠãƒªå½¢å¼(ソース・コードをå«ã¾ãªã„å½¢å¼å…¨ã¦)ã§ã®å†é…布ã«ã¤ã„ã¦ã¯ã€æ¡ä»¶ã¯è¨­ã‘ã¦ã„ã¾ã›ã‚“。ãã®å ´åˆã¯ã€FatFsãŠã‚ˆã³ãã®ãƒ©ã‚¤ã‚»ãƒ³ã‚¹æ–‡æ›¸ã«ã¤ã„ã¦ã¯ãƒ‰ã‚­ãƒ¥ãƒ¡ãƒ³ãƒˆã«æ˜Žè¨˜ã—ã¦ã‚‚ã—ãªãã¦ã‚‚ã‹ã¾ã„ã¾ã›ã‚“。もã¡ã‚ã‚“GNU GPLプロジェクトã¨ã‚‚共存å¯èƒ½ã§ã™ã€‚何らã‹ã®å¤‰æ›´ã‚’加ãˆã¦å†é…布ã™ã‚‹éš›ã¯ã€ä»–ã®ãƒ©ã‚¤ã‚»ãƒ³ã‚¹(GNU GPLã‹BSDライセンス)ã«å¤‰æ›´ã™ã‚‹ã“ã¨ã‚‚å¯èƒ½ã§ã™ã€‚

+
+ +

戻る

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chdir.html new file mode 100644 index 0000000..6a72931 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chdir.html @@ -0,0 +1,91 @@ + + + + + + + +FatFs - f_chdir + + + + +
+

f_chdir

+

ƒJƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚ð•ÏX‚µ‚Ü‚·B

+
+FRESULT f_chdir (
+  const XCHAR* Path /* ƒfƒBƒŒƒNƒgƒŠ–¼‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
Path
+
ˆÚ“®‘Îۂ̃fƒBƒŒƒNƒgƒŠ‚̃pƒX–¼‚Ì“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_FILE
+
ƒtƒ@ƒCƒ‹‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ª—^‚¦‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

f_chdirŠÖ”‚ÍŠeƒ{ƒŠƒ…[ƒ€‚̃JƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚ð•ÏX‚µ‚Ü‚·BƒJƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚̓tƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg‚̉Šú‰»‚ªs‚í‚ꂽ‚Æ‚«Aƒ‹[ƒgEƒfƒBƒŒƒNƒgƒŠ‚Éݒ肳‚ê‚Ü‚·BƒJƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚ÍAƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg‚É‹L˜^‚³‚ê‚邽‚ßA‚»‚̃{ƒŠƒ…[ƒ€‚ðŽg—p‚·‚é‘S‚Ẵ^ƒXƒN‚ɑ΂µ‚ĉe‹¿‚ð—^‚¦‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_RPATH == 1‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Æ‚È‚è‚Ü‚·B

+
+ + +
+

ƒTƒ“ƒvƒ‹EƒR[ƒh

+
+    // ƒJƒŒƒ“ƒgEƒhƒ‰ƒCƒu‚̃JƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚ð•ÏX (ƒ‹[ƒg‰º‚Ìdir1‚Ö)
+    f_chdir("/dir1");
+
+    // ƒhƒ‰ƒCƒu2‚̃JƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚ð•ÏX (eƒfƒBƒŒƒNƒgƒŠ‚Ö)
+    f_chdir("2:..");
+
+
+ +
+

ŽQÆ

+

f_chdrive

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chdrive.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chdrive.html new file mode 100644 index 0000000..cd0f31b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chdrive.html @@ -0,0 +1,62 @@ + + + + + + + +FatFs - f_chdrive + + + + +
+

f_chdrive

+

ƒJƒŒƒ“ƒgEƒhƒ‰ƒCƒu‚ð•ÏX‚µ‚Ü‚·B

+
+FRESULT f_chdrive (
+  BYTE Drive /* ˜_—ƒhƒ‰ƒCƒu”Ô† */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
ƒJƒŒƒ“ƒgEƒhƒ‰ƒCƒu‚ÉÝ’è‚·‚é˜_—ƒhƒ‰ƒCƒu”Ô†‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
+
+ + +
+

‰ðà

+

f_chdriveŠÖ”‚̓JƒŒƒ“ƒgEƒhƒ‰ƒCƒu‚ð•ÏX‚µ‚Ü‚·BƒVƒXƒeƒ€‹N“®Žž‚̉Šú’l‚Í0‚Å‚·B‚±‚ÌÝ’è‚ÍFatFsƒ‚ƒWƒ…[ƒ‹‚ÌÓI•Ï”‚É‹L˜^‚³‚ê‚邽‚ßA‘S‚Ẵ^ƒXƒN‚ɑ΂µ‚ĉe‹¿‚ð—^‚¦‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_RPATH == 1‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Æ‚È‚è‚Ü‚·B

+
+ + +
+

ŽQÆ

+

f_chdir

+
+ +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chmod.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chmod.html new file mode 100644 index 0000000..34fd695 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/chmod.html @@ -0,0 +1,97 @@ + + + + + + + +FatFs - f_chmod + + + + +
+

f_chmod

+

ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚Ì‘®«‚ð•ÏX‚µ‚Ü‚·B

+
+FRESULT f_chmod (
+  const XCHAR* FileName, /* ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ–¼‚ւ̃|ƒCƒ“ƒ^ */
+  BYTE Attribute,        /* Ý’è’l */
+  BYTE AttributeMask     /* •ÏXƒ}ƒXƒN */
+);
+
+
+ +
+

ˆø”

+
+
FileName
+
‘®«•ÏX‘Îۂ̃tƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚̃pƒX–¼‚Ì“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ðŽw’肵‚Ü‚·B
+
Attribute
+
Ý’è‚·‚é‘®«BŽw’è‰Â”\‚È‘®«‚ÍŽŸ‚Ì’Ê‚è‚ÅA‚±‚ê‚ç‚Ì‘g‚݇‚킹‚ÅŽw’肵‚Ü‚·BŽw’肳‚ê‚È‚©‚Á‚½‘®«‚͉𜂳‚ê‚Ü‚·B
+ + + + + + +
’lˆÓ–¡
AM_RDOƒŠ[ƒhEƒIƒ“ƒŠ[
AM_ARCƒA[ƒJƒCƒu
AM_SYSƒVƒXƒeƒ€
AM_HIDƒqƒhƒDƒ“
+
+
AttributeMask
+
•ÏX‚·‚é‘®«‚̃}ƒXƒNBŽw’肵‚½‘®«‚ªÝ’è‚Ü‚½‚͉𜂳‚êAŽw’肳‚ê‚È‚©‚Á‚½‘®«‚Íó‘Ô‚ª•ÛŽ‚³‚ê‚Ü‚·BAttribute‚Æ“¯‚¶’l‚ðŽg‚¢‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_FILE
+
ƒtƒ@ƒCƒ‹‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ª—^‚¦‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚Ì‘®«‚ð•ÏX‚µ‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—á

+
+    /* ƒŠ[ƒhƒIƒ“ƒŠ[‚ðƒZƒbƒgAƒA[ƒJƒCƒu‚ðƒNƒŠƒAA‚»‚Ì‘¼‚Í•ÏX‚µ‚È‚¢ */
+    f_chmod("file.txt", AM_RDO, AM_RDO | AM_ARC);
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/close.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/close.html new file mode 100644 index 0000000..dfa5eec --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/close.html @@ -0,0 +1,68 @@ + + + + + + + +FatFs - f_close + + + + +
+

f_close

+

ƒtƒ@ƒCƒ‹‚ð•Â‚¶‚Ü‚·B

+
+FRESULT f_close (
+  FIL* FileObject     /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
•Â‚¶‚悤‚Æ‚·‚éƒtƒ@ƒCƒ‹‚̃tƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

ƒtƒ@ƒCƒ‹‚ð•Â‚¶‚Ü‚·B‘‚«ž‚Ý‚Ìs‚í‚ꂽƒtƒ@ƒCƒ‹‚Ìê‡AƒLƒƒƒbƒVƒ…‚³‚ꂽó‘ÔiR/Wƒoƒbƒtƒ@ã‚̃f[ƒ^A•ÏX‚³‚ꂽFAT‚âƒfƒBƒŒƒNƒgƒŠ€–Új‚̓fƒBƒXƒN‚É‘‚«–ß‚³‚ê‚Ü‚·BŠÖ”‚ª³íI—¹‚·‚é‚ÆA‚»‚̃tƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚Í–³Œø‚É‚È‚èA‚»‚̃ƒ‚ƒŠ‚à‰ð•ú‚Å‚«‚Ü‚·B“Ç‚Ýž‚Ýê—pƒ‚[ƒh‚ÅŠJ‚©‚ꂽƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ÍA‚±‚ÌŠÖ”‚É‚æ‚éƒNƒ[ƒYˆ—‚ðŒo‚¸‚É”jŠü‚·‚邱‚Æ‚à‚Å‚«‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

‘S‚Ä‚Ì\¬‚ÅŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+f_open, f_read, f_write, f_sync, FIL, FATFS +
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dinit.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dinit.html new file mode 100644 index 0000000..4cba323 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dinit.html @@ -0,0 +1,45 @@ + + + + + + + +FatFs - disk_initialize + + + + +
+

disk_initialize

+

ƒfƒBƒXƒNEƒhƒ‰ƒCƒu‚ð‰Šú‰»‚µ‚Ü‚·B

+
+DSTATUS disk_initialize (
+  BYTE Drive      /* •¨—ƒhƒ‰ƒCƒu”Ô† */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
‰Šú‰»‚·‚镨—ƒhƒ‰ƒCƒu”Ô†(0-9)‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+

‚±‚ÌŠÖ”‚Í–ß‚è’l‚Æ‚µ‚ăfƒBƒXƒNEƒXƒe[ƒ^ƒX‚ð•Ô‚µ‚Ü‚·BƒfƒBƒXƒNEƒXƒe[ƒ^ƒX‚ÌÚׂɊւµ‚Ä‚Ídisk_status()‚ðŽQÆ‚µ‚Ä‚­‚¾‚³‚¢B

+
+ +
+

‰ðà

+

ƒfƒBƒXƒNEƒhƒ‰ƒCƒu‚ð‰Šú‰»‚µ‚Ü‚·BŠÖ”‚ª¬Œ÷‚·‚é‚ÆA–ß‚è’l‚ÌSTA_NOINITƒtƒ‰ƒO‚ªƒNƒŠƒA‚³‚ê‚Ü‚·B

+

FatFsƒ‚ƒWƒ…[ƒ‹‚ÍAŽ©“®ƒ}ƒEƒ“ƒg“®ì‚É‚æ‚è•K—v‚ɉž‚¶‚Ä‚±‚ÌŠÖ”‚ðŒÄ‚Ño‚µ‚Ü‚·BFatFsƒ‚ƒWƒ…[ƒ‹Žg—p’†‚̓AƒvƒŠƒP[ƒVƒ‡ƒ“‚©‚炱‚ÌŠÖ”‚ðŒÄ‚Ño‚µ‚Ä‚Í‚È‚è‚Ü‚¹‚ñB‚³‚à‚È‚¢‚ÆFAT\‘¢‚ª”j‰ó‚³‚ê‚é‰Â”\«‚ª‚ ‚è‚Ü‚·BƒGƒ‰[“™‚É‚æ‚èĉŠú‰»‚ª•K—v‚È‚Æ‚«‚ÍAf_mount()‚ðŽg—p‚µ‚Ü‚·B

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dioctl.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dioctl.html new file mode 100644 index 0000000..af5f4b3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dioctl.html @@ -0,0 +1,67 @@ + + + + + + + +FatFs - disk_ioctl + + + + +
+

disk_ioctl

+

ƒZƒNƒ^‚Ì“Ç‚Ý‘‚«ˆÈŠO‚̃fƒBƒXƒNEƒhƒ‰ƒCƒuŽ©‘̂ɑ΂·‚é—lX‚ȧŒä‚ð‚µ‚Ü‚·B

+
+DRESULT disk_ioctl (
+  BYTE Drive,      /* •¨—ƒhƒ‰ƒCƒu”Ô† */
+  BYTE Command,    /* §ŒäƒRƒ}ƒ“ƒh */
+  void* Buffer     /* ƒf[ƒ^Žó‚¯“n‚µƒoƒbƒtƒ@ */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
•¨—ƒhƒ‰ƒCƒu”Ô†(0-9)‚ðŽw’肵‚Ü‚·B
+
Command
+
§ŒäƒRƒ}ƒ“ƒhEƒR[ƒh‚ðŽw’肵‚Ü‚·B
+
Buffer
+
§ŒäƒRƒ}ƒ“ƒh‚Ɉˑ¶‚µ‚½ƒpƒ‰ƒ[ƒ^‚ðŽöŽó‚·‚éƒoƒbƒtƒ@‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·Bƒoƒbƒtƒ@‚ðŽg—p‚µ‚È‚¢ƒRƒ}ƒ“ƒh‚ÌꇂÍANULL‚ðŽw’肵‚Ü‚·B
+
+
+ +
+

–ß‚è’l

+
+
RES_OK (0)
+
³íI—¹B
+
RES_ERROR
+
‰½‚ç‚©‚̃Gƒ‰[‚ª”­¶‚µ‚½B
+
RES_PARERR
+
ƒRƒ}ƒ“ƒh‚ª•s³B
+
RES_NOTRDY
+
ƒhƒ‰ƒCƒu‚ª“®ì‰Â”\ó‘Ô‚Å‚Í‚È‚¢A‚Ü‚½‚͉Šú‰»‚³‚ê‚Ä‚¢‚È‚¢B
+
+
+ +
+

‰ðà

+

•¨—ƒhƒ‰ƒCƒu‚ÌŽí—Þ‚É‚æ‚èƒTƒ|[ƒg‚³‚ê‚éƒRƒ}ƒ“ƒh‚͈قȂè‚Ü‚·‚ªAFatFsƒ‚ƒWƒ…[ƒ‹‚Å‚ÍAŽŸ‚̔ėpƒRƒ}ƒ“ƒh‚Ì‚ÝŽg—p‚µAƒhƒ‰ƒCƒu‚ÌŽí—ނɈˑ¶‚µ‚½§Œä‚Ís‚¢‚Ü‚¹‚ñB

+

‚±‚ÌŠÖ”‚̓Š[ƒhEƒIƒ“ƒŠ[\¬‚Å‚Í•K—v‚Æ‚³‚ê‚Ü‚¹‚ñB

+ + + + + + +
ƒRƒ}ƒ“ƒh‰ðà
CTRL_SYNCƒhƒ‰ƒCƒu‚ªƒf[ƒ^‚Ì‘‚«ž‚Ý‚ðŠ®—¹‚·‚é‚Ì‚ð‘Ò‚¿‚Ü‚·Bƒ‰ƒCƒgEƒoƒbƒNEƒLƒƒƒbƒVƒ…‚ª‚ ‚éꇂÍA‘‚«ž‚Ü‚ê‚Ä‚¢‚È‚¢ƒf[ƒ^‚𑦎ž‘‚«–ß‚µ‚Ü‚·B
GET_SECTOR_SIZEBuffer‚ÌŽw‚·WORD•Ï”‚Ƀhƒ‰ƒCƒu‚̃ZƒNƒ^EƒTƒCƒY‚ð•Ô‚µ‚Ü‚·B_MAX_SS‚ª1024ˆÈã‚Ì‚Æ‚«•K—v‚Æ‚³‚ê‚Ü‚·B
GET_SECTOR_COUNTBuffer‚ÌŽw‚·DWORD•Ï”‚Ƀhƒ‰ƒCƒuã‚Ì‘ƒZƒNƒ^”‚ð•Ô‚µ‚Ü‚·Bf_mkfs“à‚Å‚Ì‚ÝŽg—pB
GET_BLOCK_SIZEBuffer‚ÌŽw‚·DWORD•Ï”‚Ƀƒ‚ƒŠEƒAƒŒ[‚ÌÁ‹ŽƒuƒƒbƒNƒTƒCƒY‚ðƒZƒNƒ^’PˆÊ‚Å•Ô‚µ‚Ü‚·B•s–¾‚Èꇂ܂½‚ÍHDD‚Å‚Í1‚ð•Ô‚µ‚Ü‚·Bf_mkfs“à‚Å‚Ì‚ÝŽg—pB
+
+ + +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dread.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dread.html new file mode 100644 index 0000000..5baf770 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dread.html @@ -0,0 +1,58 @@ + + + + + + + +FatFs - disk_read + + + + +
+

disk_read

+

ƒfƒBƒXƒN‚©‚çƒZƒNƒ^‚ð“Ç‚Ýo‚µ‚Ü‚·B

+
+DRESULT disk_read (
+  BYTE Drive,          /* •¨—ƒhƒ‰ƒCƒu”Ô† */
+  BYTE* Buffer,        /* “Ç‚Ýo‚µƒoƒbƒtƒ@‚ւ̃|ƒCƒ“ƒ^ */
+  DWORD SectorNumber,  /* “Ç‚Ýo‚µŠJŽnƒZƒNƒ^”Ô† */
+  BYTE SectorCount     /* “Ç‚Ýo‚µƒZƒNƒ^” */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
•¨—ƒhƒ‰ƒCƒu”Ô†(0-9)‚ðŽw’肵‚Ü‚·B
+
Buffer
+
ƒfƒBƒXƒN‚©‚ç“Ç‚Ýo‚µ‚½ƒf[ƒ^‚ðŠi”[‚·‚éƒoƒCƒg”z—ñ‚ÅA“Ç‚Ýo‚³‚ê‚éƒoƒCƒg”•ª‚̃TƒCƒY‚ª•K—v‚Å‚·BƒAƒhƒŒƒX‚̓Aƒ‰ƒCƒƒ“ƒg‚³‚ê‚Ä‚¢‚é‚Æ‚ÍŒÀ‚è‚Ü‚¹‚ñB
+
SectorNumber
+
“Ç‚Ýo‚µ‚ðŠJŽn‚·‚éƒZƒNƒ^”Ô†BLBA‚ÅŽw’肵‚Ü‚·B
+
SectorCount
+
“Ç‚Ýo‚·ƒZƒNƒ^”B 1`255‚͈̔͂Åݒ肵‚Ü‚·
+
+
+ + +
+

–ß‚è’l

+
+
RES_OK (0)
+
³íI—¹B
+
RES_ERROR
+
“Ç‚Ýž‚Ý’†‚ɃGƒ‰[‚ª”­¶‚µA‚»‚̉ñ•œ‚É‚àŽ¸”s‚µ‚½B
+
RES_PARERR
+
ƒpƒ‰ƒ[ƒ^‚ª•s³B
+
RES_NOTRDY
+
ƒhƒ‰ƒCƒu‚ª“®ì‰Â”\ó‘Ô‚Å‚Í‚È‚¢i‰Šú‰»‚³‚ê‚Ä‚¢‚È‚¢jB
+
+
+ + +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dstat.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dstat.html new file mode 100644 index 0000000..9e04ccb --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dstat.html @@ -0,0 +1,47 @@ + + + + + + + +FatFs - disk_status + + + + +
+

disk_status

+

ƒfƒBƒXƒNEƒhƒ‰ƒCƒu‚Ìó‘Ô‚ðŽæ“¾‚µ‚Ü‚·B

+
+DSTATUS disk_status (
+  BYTE Drive           /* •¨—ƒhƒ‰ƒCƒu”Ô† */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
ƒXƒe[ƒ^ƒX‚ðŽæ“¾‚·‚镨—ƒhƒ‰ƒCƒu”Ô†‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+

•¨—ƒhƒ‰ƒCƒu‚Ìó‘Ô‚ªŽŸ‚̃tƒ‰ƒO‚Ì‘g‚݇‚킹‚Ì’l‚Å•Ô‚³‚ê‚Ü‚·B

+
+
STA_NOINIT
+
ƒhƒ‰ƒCƒu‚ª‰Šú‰»‚³‚ê‚Ä‚¢‚È‚¢‚±‚Æ‚ðŽ¦‚·ƒtƒ‰ƒOBƒVƒXƒeƒ€EƒŠƒZƒbƒg‚⃃fƒBƒA‚ÌŽæ‚èŠO‚µ“™‚ŃZƒbƒg‚³‚êAdisk_initialize() ‚̳íI—¹‚ŃNƒŠƒAAŽ¸”s‚ŃZƒbƒg‚³‚ê‚Ü‚·B
+
STA_NODISK
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚±‚Æ‚ðŽ¦‚·ƒtƒ‰ƒOBƒƒfƒBƒA‚ªŽæ‚èŠO‚³‚ê‚Ä‚¢‚éŠÔ‚̓Zƒbƒg‚³‚êAƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚éŠÔ‚̓NƒŠƒA‚³‚ê‚Ü‚·BŒÅ’èƒfƒBƒXƒN‚Å‚Íí‚ɃNƒŠƒA‚³‚ê‚Ä‚¢‚Ü‚·B
+
STA_PROTECTED
+
ƒƒfƒBƒA‚ªƒ‰ƒCƒgEƒvƒƒeƒNƒg‚³‚ê‚Ä‚¢‚邱‚Æ‚ðŽ¦‚·ƒtƒ‰ƒOBƒ‰ƒCƒgEƒvƒƒeƒNƒg‹@”\‚ðƒTƒ|[ƒg‚µ‚È‚¢ƒƒfƒBƒA‚Å‚Íí‚ɃNƒŠƒA‚³‚ê‚Ä‚¢‚Ü‚·B
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dwrite.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dwrite.html new file mode 100644 index 0000000..821989c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/dwrite.html @@ -0,0 +1,66 @@ + + + + + + + +FatFs - disk_write + + + + +
+

disk_write

+

ƒfƒBƒXƒN‚Ƀf[ƒ^‚ð‘‚«ž‚Ý‚Ü‚·B

+
+DRESULT disk_write (
+  BYTE Drive,          /* •¨—ƒhƒ‰ƒCƒu”Ô† */
+  const BYTE* Buffer,  /* ‘‚«ž‚Þƒf[ƒ^‚ւ̃|ƒCƒ“ƒ^ */
+  DWORD SectorNumber,  /* ‘‚«ž‚ÝŠJŽnƒZƒNƒ^”Ô† */
+  BYTE SectorCount     /* ‘‚«ž‚݃ZƒNƒ^” */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
•¨—ƒhƒ‰ƒCƒu”Ô†(0-9)‚ðŽw’肵‚Ü‚·B
+
Buffer
+
ƒfƒBƒXƒN‚É‘‚«ž‚ÞƒoƒCƒg”z—ñ‚ðŽw’肵‚Ü‚·BƒAƒhƒŒƒX‚̓Aƒ‰ƒCƒƒ“ƒg‚³‚ê‚Ä‚¢‚é‚Æ‚ÍŒÀ‚è‚Ü‚¹‚ñB
+
SectorNumber
+
‘‚«ž‚Ý‚ðŠJŽn‚·‚éƒZƒNƒ^”Ô†BLBA‚ÅŽw’肵‚Ü‚·B
+
SectorCount
+
‘‚«ž‚ÞƒZƒNƒ^”B 1`255‚Åݒ肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
RES_OK (0)
+
³íI—¹B
+
RES_ERROR
+
‘‚«ž‚Ý’†‚ɃGƒ‰[‚ª”­¶‚µA‚»‚̉ñ•œ‚É‚àŽ¸”s‚µ‚½B
+
RES_WRPRT
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
RES_PARERR
+
ƒpƒ‰ƒ[ƒ^‚ª•s³B
+
RES_NOTRDY
+
ƒhƒ‰ƒCƒu‚ª“®ì‰Â”\ó‘Ô‚Å‚Í‚È‚¢i‰Šú‰»‚³‚ê‚Ä‚¢‚È‚¢jB
+
+
+ + +
+

‰ðà

+

ƒŠ[ƒhEƒIƒ“ƒŠ[\¬‚Å‚Í‚±‚ÌŠÖ”‚Í•K—v‚Æ‚³‚ê‚Ü‚¹‚ñB

+
+ + +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/fattime.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/fattime.html new file mode 100644 index 0000000..d627a12 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/fattime.html @@ -0,0 +1,50 @@ + + + + + + + +FatFs - get_fattime + + + + +
+

get_fattime

+

Œ»ÝŽž‚ðŽæ“¾‚µ‚Ü‚·B

+
+DWORD get_fattime (void);
+
+
+ + +
+

–ß‚è’l

+

Œ»Ý‚̃[ƒJƒ‹Eƒ^ƒCƒ€‚ªDWORD’l‚ɃpƒbƒN‚³‚ê‚Ä•Ô‚³‚ê‚Ü‚·BƒrƒbƒgEƒtƒB[ƒ‹ƒh‚ÍŽŸ‚ÉŽ¦‚·‚悤‚É‚È‚è‚Ü‚·B

+
+
bit31:25
+
1980”N‚ð‹N“_‚Æ‚µ‚½”N‚ª 0..127 ‚Å“ü‚è‚Ü‚·B
+
bit24:21
+
ŒŽ‚ª 1..12 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit20:16
+
“ú‚ª 1..31 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit15:11
+
Žž‚ª 0..23 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit10:5
+
•ª‚ª 0..59 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit4:0
+
•b/2‚ª 0..29 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
+
+ + +
+

‰ðà

+

RTC‚ðƒTƒ|[ƒg‚µ‚È‚¢ƒVƒXƒeƒ€‚Å‚àA‰½‚ç‚©‚Ì“ú•t‚Æ‚µ‚Ä—LŒø‚È’l‚ð•Ô‚³‚È‚¯‚ê‚΂Ȃè‚Ü‚¹‚ñB0‚ð•Ô‚µ‚½ê‡A‚»‚̃tƒ@ƒCƒ‹‚Í“ú•t‚ðŽ‚¿‚Ü‚¹‚ñBƒŠ[ƒhEƒIƒ“ƒŠ[\¬‚Å‚Í‚±‚ÌŠÖ”‚Í•K—v‚Æ‚³‚ê‚Ü‚¹‚ñB

+
+ + +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/filename.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/filename.html new file mode 100644 index 0000000..0e9fd99 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/filename.html @@ -0,0 +1,67 @@ + + + + + + + +FatFs - ファイル・ディレクトリã®æŒ‡å®šæ–¹æ³• + + + +
+

ファイル・ディレクトリã®æŒ‡å®šæ–¹æ³•

+

FatFsモジュールã§ã®ãƒ•ã‚¡ã‚¤ãƒ«ã€ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªã€ãƒ‰ãƒ©ã‚¤ãƒ–ã®æŒ‡å®šæ–¹æ³•ã¯DOS/Windowsã¨ã»ã¼åŒã˜ã§ã™ã€‚パスåã®ãƒ•ã‚©ãƒ¼ãƒžãƒƒãƒˆã¯æ¬¡ã®é€šã‚Šã§ã™ã€‚

+
+ "[è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–番å·:][/]ディレクトリå/ファイルå"
+
+

FatFsモジュールã¯é•·ã„ファイルå(LFN)ãŠã‚ˆã³8.3å½¢å¼ãƒ•ã‚¡ã‚¤ãƒ«å(SFN)ã«å¯¾å¿œã—ã¦ã„ã¾ã™ã€‚LFNã¯ã€(_USE_LFN > 0)ã®ã¨ã使用å¯èƒ½ã«ãªã‚Šã¾ã™ã€‚DOS/Windowsã¨ã®é•ã„ã¯ã€ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªãƒ»ã‚»ãƒ‘レータã¨è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–番å·ã®æŒ‡å®šã§ã™ã€‚ディレクトリ・セパレータã«ã¯ / ã¾ãŸã¯ \ を使用ã—ã¾ã™ã€‚è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–番å·ã¯ã€'0'～'9'ã®ä¸€æ–‡å­—ã®æ•°å­—ã¨ã‚³ãƒ­ãƒ³ã§æŒ‡å®šã—ã€çœç•¥ã—ãŸå ´åˆã¯ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆãƒ»ãƒ‰ãƒ©ã‚¤ãƒ–(0ã¾ãŸã¯ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‰ãƒ©ã‚¤ãƒ–)ãŒé¸æŠžã•ã‚Œã¾ã™ã€‚パスåã«å…ˆè¡Œã‚ã‚‹ã„ã¯ä¸­ã«å«ã¾ã‚Œã‚‹ã‚¹ãƒšãƒ¼ã‚¹ã¯ã€LFN構æˆã§ã¯åå‰ã®ä¸€éƒ¨ã¨ã—ã¦æœ‰åŠ¹ã§ã™ãŒã€éžLFN構æˆã§ã¯ãƒ‘スåã®çµ‚端ã¨ã—ã¦èªè­˜ã•ã‚Œã¾ã™ã€‚

+

標準構æˆ(_FS_RPATH == 0)ã®ã¨ãã¯ã€å…¨ã¦ã®ã‚ªãƒ–ジェクトãŒãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªã‹ã‚‰è¾¿ã‚‹çµ¶å¯¾ãƒ‘スã§æŒ‡å®šã•ã‚Œã¾ã™ã€‚OS指å‘ãªã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªã¨ã„ã†æ¦‚念ã¯ç„¡ãã€ã¾ãŸãƒ‰ãƒƒãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª("."ã‚„"..")ã¯ä½¿ç”¨ã§ãã¾ã›ã‚“。パスå先頭ã®ã‚»ãƒ‘レータã¯ç„¡è¦–ã•ã‚Œã¾ã™ã€‚デフォルト・ドライブ番å·ã¯å¸¸ã«0ã«ãªã‚Šã¾ã™ã€‚

+

相対パスを有効(_FS_RPATH == 1)ã«ã—ãŸã¨ãã¯ã€å…ˆè¡Œã™ã‚‹ã‚»ãƒ‘レータã®æœ‰ç„¡ã«ã‚ˆã£ã¦æ¤œç´¢é–‹å§‹ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªãŒå¤‰ã‚ã‚Šã€ã‚»ãƒ‘レータãŒã‚ã‚‹å ´åˆã¯ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªã‹ã‚‰ã€ç„¡ã„å ´åˆã¯f_chdir関数ã§è¨­å®šã•ã‚Œã‚‹ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªã‹ã‚‰ã«ãªã‚Šã¾ã™ã€‚ã¾ãŸãƒ‘スåã«ãƒ‰ãƒƒãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªãŒä½¿ç”¨ã§ãã¾ã™ã€‚デフォルト・ドライブ番å·ã¯f_chdrive関数ã§è¨­å®šã•ã‚ŒãŸå€¤ã¨ãªã‚Šã¾ã™ã€‚

+ + + + + + + + + + + + + +
パスå_FS_RPATH == 0_FS_RPATH == 1
file.txtドライブ0ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªä¸‹ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‰ãƒ©ã‚¤ãƒ–ã®ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªä¸‹ã®ãƒ•ã‚¡ã‚¤ãƒ«
/file.txtドライブ0ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªä¸‹ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‰ãƒ©ã‚¤ãƒ–ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªä¸‹ã®ãƒ•ã‚¡ã‚¤ãƒ«
ドライブ0ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‰ãƒ©ã‚¤ãƒ–ã®ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª
2:ドライブ2ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªãƒ‰ãƒ©ã‚¤ãƒ–2ã®ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª
2:file1.txtドライブ2ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªä¸‹ã®ãƒ•ã‚¡ã‚¤ãƒ«ãƒ‰ãƒ©ã‚¤ãƒ–2ã®ã‚«ãƒ¬ãƒ³ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªä¸‹ã®ãƒ•ã‚¡ã‚¤ãƒ«
2:/ドライブ2ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒªãƒ‰ãƒ©ã‚¤ãƒ–2ã®ãƒ«ãƒ¼ãƒˆãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª
../file.txt無効親ディレクトリ下ã®ãƒ•ã‚¡ã‚¤ãƒ«
.無効ã“ã®ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª
..無効カレント・ディレクトリã®è¦ªãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª
dir1/..無効カレント・ディレクトリ
/..無効無効(ルート・ディレクトリã§ã¯ãƒ‰ãƒƒãƒˆåã¯ä½¿ç”¨ä¸å¯)
+
+ +


+
+

Unicode API

+

ファイル関数ã®å…¥å‡ºåŠ›ã®ã†ã¡ãƒ•ã‚¡ã‚¤ãƒ«åやパスåを指定ã™ã‚‹å¼•æ•°ã®åž‹ã¯ã€XCHARã§å®šç¾©ã•ã‚Œã¦ã„ã¾ã™ãŒã€ã“ã‚Œã¯charã®ã‚¨ãƒªã‚¢ã‚¹ã«ãªã£ã¦ã„ã¾ã™ã€‚ãã—ã¦ã€_CODE_PAGEã§æŒ‡å®šã•ã‚Œã‚‹ OEMコード(SBCSã¾ãŸã¯DBCS)ã®æ–‡å­—列ã¨ã—ã¦æ‰±ã‚ã‚Œã¾ã™ã€‚ファイルå入出力をUnicodeã¨ã™ã‚‹æ§‹æˆ(LFN構æˆã§ã€ã‹ã¤_LFN_UNICODEã‚’ 1)ã«ã—ãŸã¨ãã¯ã€XCHARã¯ãƒ¯ã‚¤ãƒ‰æ–‡å­—(unsigned short)ã«åˆ‡ã‚Šæ›¿ã‚ã‚Šã€ãƒ‘スåã«Unicodeを使用ã™ã‚‹ã‚ˆã†ã«ãªã‚Šã¾ã™ã€‚ã“ã‚Œã«ã‚ˆã‚Š LFNフル対応ã¨ãªã‚Šã€OEMコードã«ãªã„文字(ãŸã¨ãˆã° âœâ˜ªâœ¡â˜¸â˜­ãªã©)も使用ã§ãã¾ã™ã€‚

+
+ +


+
+

è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–(ボリューム)ã¨ç‰©ç†ãƒ‰ãƒ©ã‚¤ãƒ–(ディスク装置)ã®å¯¾å¿œ

+

デフォルトã®æ§‹æˆã§ã¯ã€ãã‚Œãžã‚Œã®è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã¯åŒã˜ç•ªå·ã®ç‰©ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã«1:1ã§çµã³ã¤ã‘られã¦ã„ã¦ã€ç‰©ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã®å…ˆé ­ã®åŒºç”»ãŒãƒžã‚¦ãƒ³ãƒˆã•ã‚Œã¾ã™ã€‚_MULTI_PARTITIONã« 1を指定ã™ã‚‹ã¨ã€è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã«å¯¾ã—ã¦å€‹åˆ¥ã«ç‰©ç†ãƒ‰ãƒ©ã‚¤ãƒ–番å·ãƒ»åŒºç”»ã‚’指定ã§ãるよã†ã«ãªã‚Šã¾ã™ã€‚ã“ã®æ§‹æˆã§ã¯ã€è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã¨åŒºç”»ã®å¯¾å¿œã‚’解決ã™ã‚‹ãŸã‚ã®ãƒ†ãƒ¼ãƒ–ルを次ã«ç¤ºã™ã‚ˆã†ã«å®šç¾©ã™ã‚‹å¿…è¦ãŒã‚ã‚Šã¾ã™ã€‚

+
+例:è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–0～2を物ç†ãƒ‰ãƒ©ã‚¤ãƒ–0(固定ディスク)ã®3ã¤ã®åŸºæœ¬åŒºç”»ã«å‰²ã‚Šå½“ã¦ã€
+   è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–3を物ç†ãƒ‰ãƒ©ã‚¤ãƒ–1(リムーãƒãƒ–ル・ディスク)ã«å‰²ã‚Šå½“ã¦ã‚‹å ´åˆã€‚
+
+const PARTITION Drives[] = {
+    {0, 0},     /* Logical drive 0 ==> Physical drive 0, 1st partition */
+    {0, 1},     /* Logical drive 1 ==> Physical drive 0, 2nd partition */
+    {0, 2},     /* Logical drive 2 ==> Physical drive 0, 3rd partition */
+    {1, 0}      /* Logical drive 3 ==> Physical drive 1 */
+};
+
+

複数区画指定を使用ã™ã‚‹å ´åˆã€æ¬¡ã®ç‚¹ã«æ³¨æ„ã—ãªã‘ã‚Œã°ãªã‚Šã¾ã›ã‚“。 +

    +
  • 指定å¯èƒ½ãªåŒºç”»ã¯åŸºæœ¬åŒºç”»(0～3)ã®ã¿ã€‚
    • +
  • 物ç†ãƒ‰ãƒ©ã‚¤ãƒ–ãŒSFDå½¢å¼(区画テーブル無ã—)ã®å ´åˆã€åŒºç”»æŒ‡å®šã¯ç„¡è¦–ã•ã‚Œã‚‹ã€‚
    • +
  • 複数ã®è«–ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã‚’æŒã¤ç‰©ç†ãƒ‰ãƒ©ã‚¤ãƒ–ã¯ã€å›ºå®šãƒ‡ã‚£ã‚¹ã‚¯ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。
    • +
+
+ + + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/forward.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/forward.html new file mode 100644 index 0000000..6101449 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/forward.html @@ -0,0 +1,141 @@ + + + + + + + +FatFs - f_forward + + + + +
+

f_forward

+

ƒtƒ@ƒCƒ‹‚©‚çƒf[ƒ^‚ð“Ç‚Ýo‚µA‘—MƒXƒgƒŠ[ƒ€‚É’¼Ú“]‘—‚µ‚Ü‚·B

+
+FRESULT f_forward (
+  FIL* FileObject,                 /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘Ì */
+  UINT (*Func)(const BYTE*,UINT),  /* ƒf[ƒ^“]‘—ŠÖ” */
+  UINT ByteToFwd,                  /* “]‘—‚·‚éƒoƒCƒg” */
+  UINT* ByteFwd                    /* “]‘—‚³‚ꂽƒoƒCƒg” */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Func
+
ƒf[ƒ^‚ð“n‚·ƒ†[ƒU’è‹`ŠÖ”‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B‚±‚ÌŠÖ”‚ÌŽd—l‚̓Tƒ“ƒvƒ‹‚ðŽQÆ‚µ‚Ä‚­‚¾‚³‚¢B
+
ByteToRead
+
“]‘—‚·‚éƒoƒCƒg”(0`UINT‚ÌÅ‘å’l)‚ðŽw’肵‚Ü‚·B
+
ByteRead
+
ŽÀÛ‚É“]‘—‚³‚ꂽƒoƒCƒg”‚ðŠi”[‚·‚é•Ï”‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DENIED
+
”ñ“Ç‚Ýž‚݃‚[ƒh‚ÅŠJ‚¢‚½ƒtƒ@ƒCƒ‹‚©‚ç“Ç‚Ýž‚à‚¤‚Æ‚µ‚½B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

ƒtƒ@ƒCƒ‹‚̃f[ƒ^‚ðƒoƒbƒtƒ@‚É“Ç‚Ýo‚³‚¸‚É‘—MƒXƒgƒŠ[ƒ€‚É’¼Ú“]‘—‚µ‚Ü‚·BƒAƒvƒŠƒP[ƒVƒ‡ƒ“‘¤‚Ńf[ƒ^Eƒoƒbƒtƒ@‚ð•K—v‚Æ‚µ‚È‚¢‚Ì‚ÅAƒƒ‚ƒŠ‚ÌŒÀ‚ç‚ꂽŠÂ‹«‚Å—LŒø‚Å‚·B“]‘—ŠJŽnˆÊ’u‚ÍAŒ»Ý‚̃tƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚©‚ç‚É‚È‚è‚Ü‚·Bƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚Í“]‘—‚³‚ꂽƒoƒCƒg”‚¾‚¯i‚Ý‚Ü‚·BŽw’肳‚ꂽƒoƒCƒg”‚Ì“]‘—’†‚Ƀtƒ@ƒCƒ‹‚ÌI’[‚É’B‚µ‚½ê‡‚â‘—MƒXƒgƒŠ[ƒ€‚ªƒrƒW[‚É‚È‚Á‚½ê‡A*ByteFwd‚ÍByteToFwd‚æ‚è‚ଂ³‚­‚È‚è‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_USE_FORWARD == 1‚ÅAŠŽ‚Â_FS_TINY == 1‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—áiƒI[ƒfƒBƒIĶj

+
+/*-----------------------------------------------------------------------*/
+/* f_forwardŠÖ”‚©‚çŒÄ‚΂ê‚éƒf[ƒ^‘—MŠÖ”‚Ì—á                           */
+/*-----------------------------------------------------------------------*/
+
+UINT out_stream (   /* –ß‚è’l: “]‘—‚³‚ꂽƒoƒCƒg”‚Ü‚½‚̓XƒgƒŠ[ƒ€‚Ìó‘Ô */
+    const BYTE *p,  /* “]‘—‚·‚éƒf[ƒ^‚ðŽw‚·ƒ|ƒCƒ“ƒ^ */
+    UINT btf        /* >0: “]‘—‚ðs‚¤(ƒoƒCƒg”). 0: ƒXƒgƒŠ[ƒ€‚Ìó‘Ԃ𒲂ׂé */
+)
+{
+    UINT cnt = 0;
+
+
+    if (btf == 0) {     /* ƒZƒ“ƒX—v‹ */
+        /* ƒXƒgƒŠ[ƒ€‚Ìó‘Ô‚ð•Ô‚· (0: ƒrƒW[, 1: ƒŒƒfƒB) */
+        /* ˆê’UAƒŒƒfƒB‚ð•Ô‚µ‚½‚çA‘±‚­“]‘——v‹‚Å­‚È‚­‚Æ‚à1ƒoƒCƒg‚Í */
+        /* “]‘—‚³‚ê‚È‚¢‚Æ f_forwardŠÖ”‚Í FR_RW_ERROR ‚Æ‚È‚éB */
+        if (FIFO_READY) cnt = 1;
+    }
+    else {              /* “]‘——v‹ */
+        do {    /* ‘S‚ẴoƒCƒg‚ð“]‘—‚·‚é‚©AƒXƒgƒŠ[ƒ€‚ªƒrƒW[‚É‚È‚é‚Ü‚ÅŒJ‚è•Ô‚· */
+            FIFO_PORT = *p++;
+            cnt++;
+        } while (cnt < btf && FIFO_READY);
+    }
+
+    return cnt;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* f_forwardŠÖ”‚ÌŽg—p—á                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT play_file (
+    char *fn        /* Ķ‚·‚éƒI[ƒfƒBƒIEƒtƒ@ƒCƒ‹–¼‚ðŽw‚·ƒ|ƒCƒ“ƒ^ */
+)
+{
+    FRESULT rc;
+    FIL fil;
+    UINT dmy;
+
+    /* ƒtƒ@ƒCƒ‹‚ð“Ç‚Ýo‚µƒ‚[ƒh‚ÅŠJ‚­ */
+    rc = f_open(&fil, fn, FA_READ);
+
+    /* ‘S‚Ẵf[ƒ^‚ª“]‘—‚³‚ê‚é‚©ƒGƒ‰[‚ª”­¶‚·‚é‚Ü‚Å‘±‚¯‚é */
+    while (rc == FR_OK && fil.fptr < fil.fsize) {
+
+        /* ‚Ù‚©‚̈—... */
+
+        /* ’èŠú“I‚Ü‚½‚Í—v‹‚ɉž‚¶‚ăf[ƒ^‚ðƒXƒgƒŠ[ƒ€‚É‘—o‚·‚é */
+        rc = f_forward(&fil, out_stream, 1000, &dmy);
+    }
+
+    return rc;	/* FR_OK: ³íI—¹, ‚Ù‚©:ˆÙíI—¹ */
+}
+
+
+ + +
+

ŽQÆ

+

f_open, fgets, f_write, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/getfree.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/getfree.html new file mode 100644 index 0000000..23751c6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/getfree.html @@ -0,0 +1,101 @@ + + + + + + + +FatFs - f_getfree + + + + +
+

f_getfree

+

˜_—ƒhƒ‰ƒCƒuã‚Ì–¢Žg—pƒNƒ‰ƒXƒ^”‚𓾂܂·B

+
+FRESULT f_getfree (
+  const XCHAR* Path,       /* ‘ÎÛƒhƒ‰ƒCƒu‚̃‹[ƒgEƒfƒBƒŒƒNƒgƒŠ */
+  DWORD* Clusters,         /* ‹ó‚«ƒNƒ‰ƒXƒ^”‚ðŠi”[‚·‚é•Ï”‚ւ̃|ƒCƒ“ƒ^ */
+  FATFS** FileSystemObject /* ƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
Path
+
‘Îۂ̘_—ƒhƒ‰ƒCƒu‚̃‹[ƒgƒfƒBƒŒƒNƒgƒŠ‚̃pƒX–¼‚ª“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Clusters
+
‹ó‚«ƒNƒ‰ƒXƒ^”‚ðŠi”[‚·‚éDWORD•Ï”‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
FileSystemObject
+
‘ÎÛƒhƒ‰ƒCƒu‚̃tƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ª•Ô‚³‚ê‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B*Clusters‚ɋ󂫃Nƒ‰ƒXƒ^”‚ª•Ô‚³‚ê‚Ü‚·B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ª—^‚¦‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒp[ƒe[ƒVƒ‡ƒ“‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

˜_—ƒhƒ‰ƒCƒuã‚̋󂫃Nƒ‰ƒXƒ^”‚ðŽæ“¾‚µ‚Ü‚·B•Ô‚³‚ꂽƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg‚Ìcsizeƒƒ“ƒo‚ªƒNƒ‰ƒXƒ^‚ ‚½‚è‚̃ZƒNƒ^”‚ðŽ¦‚µ‚Ä‚¢‚é‚Ì‚ÅA‚±‚ê‚ðŒ³‚ÉŽÀۂ̋󂫃TƒCƒY‚ªŒvŽZ‚Å‚«‚Ü‚·BFAT32ƒ{ƒŠƒ…[ƒ€‚É‚¨‚¢‚Ä‚ÍAFSINFO‚Ìó‘Ô‚É‚æ‚Á‚Ä‚Í•s³Šm‚È’l‚ð•Ô‚µ‚½‚èAˆ—‚ÉŽžŠÔ‚ª‚©‚©‚Á‚½‚è‚·‚é‰Â”\«‚ª‚ ‚è‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—á

+
+    FATFS *fs;
+    DWORD fre_clust, fre_sect, tot_sect;
+
+
+    /* Get drive information and free clusters */
+    res = f_getfree("/", &fre_clust, &fs);
+    if (res) die(res);
+
+    /* Get total sectors and free sectors */
+    tot_sect = (fs->max_clust - 2) * fs->csize;
+    fre_sect = fre_clust * fs->csize;
+
+    /* Print free space in unit of KB (assuming 512B/sector) */
+    printf("%lu KB total drive space.\n"
+           "%lu KB available.\n",
+           fre_sect / 2, tot_sect / 2);
+
+
+ + +
+

ŽQÆ

+FATFS +
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/gets.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/gets.html new file mode 100644 index 0000000..a464a9f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/gets.html @@ -0,0 +1,63 @@ + + + + + + + +FatFs - f_gets + + + + +
+

f_gets

+

ƒtƒ@ƒCƒ‹‚©‚當Žš—ñ‚ð“Ç‚Ýo‚µ‚Ü‚·B

+
+char* f_gets (
+  char* Str,        /* ƒoƒbƒtƒ@ */
+  int Size,         /* ƒoƒbƒtƒ@‚̃TƒCƒY */
+  FIL* FileObject   /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg */
+);
+
+
+ +
+

ˆø”

+
+
Str
+
•¶Žš—ñ‚ð“Ç‚Ýo‚·ƒoƒbƒtƒ@‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Size
+
ƒoƒbƒtƒ@‚̃TƒCƒY‚ðŽw’肵‚Ü‚·B
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+

ŠÖ”‚ª¬Œ÷‚·‚é‚ÆStr‚ª•Ô‚³‚ê‚Ü‚·B

+
+ + +
+

‰ðà

+

‚±‚ÌŠÖ”‚Íf_read()‚̃‰ƒbƒp[ŠÖ”‚Å‚·B“Ç‚Ýo‚µ“®ì‚ÍAʼn‚Ì'\n'‚ð“Ç‚Ýž‚Þ‚©Aƒtƒ@ƒCƒ‹I’[‚É’B‚·‚é‚©ASize - 1•¶Žš‚ð“Ç‚Ýo‚·‚Ü‚Å‘±‚«‚Ü‚·B“Ç‚Ýž‚܂ꂽ•¶Žš—ñ‚ÌI’[‚É‚Í'\0'‚ª•t‰Á‚³‚ê‚Ü‚·BŠù‚Ƀtƒ@ƒCƒ‹I’[‚Å1•¶Žš‚à“Ç‚Ýž‚Ü‚ê‚È‚©‚Á‚½‚Æ‚«A‚Ü‚½‚͉½‚ç‚©‚̃Gƒ‰[‚ª”­¶‚µ‚½‚Æ‚«‚ÍNULL‚ð•Ô‚µ‚Ü‚·Bƒtƒ@ƒCƒ‹I’[‚©ƒGƒ‰[‚©‚Íf_eof(),f_error()ƒ}ƒNƒ‚Å’²‚ׂç‚ê‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_USE_STRFUNC‚ª 1‚Ü‚½‚Í 2‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B2‚Ì‚Æ‚«‚ÍAƒtƒ@ƒCƒ‹‚ÉŠÜ‚Ü‚ê‚é'\r'‚ªŽæ‚蜂©‚ê‚ăoƒbƒtƒ@‚É“Ç‚Ýž‚Ü‚ê‚Ü‚·B

+
+ + +
+

ŽQÆ

+

f_open, f_read, f_putc, f_puts, f_printf, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/lseek.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/lseek.html new file mode 100644 index 0000000..3ea09a5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/lseek.html @@ -0,0 +1,110 @@ + + + + + + + +FatFs - f_lseek + + + + +
+

f_lseek

+

ƒtƒ@ƒCƒ‹‚ÌR/Wƒ|ƒCƒ“ƒ^‚ðˆÚ“®‚µ‚Ü‚·B

+
+FRESULT f_lseek (
+  FIL* FileObject,   /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^ */
+  DWORD Offset       /* ˆÚ“®æƒIƒtƒZƒbƒg */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
‘ÎÛ‚Æ‚È‚éƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Offset
+
ˆÚ“®æ‚̃IƒtƒZƒbƒgiR/Wƒ|ƒCƒ“ƒ^j’lBƒtƒ@ƒCƒ‹æ“ª‚©‚ç‚̃IƒtƒZƒbƒg‚ðƒoƒCƒg’PˆÊ‚ÅŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

ƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^(ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg“à‚Ìfptrƒƒ“ƒo‚ÅAŽŸ‚É“Ç‚Ýo‚µE‘‚«ž‚Ý‚³‚ê‚éƒoƒCƒg‚̃IƒtƒZƒbƒg‚ðŽ¦‚·)‚ðˆÚ“®‚µ‚Ü‚·BƒIƒtƒZƒbƒg‚ÌŒ´“_‚̓tƒ@ƒCƒ‹æ“ª‚©‚ç‚Å‚·B‘‚«ž‚݃‚[ƒh‚Ńtƒ@ƒCƒ‹EƒTƒCƒY‚æ‚è‘å‚«‚È’l‚ðŽw’è‚·‚é‚ÆA‚»‚±‚܂Ńtƒ@ƒCƒ‹‚ªŠg’£‚³‚êAŠg’£‚³‚ꂽ•”•ª‚̃f[ƒ^‚Í–¢’è‹`‚Æ‚È‚è‚Ü‚·Bƒf[ƒ^‚ð’x‰„–³‚­‚‘¬‚É‘‚«ž‚Ý‚½‚¢‚Æ‚«‚ÍA—\‚ß‚±‚ÌŠÖ”‚Å•K—v‚ȃTƒCƒY‚܂Ńtƒ@ƒCƒ‹EƒTƒCƒY‚ðŠg’£‚µ‚Ä‚¨‚­‚Æ—Ç‚¢‚Å‚µ‚傤Bf_lseekŠÖ”‚ª³íI—¹‚µ‚½‚ ‚Æ‚ÍAƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚ª³‚µ‚­ˆÚ“®‚µ‚½‚©fptr‚ðƒ`ƒFƒbƒN‚·‚é‚ׂ«‚Å‚·Bƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚ªŽw’è‚æ‚謂³‚¢‚Æ‚«‚ÍAŽŸ‚ÌŒ´ˆö‚ªl‚¦‚ç‚ê‚Ü‚·B

+
    +
  • ”ñ‘‚«ž‚݃‚[ƒh‚Ì‚½‚ßAƒtƒ@ƒCƒ‹EƒTƒCƒY‚ŃNƒŠƒbƒv‚³‚ꂽB
    • +
  • ƒtƒ@ƒCƒ‹Šg’£’†‚ɃfƒBƒXƒN‚ª–ž”t‚É‚È‚Á‚½B
    • +
+
+ + +
+

‘Ήžî•ñ

+

_FS_MINIMIZE < 3‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—á

+
+    /* ƒIƒtƒZƒbƒg5000‚ÖˆÚ“® */
+    res = f_lseek(&file, 5000);
+
+    /* ƒtƒ@ƒCƒ‹’Ç‹L‚Ì€”õ (ƒtƒ@ƒCƒ‹I’[‚ÖˆÚ“®) */
+    res = f_lseek(&file, file.fsize);
+
+    /* 3000ƒoƒCƒgi‚ß‚é */
+    res = f_lseek(&file, file.fptr + 3000);
+
+    /* 2000ƒoƒCƒg–ß‚· (ƒI[ƒo[ƒtƒ[‚É’ˆÓ) */
+    res = f_lseek(&file, file.fptr - 2000);
+
+
+    /* ƒNƒ‰ƒXƒ^æsŠ„‚è“–‚Ä (ƒXƒgƒŠ[ƒ~ƒ“ƒOEƒ‰ƒCƒgŽž‚̃oƒbƒtƒ@EƒI[ƒo[ƒ‰ƒ“–hŽ~) */
+
+    res = f_open(&file, "record.wav", FA_CREATE_NEW | FA_WRITE); /* ƒtƒ@ƒCƒ‹ì¬ */
+
+    res = f_lseek(&file, MAX_SIZE);        /* \•ª‚ȃNƒ‰ƒXƒ^‚ÌæsŠ„‚è“–‚Ä */
+    if (res || file.fptr != PRE_SIZE) .... /* ³‚µ‚­ƒtƒ@ƒCƒ‹‚ªŠg’£‚³‚ꂽ‚©ƒ`ƒFƒbƒN */
+
+    res = f_lseek(&file, DATA_START);      /* ƒf[ƒ^EƒXƒgƒŠ[ƒ€‚Ì‹L˜^(ƒAƒƒP[ƒVƒ‡ƒ“ƒfƒBƒŒƒC–³‚µ) */
+    ...
+
+    res = f_truncate(&file);              /* •s—v—̈æ‚ÌØ‚èŽÌ‚Ä */
+    res = f_lseek(&file, 0);              /* ƒwƒbƒ_‚Ì‹L˜^ */
+    ...
+
+    res = f_close(&file);
+
+
+ + +
+

ŽQÆ

+

f_open, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mkdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mkdir.html new file mode 100644 index 0000000..5dd3860 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mkdir.html @@ -0,0 +1,89 @@ + + + + + + + +FatFs - f_mkdir + + + + +
+

f_mkdir

+

ƒfƒBƒŒƒNƒgƒŠ‚ð쬂µ‚Ü‚·B

+
+FRESULT f_mkdir (
+  const XCHAR* DirName /* 쬂·‚éƒfƒBƒŒƒNƒgƒŠ–¼‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
DirName
+
쬂·‚éƒfƒBƒŒƒNƒgƒŠ‚̃pƒX–¼‚ª“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_DENIED
+
ƒfƒBƒXƒN‚âƒfƒBƒŒƒNƒgƒŠEƒGƒ“ƒgƒŠ‚ª–ž”t‚ÌꇂȂÇB
+
FR_EXIST
+
“¯–¼‚̃fƒBƒŒƒNƒgƒŠ‚âƒtƒ@ƒCƒ‹‚ª‘¶Ý‚·‚éB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ª—^‚¦‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

‹ó‚̃fƒBƒŒƒNƒgƒŠ‚ð쬂µ‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—á

+
+    res = f_mkdir("sub1");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2/sub3");
+    if (res) die(res);
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mkfs.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mkfs.html new file mode 100644 index 0000000..14fdff4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mkfs.html @@ -0,0 +1,78 @@ + + + + + + + +FatFs - f_mkfs + + + + +
+

f_mkfs

+

ƒhƒ‰ƒCƒuã‚ÉFATƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€‚ðì¬(ƒtƒH[ƒ}ƒbƒg)‚µ‚Ü‚·B

+
+FRESULT f_mkfs (
+  BYTE  Drive,              /* ˜_—ƒhƒ‰ƒCƒu”Ô† */
+  BYTE  PartitioningRule,   /* ‹æ‰æ쬕û–@ */
+  WORD  AllocSize           /* ƒNƒ‰ƒXEƒ^ƒTƒCƒY */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
ƒtƒH[ƒ}ƒbƒg‚·‚é˜_—ƒhƒ‰ƒCƒu(0-9)B
+
PartitioningRule
+
0‚ðŽw’è‚·‚é‚ÆAƒhƒ‰ƒCƒu‚Ì‘S—̈æ‚ðè‚ß‚éŠî–{DOS‹æ‰æ‚ð쬂µ‚½‚ ‚Æ‚»‚Ì‹æ‰æ‚Ƀtƒ@ƒCƒ‹EƒVƒXƒeƒ€‚ð쬂µ‚Ü‚·(FDISKƒtƒH[ƒ}ƒbƒg)B1‚ðŽw’è‚·‚é‚ÆA‹æ‰æƒe[ƒuƒ‹‚ð쬂¹‚¸ƒhƒ‰ƒCƒu‚Ì擪ƒZƒNƒ^‚©‚ç’¼Úƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€‚ð쬂µ‚Ü‚·(super floppy (SFD) ƒtƒH[ƒ}ƒbƒg)B
+
AllocSize
+
ƒNƒ‰ƒXƒ^EƒTƒCƒY‚ðƒoƒCƒg’PˆÊ‚ÅŽw’肵‚Ü‚·B0‚Ü‚½‚Í512`32768‚͈̔͂ł©‚Â2‚Ì—Ýæ‚Å‚È‚¯‚ê‚΂Ȃè‚Ü‚¹‚ñB0‚ðŽw’è‚·‚é‚ƃhƒ‰ƒCƒuEƒTƒCƒY‚ɉž‚¶‚½ƒfƒtƒHƒ‹ƒg‚̃Nƒ‰ƒXƒ^EƒTƒCƒY‚ð‘I‘ð‚µ‚Ü‚·BFAT64(64KB/ƒNƒ‰ƒXƒ^)‚Í‘I‘ð‚Å‚«‚Ü‚¹‚ñB
+
+
+ +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª–³ŒøB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ªŠ„‚è“–‚Ä‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_MKFS_ABORTED
+
ŽŸ‚Ì——R‚ÅŠJŽn‘O‚Ɉ—‚ª’†’f‚³‚ꂽB +
    +
  • ƒfƒBƒXƒNEƒTƒCƒY‚ª¬‚³‚·‚¬‚éB
    • +
  • ‰½‚ç‚©‚̈ø”‚ª•s³B
    • +
  • ‚»‚̃Nƒ‰ƒXƒ^EƒTƒCƒY‚ªŽg‚¦‚È‚¢BƒNƒ‰ƒXƒ^”‚ª0xFF7‚Æ0xFFF7‹ß•Ó‚É‚È‚é‚Æ‚«”­¶‚·‚é‰Â”\«‚ª‚ ‚éB
    • +
+
+
+
+ +
+

à–¾

+

f_mkfsŠÖ”‚ÍFATƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€‚ðƒhƒ‰ƒCƒuã‚É쬂µ‚Ü‚·BƒŠƒ€[ƒoƒuƒ‹EƒƒfƒBƒA‚̃p[ƒe[ƒVƒ‡ƒjƒ“ƒOEƒ‹[ƒ‹‚Æ‚µ‚Ä‚ÍFDISKŒ`Ž®‚ÆSFDŒ`Ž®‚ª‚ ‚èAƒƒ‚ƒŠEƒJ[ƒh‚Å‚ÍFDISKŒ`Ž®‚ª•’Ê‚Å‚·B‚±‚ÌŠÖ”‚Í•¡”‹æ‰æ‚ɂ͑Ήž‚µ‚Ä‚¢‚È‚¢‚Ì‚ÅA‚»‚Ì•¨—ƒhƒ‰ƒCƒu‚ÌŠù‘¶‚Ì‹æ‰æ‚Í‘S‚Ä휂³‚êA‘S‘Ì‚ªˆê‚‚̋æ‰æ‚É‚È‚è‚Ü‚·B

+

FATƒ^ƒCƒv(FAT12/FAT16/FAT32)‚ÍA‚»‚̘_—ƒhƒ‰ƒCƒuã‚̃Nƒ‰ƒXƒ^”‚É‚æ‚Á‚Ä‚Ì‚ÝŒˆ’肳‚ê‚é[FATŽd—l‘‚æ‚è]Œˆ‚Ü‚è‚É‚È‚Á‚Ä‚¢‚ÄA‚»‚êˆÈŠO‚Ì—vˆö‚Í‚ ‚è‚Ü‚¹‚ñB‚µ‚½‚ª‚Á‚ÄA‚Ç‚ÌFATƒ^ƒCƒv‚É‚È‚é‚©‚̓hƒ‰ƒCƒuEƒTƒCƒY‚ÆŽw’肳‚ꂽƒNƒ‰ƒXƒ^EƒTƒCƒY‚Ɉˑ¶‚µ‚Ü‚·BƒNƒ‰ƒXƒ^EƒTƒCƒY‚Í‘å‚«‚­‚·‚é‚Ù‚Ç«”\‚ªã‚ª‚èA‹t‚ɃfƒBƒXƒN—˜—pŒø—¦‚Í—Ž‚¿‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_USE_MKFS == 1‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mount.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mount.html new file mode 100644 index 0000000..425f921 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/mount.html @@ -0,0 +1,65 @@ + + + + + + + +FatFs - f_mount + + + + +
+

f_mount

+

˜_—ƒhƒ‰ƒCƒu(ƒ{ƒŠƒ…[ƒ€)‚̃[ƒNEƒGƒŠƒA‚ð“o˜^E–•Á‚µ‚Ü‚·B

+
+FRESULT f_mount (
+  BYTE  Drive,               /* ˜_—ƒhƒ‰ƒCƒu”Ô† */
+  FATFS*  FileSystemObject   /* ƒ[ƒNEƒGƒŠƒA‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
Drive
+
˜_—ƒhƒ‰ƒCƒu”Ô†(0-9)B
+
FileSystemObject
+
“o˜^‚·‚éƒ[ƒNEƒGƒŠƒA(ƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg)‚ւ̃|ƒCƒ“ƒ^B
+
+
+ +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª–³ŒøB
+
+
+ + +
+

‰ðà

+

FatFsƒ‚ƒWƒ…[ƒ‹‚Å‚Í‚»‚ꂼ‚ê‚̘_—ƒhƒ‰ƒCƒu‚Ƀtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg‚Æ‚¢‚¤ƒ[ƒNEƒGƒŠƒA‚ª•K—v‚Å‚·B‚±‚ÌŠÖ”‚͘_—ƒhƒ‰ƒCƒu‚É‚»‚̃[ƒNEƒGƒŠƒA‚ð“o˜^‚µ‚½‚è–•Á‚µ‚½‚肵‚Ü‚·B‰½‚ç‚©‚̃tƒ@ƒCƒ‹ŠÖ”‚ðŽg—p‚·‚é‘O‚É‚±‚ÌŠÖ”‚Å‚»‚̘_—ƒhƒ‰ƒCƒu‚̃[ƒNEƒGƒŠƒA‚ð—^‚¦‚Ä‚¨‚©‚È‚¯‚ê‚΂Ȃè‚Ü‚¹‚ñBFileSystemObject‚Ƀkƒ‹Eƒ|ƒCƒ“ƒ^‚ðŽw’è‚·‚é‚Æ‚»‚̘_—ƒhƒ‰ƒCƒu‚̃[ƒNEƒGƒŠƒA‚Ì“o˜^‚Í–•Á‚³‚êA“o˜^‚³‚ê‚Ä‚¢‚½ƒ[ƒNEƒGƒŠƒA‚Í”jŠü‚Å‚«‚Ü‚·B

+

‚±‚ÌŠÖ”“à‚Å‚Í•¨—ƒhƒ‰ƒCƒu‚ւ̃AƒNƒZƒX‚Í”­¶‚¹‚¸Aƒ[ƒNEƒGƒŠƒA‚ð‰Šú‰»‚µ‚Ä“à•””z—ñ‚É‚»‚̃AƒhƒŒƒX‚ð“o˜^‚·‚邾‚¯‚Å‚·BŽÀۂ̃}ƒEƒ“ƒg“®ì‚ÍAf_mount()‚Ü‚½‚̓ƒfƒBƒAŒðŠ·ŒãAʼn‚̃tƒ@ƒCƒ‹EƒAƒNƒZƒX‚Ì‚Æ‚«‚És‚í‚ê‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

‘S‚Ä‚Ì\¬‚ÅŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

FATFS

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/open.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/open.html new file mode 100644 index 0000000..6be7497 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/open.html @@ -0,0 +1,144 @@ + + + + + + + +FatFs - f_open + + + + +
+

f_open

+

ƒtƒ@ƒCƒ‹‚ðƒI[ƒvƒ“‚Ü‚½‚Í쬂µ‚Ü‚·B

+
+FRESULT f_open (
+  FIL* FileObject,       /* ‹ó‚̃tƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^ */
+  const XCHAR* FileName, /* ƒtƒ@ƒCƒ‹‚̃tƒ‹ƒpƒX–¼‚ւ̃|ƒCƒ“ƒ^ */
+  BYTE ModeFlags         /* ƒ‚[ƒhƒtƒ‰ƒO */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
V‚µ‚­ì¬‚·‚éƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·BˆÈ~A‚»‚̃tƒ@ƒCƒ‹‚ð•Â‚¶‚é‚Ü‚Å‚±‚̃tƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ðŽg—p‚µ‚ătƒ@ƒCƒ‹‘€ì‚ð‚µ‚Ü‚·B
+
FileName
+
ŠJ‚­(‚Ü‚½‚Í쬂·‚é)ƒtƒ@ƒCƒ‹‚Ì ƒtƒ@ƒCƒ‹–¼‚ª“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
ModeFlags
+
ƒtƒ@ƒCƒ‹‚̃AƒNƒZƒX•û–@‚âƒI[ƒvƒ“•û–@‚ðŒˆ‚ß‚éƒtƒ‰ƒO‚Å‚·B‚±‚̃pƒ‰ƒ[ƒ^‚É‚ÍŽŸ‚Ì‘g‚݇‚킹‚ðŽw’肵‚Ü‚·B
+ + + + + + + + +
’lˆÓ–¡
FA_READ“Ç‚Ýo‚µƒ‚[ƒh‚ÅŠJ‚«‚Ü‚·B“Ç‚Ý‘‚«‚·‚éꇂÍFA_WRITE‚Æ‹¤‚ÉŽw’肵‚Ü‚·B
FA_WRITE‘‚«ž‚݃‚[ƒh‚ÅŠJ‚«‚Ü‚·B“Ç‚Ý‘‚«‚·‚éꇂÍFA_READ‚Æ‹¤‚ÉŽw’肵‚Ü‚·B
FA_OPEN_EXISTINGŠù‘¶‚̃tƒ@ƒCƒ‹‚ðŠJ‚«‚Ü‚·Bƒtƒ@ƒCƒ‹‚ª–³‚¢‚Æ‚«‚̓Gƒ‰[‚É‚È‚è‚Ü‚·B(ƒfƒtƒHƒ‹ƒg)
FA_OPEN_ALWAYSŠù‘¶‚̃tƒ@ƒCƒ‹‚ðŠJ‚«‚Ü‚·Bƒtƒ@ƒCƒ‹‚ª–³‚¢‚Æ‚«‚̓tƒ@ƒCƒ‹‚ð쬂µ‚Ü‚·B
FA_CREATE_NEWƒtƒ@ƒCƒ‹‚ð쬂µ‚Ü‚·B“¯–¼‚̃tƒ@ƒCƒ‹‚ª‚ ‚éꇂÍAƒGƒ‰[‚É‚È‚è‚Ü‚·B
FA_CREATE_ALWAYSƒtƒ@ƒCƒ‹‚ð쬂µ‚Ü‚·B“¯–¼‚̃tƒ@ƒCƒ‹‚ª‚ ‚éꇂÍAƒTƒCƒY‚ð0‚É‚µ‚Ä‚©‚çŠJ‚«‚Ü‚·B
+
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹BˆÈ~AFileObject\‘¢‘Ì‚ðŽg‚Á‚Ä‚±‚̃tƒ@ƒCƒ‹‚ð‘€ì‚Å‚«‚Ü‚·B
+
FR_NO_FILE
+
ƒtƒ@ƒCƒ‹‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒtƒ@ƒCƒ‹–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_EXIST
+
“¯–¼‚̃tƒ@ƒCƒ‹‚ªŠù‚É‚ ‚éB
+
FR_DENIED
+
ƒAƒNƒZƒX‚ª‹‘”Û‚³‚ꂽBƒŠ[ƒhEƒIƒ“ƒŠ[Eƒtƒ@ƒCƒ‹‚Ì‘‚«ž‚݃‚[ƒhEƒI[ƒvƒ“A“¯–¼‚̃fƒBƒŒƒNƒgƒŠ‚Ü‚½‚̓Š[ƒhEƒIƒ“ƒŠ[Eƒtƒ@ƒCƒ‹‚ª‚ ‚éó‘Ԃł̃tƒ@ƒCƒ‹ì¬AƒfƒBƒXƒN‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠEƒe[ƒuƒ‹‚ª–ž”t‚Ńtƒ@ƒCƒ‹‚ð쬂ł«‚È‚¢‚È‚ÇB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘Ô‚Å‘‚«ž‚ÝŒnƒI[ƒvƒ“‚ð‚µ‚½B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ªŠ„‚è“–‚Ä‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

Šù‘¶‚̃tƒ@ƒCƒ‹‚ðŠJ‚¢‚½‚èAV‚µ‚¢ƒtƒ@ƒCƒ‹‚ð쬂µ‚Ü‚·BŠÖ”‚ª¬Œ÷‚·‚é‚ƃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ªì¬‚³‚êAˆÈ~‚»‚̃tƒ@ƒCƒ‹‚ɑ΂·‚éƒAƒNƒZƒX‚ÉŽg—p‚µ‚Ü‚·Bƒtƒ@ƒCƒ‹‚ð•Â‚¶‚é‚Æ‚«‚ÍAf_close()‚ðŽg—p‚µ‚Ü‚·B‰½‚ç‚©‚Ì•ÏX‚ªs‚í‚ꂽƒtƒ@ƒCƒ‹‚ª‚»‚̌㳂µ‚­•Â‚¶‚ç‚ê‚È‚©‚Á‚½ê‡A‚»‚̃tƒ@ƒCƒ‹‚ª”j‘¹‚·‚éꇂª‚ ‚è‚Ü‚·B

+

ƒtƒ@ƒCƒ‹EƒAƒNƒZƒX‚ðŠJŽn‚·‚é‘O‚ÉAf_mount()‚ðŽg‚Á‚Ä‚»‚ꂼ‚ê‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA(ƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg)‚ð—^‚¦‚é•K—v‚ª‚ ‚è‚Ü‚·B‚±‚̉Šú‰»‚ÌŒãA‚»‚̘_—ƒhƒ‰ƒCƒu‚ɑ΂µ‚Ä‘S‚Ẵtƒ@ƒCƒ‹ŠÖ”‚ªŽg‚¦‚é‚悤‚É‚È‚è‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

‘S‚Ä‚Ì\¬‚ÅŽg—p‰Â”\‚Å‚·B_FS_READONLY == 1‚Ì‚Æ‚«‚ÍAFA_WRITE, FA_CREATE_ALWAYS, FA_CREATE_NEW, FA_OPEN_ALWAYS‚ÌŠeƒtƒ‰ƒO‚̓Tƒ|[ƒg‚³‚ê‚Ü‚¹‚ñB

+
+ + +
+

Žg—p—áiƒtƒ@ƒCƒ‹EƒRƒs[j

+
+void main (void)
+{
+    FATFS fs[2];         /* ˜_—ƒhƒ‰ƒCƒu‚̃[ƒNEƒGƒŠƒA(ƒtƒ@ƒCƒ‹EƒVƒXƒeƒ€EƒIƒuƒWƒFƒNƒg) */
+    FIL fsrc, fdst;      /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg */
+    BYTE buffer[4096];   /* file copy buffer */
+    FRESULT res;         /* FatFs function common result code */
+    UINT br, bw;         /* File R/W count */
+
+    /* ƒhƒ‰ƒCƒu0,1‚Ƀ[ƒNEƒGƒŠƒA‚ð—^‚¦‚é */
+    f_mount(0, &fs[0]);
+    f_mount(1, &fs[1]);
+
+    /* ƒhƒ‰ƒCƒu1‚̃\[ƒXEƒtƒ@ƒCƒ‹‚ðŠJ‚­ */
+    res = f_open(&fsrc, "1:srcfile.dat", FA_OPEN_EXISTING | FA_READ);
+    if (res) die(res);
+
+    /* ƒhƒ‰ƒCƒu0‚ɃfƒXƒeƒBƒl[ƒVƒ‡ƒ“Eƒtƒ@ƒCƒ‹‚ð쬂·‚é */
+    res = f_open(&fdst, "0:dstfile.dat", FA_CREATE_ALWAYS | FA_WRITE);
+    if (res) die(res);
+
+    /* ƒ\[ƒX‚©‚çƒfƒXƒeƒBƒl[ƒVƒ‡ƒ“‚ɃRƒs[‚·‚é */
+    for (;;) {
+        res = f_read(&fsrc, buffer, sizeof(buffer), &br);
+        if (res || br == 0) break;   /* ƒGƒ‰[‚©ƒtƒ@ƒCƒ‹I’[ */
+        res = f_write(&fdst, buffer, br, &bw);
+        if (res || bw < br) break;   /* ƒGƒ‰[‚©ƒfƒBƒXƒN–ž”t */
+    }
+
+    /* ‘S‚Ẵtƒ@ƒCƒ‹‚ð•Â‚¶‚é */
+    f_close(&fsrc);
+    f_close(&fdst);
+
+    /* ƒ[ƒNEƒGƒŠƒA‚ðŠJ•ú‚·‚é */
+    f_mount(0, NULL);
+    f_mount(1, NULL);
+}
+
+
+ + +
+

ŽQÆ

+

f_read, f_write, f_close, FIL, FATFS

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/opendir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/opendir.html new file mode 100644 index 0000000..311ffeb --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/opendir.html @@ -0,0 +1,79 @@ + + + + + + + +FatFs - f_opendir + + + + +
+

f_opendir

+

ƒfƒBƒŒƒNƒgƒŠ‚ðŠJ‚«‚Ü‚·B

+
+FRESULT f_opendir (
+  DIR* DirObject,       /* ƒfƒBƒŒƒNƒgƒŠEƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^ */
+  const XCHAR* DirName  /* ƒfƒBƒŒƒNƒgƒŠ–¼‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
DirObject
+
‰Šú‰»‚·‚éƒfƒBƒŒƒNƒgƒŠEƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
DirName
+
ƒI[ƒvƒ“‚·‚éƒfƒBƒŒƒNƒgƒŠ‚ւ̃pƒX–¼‚ª“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
˜_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ª—^‚¦‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

ƒfƒBƒŒƒNƒgƒŠ‚ðŠJ‚«‚Ü‚·B³íI—¹‚µ‚½‚çADirObject\‘¢‘Ì‚ðŽg‚Á‚Ä‚±‚̃fƒBƒŒƒNƒgƒŠ‚Ì€–Ú‚ð‡ŽŸ“Ç‚Ýo‚¹‚Ü‚·BDirObject\‘¢‘Ì‚ÍŽg—pŒã‚Í”CˆÓ‚ÌŽž“_‚Å”jŠü‚Å‚«‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_MINIMIZE <= 1‚Ì‚Æ‚«Žg—p‰Â”\‚É‚È‚è‚Ü‚·B

+
+ + +
+

ŽQÆ

+

f_readdir, DIR

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/printf.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/printf.html new file mode 100644 index 0000000..c742972 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/printf.html @@ -0,0 +1,82 @@ + + + + + + + +FatFs - f_printf + + + + +
+

f_printf

+

ƒtƒ@ƒCƒ‹‚É‘Ž®‰»•¶Žš—ñ‚ð‘‚«ž‚Ý‚Ü‚·B

+
+int f_printf (
+  FIL* FileObject,     /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg */
+  const char* Foramt,  /* ‘Ž®§Œä•¶Žš—ñ */
+  ...
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Format
+
'\0'‚ÅI‚í‚é‘Ž®§Œä•¶Žš—ñ‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B'\0'‚Í‘‚«ž‚Ü‚ê‚Ü‚¹‚ñB
+
...
+
ƒIƒvƒVƒ‡ƒ“‚̈ø”B
+ +
+
+ + +
+

–ß‚è’l

+

•¶Žš—ñ‚ª³í‚É‘‚«ž‚Ü‚ê‚é‚Æ‘‚«ž‚ñ‚¾•¶Žš”‚ª•Ô‚³‚ê‚Ü‚·BƒfƒBƒXƒN‚ª–ž”t‚Ü‚½‚Í‚»‚Ì‘¼ƒGƒ‰[‚É‚æ‚è³í‚É‘‚«ž‚Ü‚ê‚È‚©‚Á‚½‚Æ‚«‚ÍEOF(-1)‚ª•Ô‚³‚ê‚Ü‚·B

+
+ + +
+

‰ðà

+

‚±‚ÌŠÖ”‚Íf_putc()‚¨‚æ‚Ñf_puts()‚̃‰ƒbƒp[ŠÖ”‚Å‚·B‘Ž®§Œä‹@”\‚̓TƒuƒZƒbƒg‚Æ‚È‚Á‚Ä‚¢‚ÄA‘Ž®§Œä•¶Žš‚ÍŽŸ‚ÉŽ¦‚·‚à‚Ì‚ªŽg—p‰Â”\‚Å‚·B

+
    +
  • ƒ^ƒCƒv: c s d u X
    • +
  • ¸“xŽw’è: l
    • +
  • ƒtƒ‰ƒO: 0
    • +
+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_USE_STRFUNC‚ª 1‚Ü‚½‚Í 2‚Ì‚Æ‚«Žg—p‰Â”\‚É‚È‚è‚Ü‚·B2‚ÌŽž‚ÍAo—Í‚ÉŠÜ‚Ü‚ê‚é'\n'‚ª"\r\n"‚É“WŠJ‚³‚ê‚ătƒ@ƒCƒ‹‚É‘‚«ž‚Ü‚ê‚Ü‚·B

+
+ + +
+

Žg—p—á

+
+    f_printf(&fil, "%6d", -200);         // "  -200"
+    f_printf(&fil, "%02u", 5);           // "05"
+    f_printf(&fil, "%ld", 12345678L);    // "12345678"
+    f_printf(&fil, "%08lX", 1194684UL);  // "00123ABC"
+    f_printf(&fil, "%s", "String");      // "String"
+    f_printf(&fil, "%c", 'a');           // "a"
+
+
+ + +
+

ŽQÆ

+

f_open, f_putc, f_puts, f_gets, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/putc.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/putc.html new file mode 100644 index 0000000..c117cf3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/putc.html @@ -0,0 +1,60 @@ + + + + + + + +FatFs - f_putc + + + + +
+

f_putc

+

ƒtƒ@ƒCƒ‹‚É•¶Žš‚ð‘‚«ž‚Ý‚Ü‚·B

+
+int f_putc (
+  int Chr,          /* ‘‚«ž‚Þ•¶Žš */
+  FIL* FileObject   /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg */
+);
+
+
+ +
+

ˆø”

+
+
Chr
+
‘‚«ž‚Þ•¶Žš‚ðŽw’肵‚Ü‚·B
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+

•¶Žš‚ª³í‚É‘‚«ž‚Ü‚ê‚é‚Æ‘‚«ž‚ñ‚¾•¶Žš‚ª•Ô‚³‚ê‚Ü‚·BƒfƒBƒXƒN‚ª–ž”t‚Ü‚½‚Í‚»‚Ì‘¼ƒGƒ‰[‚É‚æ‚è‘‚«ž‚Ü‚ê‚È‚©‚Á‚½‚Æ‚«‚ÍEOF‚ª•Ô‚³‚ê‚Ü‚·B

+
+ + +
+

‰ðà

+

1•¶Žš‚ðƒtƒ@ƒCƒ‹‚É‘‚«ž‚Ý‚Ü‚·B‚±‚ÌŠÖ”‚Íf_write()‚̃‰ƒbƒp[ŠÖ”‚Å‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_USE_STRFUNC‚ª 1‚Ü‚½‚Í 2‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B2‚ðŽw’è‚·‚é‚ÆA'\n'‚Í"\r\n"‚É“WŠJ‚³‚ê‚ătƒ@ƒCƒ‹‚É‘‚«ž‚Ü‚ê‚Ü‚·B

+
+ + +
+

ŽQÆ

+

f_open, f_puts, f_printf, f_gets, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/puts.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/puts.html new file mode 100644 index 0000000..7d8044f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/puts.html @@ -0,0 +1,60 @@ + + + + + + + +FatFs - f_puts + + + + +
+

f_puts

+

ƒtƒ@ƒCƒ‹‚É•¶Žš—ñ‚ð‘‚«ž‚Ý‚Ü‚·B

+
+int f_puts (
+  const char* Str,  /* •¶Žš—ñ */
+  FIL* FileObject   /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg */
+);
+
+
+ +
+

ˆø”

+
+
Str
+
‘‚«ž‚Þ'\0'‚ÅI‚í‚镶Žš—ñ‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B'\0'‚Í‘‚«ž‚Ü‚ê‚Ü‚¹‚ñB
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+

•¶Žš—ñ‚ª³í‚É‘‚«ž‚Ü‚ê‚é‚Æ‘‚«ž‚ñ‚¾•¶Žš”‚ª•Ô‚³‚ê‚Ü‚·BƒfƒBƒXƒN‚ª–ž”t‚Ü‚½‚Í‚»‚Ì‘¼ƒGƒ‰[‚É‚æ‚è³í‚É‘‚«ž‚Ü‚ê‚È‚©‚Á‚½‚Æ‚«‚ÍEOF‚ª•Ô‚³‚ê‚Ü‚·B

+
+ + +
+

‰ðà

+

•¶Žš—ñ‚ðƒtƒ@ƒCƒ‹‚É‘‚«ž‚Ý‚Ü‚·B‚±‚ÌŠÖ”‚Íf_putc()‚̃‰ƒbƒp[ŠÖ”‚Å‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_USE_STRFUNC‚ª 1‚Ü‚½‚Í 2‚Ì‚Æ‚«Žg—p‰Â”\‚Å‚·B2‚ðŽw’è‚·‚é‚ÆA•¶Žš—ñ‚ÉŠÜ‚Ü‚ê‚é'\n'‚Í"\r\n"‚É“WŠJ‚³‚ê‚ătƒ@ƒCƒ‹‚É‘‚«ž‚Ü‚ê‚Ü‚·B

+
+ + +
+

ŽQÆ

+

f_open, f_putc, f_printf, f_gets, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/read.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/read.html new file mode 100644 index 0000000..b4096de --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/read.html @@ -0,0 +1,79 @@ + + + + + + + +FatFs - f_read + + + + +
+

f_read

+

ƒtƒ@ƒCƒ‹‚©‚çƒf[ƒ^‚ð“Ç‚Ýo‚µ‚Ü‚·B

+
+FRESULT f_read (
+  FIL* FileObject,    /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘Ì */
+  void* Buffer,       /* “Ç‚Ýo‚µ‚½ƒf[ƒ^‚ðŠi”[‚·‚éƒoƒbƒtƒ@ */
+  UINT ByteToRead,    /* “Ç‚Ýo‚·ƒoƒCƒg” */
+  UINT* ByteRead      /* “Ç‚Ýo‚³‚ꂽƒoƒCƒg” */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Buffer
+
“Ç‚Ýo‚µ‚½ƒf[ƒ^‚ðŠi”[‚·‚éƒoƒbƒtƒ@‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
ByteToRead
+
“Ç‚Ýo‚·ƒoƒCƒg”(0`UINT‚ÌÅ‘å’l)‚ðŽw’肵‚Ü‚·B
+
ByteRead
+
ŽÀÛ‚É“Ç‚Ýo‚³‚ꂽƒoƒCƒg”‚ðŠi”[‚·‚é•Ï”‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B–ß‚è’l‚ÍŠÖ”‚̬”Û‚É‚©‚©‚í‚炸í‚É—LŒø‚Å‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DENIED
+
”ñ“Ç‚Ýž‚݃‚[ƒh‚ÅŠJ‚¢‚½ƒtƒ@ƒCƒ‹‚©‚ç“Ç‚Ýž‚à‚¤‚Æ‚µ‚½B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

“Ç‚Ýž‚ÝŠJŽnˆÊ’u‚ÍAŒ»Ý‚̃tƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚©‚ç‚É‚È‚è‚Ü‚·Bƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚Í“Ç‚Ýž‚܂ꂽƒoƒCƒg”‚¾‚¯i‚Ý‚Ü‚·B“Ç‚Ýž‚Ý’†‚Ƀtƒ@ƒCƒ‹‚ÌI’[‚É’B‚·‚é‚ÆA*ByteRead‚ÍByteToRead‚æ‚è‚ଂ³‚­‚È‚è‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

‘S‚Ä‚Ì\¬‚ÅŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

f_open, fgets, f_write, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/readdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/readdir.html new file mode 100644 index 0000000..13c6b56 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/readdir.html @@ -0,0 +1,124 @@ + + + + + + + +FatFs - f_readdir + + + + +
+

f_readdir

+

ƒfƒBƒŒƒNƒgƒŠ€–Ú‚ð“Ç‚Ýo‚µ‚Ü‚·

+
+FRESULT f_readdir (
+  DIR* DirObject,    /* ƒfƒBƒŒƒNƒgƒŠEƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^ */
+  FILINFO* FileInfo  /* ƒtƒ@ƒCƒ‹î•ñ\‘¢‘̂ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
DirObject
+
ƒfƒBƒŒƒNƒgƒŠEƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
FileInfo
+
“Ç‚Ýo‚µ‚½ƒfƒBƒŒƒNƒgƒŠ€–Ú‚ðŠi”[‚·‚éƒtƒ@ƒCƒ‹î•ñ\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃfƒBƒŒƒNƒgƒŠEƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

ƒfƒBƒŒƒNƒgƒŠ€–Ú‚ð‡ŽŸ“Ç‚Ýo‚µ‚Ü‚·B‚±‚ÌŠÖ”‚ðŒJ‚è•Ô‚µŽÀs‚·‚邱‚Æ‚É‚æ‚èƒfƒBƒŒƒNƒgƒŠ‚Ì‘S‚Ä‚Ì€–Ú‚ð“Ç‚Ýo‚·‚±‚Æ‚ª‚Å‚«‚Ü‚·B‘S‚Ä‚Ì€–Ú‚ð“Ç‚Ýo‚µA“Ç‚Ýo‚·€–Ú‚ª‚à‚¤–³‚¢‚Æ‚«‚ÍAf_name[]ƒƒ“ƒo‚Ƀkƒ‹•¶Žš—ñ‚ª•Ô‚³‚ê‚Ü‚·Bƒ{ƒŠƒ…[ƒ€–¼‚Í“Ç‚Ýo‚·‚Æ‚«‚ÉŠü‚Ä‚ç‚êAŒ»‚ê‚邱‚Æ‚Í‚ ‚è‚Ü‚¹‚ñB"."A".."‚ÍA‘Š‘΃pƒX‚ª—LŒø‚È‚Æ‚«(_FS_RPATH == 1)‚É‚Ì‚ÝŒ»‚ê‚Ü‚·B“¾‚ç‚ê‚éƒtƒ@ƒCƒ‹î•ñ‚ÌÚׂɂ‚¢‚Ä‚Í FILINFO\‘¢‘Ì‚ðŽQÆ‚µ‚Ä‚­‚¾‚³‚¢BFileInfo‚Ƀkƒ‹Eƒ|ƒCƒ“ƒ^‚ðŽw’è‚·‚é‚ÆA‚»‚̃fƒBƒŒƒNƒgƒŠ‚̃Š[ƒhEƒCƒ“ƒfƒbƒNƒX‚ðŠª‚«–ß‚µ‚Ü‚·B

+

LFN‹@”\‚ª—LŒø‚ÈŽž‚ÍAf_readdirŠÖ”‚̌ĂÑo‚µ‚Éæ—§‚Á‚ÄFILINFO\‘¢‘Ì‚Ìlfname‚Ælfsize‚ª—LŒø‚È’l‚ʼnŠú‰»‚³‚ê‚Ä‚¢‚È‚¯‚ê‚΂Ȃè‚Ü‚¹‚ñBlfname‚ÍLFN‚ðŠi”[‚·‚éƒoƒbƒtƒ@‚ÅAlfsize‚Í‚»‚̃oƒbƒtƒ@EƒTƒCƒY(•¶Žš”)‚Å‚·BŽŸ‚ÌðŒ‚Ɉê‚‚łàŠY“–‚·‚éꇂÍALFNŠi”[ƒoƒbƒtƒ@‚Ƀkƒ‹•¶Žš—ñ‚ª•Ô‚³‚ê‚Ü‚·B

+
    +
  • ‚»‚̃fƒBƒŒƒNƒgƒŠ€–Ú‚ÉLFN‚ª‘¶Ý‚µ‚È‚¢B
    • +
  • LFN‚Ì’·‚³‚ɑ΂µ‚ÄLFNŠi”[ƒoƒbƒtƒ@‚Ü‚½‚ÍLFN‘€ìƒoƒbƒtƒ@‚̃TƒCƒY‚ª•s\•ªB
    • +
  • LFN‚ÉOEMƒR[ƒh‚É‘¶Ý‚µ‚È‚¢•¶Žš‚ªŠÜ‚Ü‚ê‚Ä‚¢‚éB(Unicode API‚Å‚Í‚È‚¢‚Æ‚«)
    • +
+

‚Ü‚½Alfname‚Ƀkƒ‹Eƒ|ƒCƒ“ƒ^‚ðŽw’肵‚½ê‡‚ÍALFN‚ÉŠÖ‚µ‚ĉ½‚à•Ô‚³‚ê‚Ü‚¹‚ñBLFN‚ª‘¶Ý‚µ‚È‚¢‚Æ‚«‚ÍAf_name[]ƒƒ“ƒo‚ÌSFN‚ÉASCII‰p¬•¶Žš‚ªŠÜ‚Ü‚ê‚éꇂª‚ ‚è‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_MINIMIZE <= 1‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—á

+
+FRESULT scan_files (char* path)
+{
+    FRESULT res;
+    FILINFO fno;
+    DIR dir;
+    int i;
+    char *fn;
+#if _USE_LFN
+    static char lfn[_MAX_LFN * (_DF1S ? 2 : 1) + 1];
+    fno.lfname = lfn;
+    fno.lfsize = sizeof(lfn);
+#endif
+
+
+    res = f_opendir(&dir, path);
+    if (res == FR_OK) {
+        i = strlen(path);
+        for (;;) {
+            res = f_readdir(&dir, &fno);
+            if (res != FR_OK || fno.fname[0] == 0) break;
+            if (fno.fname[0] == '.') continue;
+#if _USE_LFN
+            fn = *fno.lfname ? fno.lfname : fno.fname;
+#else
+            fn = fno.fname;
+#endif
+            if (fno.fattrib & AM_DIR) {
+                sprintf(&path[i], "/%s", fn);
+                res = scan_files(path);
+                if (res != FR_OK) break;
+                path[i] = 0;
+            } else {
+                printf("%s/%s\n", path, fn);
+            }
+        }
+    }
+
+    return res;
+}
+
+
+ + +
+

ŽQÆ

+

f_opendir, f_stat, FILINFO, DIR

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/rename.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/rename.html new file mode 100644 index 0000000..4f4e796 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/rename.html @@ -0,0 +1,93 @@ + + + + + + + +FatFs - f_rename + + + + +
+

f_rename

+

ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚Ì–¼‘O‚Ì•ÏX‚Ü‚½‚͈ړ®B

+
+FRESULT f_rename (
+  const XCHAR* OldName, /* ŒÃ‚¢ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ–¼ */
+  const XCHAR* NewName  /* V‚µ‚¢ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ–¼ */
+);
+
+
+ +
+

ˆø”

+
+
OldName
+
•ÏX‘Îۂ̃IƒuƒWƒFƒNƒg(ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ)‚ւ̃pƒX–¼‚Ì“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
NewName
+
V‚µ‚¢ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚̃tƒ‹ƒpƒX–¼‚Ì“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·BŠù‚É‘¶Ý‚·‚é–¼‘O‚ÍŽg‚¦‚Ü‚¹‚ñB‚Ü‚½Aƒhƒ‰ƒCƒu”Ô†‚ÍŽw’è‚Å‚«‚¸AOldName‚ÅŽw’肳‚ꂽƒ{ƒŠƒ…[ƒ€ã‚̃IƒuƒWƒFƒNƒg‚Æ‚µ‚Ĉµ‚í‚ê‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_FILE
+
OldName‚̃IƒuƒWƒFƒNƒg‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_DENIED
+
ƒhƒ‰ƒCƒu—e—Ê‚Ì•s‘«“™‚Ì——R‚ÅV‚µ‚¢–¼‘O‚̃IƒuƒWƒFƒNƒg‚ªì‚ê‚È‚¢B
+
FR_EXIST
+
NewName‚Æ“¯‚¶–¼‘O‚ªŠù‚É‘¶Ý‚·‚éB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
˜_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNƒGƒŠƒA‚ªŠ„‚è“–‚Ä‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

ƒIƒuƒWƒFƒNƒg‚Ì–¼‘O‚ð•ÏX‚µ‚Ü‚·B‚Ü‚½A•Ê‚̃fƒBƒŒƒNƒgƒŠ‚ւ̈ړ®(“¯‚¶ƒhƒ‰ƒCƒu“à‚Ì‚Ý)‚à‰Â”\‚Å‚·BŠJ‚©‚ê‚Ä‚¢‚éƒIƒuƒWƒFƒNƒg‚ɑ΂µ‚ÄŽg—p‚µ‚Ä‚Í‚È‚è‚Ü‚¹‚ñB

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

Žg—p—á

+
+    /* ƒtƒ@ƒCƒ‹‚Ü‚½‚̓TƒuƒfƒBƒŒƒNƒgƒŠ‚Ì–¼‘O‚ð•ÏX‚·‚é */
+    f_rename("oldname.txt", "newname.txt");
+
+    /* ƒtƒ@ƒCƒ‹‚Ü‚½‚̓TƒuƒfƒBƒŒƒNƒgƒŠ‚Ì–¼‘O‚Ì•ÏX‚ƕʂ̃fƒBƒŒƒNƒgƒŠ‚ւ̈ړ® */
+    f_rename("oldname.txt", "dir1/newname.txt");
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sdir.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sdir.html new file mode 100644 index 0000000..7e8d5f7 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sdir.html @@ -0,0 +1,36 @@ + + + + + + + +FatFs - DIR + + + + +
+

DIR

+

DIR\‘¢‘Ì‚ÍAf_opendir(), f_readdir()‚̃[ƒNEƒGƒŠƒA‚Æ‚µ‚ÄŽg—p‚³‚ê‚Ü‚·BƒAƒvƒŠƒP[ƒVƒ‡ƒ“‚©‚ç•ÏX‰Â”\‚ȃƒ“ƒo‚Í‚ ‚è‚Ü‚¹‚ñB

+
+typedef struct _DIR_ {
+    FATFS*  fs;        /* Pointer to the owner file system object */
+    WORD    id;        /* Owner file system mount ID */
+    WORD    index;     /* Current index number */
+    DWORD   sclust;    /* Table start cluster (0:Static table) */
+    DWORD   clust;     /* Current cluster */
+    DWORD   sect;      /* Current sector */
+    BYTE*   dir;       /* Pointer to the current SFN entry in the win[] */
+    BYTE*   fn;        /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+    WCHAR*  lfn;       /* Pointer to the LFN working buffer */
+    WORD    lfn_idx;   /* Last matched LFN index (0xFFFF:No LFN) */
+#endif
+} DIR;
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfatfs.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfatfs.html new file mode 100644 index 0000000..2789e40 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfatfs.html @@ -0,0 +1,51 @@ + + + + + + + +FatFs - FATFS + + + + +
+

FATFS

+

FATFS\‘¢‘Ì‚ÍAŒÂX‚̘_—ƒhƒ‰ƒCƒu‚̃_ƒCƒiƒ~ƒbƒNEƒ[ƒNEƒGƒŠƒA‚ð•ÛŽ‚µAf_mount()‚ÅFatFsƒ‚ƒWƒ…[ƒ‹‚É“o˜^‚³‚ê‚Ü‚·B•W€ó‘Ô‚Å‚ÍŽŸ‚̂悤‚ȃƒ“ƒo‚É‚È‚Á‚Ä‚¢‚Ü‚·BƒAƒvƒŠƒP[ƒVƒ‡ƒ“‚©‚ç‘‚«Š·‚¦‰Â”\‚ȃƒ“ƒo‚Í‚ ‚è‚Ü‚¹‚ñB

+ +
+typedef struct _FATFS_ {
+    BYTE    fs_type;      /* FAT sub type */
+    BYTE    drive;        /* Physical drive number */
+    BYTE    csize;        /* Number of sectors per cluster */
+    BYTE    n_fats;       /* Number of FAT copies */
+    BYTE    wflag;        /* win[] dirty flag (1:must be written back) */
+    BYTE    fsi_flag;     /* fsinfo dirty flag (1:must be written back) */
+    WORD    id;           /* File system mount ID */
+    WORD    n_rootdir;    /* Number of root directory entries (0 on FAT32) */
+#if _FS_REENTRANT
+    HANDLE  h_mutex;      /* Handle to the mutex (Platform dependent) */
+#endif
+#if _MAX_SS != 512
+    WORD    s_size;       /* Sector size */
+#endif
+#if !_FS_READONLY
+    DWORD   last_clust;   /* Last allocated cluster */
+    DWORD   free_clust;   /* Number of free clusters */
+    DWORD   fsi_sector;   /* fsinfo sector */
+#endif
+    DWORD   sects_fat;    /* Sectors per fat */
+    DWORD   max_clust;    /* Maximum cluster# + 1. Number of clusters is max_clust - 2 */
+    DWORD   fatbase;      /* FAT start sector */
+    DWORD   dirbase;      /* Root directory start sector (Cluster# on FAT32) */
+    DWORD   database;     /* Data start sector */
+    DWORD   winsect;      /* Current sector appearing in the win[] */
+    BYTE    win[_MAX_SS]; /* Disk access window for Directory/FAT */
+} FATFS;
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfile.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfile.html new file mode 100644 index 0000000..e30b910 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfile.html @@ -0,0 +1,41 @@ + + + + + + + +FatFs - FIL + + + + +
+

FIL

+

FIL\‘¢‘Ì‚ÍAf_open()‚Å쬂³‚êA‚»‚̃tƒ@ƒCƒ‹‚Ìó‘Ô‚ð•ÛŽ‚µ‚Ü‚·BƒAƒvƒŠƒP[ƒVƒ‡ƒ“‚©‚ç‘‚«Š·‚¦‰Â”\‚ȃƒ“ƒo‚Í‚ ‚è‚Ü‚¹‚ñB

+ +
+typedef struct _FIL_ {
+    FATFS*  fs;           /* Pointer to the owner file system object */
+    WORD    id;           /* Owner file system mount ID */
+    BYTE    flag;         /* File status flags */
+    BYTE    csect;        /* Sector address in the cluster */
+    DWORD   fptr;         /* File R/W pointer */
+    DWORD   fsize;        /* File size */
+    DWORD   org_clust;    /* File start cluster */
+    DWORD   curr_clust;   /* Current cluster */
+    DWORD   dsect;        /* Current data sector */
+#if _FS_READONLY == 0
+    DWORD   dir_sect;     /* Sector containing the directory entry */
+    BYTE*   dir_ptr;      /* Ponter to the directory entry in the window */
+#endif
+#if !_FS_TINY
+    BYTE    buf[_MAX_SS];  /* File R/W buffer */
+#endif
+} FIL;
+
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfileinfo.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfileinfo.html new file mode 100644 index 0000000..dfdb704 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sfileinfo.html @@ -0,0 +1,69 @@ + + + + + + + +FatFs - FILINFO + + + + +
+

FILINFO

+

FILINFO\‘¢‘Ì‚ÍAf_stat(), f_readdir()‚Å•Ô‚³‚ê‚éƒtƒ@ƒCƒ‹î•ñ‚ð•ÛŽ‚µ‚Ü‚·B

+
+typedef struct _FILINFO_ {
+    DWORD fsize;     /* File size */
+    WORD fdate;      /* Last modified date */
+    WORD ftime;      /* Last modified time */
+    BYTE fattrib;    /* Attribute */
+    char fname[13];  /* Short file name (8.3 format) */
+#if _USE_LFN
+    XCHAR* lfname;   /* Pointer to the LFN buffer */
+    int lfsize;      /* Size of LFN buffer [characters] */
+#endif
+} FILINFO;
+
+
+ +

ƒƒ“ƒo

+
+
fsize
+
ƒtƒ@ƒCƒ‹‚̃oƒCƒg’PˆÊ‚̃TƒCƒY‚ªŠi”[‚³‚ê‚Ü‚·BƒfƒBƒŒƒNƒgƒŠ‚ÌꇂÍí‚É0‚Å‚·B
+
fdate
+
ƒtƒ@ƒCƒ‹‚Ì•ÏX‚³‚ꂽ“ú•tA‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚Ì쬂³‚ꂽ“ú•t‚ªŠi”[‚³‚ê‚Ü‚·B
+
+
bit15:9
+
1980”N‚ð‹N“_‚Æ‚µ‚½”N‚ª 0..127 ‚Å“ü‚è‚Ü‚·B
+
bit8:5
+
ŒŽ‚ª 1..12 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit4:0
+
“ú‚ª 1..31 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
+
+
ftime
+
ƒtƒ@ƒCƒ‹‚Ì•ÏX‚³‚ꂽŽžA‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚Ì쬂³‚ꂽŽž‚ªŠi”[‚³‚ê‚Ü‚·B
+
+
bit15:11
+
Žž‚ª 0..23 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit10:5
+
•ª‚ª 0..59 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
bit4:0
+
•b/2‚ª 0..29 ‚Ì’l‚Å“ü‚è‚Ü‚·B
+
+
+
fattrib
+
‘®«ƒtƒ‰ƒO‚ªŠi”[‚³‚ê‚Ü‚·Bƒtƒ‰ƒO‚ÍAM_DIR, AM_RDO, AM_HID, AM_SYS, AM_ARC‚Ì‘g‚݇‚킹‚Æ‚È‚è‚Ü‚·B
+
fname[]
+
8.3Œ`Ž®‚Ì–¼‘O‚ª'\0'‚ÅI‚í‚镶Žš—ñ‚Æ‚µ‚ÄŠi”[‚³‚ê‚Ü‚·B”ñLFN\¬‚Ì‚Æ‚«‚ÍAí‚ɑ啶Žš‚Å•Ô‚³‚ê‚Ü‚·BLFN\¬‚Ì‚Æ‚«‚Í’Z‚¢–¼‘O‚ª•Ô‚³‚ê‚Ü‚·‚ªAASCII‰pŽš‚ª¬•¶Žš‚É‚È‚éꇂª‚ ‚è‚Ü‚·B
+
lfname
+
•Ô‚³‚ê‚é’·‚¢ƒtƒ@ƒCƒ‹–¼‚ðŠi”[‚·‚éƒoƒbƒtƒ@‚ւ̃|ƒCƒ“ƒ^B‚±‚Ì\‘¢‘Ì‚ðŽg—p‚·‚é‘O‚ɃAƒvƒŠƒP[ƒVƒ‡ƒ“‚É‚æ‚艊ú‰»‚³‚ê‚È‚¯‚ê‚΂Ȃè‚Ü‚¹‚ñB”ñLFN\¬‚Ì‚Æ‚«‚Í‚±‚̃ƒ“ƒo‚Í‘¶Ý‚µ‚Ü‚¹‚ñB
+
lfsize
+
’·‚¢ƒtƒ@ƒCƒ‹–¼‚ðŠi”[‚·‚éƒoƒbƒtƒ@‚̃TƒCƒY(•¶Žš”)B‚±‚Ì\‘¢‘Ì‚ðŽg—p‚·‚é‘O‚ɃAƒvƒŠƒP[ƒVƒ‡ƒ“‚É‚æ‚艊ú‰»‚³‚ê‚È‚¯‚ê‚΂Ȃè‚Ü‚¹‚ñB”ñLFN\¬‚Ì‚Æ‚«‚Í‚±‚̃ƒ“ƒo‚Í‘¶Ý‚µ‚Ü‚¹‚ñB
+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/stat.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/stat.html new file mode 100644 index 0000000..3db289c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/stat.html @@ -0,0 +1,80 @@ + + + + + + + +FatFs - f_stat + + + + +
+

f_stat

+
+FRESULT f_stat (
+  const char* FileName,  /* ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ–¼‚ւ̃|ƒCƒ“ƒ^ */
+  FILINFO* FileInfo      /* ƒtƒ@ƒCƒ‹î•ñ\‘¢‘̂ւ̃|ƒCƒ“ƒ^ *
+);
+
+
+ +
+

ˆø”

+
+
FileName
+
î•ñ‚𓾂éƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ–¼‚Ì'\0'‚ÅI‚í‚镶Žš—ñ‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
FileInfo
+
“Ç‚Ýo‚µ‚½ƒtƒ@ƒCƒ‹î•ñ‚ðŠi”[‚·‚éƒtƒ@ƒCƒ‹î•ñ\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_FILE
+
ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
˜_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNƒGƒŠƒA‚ªŠ„‚è“–‚Ä‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

ƒtƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚ÉŠÖ‚·‚éî•ñ‚𓾂܂·B“¾‚ç‚ê‚éƒtƒ@ƒCƒ‹î•ñ‚ÌÚׂɂ‚¢‚Ä‚Í FILINFO\‘¢‘Ì‚ðŽQÆ‚µ‚Ä‚­‚¾‚³‚¢B

+
+ + +
+

‘Ήžî•ñ

+

_FS_MINIMIZE == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

f_opendir, f_readdir, FILINFO, DIR

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sync.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sync.html new file mode 100644 index 0000000..670ccfb --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/sync.html @@ -0,0 +1,68 @@ + + + + + + + +FatFs - f_sync + + + + +
+

f_sync

+

‘‚«ž‚Ý’†‚̃tƒ@ƒCƒ‹‚̃LƒƒƒbƒVƒ…‚³‚ꂽî•ñ‚ðƒtƒ‰ƒbƒVƒ…‚µ‚Ü‚·B

+
+FRESULT f_sync (
+  FIL* FileObject     /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
sync‚·‚éƒtƒ@ƒCƒ‹‚̃tƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ª–³ŒøB
+
+
+ + +
+

‰ðà

+

‚±‚ÌŠÖ”‚Íf_close()‚Æ“¯‚¶ˆ—‚ðŽÀs‚µ‚Ü‚·‚ªAƒtƒ@ƒCƒ‹‚͈ø‚«‘±‚«ŠJ‚©‚ꂽ‚Ü‚Ü‚É‚È‚èA“Ç‚Ý‘‚«‚ð‘±s‚Å‚«‚Ü‚·BƒƒMƒ“ƒO‚È‚ÇA‘‚«ž‚݃‚[ƒh‚Å’·ŽžŠÔƒtƒ@ƒCƒ‹‚ªŠJ‚©‚ê‚Ä‚¢‚éƒAƒvƒŠƒP[ƒVƒ‡ƒ“‚É‚¨‚¢‚ÄA’èŠú“I‚Ü‚½‚Í‹æØ‚è‚Ì—Ç‚¢‚Æ‚±‚ë‚Åsync‚·‚邱‚Æ‚É‚æ‚èA•sˆÓ‚Ì“dŒ¹’f‚⃃fƒBƒA‚ÌŽæ‚èŠO‚µ‚É‚æ‚莸‚í‚ê‚éƒf[ƒ^‚ðŬ‚É‚·‚邱‚Æ‚ª‚Å‚«‚Ü‚·BŽÀÛ‚Ì‚Æ‚±‚ëAf_close‚Å‚Ísync‚µ‚½‚ ‚ƃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ð”jŠü‚µ‚Ä‚¢‚邾‚¯‚È‚Ì‚ÅAf_close’¼‘O‚Ìsync‚͈Ӗ¡‚ª‚ ‚è‚Ü‚¹‚ñB

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

f_close

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/truncate.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/truncate.html new file mode 100644 index 0000000..c002609 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/truncate.html @@ -0,0 +1,71 @@ + + + + + + + +FatFs - f_truncate + + + + +
+

f_truncate

+

ƒtƒ@ƒCƒ‹’·‚ðØ‚è‹l‚ß‚Ü‚·B

+
+FRESULT f_truncate (
+  FIL* FileObject     /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
Ø‚è‹l‚ß‘ÎÛƒtƒ@ƒCƒ‹‚̃tƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg‚ւ̃|ƒCƒ“ƒ^
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DENIED
+
ƒtƒ@ƒCƒ‹‚ª”ñ‘‚«ž‚݃‚[ƒh‚ÅŠJ‚©‚ê‚Ä‚¢‚éB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

ƒtƒ@ƒCƒ‹‚Ì’·‚³‚ªŒ»Ý‚̃tƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚ÉØ‚è‹l‚ß‚ç‚ê‚Ü‚·Bƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚ªƒtƒ@ƒCƒ‹‚ÌI’[‚ðŽw‚µ‚Ä‚¢‚é‚Æ‚«‚ÍA‚±‚ÌŠÖ”‚͉½‚ÌŒø‰Ê‚àŽ‚¿‚Ü‚¹‚ñB

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

f_open, f_lseek, FIL

+
+ + +

Return

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/unlink.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/unlink.html new file mode 100644 index 0000000..de3fb75 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/unlink.html @@ -0,0 +1,76 @@ + + + + + + + +FatFs - f_unlink + + + + +
+

f_unlink

+

ƒIƒuƒWƒFƒNƒg‚ð휂µ‚Ü‚·B

+
+FRESULT f_unlink (
+  const XCHAR* FileName  /* ƒIƒuƒWƒFƒNƒg–¼‚ւ̃|ƒCƒ“ƒ^ */
+);
+
+
+ +
+

ˆø”

+
+
FileName
+
휑Îۂ̃tƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ–¼‚Ì“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_FILE
+
ƒtƒ@ƒCƒ‹‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_DRIVE
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_DENIED
+
‘ÎÛƒIƒuƒWƒFƒNƒg‚ªƒŠ[ƒhEƒIƒ“ƒŠ[‘®«AƒfƒBƒŒƒNƒgƒŠ‚Ìꇂ͋ó‚Å‚È‚¢ê‡‚È‚ÇB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
˜_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ªŠ„‚è“–‚Ä‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

ƒIƒuƒWƒFƒNƒg‚ð휂µ‚Ü‚·BŠJ‚©‚ê‚Ä‚¢‚éƒIƒuƒWƒFƒNƒg‚âƒJƒŒƒ“ƒgEƒfƒBƒŒƒNƒgƒŠ‚Í휂µ‚Ä‚Í‚È‚è‚Ü‚¹‚ñB

+
+ +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/utime.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/utime.html new file mode 100644 index 0000000..05a36a6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/utime.html @@ -0,0 +1,83 @@ + + + + + + + +FatFs - f_utime + + + + +
+

f_utime

+

ƒIƒuƒWƒFƒNƒg‚̃^ƒCƒ€ƒXƒ^ƒ“ƒv‚ð•ÏX‚µ‚Ü‚·B

+
+FRESULT f_utime (
+  const XCHAR* FileName,   /* ƒIƒuƒWƒFƒNƒg–¼‚ւ̃|ƒCƒ“ƒ^ */
+  const FILINFO* TimeDate  /* Ý’è‚·‚é“ú•t */
+);
+
+
+ +
+

ˆø”

+
+
FileName
+
•ÏX‘Îۂ̃tƒ@ƒCƒ‹‚Ü‚½‚̓fƒBƒŒƒNƒgƒŠ‚ւ̃pƒX–¼‚Ì“ü‚Á‚½'\0'‚ÅI‚í‚镶Žš—ñ‚ðŽw’肵‚Ü‚·B
+
TimeDate
+
Ý’è‚·‚é“ú•t‚ÆŽžŠÔ‚ðfdate‚Æftimeƒƒ“ƒo‚Éݒ肳‚ꂽFILINFO\‘¢‘̂ւ̃|ƒCƒ“ƒ^B‘¼‚̃ƒ“ƒo‚ÍDon't care‚Å‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_NO_FILE
+
ƒtƒ@ƒCƒ‹‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_NO_PATH
+
ƒpƒX‚ªŒ©‚‚©‚ç‚È‚¢B
+
FR_INVALID_NAME
+
ƒpƒX–¼‚ª•s³B
+
FR_INVALID_NAME
+
ƒhƒ‰ƒCƒu”Ô†‚ª•s³B
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_WRITE_PROTECTED
+
ƒƒfƒBƒA‚ª‘‚«ž‚Ý‹ÖŽ~ó‘ÔB
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_ENABLED
+
‚»‚̘_—ƒhƒ‰ƒCƒu‚Ƀ[ƒNEƒGƒŠƒA‚ª—^‚¦‚ç‚ê‚Ä‚¢‚È‚¢B
+
FR_NO_FILESYSTEM
+
ƒfƒBƒXƒNã‚É—LŒø‚ÈFATƒ{ƒŠƒ…[ƒ€‚ªŒ©‚‚©‚ç‚È‚¢B
+
+
+ + +
+

‰ðà

+

ƒIƒuƒWƒFƒNƒg‚̃^ƒCƒ€ƒXƒ^ƒ“ƒv‚ð•ÏX‚µ‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚ÅAŠŽ‚Â_FS_MINIMIZE == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

f_stat, FILINFO

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/write.html b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/write.html new file mode 100644 index 0000000..447e779 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/ja/write.html @@ -0,0 +1,79 @@ + + + + + + + +FatFs - f_write + + + + +
+

f_write

+

ƒtƒ@ƒCƒ‹‚Ƀf[ƒ^‚ð‘‚«ž‚Ý‚Ü‚·B

+
+FRESULT f_write (
+  FIL* FileObject,     /* ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg */
+  const void* Buffer,  /* ‘‚«ž‚݃f[ƒ^ */
+  UINT ByteToWrite,    /* ‘‚«ž‚ÞƒoƒCƒg” */
+  UINT* ByteWritten    /* ‘‚«ž‚܂ꂽƒoƒCƒg” */
+);
+
+
+ +
+

ˆø”

+
+
FileObject
+
ƒtƒ@ƒCƒ‹EƒIƒuƒWƒFƒNƒg\‘¢‘̂ւ̃|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
Buffer
+
‘‚«ž‚Þƒf[ƒ^‚ðŠi”[‚µ‚½ƒoƒbƒtƒ@‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B
+
ByteToWrite
+
‘‚«ž‚ÞƒoƒCƒg”(0`UINT‚ÌÅ‘å’l)‚ðŽw’肵‚Ü‚·B
+
ByteWritten
+
‘‚«ž‚܂ꂽƒoƒCƒg”‚ðŠi”[‚·‚é•Ï”‚ðŽw‚·ƒ|ƒCƒ“ƒ^‚ðŽw’肵‚Ü‚·B–ß‚è’l‚ÍŠÖ”‚̬”Û‚É‚©‚©‚í‚炸í‚É—LŒø‚Å‚·B
+
+
+ + +
+

–ß‚è’l

+
+
FR_OK (0)
+
³íI—¹B
+
FR_DENIED
+
”ñ‘‚«ž‚݃‚[ƒh‚ÅŠJ‚©‚ꂽƒtƒ@ƒCƒ‹‚É‘‚«ž‚à‚¤‚Æ‚µ‚½B
+
FR_DISK_ERR
+
ƒfƒBƒXƒNEƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_INT_ERR
+
•s³‚ÈFAT\‘¢‚Ü‚½‚Í“à•”ƒGƒ‰[‚É‚æ‚鎸”sB
+
FR_NOT_READY
+
ƒƒfƒBƒA‚ªƒZƒbƒg‚³‚ê‚Ä‚¢‚È‚¢‚È‚ÇA•¨—ƒhƒ‰ƒCƒu‚ª“®ì•s”\ó‘ÔB
+
FR_INVALID_OBJECT
+
–³Œø‚ȃtƒ@ƒCƒ‹ƒIƒuƒWƒFƒNƒgB
+
+
+ + +
+

‰ðà

+

‘‚«ž‚ÝŠJŽnˆÊ’u‚ÍAƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚̈ʒu‚©‚ç‚É‚È‚è‚Ü‚·Bƒtƒ@ƒCƒ‹R/Wƒ|ƒCƒ“ƒ^‚ÍŽÀÛ‚É‘‚«ž‚܂ꂽƒoƒCƒg”‚¾‚¯i‚Ý‚Ü‚·BŠÖ”‚ª³íI—¹‚µ‚½ŒãA—v‹‚µ‚½ƒoƒCƒg”‚ª‘‚«ž‚܂ꂽ‚©‚Ç‚¤‚©*ByteWritten‚ðƒ`ƒFƒbƒN‚·‚ׂ«‚Å‚·B*ByteWritten < ByteToWrite‚Ì‚Æ‚«‚ÍAƒfƒBƒXƒNEƒtƒ‹‚ðˆÓ–¡‚µ‚Ü‚·B

+
+ + +
+

‘Ήžî•ñ

+

_FS_READONLY == 0‚Ì‚Æ‚«‚ÉŽg—p‰Â”\‚Å‚·B

+
+ + +
+

ŽQÆ

+

f_open, f_read, fputc, fputs, fprintf, f_close, FIL

+
+ +

–ß‚é

+ + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/updates.txt b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/updates.txt new file mode 100644 index 0000000..e2eda29 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/doc/updates.txt @@ -0,0 +1,89 @@ +R0.07e, Nov 3, 2009 + Separated out configuration options from ff.h to ffconf.h. + Added a configuration option, _LFN_UNICODE. + Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. + Fixed name matching error on the 13 char boundary. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + +R0.07c, Jun 21, 2009 + Fixed f_unlink() may return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir(). + Added f_chdrive(). + Added proper case conversion to extended characters. + +R0.07a, Apr 14, 2009 + Separated out OS dependent code on re-entrant configuration. + Added multiple sector size support. + +R0.07, Apr 01, 2009 + Merged Tiny-FatFs into FatFs as a buffer configuration option. + Added long file name support. + Added multiple code page support. + Added re-entrancy for multitask operation. + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + +R0.06, Apr 01, 2008 + Added f_forward. (Tiny-FatFs) + Added string functions: fgets, fputc, fputs and fprintf. + Improved performance of f_lseek on moving to the same or following cluster. + +R0.05a, Feb 03, 2008 + Added f_truncate. + Added f_utime. + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read can be mistruncated. + Fixed cached sector is left not flushed when create and close without write. + +R0.05, Aug 26, 2007 + Changed arguments of f_read, f_write. + Changed arguments of f_mkfs. (FatFs) + Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs) + Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs) + +R0.04b, May 05, 2007 + Added _USE_NTFLAG option. + Added FSInfo support. + Fixed some problems corresponds to FAT32. (Tiny-FatFs) + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (<= csize) collapses the file object. + +R0.04a, Apr 01, 2007 + Supported multiple partitions on a plysical drive. (FatFs) + Added minimization level 3. + Added a capability of extending file size to f_lseek. + Fixed an endian sensitive code in f_mkfs. (FatFs) + Fixed a problem corresponds to FAT32 support. (Tiny-FatFs) + +R0.04, Feb 04, 2007 + Supported multiple drive system. (FatFs) + Changed some APIs for multiple drive system. + Added f_mkfs. (FatFs) + Added _USE_FAT32 option. (Tiny-FatFs) + +R0.03a, Dec 11, 2006 + Improved cluster scan algolithm to write files fast. + Fixed f_mkdir creates incorrect directory on FAT32. + +R0.03, Sep 22, 2006 + Added f_rename. + Changed option _FS_MINIMUM to _FS_MINIMIZE. + +R0.02a, Jun 10, 2006 + Added a configuration option _FS_MINIMUM. + +R0.02, Jun 01, 2006 + Added FAT12. + Removed unbuffered mode. + Fixed a problem on small (<32M) patition. + +R0.01, Apr 29, 2006 + First release + +R0.00, Feb 26, 2006 + Prototype (not released) + diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/00readme.txt b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/00readme.txt new file mode 100644 index 0000000..c46a0fa --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/00readme.txt @@ -0,0 +1,110 @@ +FatFs Module Source Files R0.07e (C)ChaN, 2009 + + +FILES + + ffconf.h Configuration file for FatFs module. + ff.h Common include file for FatFs and application module. + ff.c FatFs module. + diskio.h Common include file for FatFs and disk I/O module. + diskio.c Skeleton of low level disk I/O module. + integer.h Alternative type definitions for integer variables. + option Optional external functions. + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and not depend on any specific + storage device. You have to provide a low level disk I/O module that written + to control your storage device. + + + +AGREEMENTS + + FatFs module is an open source software to implement FAT file system to + small embedded systems. This is a free software and is opened for education, + research and commercial developments under license policy of following trems. + + Copyright (C) 2009, ChaN, all right reserved. + + * The FatFs module is a free software and there is NO WARRANTY. + * No restriction on use. You can use, modify and redistribute it for + personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. + * Redistributions of source code must retain the above copyright notice. + + + +REVISION HISTORY + + Feb 26, 2006 R0.00 Prototype + + Apr 29, 2006 R0.01 First release. + + Jun 01, 2006 R0.02 Added FAT12. + Removed unbuffered mode. + Fixed a problem on small (<32M) patition. + + Jun 10, 2006 R0.02a Added a configuration option _FS_MINIMUM. + + Sep 22, 2006 R0.03 Added f_rename. + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + Dec 11, 2006 R0.03a Improved cluster scan algolithm to write files fast. + Fixed f_mkdir creates incorrect directory on FAT32. + + Feb 04, 2007 R0.04 Supported multiple drive system. (FatFs) + Changed some APIs for multiple drive system. + Added f_mkfs. (FatFs) + Added _USE_FAT32 option. (Tiny-FatFs) + + Apr 01, 2007 R0.04a Supported multiple partitions on a plysical drive. (FatFs) + Fixed an endian sensitive code in f_mkfs. (FatFs) + Added a capability of extending the file size to f_lseek. + Added minimization level 3. + Fixed a problem that can collapse a sector when recreate an + existing file in any sub-directory at non FAT32 cfg. (Tiny-FatFs) + + May 05, 2007 R0.04b Added _USE_NTFLAG option. + Added FSInfo support. + Fixed some problems corresponds to FAT32. (Tiny-FatFs) + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (0 < ofs <= csize) collapses the file object. + + Aug 25, 2007 R0.05 Changed arguments of f_read, f_write. + Changed arguments of f_mkfs. (FatFs) + Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs) + Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs) + + Feb 03, 2008 R0.05a Added f_truncate(). + Added f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + Apr 01, 2008 R0.06 Added f_forward(). (Tiny-FatFs) + Added string functions: fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on move to the same or following cluster. + + Apr 01, 2009, R0.07 Merged Tiny-FatFs as a buffer configuration option. + Added long file name support. + Added multiple code page support. + Added re-entrancy for multitask operation. + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + Apr 14, 2009, R0.07a Separated out OS dependent code on reentrant cfg. + Added multiple sector size support. + + Jun 21, 2009, R0.07c Fixed f_unlink() may return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir(). + Added f_chdrive(). + Added proper case conversion for extended characters. + + Nov 03,'2009 R0.07e Separated out configuration options from ff.h to ffconf.h. + Added a configuration option, _LFN_UNICODE. + Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. + Fixed name matching error on the 13 char boundary. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/Copy of ff.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/Copy of ff.c new file mode 100644 index 0000000..80efa7b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/Copy of ff.c @@ -0,0 +1,3153 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.07e (C)ChaN, 2009 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following trems. +/ +/ Copyright (C) 2009, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) patition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algolithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a plysical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close +/ without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same +/ or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. +/ Added long file name support. +/ Added multiple code page support. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size support. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended char. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. +/ Fixed name matching error on the 13 char boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper +/ case on non-LFN cfg. +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* FatFs configurations and declarations */ +#include "diskio.h" /* Declarations of low level disk I/O functions */ + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 0x007E +#error Wrong include file (ff.h). +#endif + +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area must not be used in re-entrant configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } + +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res + +#endif + +#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } + +#ifndef NULL +#define NULL 0 +#endif + +/* Name status flags */ +#define NS 11 /* Offset of name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + + + +/*-------------------------------------------------------------------------- + + Private Work Area + +---------------------------------------------------------------------------*/ + +#if _DRIVES < 1 || _DRIVES > 9 +#error Number of drives must be 1-9. +#endif +static +FATFS *FatFs[_DRIVES]; /* Pointer to the file system objects (logical drives) */ + +static +WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH +static +BYTE Drive; /* Current drive */ +#endif + + +#if _USE_LFN == 1 /* LFN with static LFN working buffer */ +static +WCHAR LfnBuf[_MAX_LFN + 1]; +#define NAMEBUF(sp,lp) BYTE sp[12]; WCHAR *lp = LfnBuf +#define INITBUF(dj,sp,lp) dj.fn = sp; dj.lfn = lp + +#elif _USE_LFN > 1 /* LFN with dynamic LFN working buffer */ +#define NAMEBUF(sp,lp) BYTE sp[12]; WCHAR lbuf[_MAX_LFN + 1], *lp = lbuf +#define INITBUF(dj,sp,lp) dj.fn = sp; dj.lfn = lp + +#else /* No LFN */ +#define NAMEBUF(sp,lp) BYTE sp[12] +#define INITBUF(dj,sp,lp) dj.fn = sp + +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, int cnt) { + char *d = (char*)dst; + const char *s = (const char *)src; + while (cnt--) *d++ = *s++; +} + +/* Fill memory */ +static +void mem_set (void* dst, int val, int cnt) { + char *d = (char*)dst; + while (cnt--) *d++ = (char)val; +} + +/* Compare memory to memory */ +static +int mem_cmp (const void* dst, const void* src, int cnt) { + const char *d = (const char *)dst, *s = (const char *)src; + int r = 0; + while (cnt-- && (r = *d++ - *s++) == 0) ; + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + while (*str && *str != chr) str++; + return *str; +} + + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT + +static +BOOL lock_fs ( + FATFS *fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS *fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT move_window ( + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make apperance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + if (fs->wflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drive, fs->win, wsect, 1) != RES_OK) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect < (fs->fatbase + fs->sects_fat)) { /* In FAT area */ + BYTE nf; + for (nf = fs->n_fats; nf > 1; nf--) { /* Refrect the change to all FAT copies */ + wsect += fs->sects_fat; + disk_write(fs->drive, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drive, fs->win, sector, 1) != RES_OK) + return FR_DISK_ERR; + fs->winsect = sector; + } + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS *fs /* File system object */ +) +{ + FRESULT res; + + + res = move_window(fs, 0); + if (res == FR_OK) { + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + mem_set(fs->win, 0, 512); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + disk_write(fs->drive, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drive, CTRL_SYNC, (void*)NULL) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Interal error, Else:Cluster status */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + DWORD fsect; + + + if (clst < 2 || clst >= fs->max_clust) /* Range check */ + return 1; + + fsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + if (move_window(fs, fsect + (bc / SS(fs)))) break; + wc = fs->win[bc & (SS(fs) - 1)]; bc++; + if (move_window(fs, fsect + (bc / SS(fs)))) break; + wc |= (WORD)fs->win[bc & (SS(fs) - 1)] << 8; + return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fsect + (clst / (SS(fs) / 2)))) break; + return LD_WORD(&fs->win[((WORD)clst * 2) & (SS(fs) - 1)]); + + case FS_FAT32 : + if (move_window(fs, fsect + (clst / (SS(fs) / 4)))) break; + return LD_DWORD(&fs->win[((WORD)clst * 4) & (SS(fs) - 1)]) & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occured at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +FRESULT put_fat ( + FATFS *fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->max_clust - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + DWORD fsect; + FRESULT res; + + + if (clst < 2 || clst >= fs->max_clust) { /* Range check */ + res = FR_INT_ERR; + + } else { + fsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + res = move_window(fs, fsect + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fsect + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fsect + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + ST_WORD(&fs->win[((WORD)clst * 2) & (SS(fs) - 1)], (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fsect + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + ST_DWORD(&fs->win[((WORD)clst * 4) & (SS(fs) - 1)], val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; + + + if (clst < 2 || clst >= fs->max_clust) { /* Check the range of cluster# */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->max_clust) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ + fs->free_clust++; + fs->fsi_flag = 1; + } + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl, mcl; + + + mcl = fs->max_clust; + if (clst == 0) { /* Create new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (scl == 0 || scl >= mcl) scl = 1; + } + else { /* Stretch existing chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* It is an invalid cluster */ + if (cs < mcl) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= mcl) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free custer */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occured */ + return cs; + if (ncl == scl) return 0; /* No free custer */ + } + + if (put_fat(fs, ncl, 0x0FFFFFFF)) /* Mark the new cluster "in use" */ + return 0xFFFFFFFF; + if (clst != 0) { /* Link it to the previous one if needed */ + if (put_fat(fs, clst, ncl)) + return 0xFFFFFFFF; + } + + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag = 1; + } + + return ncl; /* Return new cluster number */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->max_clust - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Seek directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_seek ( + DIR *dj, /* Pointer to directory object */ + WORD idx /* Directory index number */ +) +{ + DWORD clst; + WORD ic; + + + dj->index = idx; + clst = dj->sclust; + if (clst == 1 || clst >= dj->fs->max_clust) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dj->fs->dirbase; + + if (clst == 0) { /* Static table */ + dj->clust = clst; + if (idx >= dj->fs->n_rootdir) /* Index is out of range */ + return FR_INT_ERR; + dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */ + } + else { /* Dynamic table */ + ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dj->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dj->fs->max_clust) /* Reached to end of table or int error */ + return FR_INT_ERR; + idx -= ic; + } + dj->clust = clst; + dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */ + } + + dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not streach */ + DIR *dj, /* Pointer to directory object */ + BOOL streach /* FALSE: Do not streach table, TRUE: Streach table if needed */ +) +{ + DWORD clst; + WORD i; + + + i = dj->index + 1; + if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */ + dj->sect++; /* Next sector */ + + if (dj->clust == 0) { /* Static table */ + if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dj->fs->max_clust) { /* When it reached end of dynamic table */ +#if !_FS_READONLY + BYTE c; + if (!streach) return FR_NO_FILE; /* When do not streach, report EOT */ + clst = create_chain(dj->fs, dj->clust); /* Streach cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up streached table */ + if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ + mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ + dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ + for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ + dj->fs->wflag = 1; + if (move_window(dj->fs, 0)) return FR_DISK_ERR; + dj->fs->winsect++; + } + dj->fs->winsect -= c; /* Rewind window address */ +#else + return FR_NO_FILE; /* Report EOT */ +#endif + } + dj->clust = clst; /* Initialize data for new cluster */ + dj->sect = clust2sect(dj->fs, clst); + } + } + } + + dj->index = i; + dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ + + +static +BOOL cmp_lfn ( /* TRUE:Matched, FALSE:Not matched */ + WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ + BYTE *dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + int i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return FALSE; /* Not matched */ + } else { + if (uc != 0xFFFF) return FALSE; /* Check filler */ + } + } while (++s < 13); /* Repeat until all chars in the entry are checked */ + + if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return FALSE; + + return TRUE; /* The part of LFN matched */ +} + + + +static +BOOL pick_lfn ( /* TRUE:Succeeded, FALSE:Buffer overflow */ + WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE *dir /* Pointer to the directory entry */ +) +{ + int i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + if (i >= _MAX_LFN) return FALSE; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return FALSE; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return FALSE; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return TRUE; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ + BYTE *dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + int i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding chars following last char */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +void gen_numname ( + BYTE *dst, /* Pointer to genartated SFN */ + const BYTE *src, /* Pointer to source SFN to be modified */ + const WCHAR *lfn, /* Pointer to LFN */ + WORD num /* Sequense number */ +) +{ + char ns[8]; + int i, j; + + + mem_cpy(dst, src, 11); + + if (num > 5) { /* On many collisions, generate a hash number instead of sequencial number */ + do num = (num >> 1) + (num << 15) + (WORD)*lfn++; while (*lfn); + } + + /* itoa */ + i = 7; + do { + ns[i--] = (num % 10) + '0'; + num /= 10; + } while (num); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE *dir /* Ptr to directory entry */ +) +{ + BYTE sum = 0; + int n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR *dj /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_seek(dj, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; +#endif + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dj->lfn) { + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; /* LFN start order */ + dj->lfn_idx = dj->index; + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, FALSE); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +FRESULT dir_read ( + DIR *dj /* Pointer to the directory object that pointing the entry to be read */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dj->sect) { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; + dj->lfn_idx = dj->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dj->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, FALSE); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dj->sect = 0; + + return res; +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR *dj /* Target directory with object name to be created */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN /* LFN configuration */ + WORD n, ne, is; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dj->fn; lfn = dj->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) return FR_INVALID_NAME; /* Cannot create dot entry */ + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dj->lfn = NULL; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dj); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dj->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve reserve an SFN + LFN entries. */ + for (ne = 0; lfn[ne]; ne++) ; + ne = (ne + 25) / 13; + } else { /* Otherwise reserve only an SFN entry. */ + ne = 1; + } + + /* Reserve contiguous entries */ + res = dir_seek(dj, 0); + if (res != FR_OK) return res; + n = is = 0; + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; /* Check the entry status */ + if (c == 0xE5 || c == 0) { /* Is it a blank entry? */ + if (n == 0) is = dj->index; /* First index of the contigulus entry */ + if (++n == ne) break; /* A contiguous entry that requiered count is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dj, TRUE); /* Next entry with table streach */ + } while (res == FR_OK); + + if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ + res = dir_seek(dj, is); + if (res == FR_OK) { + sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ + ne--; + do { /* Store LFN entries in bottom first */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); + dj->fs->wflag = 1; + res = dir_next(dj, FALSE); /* Next entry */ + } while (res == FR_OK && --ne); + } + } + +#else /* Non LFN configuration */ + res = dir_seek(dj, 0); + if (res == FR_OK) { + do { /* Find a blank entry for the SFN */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; + if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */ + res = dir_next(dj, TRUE); /* Next entry with table streach */ + } while (res == FR_OK); + } +#endif + + if (res == FR_OK) { /* Initialize the SFN entry */ + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + dir = dj->dir; + mem_set(dir, 0, 32); /* Clean the entry */ + mem_cpy(dir, dj->fn, 11); /* Put SFN */ + dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ + dj->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR *dj /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD i; + + i = dj->index; /* SFN index */ + res = dir_seek(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dj, FALSE); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_seek(dj, dj->index); + if (res == FR_OK) { + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR *dj, /* Pointer to the directory object */ + const XCHAR **path /* Pointer to pointer to the segment in the path string */ +) +{ +#ifdef _EXCVT + static const BYTE cvt[] = _EXCVT; +#endif + +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + int i, ni, si, di; + const XCHAR *p; + + /* Create LFN in Unicode */ + si = di = 0; + p = *path; + lfn = dj->lfn; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* If it is a DBC 1st byte */ + b = p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) /* Reject invalid code for DBC */ + return FR_INVALID_NAME; + w = (w << 8) + b; + } + w = ff_convert(w, 1); /* Convert OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode char */ + } + *path = &p[si]; /* Rerurn pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di - 1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dj->fn[i] = (i < di) ? '.' : ' '; + dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di - 1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject null string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dj->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN char */ + if (!w) break; /* Break on enf of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII char */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = cvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte char */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dj->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte char */ + if (!w || chk_chr("+,;[=]", w)) { /* Replace illegal chars for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN; /* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dj->fn[i++] = (BYTE)w; + } + + if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dj->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + int ni, si, i; + const char *p; + + /* Create file name in directory form */ + sfn = dj->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; + p = *path; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Rerurn pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended char */ +#ifdef _EXCVT + c = cvt[c - 0x80]; /* Convert extend char (SBCS) */ +#else + b |= 3; /* Eliminate NT flag if ext char is exist */ +#if !_DF1S /* ASCII only cfg */ + return FR_INVALID_NAME; +#endif +#endif + } + if (IsDBCS1(c)) { /* DBC 1st byte? */ + d = p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr(" \"*+,[=]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Rerurn pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject null string */ + if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Filename has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + DIR *dj, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ +) +{ + int i; + BYTE c, nt, *dir; + char *p; + + + p = fno->fname; + if (dj->sect) { + dir = dj->dir; + nt = dir[DIR_NTres]; /* NT flag */ + for (i = 0; i < 8; i++) { /* Copy name body */ + c = dir[i]; + if (c == ' ') break; + if (c == 0x05) c = 0xE5; + if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; + *p++ = c; + } + if (dir[8] != ' ') { /* Copy name extension */ + *p++ = '.'; + for (i = 8; i < 11; i++) { + c = dir[i]; + if (c == ' ') break; + if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; + *p++ = c; + } + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + } + *p = 0; + +#if _USE_LFN + if (fno->lfname) { + XCHAR *tp = fno->lfname; + WCHAR w, *lfn; + + i = 0; + if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ + lfn = dj->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN char */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM conversion */ + if (!w) { i = 0; break; } /* Could not convert, no LFN */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC */ + tp[i++] = (XCHAR)(w >> 8); +#endif + if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overrun, no LFN */ + tp[i++] = (XCHAR)w; + } + } + tp[i] = 0; /* Terminator */ + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Directory object to return last directory and found object */ + const XCHAR *path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, last; + + + while (!_USE_LFN && *path == ' ') path++; /* Skip leading spaces */ +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dj->sclust = 0; /* Strip it and start from the root dir */ + } else { /* No heading saparator */ + dj->sclust = dj->fs->cdir; /* Start from the current dir */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dj->sclust = 0; /* Start from the root dir */ +#endif + + if ((UINT)*path < ' ') { /* Null path means the start directory itself */ + res = dir_seek(dj, 0); + dj->dir = NULL; + + } else { /* Follow path */ + for (;;) { + res = create_name(dj, &path); /* Get a segment */ + if (res != FR_OK) break; + res = dir_find(dj); /* Find it */ + last = *(dj->fn+NS) & NS_LAST; + if (res != FR_OK) { /* Could not find the object */ + if (res == FR_NO_FILE && !last) + res = FR_NO_PATH; + break; + } + if (last) break; /* Last segment match. Function completed. */ + dir = dj->dir; /* There is next segment. Follow the sub directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ + res = FR_NO_PATH; break; + } + dj->sclust = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load boot record and check if it is an FAT boot record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drive, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 3; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Make sure that the file system is valid */ +/*-----------------------------------------------------------------------*/ + + +FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occured */ + const XCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE fmt, *tbl; + UINT vol; + DSTATUS stat; + DWORD bsect, fsize, tsect, mclst; + const XCHAR *p = *path; + FATFS *fs; + + /* Get logical drive number from the path name */ + vol = p[0] - '0'; /* Is there a drive number? */ + if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ + p += 2; *path = p; /* Return pointer to the path name */ + } else { /* No drive number is given */ +#if _FS_RPATH + vol = Drive; /* Use current drive */ +#else + vol = 0; /* Use drive 0 */ +#endif + } + + /* Check if the logical drive is valid or not */ + if (vol >= _DRIVES) /* Is the drive number valid? */ + return FR_INVALID_DRIVE; + *rfs = fs = FatFs[vol]; /* Returen pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock file system */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drive); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be mounted. Following code attempts to mount the volume */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drive = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drive); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the drive is ready */ + return FR_NOT_READY; +#if _MAX_SS != 512 /* Get disk sector size if needed */ + if (disk_ioctl(fs->drive, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) + return FR_NO_FILESYSTEM; +#endif +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + /* Search FAT partition on the drive */ + fmt = check_fs(fs, bsect = 0); /* Check sector 0 as an SFD format */ + if (fmt == 1) { /* Not an FAT boot record, it may be patitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bsect); /* Check the partition */ + } + } + if (fmt == 3) return FR_DISK_ERR; + if (fmt || LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* No valid FAT patition is found */ + return FR_NO_FILESYSTEM; + + /* Initialize the file system object */ + fsize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fsize) fsize = LD_DWORD(fs->win+BPB_FATSz32); + fs->sects_fat = fsize; + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + fsize *= fs->n_fats; /* (Number of sectors in FAT area) */ + fs->fatbase = bsect + LD_WORD(fs->win+BPB_RsvdSecCnt); /* FAT start sector (lba) */ + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Nmuber of root directory entries */ + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + fs->max_clust = mclst = (tsect /* Last cluster# + 1 (Number of clusters + 2) */ + - LD_WORD(fs->win+BPB_RsvdSecCnt) - fsize - fs->n_rootdir / (SS(fs)/32) + ) / fs->csize + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if (mclst >= 0xFF7) fmt = FS_FAT16; /* Number of clusters >= 0xFF5 */ + if (mclst >= 0xFFF7) fmt = FS_FAT32; /* Number of clusters >= 0xFFF5 */ + + if (fmt == FS_FAT32) + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + else + fs->dirbase = fs->fatbase + fsize; /* Root directory start sector (lba) */ + fs->database = fs->fatbase + fsize + fs->n_rootdir / (SS(fs)/32); /* Data start sector (lba) */ + +#if !_FS_READONLY + /* Initialize allocation information */ + fs->free_clust = 0xFFFFFFFF; + fs->wflag = 0; + /* Get fsinfo if needed */ + if (fmt == FS_FAT32) { + fs->fsi_flag = 0; + fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); + if (disk_read(fs->drive, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(fs->win+BS_55AA) == 0xAA55 && + LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && + LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); + } + } +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->winsect = 0; /* Invalidate sector cache */ +#if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ +#endif + fs->id = ++Fsid; /* File system mount ID */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + + ENTER_FF(fs); /* Lock file system */ + + if (disk_status(fs->drive) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Locical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE vol, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + FATFS *rfs; + + + if (vol >= _DRIVES) /* Check if the drive number is valid */ + return FR_INVALID_DRIVE; + rfs = FatFs[vol]; /* Get current fs object */ + + if (rfs) { +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; +#endif + rfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const XCHAR *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + fp->fs = NULL; /* Clear file object */ +#if !_FS_READONLY + mode &= (FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW); + res = chk_mounted(&path, &dj.fs, (BYTE)(mode & (FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW))); +#else + mode &= FA_READ; + res = chk_mounted(&path, &dj.fs, 0); +#endif + if (res != FR_OK) LEAVE_FF(dj.fs, res); + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + +#if !_FS_READONLY + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD ps, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ + res = dir_register(&dj); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + mode |= FA_CREATE_ALWAYS; + dir = dj.dir; /* Created entry (SFN entry) */ + } + else { /* Any object is already existing */ + if (mode & FA_CREATE_NEW) /* Cannot create new */ + LEAVE_FF(dj.fs, FR_EXIST); + dir = dj.dir; + if (!dir || (dir[DIR_Attr] & (AM_RDO | AM_DIR))) /* Cannot overwrite it (R/O or DIR) */ + LEAVE_FF(dj.fs, FR_DENIED); + if (mode & FA_CREATE_ALWAYS) { /* Resize it to zero on over write mode */ + cl = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); /* Get start cluster */ + ST_WORD(dir+DIR_FstClusHI, 0); /* cluster = 0 */ + ST_WORD(dir+DIR_FstClusLO, 0); + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + dj.fs->wflag = 1; + ps = dj.fs->winsect; /* Remove the cluster chain */ + if (cl) { + res = remove_chain(dj.fs, cl); + if (res) LEAVE_FF(dj.fs, res); + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + } + res = move_window(dj.fs, ps); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + } + } + if (mode & FA_CREATE_ALWAYS) { + dir[DIR_Attr] = 0; /* Reset attribute */ + ps = get_fattime(); + ST_DWORD(dir+DIR_CrtTime, ps); /* Created time */ + dj.fs->wflag = 1; + mode |= FA__WRITTEN; /* Set file changed flag */ + } + } + /* Open an existing file */ + else { +#endif /* !_FS_READONLY */ + if (res != FR_OK) LEAVE_FF(dj.fs, res); /* Follow failed */ + dir = dj.dir; + if (!dir || (dir[DIR_Attr] & AM_DIR)) /* It is a directory */ + LEAVE_FF(dj.fs, FR_NO_FILE); +#if !_FS_READONLY + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + LEAVE_FF(dj.fs, FR_DENIED); + } + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; +#endif + fp->flag = mode; /* File access mode */ + fp->org_clust = /* File start cluster */ + ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; fp->csect = 255; /* File pointer */ + fp->dsect = 0; + fp->fs = dj.fs; fp->id = dj.fs->id; /* Owner file system object of the file */ + + LEAVE_FF(dj.fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE *rbuff = buff; + + + *br = 0; /* Initialize bytes read */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data transferred */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector offset in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += fp->csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_read(fp->fs->drive, rbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) /* Replace one of the read sectors with cached data if it contains a dirty sector */ + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) /* Replace one of the read sectors with cached data if it contains a dirty sector */ + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); +#endif +#endif + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */ + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (disk_read(fp->fs->drive, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + fp->csect++; /* Next sector address in the cluster */ + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#endif + } + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + + + *bw = 0; /* Initialize bytes written */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data transferred */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->org_clust; /* Follow from the origin */ + if (clst == 0) /* When there is no cluster chain, */ + fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ + clst = create_chain(fp->fs, fp->curr_clust); /* Follow or streach cluster chain */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */ + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += fp->csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_write(fp->fs->drive, wbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */ + if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drive, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + fp->csect++; /* Next sector address in the cluster */ + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file changed flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ +#if !_FS_TINY /* Write-back dirty buffer */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + ST_WORD(dir+DIR_FstClusLO, fp->org_clust); /* Update start cluster */ + ST_WORD(dir+DIR_FstClusHI, fp->org_clust >> 16); + tim = get_fattime(); /* Updated time */ + ST_DWORD(dir+DIR_WrtTime, tim); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + + +#if _FS_READONLY + res = validate(fp->fs, fp->id); + if (res == FR_OK) fp->fs = NULL; + LEAVE_FF(fp->fs, res); +#else + res = f_sync(fp); + if (res == FR_OK) fp->fs = NULL; + return res; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Current Drive/Directory */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH + +FRESULT f_chdrive ( + BYTE drv /* Drive number */ +) +{ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + + Drive = drv; + + return FR_OK; +} + + + + +FRESULT f_chdir ( + const XCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + dir = dj.dir; /* Pointer to the entry */ + if (!dir) { + dj.fs->cdir = 0; /* No entry (root dir) */ + } else { + if (dir[DIR_Attr] & AM_DIR) /* Reached to the dir */ + dj.fs->cdir = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + else + res = FR_NO_PATH; /* Could not reach the dir (it is a file) */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + +#endif + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + DWORD clst, bcs, nsect, ifptr; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; fp->csect = 255; + if (ofs > 0) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->curr_clust; + } else { /* When seek to back cluster, */ + clst = fp->org_clust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->org_clust = clst; + } +#endif + fp->curr_clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force streached if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->max_clust) ABORT(fp->fs, FR_INT_ERR); + fp->curr_clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + fp->csect = (BYTE)(ofs / SS(fp->fs)); /* Sector offset in the cluster */ + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += fp->csect; + fp->csect++; + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty buffer if needed */ + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drive, fp->buf, nsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set changed flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + + LEAVE_FF(fp->fs, res); +} + + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directroy Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const XCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj->fs, 0); + if (res == FR_OK) { + INITBUF((*dj), sfn, lfn); + res = follow_path(dj, path); /* Follow the path to the directory */ + if (res == FR_OK) { /* Follow completed */ + dir = dj->dir; + if (dir) { /* It is not the root dir */ + if (dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ + dj->sclust = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + } else { /* The object is not a directory */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dj->id = dj->fs->id; + res = dir_seek(dj, 0); /* Rewind dir */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + NAMEBUF(sfn, lfn); + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res == FR_OK) { + INITBUF((*dj), sfn, lfn); + if (!fno) { + res = dir_seek(dj, 0); + } else { + res = dir_read(dj); + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dj, fno); /* Get the object information */ + res = dir_next(dj, FALSE); /* Increment index for next */ + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + } + } + } + + LEAVE_FF(dj->fs, res); +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const XCHAR *path, /* Pointer to the file path */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follwo completed */ + if (dj.dir) /* Found an object */ + get_fileinfo(&dj, fno); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const XCHAR *path, /* Pointer to the logical drive number (root dir) */ + DWORD *nclst, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get drive number */ + res = chk_mounted(&path, fatfs, 0); + if (res != FR_OK) LEAVE_FF(*fatfs, res); + + /* If number of free cluster is valid, return it without cluster scan. */ + if ((*fatfs)->free_clust <= (*fatfs)->max_clust - 2) { + *nclst = (*fatfs)->free_clust; + LEAVE_FF(*fatfs, FR_OK); + } + + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(*fatfs, clst); + if (stat == 0xFFFFFFFF) LEAVE_FF(*fatfs, FR_DISK_ERR); + if (stat == 1) LEAVE_FF(*fatfs, FR_INT_ERR); + if (stat == 0) n++; + } while (++clst < (*fatfs)->max_clust); + } else { + clst = (*fatfs)->max_clust; + sect = (*fatfs)->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(*fatfs, sect++); + if (res != FR_OK) + LEAVE_FF(*fatfs, res); + p = (*fatfs)->win; + i = SS(*fatfs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + (*fatfs)->free_clust = n; + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; + *nclst = n; + + LEAVE_FF(*fatfs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->org_clust); + fp->org_clust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->curr_clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->max_clust) { + res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } + } + if (res != FR_OK) fp->flag |= FA__ERROR; + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const XCHAR *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + NAMEBUF(sfn, lfn); + BYTE *dir; + DWORD dclst; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res != FR_OK) LEAVE_FF(dj.fs, res); /* Follow failed */ + + dir = dj.dir; + if (!dir) /* Is it the root directory? */ + LEAVE_FF(dj.fs, FR_INVALID_NAME); + if (dir[DIR_Attr] & AM_RDO) /* Is it a R/O object? */ + LEAVE_FF(dj.fs, FR_DENIED); + dclst = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + + if (dir[DIR_Attr] & AM_DIR) { /* It is a sub-directory */ + if (dclst < 2) LEAVE_FF(dj.fs, FR_INT_ERR); + mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ + sdj.sclust = dclst; + res = dir_seek(&sdj, 2); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + res = dir_read(&sdj); + if (res == FR_OK) res = FR_DENIED; /* Not empty sub-dir */ + if (res != FR_NO_FILE) LEAVE_FF(dj.fs, res); + } + + res = dir_remove(&dj); /* Remove directory entry */ + if (res == FR_OK) { + if (dclst) + res = remove_chain(dj.fs, dclst); /* Remove the cluster chain */ + if (res == FR_OK) res = sync(dj.fs); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const XCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir, n; + DWORD dsect, dclst, pclst, tim; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any file or directory is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res != FR_NO_FILE) /* Any error occured */ + LEAVE_FF(dj.fs, res); + + dclst = create_chain(dj.fs, 0); /* Allocate a new cluster for new directory table */ + res = FR_OK; + if (dclst == 0) res = FR_DENIED; + if (dclst == 1) res = FR_INT_ERR; + if (dclst == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) + res = move_window(dj.fs, 0); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + dsect = clust2sect(dj.fs, dclst); + + dir = dj.fs->win; /* Initialize the new directory table */ + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + tim = get_fattime(); + ST_DWORD(dir+DIR_WrtTime, tim); + ST_WORD(dir+DIR_FstClusLO, dclst); + ST_WORD(dir+DIR_FstClusHI, dclst >> 16); + mem_cpy(dir+32, dir, 32); /* Create ".." entry */ + dir[33] = '.'; + pclst = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pclst == dj.fs->dirbase) + pclst = 0; + ST_WORD(dir+32+DIR_FstClusLO, pclst); + ST_WORD(dir+32+DIR_FstClusHI, pclst >> 16); + for (n = 0; n < dj.fs->csize; n++) { /* Write dot entries and clear left sectors */ + dj.fs->winsect = dsect++; + dj.fs->wflag = 1; + res = move_window(dj.fs, 0); + if (res) LEAVE_FF(dj.fs, res); + mem_set(dir, 0, SS(dj.fs)); + } + + res = dir_register(&dj); + if (res != FR_OK) { + remove_chain(dj.fs, dclst); + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tim); /* Crated time */ + ST_WORD(dir+DIR_FstClusLO, dclst); /* Table start cluster */ + ST_WORD(dir+DIR_FstClusHI, dclst >> 16); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change File Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const XCHAR *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const XCHAR *path, /* Pointer to the file/directory name */ + const FILINFO *fno /* Pointer to the timestamp to be set */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const XCHAR *path_old, /* Pointer to the old name */ + const XCHAR *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR dj_old, dj_new; + NAMEBUF(sfn, lfn); + BYTE buf[21], *dir; + DWORD dw; + + + INITBUF(dj_old, sfn, lfn); + res = chk_mounted(&path_old, &dj_old.fs, 1); + if (res == FR_OK) { + dj_new.fs = dj_old.fs; + res = follow_path(&dj_old, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (dj_old.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + } + if (res != FR_OK) LEAVE_FF(dj_old.fs, res); /* The old object is not found */ + + if (!dj_old.dir) LEAVE_FF(dj_old.fs, FR_NO_FILE); /* Is root dir? */ + mem_cpy(buf, dj_old.dir+DIR_Attr, 21); /* Save the object information */ + + mem_cpy(&dj_new, &dj_old, sizeof(DIR)); + res = follow_path(&dj_new, path_new); /* Check new object */ + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ + res = dir_register(&dj_new); /* Register the new object */ + if (res == FR_OK) { + dir = dj_new.dir; /* Copy object information into new entry */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + dj_old.fs->wflag = 1; + if (dir[DIR_Attr] & AM_DIR) { /* Update .. entry in the directory if needed */ + dw = clust2sect(dj_new.fs, (DWORD)LD_WORD(dir+DIR_FstClusHI) | LD_WORD(dir+DIR_FstClusLO)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(dj_new.fs, dw); + dir = dj_new.fs->win+32; + if (res == FR_OK && dir[1] == '.') { + dw = (dj_new.fs->fs_type == FS_FAT32 && dj_new.sclust == dj_new.fs->dirbase) ? 0 : dj_new.sclust; + ST_WORD(dir+DIR_FstClusLO, dw); + ST_WORD(dir+DIR_FstClusHI, dw >> 16); + dj_new.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj_old); /* Remove old entry */ + if (res == FR_OK) + res = sync(dj_old.fs); + } + } + } + + LEAVE_FF(dj_old.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (Available on only _FS_TINY cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL *fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btr, /* Number of bytes to forward */ + UINT *bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + + + *bf = 0; + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check error flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr && (*func)(NULL, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + fp->csect++; /* Next sector address in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += fp->csect - 1; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btr) rcnt = btr; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Multiple of 32 and <= 2048 */ +#define N_FATS 1 /* 1 or 2 */ +#define MAX_SECTOR 131072000UL /* Maximum partition size */ +#define MIN_SECTOR 2000UL /* Minimum partition size */ + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE partition, /* Partitioning rule 0:FDISK, 1:SFD */ + WORD allocsize /* Allocation unit size [bytes] */ +) +{ + static const DWORD sstbl[] = { 2048000, 1024000, 512000, 256000, 128000, 64000, 32000, 16000, 8000, 4000, 0 }; + static const WORD cstbl[] = { 32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512 }; + BYTE fmt, m, *tbl; + DWORD b_part, b_fat, b_dir, b_data; /* Area offset (LBA) */ + DWORD n_part, n_rsv, n_fat, n_dir; /* Area size */ + DWORD n_clst, d, n; + WORD as; + FATFS *fs; + DSTATUS stat; + + + /* Check validity of the parameters */ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + if (partition >= 2) return FR_MKFS_ABORTED; + + /* Check mounted drive and clear work area */ + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + drv = LD2PD(drv); + + /* Get disk statics */ + stat = disk_initialize(drv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK + || SS(fs) > _MAX_SS) + return FR_MKFS_ABORTED; +#endif + if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_part) != RES_OK || n_part < MIN_SECTOR) + return FR_MKFS_ABORTED; + if (n_part > MAX_SECTOR) n_part = MAX_SECTOR; + b_part = (!partition) ? 63 : 0; /* Boot sector */ + n_part -= b_part; + for (d = 512; d <= 32768U && d != allocsize; d <<= 1) ; /* Check validity of the allocation unit size */ + if (d != allocsize) allocsize = 0; + if (!allocsize) { /* Auto selection of cluster size */ + d = n_part; + for (as = SS(fs); as > 512U; as >>= 1) d >>= 1; + for (n = 0; d < sstbl[n]; n++) ; + allocsize = cstbl[n]; + } + if (allocsize < SS(fs)) allocsize = SS(fs); + + allocsize /= SS(fs); /* Number of sectors per cluster */ + + /* Pre-compute number of clusters and FAT type */ + n_clst = n_part / allocsize; + fmt = FS_FAT12; + if (n_clst >= 0xFF5) fmt = FS_FAT16; + if (n_clst >= 0xFFF5) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + switch (fmt) { + case FS_FAT12: + n_fat = ((n_clst * 3 + 1) / 2 + 3 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + case FS_FAT16: + n_fat = ((n_clst * 2) + 4 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + default: + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 33 - partition; + n_dir = 0; + } + b_fat = b_part + n_rsv; /* FATs start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory start sector */ + b_data = b_dir + n_dir; /* Data start sector */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK) return FR_MKFS_ABORTED; + n = (b_data + n - 1) & ~(n - 1); + n_fat += (n - b_data) / N_FATS; + /* b_dir and b_data are no longer used below */ + + /* Determine number of cluster and final check of validity of the FAT type */ + n_clst = (n_part - n_rsv - n_fat * N_FATS - n_dir) / allocsize; + if ( (fmt == FS_FAT16 && n_clst < 0xFF5) + || (fmt == FS_FAT32 && n_clst < 0xFFF5)) + return FR_MKFS_ABORTED; + + /* Create partition table if needed */ + if (!partition) { + DWORD n_disk = b_part + n_part; + + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; + ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */ + if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = (BYTE)n_disk; + tbl[6] = (BYTE)((n_disk >> 2) | 63); + } else { + ST_WORD(&tbl[6], 0xFFFF); + } + tbl[5] = 254; + if (fmt != FS_FAT32) /* System ID */ + tbl[4] = (n_part < 0x10000) ? 0x04 : 0x06; + else + tbl[4] = 0x0c; + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_part); /* Partition size in LBA */ + ST_WORD(tbl+64, 0xAA55); /* Signature */ + if (disk_write(drv, fs->win, 0, 1) != RES_OK) + return FR_DISK_ERR; + partition = 0xF8; + } else { + partition = 0xF0; + } + + /* Create boot record */ + tbl = fs->win; /* Clear buffer */ + mem_set(tbl, 0, SS(fs)); + ST_DWORD(tbl+BS_jmpBoot, 0x90FEEB); /* Boot code (jmp $, nop) */ + ST_WORD(tbl+BPB_BytsPerSec, SS(fs)); /* Sector size */ + tbl[BPB_SecPerClus] = (BYTE)allocsize; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + ST_WORD(tbl+BPB_RootEntCnt, SS(fs) / 32 * n_dir); /* Number of rootdir entries */ + if (n_part < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_part); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_part); + } + tbl[BPB_Media] = partition; /* Media descripter */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_part); /* Hidden sectors */ + n = get_fattime(); /* Use current time as a VSN */ + if (fmt != FS_FAT32) { + ST_DWORD(tbl+BS_VolID, n); /* Volume serial number */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of secters per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME FAT ", 19); /* Volume lavel, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID32, n); /* Volume serial number */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of secters per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (bs+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (bs+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME FAT32 ", 19); /* Volume lavel, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature */ + if (SS(fs) > 512U) { + ST_WORD(tbl+SS(fs)-2, 0xAA55); + } + if (disk_write(drv, tbl, b_part+0, 1) != RES_OK) + return FR_DISK_ERR; + if (fmt == FS_FAT32) + disk_write(drv, tbl, b_part+6, 1); + + /* Initialize FAT area */ + for (m = 0; m < N_FATS; m++) { + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + if (fmt != FS_FAT32) { + n = (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + n |= partition; + ST_DWORD(tbl, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + ST_DWORD(tbl+0, 0xFFFFFFF8); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Following FAT entries are filled by zero */ + for (n = 1; n < n_fat; n++) { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_DISK_ERR; + } + } + + /* Initialize Root directory */ + m = (BYTE)((fmt == FS_FAT32) ? allocsize : n_dir); + do { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_DISK_ERR; + } while (--m); + + /* Create FSInfo record if needed */ + if (fmt == FS_FAT32) { + ST_WORD(tbl+BS_55AA, 0xAA55); + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); + ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF); + disk_write(drv, tbl, b_part+1, 1); + disk_write(drv, tbl, b_part+7, 1); + } + + return (disk_ioctl(drv, CTRL_SYNC, (void*)NULL) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +char* f_gets ( + char* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer */ + FIL* fil /* Pointer to the file object */ +) +{ + int i = 0; + char *p = buff; + UINT rc; + + + while (i < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, p, 1, &rc); + if (rc != 1) break; /* Break when no data to read */ +#if _USE_STRFUNC >= 2 + if (*p == '\r') continue; /* Strip '\r' */ +#endif + i++; + if (*p++ == '\n') break; /* Break when reached end of line */ + } + *p = 0; + return i ? buff : NULL; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int f_putc ( + int chr, /* A character to be output */ + FIL* fil /* Ponter to the file object */ +) +{ + UINT bw; + char c; + + +#if _USE_STRFUNC >= 2 + if (chr == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ +#endif + if (!fil) { /* Special value may be used to switch the destination to any other device */ + /* put_console(chr); */ + return chr; + } + c = (char)chr; + f_write(fil, &c, 1, &bw); /* Write a byte to the file */ + return bw ? chr : EOF; /* Return the result */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int f_puts ( + const char* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (f_putc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int f_printf ( + FIL* fil, /* Pointer to the file object */ + const char* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + UCHAR c, f, r; + ULONG val; + char s[16]; + int i, w, res, cc; + + + va_start(arp, str); + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape cahracter */ + cc = f_putc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } + while (c >= '0' && c <= '9') { /* Precision */ + w = w * 10 + (c - '0'); + c = *str++; + } + if (c == 'l') { /* Prefix: Size is long int */ + f |= 2; c = *str++; + } + if (c == 's') { /* Type is string */ + cc = f_puts(va_arg(arp, char*), fil); + continue; + } + if (c == 'c') { /* Type is character */ + cc = f_putc(va_arg(arp, int), fil); + if (cc != EOF) cc = 1; + continue; + } + r = 0; + if (c == 'd') r = 10; /* Type is signed decimal */ + if (c == 'u') r = 10; /* Type is unsigned decimal */ + if (c == 'X') r = 16; /* Type is unsigned hexdecimal */ + if (r == 0) break; /* Unknown type */ + if (f & 2) { /* Get the value */ + val = (ULONG)va_arg(arp, long); + } else { + val = (c == 'd') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int); + } + /* Put numeral string */ + if (c == 'd') { + if (val & 0x80000000) { + val = 0 - val; + f |= 4; + } + } + i = sizeof(s) - 1; s[i] = 0; + do { + c = (UCHAR)(val % r + '0'); + if (c > '9') c += 7; + s[--i] = c; + val /= r; + } while (i && val); + if (i && (f & 4)) s[--i] = '-'; + w = sizeof(s) - 1 - w; + while (i && i > w) s[--i] = (f & 1) ? '0' : ' '; + cc = f_puts(&s[i], fil); + } + + va_end(arp); + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/fat_integer.h b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/fat_integer.h new file mode 100644 index 0000000..1d6bac3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/fat_integer.h @@ -0,0 +1,37 @@ +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER + +#if 0 +#include +#else + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +/* Boolean type */ +typedef enum { FALSE = 0, TRUE } BOOL; + +#endif + +#define _INTEGER +#endif diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/ff.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/ff.c new file mode 100644 index 0000000..7c8d55a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/ff.c @@ -0,0 +1,4460 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.07e (C)ChaN, 2009 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following trems. +/ +/ Copyright (C) 2009, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) patition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algolithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a plysical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close +/ without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same +/ or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. +/ Added long file name support. +/ Added multiple code page support. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size support. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended char. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. +/ Fixed name matching error on the 13 char boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper +/ case on non-LFN cfg. +/---------------------------------------------------------------------------*/ +#include "ff.h" /* FatFs configurations and declarations */ +#include "diskio.h" /* Declarations of low level disk I/O functions */ + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ +#if _FATFS != 0x007E + #error Wrong include file (ff.h). +#endif +#if _FS_REENTRANT + #if _USE_LFN == 1 + #error Static LFN work area must not be used in re-entrant configuration. + #endif + #define ENTER_FF( fs ) \ + { \ + if( !lock_fs(fs) ) \ + { \ + return FR_TIMEOUT; \ + } \ + } + + #define LEAVE_FF( fs, res ) \ + { \ + unlock_fs( fs, res ); \ + return res; \ + } + +#else + #define ENTER_FF( fs ) + #define LEAVE_FF( fs, res ) return res +#endif +#define ABORT( fs, res ) \ + { \ + fp->flag |= FA__ERROR; \ + LEAVE_FF( fs, res ); \ + } + +#ifndef NULL + #define NULL 0 +#endif + +/* Name status flags */ +#define NS 11 /* Offset of name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + +/*-------------------------------------------------------------------------- + + Private Work Area + +---------------------------------------------------------------------------*/ +#if _DRIVES < 1 || _DRIVES > 9 + #error Number of drives must be 1-9. +#endif +static FATFS *FatFs[_DRIVES]; /* Pointer to the file system objects (logical drives) */ + +static WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH +static BYTE Drive; /* Current drive */ +#endif +#if _USE_LFN == 1 /* LFN with static LFN working buffer */ +static WCHAR LfnBuf[_MAX_LFN + 1]; + #define NAMEBUF( sp, lp ) \ + BYTE sp[12]; \ + WCHAR *lp = LfnBuf + #define INITBUF( dj, sp, lp ) \ + dj.fn = sp; \ + dj.lfn = lp + +#elif _USE_LFN > 1 /* LFN with dynamic LFN working buffer */ + #define NAMEBUF( sp, lp ) \ + BYTE sp[12]; \ + WCHAR lbuf[_MAX_LFN + 1], *lp = lbuf + #define INITBUF( dj, sp, lp ) \ + dj.fn = sp; \ + dj.lfn = lp + +#else /* No LFN */ + #define NAMEBUF( sp, lp ) BYTE sp[12] + #define INITBUF( dj, sp, lp ) dj.fn = sp +#endif + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + +/*-----------------------------------------------------------------------*/ + +/* String functions */ + +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static void mem_cpy ( void *dst, const void *src, int cnt ) +{ + char *d = ( char * ) dst; + const char *s = ( const char * ) src; + while( cnt-- ) + { + *d++ = *s++; + } +} + +/* Fill memory */ +static void mem_set ( void *dst, int val, int cnt ) +{ + char *d = ( char * ) dst; + while( cnt-- ) + { + *d++ = ( char ) val; + } +} + +/* Compare memory to memory */ +static int mem_cmp ( const void *dst, const void *src, int cnt ) +{ + const char *d = ( const char * ) dst, *s = ( const char * ) src; + int r = 0; + while( cnt-- && (r = *d++ -*s++) == 0 ); + return r; +} + +/* Check if chr is contained in the string */ +static int chk_chr ( const char *str, int chr ) +{ + while( *str && *str != chr ) + { + str++; + } + + return *str; +} + +/*-----------------------------------------------------------------------*/ + +/* Request/Release grant to access the volume */ + +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT +static BOOL lock_fs ( FATFS * fs /* File system object */ ) +{ + return ff_req_grant( fs->sobj ); +} + +static void unlock_fs ( FATFS * fs, /* File system object */ FRESULT res /* Result code to be returned */ ) +{ + if( res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_INVALID_OBJECT && res != FR_TIMEOUT ) + { + ff_rel_grant( fs->sobj ); + } +} + +#endif + +/*-----------------------------------------------------------------------*/ + +/* Change window offset */ + +/*-----------------------------------------------------------------------*/ +static FRESULT move_window ( FATFS * fs, /* File system object */ DWORD sector /* Sector number to make apperance in the fs->win[] */ ) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + wsect = fs->winsect; + if( wsect != sector ) + { /* Changed current window */ + #if !_FS_READONLY + if( fs->wflag ) + { /* Write back dirty window if needed */ + if( disk_write(fs->drive, fs->win, wsect, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + + fs->wflag = 0; + if( wsect < (fs->fatbase + fs->sects_fat) ) + { /* In FAT area */ + BYTE nf; + for( nf = fs->n_fats; nf > 1; nf-- ) + { /* Refrect the change to all FAT copies */ + wsect += fs->sects_fat; + disk_write( fs->drive, fs->win, wsect, 1 ); + } + } + } + + #endif + if( sector ) + { + if( disk_read(fs->drive, fs->win, sector, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + + fs->winsect = sector; + } + } + + return FR_OK; +} + +/*-----------------------------------------------------------------------*/ + +/* Clean-up cached data */ + +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ FATFS * fs /* File system object */ ) +{ + FRESULT res; + + res = move_window( fs, 0 ); + if( res == FR_OK ) + { + /* Update FSInfo sector if needed */ + if( fs->fs_type == FS_FAT32 && fs->fsi_flag ) + { + fs->winsect = 0; + mem_set( fs->win, 0, 512 ); + ST_WORD( fs->win + BS_55AA, 0xAA55 ); + ST_DWORD( fs->win + FSI_LeadSig, 0x41615252 ); + ST_DWORD( fs->win + FSI_StrucSig, 0x61417272 ); + ST_DWORD( fs->win + FSI_Free_Count, fs->free_clust ); + ST_DWORD( fs->win + FSI_Nxt_Free, fs->last_clust ); + disk_write( fs->drive, fs->win, fs->fsi_sector, 1 ); + fs->fsi_flag = 0; + } + + /* Make sure that no pending write process in the physical drive */ + if( disk_ioctl(fs->drive, CTRL_SYNC, ( void * ) NULL) != RES_OK ) + { + res = FR_DISK_ERR; + } + } + + return res; +} + +#endif + +/*-----------------------------------------------------------------------*/ + +/* FAT access - Read value of a FAT entry */ + +/*-----------------------------------------------------------------------*/ +DWORD get_fat + ( /* 0xFFFFFFFF:Disk error, 1:Interal error, Else:Cluster status */ + FATFS * fs, /* File system object */ DWORD clst /* Cluster# to get the link information */ + ) +{ + UINT wc, bc; + DWORD fsect; + + if( clst < 2 || clst >= fs->max_clust ) + { /* Range check */ + return 1; + } + + fsect = fs->fatbase; + switch( fs->fs_type ) + { + case FS_FAT12: + bc = clst; + bc += bc / 2; + if( move_window(fs, fsect + (bc / SS(fs))) ) + { + break; + } + + wc = fs->win[bc & ( SS(fs) - 1 )]; + bc++; + if( move_window(fs, fsect + (bc / SS(fs))) ) + { + break; + } + + wc |= ( WORD ) fs->win[bc & ( SS(fs) - 1 )] << 8; + return( clst & 1 ) ? ( wc >> 4 ) : ( wc & 0xFFF ); + + case FS_FAT16: + if( move_window(fs, fsect + (clst / (SS(fs) / 2))) ) + { + break; + } + + return LD_WORD( &fs->win[((WORD) clst * 2) & (SS(fs) - 1)] ); + + case FS_FAT32: + if( move_window(fs, fsect + (clst / (SS(fs) / 4))) ) + { + break; + } + + return + LD_DWORD( &fs->win[((WORD) clst * 4) & (SS(fs) - 1)] ) + & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occured at the disk I/O layer */ +} + +/*-----------------------------------------------------------------------*/ + +/* FAT access - Change value of a FAT entry */ + +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +FRESULT put_fat + ( FATFS * fs, /* File system object */ DWORD clst, /* Cluster# to be changed in range of 2 to fs->max_clust - 1 */ DWORD val /* New value to mark the cluster */ ) +{ + UINT bc; + BYTE * p; + DWORD fsect; + FRESULT res; + + if( clst < 2 || clst >= fs->max_clust ) + { /* Range check */ + res = FR_INT_ERR; + } + else + { + fsect = fs->fatbase; + switch( fs->fs_type ) + { + case FS_FAT12: + bc = clst; + bc += bc / 2; + res = move_window( fs, fsect + (bc / SS(fs)) ); + if( res != FR_OK ) + { + break; + } + + p = &fs->win[bc & ( SS(fs) - 1 )]; + *p = ( clst & 1 ) ? ( (*p & 0x0F) | ((BYTE) val << 4) ) : ( BYTE ) val; + bc++; + fs->wflag = 1; + res = move_window( fs, fsect + (bc / SS(fs)) ); + if( res != FR_OK ) + { + break; + } + + p = &fs->win[bc & ( SS(fs) - 1 )]; + *p = ( clst & 1 ) ? ( BYTE ) ( val >> 4 ) : ( (*p & 0xF0) | ((BYTE) (val >> 8) & 0x0F) ); + break; + + case FS_FAT16: + res = move_window( fs, fsect + (clst / (SS(fs) / 2)) ); + if( res != FR_OK ) + { + break; + } + + ST_WORD( &fs->win[((WORD) clst * 2) & (SS(fs) - 1)], (WORD) val ); + break; + + case FS_FAT32: + res = move_window( fs, fsect + (clst / (SS(fs) / 4)) ); + if( res != FR_OK ) + { + break; + } + + ST_DWORD( &fs->win[((WORD) clst * 4) & (SS(fs) - 1)], val ); + break; + + default: + res = FR_INT_ERR; + } + + fs->wflag = 1; + } + + return res; +} + +#endif /* !_FS_READONLY */ + +/*-----------------------------------------------------------------------*/ + +/* FAT handling - Remove a cluster chain */ + +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static FRESULT remove_chain ( FATFS * fs, /* File system object */ DWORD clst /* Cluster# to remove a chain from */ ) +{ + FRESULT res; + DWORD nxt; + + if( clst < 2 || clst >= fs->max_clust ) + { /* Check the range of cluster# */ + res = FR_INT_ERR; + } + else + { + res = FR_OK; + while( clst < fs->max_clust ) + { /* Not a last link? */ + nxt = get_fat( fs, clst ); /* Get cluster status */ + if( nxt == 0 ) + { + break; /* Empty cluster? */ + } + + if( nxt == 1 ) + { + res = FR_INT_ERR; + break; + } /* Internal error? */ + if( nxt == 0xFFFFFFFF ) + { + res = FR_DISK_ERR; + break; + } /* Disk error? */ + res = put_fat( fs, clst, 0 ); /* Mark the cluster "empty" */ + if( res != FR_OK ) + { + break; + } + + if( fs->free_clust != 0xFFFFFFFF ) + { /* Update FSInfo */ + fs->free_clust++; + fs->fsi_flag = 1; + } + + clst = nxt; /* Next cluster */ + } + } + + return res; +} + +#endif + +/*-----------------------------------------------------------------------*/ + +/* FAT handling - Stretch or Create a cluster chain */ + +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static DWORD create_chain + ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS * fs, /* File system object */ DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ + ) +{ + DWORD cs, ncl, scl, mcl; + + mcl = fs->max_clust; + if( clst == 0 ) + { /* Create new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if( scl == 0 || scl >= mcl ) + { + scl = 1; + } + } + else + { /* Stretch existing chain */ + cs = get_fat( fs, clst ); /* Check the cluster status */ + if( cs < 2 ) + { + return 1; /* It is an invalid cluster */ + } + + if( cs < mcl ) + { + return cs; /* It is already followed by next cluster */ + } + + scl = clst; + } + + ncl = scl; /* Start cluster */ + for( ;; ) + { + ncl++; /* Next cluster */ + if( ncl >= mcl ) + { /* Wrap around */ + ncl = 2; + if( ncl > scl ) + { + return 0; /* No free custer */ + } + } + + cs = get_fat( fs, ncl ); /* Get the cluster status */ + if( cs == 0 ) + { + break; /* Found a free cluster */ + } + + if( cs == 0xFFFFFFFF || cs == 1 ) + { /* An error occured */ + return cs; + } + + if( ncl == scl ) + { + return 0; /* No free custer */ + } + } + + if( put_fat(fs, ncl, 0x0FFFFFFF) ) + { /* Mark the new cluster "in use" */ + return 0xFFFFFFFF; + } + + if( clst != 0 ) + { /* Link it to the previous one if needed */ + if( put_fat(fs, clst, ncl) ) + { + return 0xFFFFFFFF; + } + } + + fs->last_clust = ncl; /* Update FSINFO */ + if( fs->free_clust != 0xFFFFFFFF ) + { + fs->free_clust--; + fs->fsi_flag = 1; + } + + return ncl; /* Return new cluster number */ +} + +#endif /* !_FS_READONLY */ + +/*-----------------------------------------------------------------------*/ + +/* Get sector# from cluster# */ + +/*-----------------------------------------------------------------------*/ +DWORD clust2sect + ( /* !=0: Sector number, 0: Failed - invalid cluster# */ FATFS * fs, /* File system object */ DWORD clst /* Cluster# to be converted */ ) +{ + clst -= 2; + if( clst >= (fs->max_clust - 2) ) + { + return 0; /* Invalid cluster# */ + } + + return clst * fs->csize + fs->database; +} + +/*-----------------------------------------------------------------------*/ + +/* Directory handling - Seek directory index */ + +/*-----------------------------------------------------------------------*/ +static FRESULT dir_seek ( DIR * dj, /* Pointer to directory object */ WORD idx /* Directory index number */ ) +{ + DWORD clst; + WORD ic; + + dj->index = idx; + clst = dj->sclust; + if( clst == 1 || clst >= dj->fs->max_clust ) + { /* Check start cluster range */ + return FR_INT_ERR; + } + + if( !clst && dj->fs->fs_type == FS_FAT32 ) + { /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dj->fs->dirbase; + } + + if( clst == 0 ) + { /* Static table */ + dj->clust = clst; + if( idx >= dj->fs->n_rootdir ) + { /* Index is out of range */ + return FR_INT_ERR; + } + + dj->sect = dj->fs->dirbase + idx / ( SS(dj->fs) / 32 ); /* Sector# */ + } + else + { /* Dynamic table */ + ic = + SS( dj->fs ) + / 32 * dj->fs->csize; /* Entries per cluster */ + while( idx >= ic ) + { /* Follow cluster chain */ + clst = get_fat( dj->fs, clst ); /* Get next cluster */ + if( clst == 0xFFFFFFFF ) + { + return FR_DISK_ERR; /* Disk error */ + } + + if( clst < 2 || clst >= dj->fs->max_clust ) + { /* Reached to end of table or int error */ + return FR_INT_ERR; + } + + idx -= ic; + } + + dj->clust = clst; + dj->sect = + clust2sect( dj->fs, clst ) + + idx / ( SS(dj->fs) / 32 ); /* Sector# */ + } + + dj->dir = dj->fs->win + ( idx % (SS(dj->fs) / 32) ) * 32; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + +/*-----------------------------------------------------------------------*/ + +/* Directory handling - Move directory index next */ + +/*-----------------------------------------------------------------------*/ +static FRESULT dir_next + ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not streach */ + DIR * + dj, /* Pointer to directory object */ BOOL streach /* FALSE: Do not streach table, TRUE: Streach table if needed */ + ) +{ + DWORD clst; + WORD i; + + i = dj->index + 1; + if( !i || !dj->sect ) + { /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + } + + if( !(i % (SS(dj->fs) / 32)) ) + { /* Sector changed? */ + dj->sect++; /* Next sector */ + + if( dj->clust == 0 ) + { /* Static table */ + if( i >= dj->fs->n_rootdir ) + { /* Report EOT when end of table */ + return FR_NO_FILE; + } + } + else + { /* Dynamic table */ + if( ((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0 ) + { /* Cluster changed? */ + clst = get_fat( dj->fs, dj->clust ); /* Get next cluster */ + if( clst <= 1 ) + { + return FR_INT_ERR; + } + + if( clst == 0xFFFFFFFF ) + { + return FR_DISK_ERR; + } + + if( clst >= dj->fs->max_clust ) + { /* When it reached end of dynamic table */ + #if !_FS_READONLY + BYTE c; + if( !streach ) + { + return FR_NO_FILE; /* When do not streach, report EOT */ + } + + clst = create_chain( dj->fs, dj->clust ); /* Streach cluster chain */ + if( clst == 0 ) + { + return FR_DENIED; /* No free cluster */ + } + + if( clst == 1 ) + { + return FR_INT_ERR; + } + + if( clst == 0xFFFFFFFF ) + { + return FR_DISK_ERR; + } + + /* Clean-up streached table */ + if( move_window(dj->fs, 0) ) + { + return FR_DISK_ERR; /* Flush active window */ + } + + mem_set( dj->fs->win, 0, SS(dj->fs) ); /* Clear window buffer */ + dj->fs->winsect = clust2sect( dj->fs, clst ); /* Cluster start sector */ + for( c = 0; c < dj->fs->csize; c++ ) + { /* Fill the new cluster with 0 */ + dj->fs->wflag = 1; + if( move_window(dj->fs, 0) ) + { + return FR_DISK_ERR; + } + + dj->fs->winsect++; + } + + dj->fs->winsect -= c; /* Rewind window address */ + #else + return FR_NO_FILE; /* Report EOT */ + #endif + } + + dj->clust = clst; /* Initialize data for new cluster */ + dj->sect = clust2sect( dj->fs, clst ); + } + } + } + + dj->index = i; + dj->dir = dj->fs->win + ( i % (SS(dj->fs) / 32) ) * 32; + + return FR_OK; +} + +/*-----------------------------------------------------------------------*/ + +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ + +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static const BYTE LfnOfs[] = { 1, 3, 5, 7, 9, 14, 16, 18, 20, 22, 24, 28, 30 }; + +/* Offset of LFN chars in the directory entry */ + +static BOOL cmp_lfn + ( /* TRUE:Matched, FALSE:Not matched */ + WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ + BYTE *dir /* Pointer to the directory entry containing a part of LFN */ + ) +{ + int i, s; + WCHAR wc, uc; + + i = ( (dir[LDIR_Ord] & 0xBF) - 1 ) * 13; /* Get offset in the LFN buffer */ + s = 0; + wc = 1; + do + { + uc = LD_WORD( dir + LfnOfs[s] ); /* Pick an LFN character from the entry */ + if( wc ) + { /* Last char has not been processed */ + wc = ff_wtoupper( uc ); /* Convert it to upper case */ + if( i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++]) ) + { /* Compare it */ + return FALSE; /* Not matched */ + } + } + else + { + if( uc != 0xFFFF ) + { + return FALSE; /* Check filler */ + } + } + } while( ++s < 13 ); + + /* Repeat until all chars in the entry are checked */ + + if( (dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i] ) + { /* Last segment matched but different length */ + return FALSE; + } + + return TRUE; /* The part of LFN matched */ +} + +static BOOL pick_lfn + ( /* TRUE:Succeeded, FALSE:Buffer overflow */ + WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE *dir /* Pointer to the directory entry */ + ) +{ + int i, s; + WCHAR wc, uc; + + i = ( (dir[LDIR_Ord] & 0x3F) - 1 ) * 13; /* Offset in the LFN buffer */ + + s = 0; + wc = 1; + do + { + uc = LD_WORD( dir + LfnOfs[s] ); /* Pick an LFN character from the entry */ + if( wc ) + { /* Last char has not been processed */ + if( i >= _MAX_LFN ) + { + return FALSE; /* Buffer overflow? */ + } + + lfnbuf[i++] = wc = uc; /* Store it */ + } + else + { + if( uc != 0xFFFF ) + { + return FALSE; /* Check filler */ + } + } + } while( ++s < 13 ); + + /* Read all character in the entry */ + + if( dir[LDIR_Ord] & 0x40 ) + { /* Put terminator if it is the last LFN part */ + if( i >= _MAX_LFN ) + { + return FALSE; /* Buffer overflow? */ + } + + lfnbuf[i] = 0; + } + + return TRUE; +} + + #if !_FS_READONLY +static void fit_lfn + ( + const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ + BYTE *dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ + ) +{ + int i, s; + WCHAR wc; + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD( dir + LDIR_FstClusLO, 0 ); + + i = ( ord - 1 ) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do + { + if( wc != 0xFFFF ) + { + wc = lfnbuf[i++]; /* Get an effective char */ + } + + ST_WORD( dir + LfnOfs[s], wc ); /* Put it */ + if( !wc ) + { + wc = 0xFFFF; /* Padding chars following last char */ + } + } while( ++s < 13 ); + if( wc == 0xFFFF || !lfnbuf[i] ) + { + ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */ + } + + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + + #endif +#endif + +/*-----------------------------------------------------------------------*/ + +/* Create numbered name */ + +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +void gen_numname + ( + BYTE *dst, /* Pointer to genartated SFN */ + const BYTE *src, /* Pointer to source SFN to be modified */ + const WCHAR *lfn, /* Pointer to LFN */ + WORD num /* Sequense number */ + ) +{ + char ns[8]; + int i, j; + + mem_cpy( dst, src, 11 ); + + if( num > 5 ) + { /* On many collisions, generate a hash number instead of sequencial number */ + do + { + num = ( num >> 1 ) + ( num << 15 ) + ( WORD ) * lfn++; + } while( *lfn ); + } + + /* itoa */ + i = 7; + do + { + ns[i--] = ( num % 10 ) + '0'; + num /= 10; + } while( num ); + ns[i] = '~'; + + /* Append the number */ + for( j = 0; j < i && dst[j] != ' '; j++ ) + { + if( IsDBCS1(dst[j]) ) + { + if( j == i - 1 ) + { + break; + } + + j++; + } + } + + do + { + dst[j++] = ( i < 8 ) ? ns[i++] : ' '; + } while( j < 8 ); +} + +#endif + +/*-----------------------------------------------------------------------*/ + +/* Calculate sum of an SFN */ + +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static BYTE sum_sfn( const BYTE *dir /* Ptr to directory entry */ ) +{ + BYTE sum = 0; + int n = 11; + + do + { + sum = ( sum >> 1 ) + ( sum << 7 ) +*dir++; + } while( --n ); + return sum; +} + +#endif + +/*-----------------------------------------------------------------------*/ + +/* Directory handling - Find an object in the directory */ + +/*-----------------------------------------------------------------------*/ +static FRESULT dir_find( DIR *dj /* Pointer to the directory object linked to the file name */ ) +{ + FRESULT res; + BYTE c, *dir; + #if _USE_LFN + BYTE a, ord, sum; + #endif + res = dir_seek( dj, 0 ); /* Rewind directory object */ + if( res != FR_OK ) + { + return res; + } + + #if _USE_LFN + ord = sum = 0xFF; + #endif + do + { + res = move_window( dj->fs, dj->sect ); + if( res != FR_OK ) + { + break; + } + + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if( c == 0 ) + { + res = FR_NO_FILE; + break; + } /* Reached to end of table */ + + #if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if( c == 0xE5 || ((a & AM_VOL) && a != AM_LFN) ) + { /* An entry without valid data */ + ord = 0xFF; + } + else + { + if( a == AM_LFN ) + { /* An LFN entry is found */ + if( dj->lfn ) + { + if( c & 0x40 ) + { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; + ord = c; /* LFN start order */ + dj->lfn_idx = dj->index; + } + + /* Check validity of the LFN entry and compare it with given name */ + ord = ( c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir) ) ? ord - 1 : 0xFF; + } + } + else + { /* An SFN entry is found */ + if( !ord && sum == sum_sfn(dir) ) + { + break; /* LFN matched? */ + } + + ord = 0xFF; + dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if( !(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11) ) + { + break; /* SFN matched? */ + } + } + } + + #else /* Non LFN configuration */ + if( !(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11) ) + { /* Is it a valid entry? */ + break; + } + + #endif + res = dir_next( dj, FALSE ); /* Next entry */ + } while( res == FR_OK ); + + return res; +} + +/*-----------------------------------------------------------------------*/ + +/* Read an object from the directory */ + +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static FRESULT dir_read( DIR *dj /* Pointer to the directory object that pointing the entry to be read */ ) +{ + FRESULT res; + BYTE c, *dir; + #if _USE_LFN + BYTE a, ord = 0xFF, sum = 0xFF; + #endif + res = FR_NO_FILE; + while( dj->sect ) + { + res = move_window( dj->fs, dj->sect ); + if( res != FR_OK ) + { + break; + } + + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if( c == 0 ) + { + res = FR_NO_FILE; + break; + } /* Reached to end of table */ + + #if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if( c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN) ) + { /* An entry without valid data */ + ord = 0xFF; + } + else + { + if( a == AM_LFN ) + { /* An LFN entry is found */ + if( c & 0x40 ) + { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; + ord = c; + dj->lfn_idx = dj->index; + } + + /* Check LFN validity and capture it */ + ord = ( c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir) ) ? ord - 1 : 0xFF; + } + else + { /* An SFN entry is found */ + if( ord || sum != sum_sfn(dir) ) + { /* Is there a valid LFN? */ + dj->lfn_idx = 0xFFFF; /* It has no LFN. */ + } + + break; + } + } + + #else /* Non LFN configuration */ + if( c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL) ) + { /* Is it a valid entry? */ + break; + } + + #endif + res = dir_next( dj, FALSE ); /* Next entry */ + if( res != FR_OK ) + { + break; + } + } + + if( res != FR_OK ) + { + dj->sect = 0; + } + + return res; +} + +#endif + +/*-----------------------------------------------------------------------*/ + +/* Register an object to the directory */ + +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static FRESULT dir_register + ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR *dj /* Target directory with object name to be created */ + ) +{ + FRESULT res; + BYTE c, *dir; + #if _USE_LFN /* LFN configuration */ + WORD n, ne, is; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + fn = dj->fn; + lfn = dj->lfn; + mem_cpy( sn, fn, 12 ); + + if( _FS_RPATH && (sn[NS] & NS_DOT) ) + { + return FR_INVALID_NAME; /* Cannot create dot entry */ + } + + if( sn[NS] & NS_LOSS ) + { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; + dj->lfn = NULL; /* Find only SFN */ + for( n = 1; n < 100; n++ ) + { + gen_numname( fn, sn, lfn, n ); /* Generate a numbered name */ + res = dir_find( dj ); /* Check if the name collides with existing SFN */ + if( res != FR_OK ) + { + break; + } + } + + if( n == 100 ) + { + return FR_DENIED; /* Abort if too many collisions */ + } + + if( res != FR_NO_FILE ) + { + return res; /* Abort if the result is other than 'not collided' */ + } + + fn[NS] = sn[NS]; + dj->lfn = lfn; + } + + if( sn[NS] & NS_LFN ) + { /* When LFN is to be created, reserve reserve an SFN + LFN entries. */ + for( ne = 0; lfn[ne]; ne++ ); + ne = ( ne + 25 ) / 13; + } + else + { /* Otherwise reserve only an SFN entry. */ + ne = 1; + } + + /* Reserve contiguous entries */ + res = dir_seek( dj, 0 ); + if( res != FR_OK ) + { + return res; + } + + n = is = 0; + do + { + res = move_window( dj->fs, dj->sect ); + if( res != FR_OK ) + { + break; + } + + c = *dj->dir; /* Check the entry status */ + if( c == 0xE5 || c == 0 ) + { /* Is it a blank entry? */ + if( n == 0 ) + { + is = dj->index; /* First index of the contigulus entry */ + } + + if( ++n == ne ) + { + break; /* A contiguous entry that requiered count is found */ + } + } + else + { + n = 0; /* Not a blank entry. Restart to search */ + } + + res = dir_next( dj, TRUE ); /* Next entry with table streach */ + } while( res == FR_OK ); + + if( res == FR_OK && ne > 1 ) + { /* Initialize LFN entry if needed */ + res = dir_seek( dj, is ); + if( res == FR_OK ) + { + sum = sum_sfn( dj->fn ); /* Sum of the SFN tied to the LFN */ + ne--; + do + { /* Store LFN entries in bottom first */ + res = move_window( dj->fs, dj->sect ); + if( res != FR_OK ) + { + break; + } + + fit_lfn( dj->lfn, dj->dir, (BYTE) ne, sum ); + dj->fs->wflag = 1; + res = dir_next( dj, FALSE ); /* Next entry */ + } while( res == FR_OK && --ne ); + } + } + + #else /* Non LFN configuration */ + res = dir_seek( dj, 0 ); + if( res == FR_OK ) + { + do + { /* Find a blank entry for the SFN */ + res = move_window( dj->fs, dj->sect ); + if( res != FR_OK ) + { + break; + } + + c = *dj->dir; + if( c == 0xE5 || c == 0 ) + { + break; /* Is it a blank entry? */ + } + + res = dir_next( dj, TRUE ); /* Next entry with table streach */ + } while( res == FR_OK ); + } + + #endif + if( res == FR_OK ) + { /* Initialize the SFN entry */ + res = move_window( dj->fs, dj->sect ); + if( res == FR_OK ) + { + dir = dj->dir; + mem_set( dir, 0, 32 ); /* Clean the entry */ + mem_cpy( dir, dj->fn, 11 ); /* Put SFN */ + dir[DIR_NTres] = *( dj->fn + NS ) & ( NS_BODY | NS_EXT ); /* Put NT flag */ + dj->fs->wflag = 1; + } + } + + return res; +} + +#endif /* !_FS_READONLY */ + +/*-----------------------------------------------------------------------*/ + +/* Remove an object from the directory */ + +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static FRESULT dir_remove + ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR *dj /* Directory object pointing the entry to be removed */ + ) +{ + FRESULT res; + #if _USE_LFN /* LFN configuration */ + WORD i; + + i = dj->index; /* SFN index */ + res = dir_seek( dj, (WORD) ((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx) ); /* Goto the SFN or top of the LFN entries */ + if( res == FR_OK ) + { + do + { + res = move_window( dj->fs, dj->sect ); + if( res != FR_OK ) + { + break; + } + + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + if( dj->index >= i ) + { + break; /* When reached SFN, all entries of the object has been deleted. */ + } + + res = dir_next( dj, FALSE ); /* Next entry */ + } while( res == FR_OK ); + if( res == FR_NO_FILE ) + { + res = FR_INT_ERR; + } + } + + #else /* Non LFN configuration */ + res = dir_seek( dj, dj->index ); + if( res == FR_OK ) + { + res = move_window( dj->fs, dj->sect ); + if( res == FR_OK ) + { + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + } + } + + #endif + return res; +} + +#endif /* !_FS_READONLY */ + +/*-----------------------------------------------------------------------*/ + +/* Pick a segment and create the object name in directory form */ + +/*-----------------------------------------------------------------------*/ +static FRESULT create_name + ( + DIR *dj, /* Pointer to the directory object */ + const XCHAR **path /* Pointer to pointer to the segment in the path string */ + ) +{ + #ifdef _EXCVT + + static const BYTE cvt[] = _EXCVT; + #endif + #if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + int i, ni, si, di; + const XCHAR *p; + + /* Create LFN in Unicode */ + si = di = 0; + p = *path; + lfn = dj->lfn; + for( ;; ) + { + w = p[si++]; /* Get a character */ + if( w < ' ' || w == '/' || w == '\\' ) + { + break; /* Break on end of segment */ + } + + if( di >= _MAX_LFN ) + { /* Reject too long name */ + return FR_INVALID_NAME; + } + + #if !_LFN_UNICODE + w &= 0xFF; + if( IsDBCS1(w) ) + { /* If it is a DBC 1st byte */ + b = p[si++]; /* Get 2nd byte */ + if( !IsDBCS2(b) ) + { /* Reject invalid code for DBC */ + return FR_INVALID_NAME; + } + + w = ( w << 8 ) + b; + } + + w = ff_convert( w, 1 ); /* Convert OEM to Unicode */ + if( !w ) + { + return FR_INVALID_NAME; /* Reject invalid code */ + } + + #endif + if( w < 0x80 && chk_chr("\"*:<>\?|\x7F", w) ) + { /* Reject illegal chars for LFN */ + return FR_INVALID_NAME; + } + + lfn[di++] = w; /* Store the Unicode char */ + } + + *path = &p[si]; /* Rerurn pointer to the next segment */ + cf = ( w < ' ' ) ? NS_LAST : 0; /* Set last segment flag if end of path */ + #if _FS_RPATH + if( (di == 1 && lfn[di - 1] == '.') || /* Is this a dot entry? */ (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.') ) + { + lfn[di] = 0; + for( i = 0; i < 11; i++ ) + { + dj->fn[i] = ( i < di ) ? '.' : ' '; + } + + dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } + + #endif + while( di ) + { /* Strip trailing spaces and dots */ + w = lfn[di - 1]; + if( w != ' ' && w != '.' ) + { + break; + } + + di--; + } + + if( !di ) + { + return FR_INVALID_NAME; /* Reject null string */ + } + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set( dj->fn, ' ', 11 ); + for( si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++ ); + + /* Strip leading spaces and dots */ + if( si ) + { + cf |= NS_LOSS | NS_LFN; + } + + while( di && lfn[di - 1] != '.' ) + { + di--; /* Find extension (di<=si: no extension) */ + } + + b = i = 0; + ni = 8; + for( ;; ) + { + w = lfn[si++]; /* Get an LFN char */ + if( !w ) + { + break; /* Break on enf of the LFN */ + } + + if( w == ' ' || (w == '.' && si != di) ) + { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; + continue; + } + + if( i >= ni || si == di ) + { /* Extension or end of SFN */ + if( ni == 11 ) + { /* Long extension */ + cf |= NS_LOSS | NS_LFN; + break; + } + + if( si != di ) + { + cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + } + + if( si > di ) + { + break; /* No extension */ + } + + si = di; + i = 8; + ni = 11; /* Enter extension section */ + b <<= 2; + continue; + } + + if( w >= 0x80 ) + { /* Non ASCII char */ + #ifdef _EXCVT + w = ff_convert( w, 0 ); /* Unicode -> OEM code */ + if( w ) + { + w = cvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ + } + + #else + w = ff_convert( ff_wtoupper(w), 0 ); /* Upper converted Unicode -> OEM code */ + #endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if( _DF1S && w >= 0x100 ) + { /* Double byte char */ + if( i >= ni - 1 ) + { + cf |= NS_LOSS | NS_LFN; + i = ni; + continue; + } + + dj->fn[i++] = ( BYTE ) ( w >> 8 ); + } + else + { /* Single byte char */ + if( !w || chk_chr("+,;[=]", w) ) + { /* Replace illegal chars for SFN */ + w = '_'; + cf |= NS_LOSS | NS_LFN; /* Lossy conversion */ + } + else + { + if( IsUpper(w) ) + { /* ASCII large capital */ + b |= 2; + } + else + { + if( IsLower(w) ) + { /* ASCII small capital */ + b |= 1; + w -= 0x20; + } + } + } + } + + dj->fn[i++] = ( BYTE ) w; + } + + if( dj->fn[0] == 0xE5 ) + { + dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */ + } + + if( ni == 8 ) + { + b <<= 2; + } + + if( (b & 0x0C) == 0x0C || (b & 0x03) == 0x03 ) + { /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + } + + if( !(cf & NS_LFN) ) + { /* When LFN is in 8.3 format without extended char, NT flags are created */ + if( (b & 0x03) == 0x01 ) + { + cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + } + + if( (b & 0x0C) == 0x04 ) + { + cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + } + + dj->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + #else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + int ni, si, i; + const char *p; + + /* Create file name in directory form */ + sfn = dj->fn; + mem_set( sfn, ' ', 11 ); + si = i = b = 0; + ni = 8; + p = *path; + #if _FS_RPATH + if( p[si] == '.' ) + { /* Is this a dot entry? */ + for( ;; ) + { + c = p[si++]; + if( c != '.' || si >= 3 ) + { + break; + } + + sfn[i++] = c; + } + + if( c != '/' && c != '\\' && c > ' ' ) + { + return FR_INVALID_NAME; + } + + *path = &p[si]; /* Rerurn pointer to the next segment */ + sfn[NS] = ( c <= ' ' ) ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } + + #endif + for( ;; ) + { + c = p[si++]; + if( c <= ' ' || c == '/' || c == '\\' ) + { + break; /* Break on end of segment */ + } + + if( c == '.' || i >= ni ) + { + if( ni != 8 || c != '.' ) + { + return FR_INVALID_NAME; + } + + i = 8; + ni = 11; + b <<= 2; + continue; + } + + if( c >= 0x80 ) + { /* Extended char */ + #ifdef _EXCVT + c = cvt[c - 0x80]; /* Convert extend char (SBCS) */ + #else + b |= 3; /* Eliminate NT flag if ext char is exist */ + #if !_DF1S /* ASCII only cfg */ + return FR_INVALID_NAME; + #endif + #endif + } + + if( IsDBCS1(c) ) + { /* DBC 1st byte? */ + d = p[si++]; /* Get 2nd byte */ + if( !IsDBCS2(d) || i >= ni - 1 ) + { /* Reject invalid DBC */ + return FR_INVALID_NAME; + } + + sfn[i++] = c; + sfn[i++] = d; + } + else + { /* Single byte code */ + if( chk_chr(" \"*+,[=]|\x7F", c) ) + { /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + } + + if( IsUpper(c) ) + { /* ASCII large capital? */ + b |= 2; + } + else + { + if( IsLower(c) ) + { /* ASCII small capital? */ + b |= 1; + c -= 0x20; + } + } + + sfn[i++] = c; + } + } + + *path = &p[si]; /* Return pointer to the next segment */ + c = ( c <= ' ' ) ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if( !i ) + { + return FR_INVALID_NAME; /* Reject null string */ + } + + if( sfn[0] == 0xE5 ) + { + sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */ + } + + if( ni == 8 ) + { + b <<= 2; + } + + if( (b & 0x03) == 0x01 ) + { + c |= NS_EXT; /* NT flag (Extension has only small capital) */ + } + + if( (b & 0x0C) == 0x04 ) + { + c |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; + #endif +} + +/*-----------------------------------------------------------------------*/ + +/* Get file information from directory entry */ + +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static void get_fileinfo + ( /* No return code */ + DIR *dj, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ + ) +{ + int i; + BYTE c, nt, *dir; + char *p; + + p = fno->fname; + if( dj->sect ) + { + dir = dj->dir; + nt = dir[DIR_NTres]; /* NT flag */ + for( i = 0; i < 8; i++ ) + { /* Copy name body */ + c = dir[i]; + if( c == ' ' ) + { + break; + } + + if( c == 0x05 ) + { + c = 0xE5; + } + + if( _USE_LFN && (nt & NS_BODY) && IsUpper(c) ) + { + c += 0x20; + } + + *p++ = c; + } + + if( dir[8] != ' ' ) + { /* Copy name extension */ + *p++ = '.'; + for( i = 8; i < 11; i++ ) + { + c = dir[i]; + if( c == ' ' ) + { + break; + } + + if( _USE_LFN && (nt & NS_EXT) && IsUpper(c) ) + { + c += 0x20; + } + + *p++ = c; + } + } + + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD( dir + DIR_FileSize ); /* Size */ + fno->fdate = LD_WORD( dir + DIR_WrtDate ); /* Date */ + fno->ftime = LD_WORD( dir + DIR_WrtTime ); /* Time */ + } + + *p = 0; + + #if _USE_LFN + if( fno->lfname ) + { + XCHAR *tp = fno->lfname; + WCHAR w, *lfn; + + i = 0; + if( dj->sect && dj->lfn_idx != 0xFFFF ) + { /* Get LFN if available */ + lfn = dj->lfn; + while( (w = *lfn++) != 0 ) + { /* Get an LFN char */ + #if !_LFN_UNICODE + w = ff_convert( w, 0 ); /* Unicode -> OEM conversion */ + if( !w ) + { + i = 0; + break; + } /* Could not convert, no LFN */ + + if( _DF1S && w >= 0x100 ) + { /* Put 1st byte if it is a DBC */ + tp[i++] = ( XCHAR ) ( w >> 8 ); + } + + #endif + if( i >= fno->lfsize - 1 ) + { + i = 0; + break; + } /* Buffer overrun, no LFN */ + + tp[i++] = ( XCHAR ) w; + } + } + + tp[i] = 0; /* Terminator */ + } + + #endif +} + +#endif /* _FS_MINIMIZE <= 1 */ + +/*-----------------------------------------------------------------------*/ + +/* Follow a file path */ + +/*-----------------------------------------------------------------------*/ +static FRESULT follow_path + ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Directory object to return last directory and found object */ + const XCHAR *path /* Full-path string to find a file or directory */ + ) +{ + FRESULT res; + BYTE *dir, last; + + while( !_USE_LFN && *path == ' ' ) + { + path++; /* Skip leading spaces */ + } + + #if _FS_RPATH + if( *path == '/' || *path == '\\' ) + { /* There is a heading separator */ + path++; + dj->sclust = 0; /* Strip it and start from the root dir */ + } + else + { /* No heading saparator */ + dj->sclust = dj->fs->cdir; /* Start from the current dir */ + } + + #else + if( *path == '/' || *path == '\\' ) + { /* Strip heading separator if exist */ + path++; + } + + dj->sclust = 0; /* Start from the root dir */ + #endif + if( (UINT) * path < ' ' ) + { /* Null path means the start directory itself */ + res = dir_seek( dj, 0 ); + dj->dir = NULL; + } + else + { /* Follow path */ + for( ;; ) + { + res = create_name( dj, &path ); /* Get a segment */ + if( res != FR_OK ) + { + break; + } + + res = dir_find( dj ); /* Find it */ + last = *( dj->fn + NS ) & NS_LAST; + if( res != FR_OK ) + { /* Could not find the object */ + if( res == FR_NO_FILE && !last ) + { + res = FR_NO_PATH; + } + + break; + } + + if( last ) + { + break; /* Last segment match. Function completed. */ + } + + dir = dj->dir; /* There is next segment. Follow the sub directory */ + if( !(dir[DIR_Attr] & AM_DIR) ) + { /* Cannot follow because it is a file */ + res = FR_NO_PATH; + break; + } + + dj->sclust = ( (DWORD) LD_WORD(dir + DIR_FstClusHI) << 16 ) | LD_WORD( dir + DIR_FstClusLO ); + } + } + + return res; +} + +/*-----------------------------------------------------------------------*/ + +/* Load boot record and check if it is an FAT boot record */ + +/*-----------------------------------------------------------------------*/ +static BYTE check_fs + ( /* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ + ) +{ + if( disk_read(fs->drive, fs->win, sect, 1) != RES_OK ) + { /* Load boot record */ + return 3; + } + + if( LD_WORD(&fs->win[BS_55AA]) != 0xAA55 ) + { /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + } + + if( (LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146 ) + { /* Check "FAT" string */ + return 0; + } + + if( (LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146 ) + { + return 0; + } + + return 1; +} + +/*-----------------------------------------------------------------------*/ + +/* Make sure that the file system is valid */ + +/*-----------------------------------------------------------------------*/ +FRESULT chk_mounted + ( /* FR_OK(0): successful, !=0: any error occured */ + const XCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ + ) +{ + BYTE fmt, *tbl; + UINT vol; + DSTATUS stat; + DWORD bsect, fsize, tsect, mclst; + const XCHAR *p = *path; + FATFS *fs; + + /* Get logical drive number from the path name */ + vol = p[0] - '0'; /* Is there a drive number? */ + if( vol <= 9 && p[1] == ':' ) + { /* Found a drive number, get and strip it */ + p += 2; + *path = p; /* Return pointer to the path name */ + } + else + { /* No drive number is given */ + #if _FS_RPATH + vol = Drive; /* Use current drive */ + #else + vol = 0; /* Use drive 0 */ + #endif + } + + /* Check if the logical drive is valid or not */ + if( vol >= _DRIVES ) + { /* Is the drive number valid? */ + return FR_INVALID_DRIVE; + } + + *rfs = fs = FatFs[vol]; /* Returen pointer to the corresponding file system object */ + if( !fs ) + { + return FR_NOT_ENABLED; /* Is the file system object available? */ + } + + ENTER_FF( fs ); /* Lock file system */ + + if( fs->fs_type ) + { /* If the logical drive has been mounted */ + stat = disk_status( fs->drive ); + if( !(stat & STA_NOINIT) ) + { /* and the physical drive is kept initialized (has not been changed), */ + #if !_FS_READONLY + if( chk_wp && (stat & STA_PROTECT) ) + { /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + } + + #endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be mounted. Following code attempts to mount the volume */ + fs->fs_type = 0; /* Clear the file system object */ + fs->drive = ( BYTE ) LD2PD( vol ); /* Bind the logical drive and a physical drive */ + stat = disk_initialize( fs->drive ); /* Initialize low level disk I/O layer */ + if( stat & STA_NOINIT ) + { /* Check if the drive is ready */ + return FR_NOT_READY; + } + + #if _MAX_SS != 512 /* Get disk sector size if needed */ + if( disk_ioctl(fs->drive, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS ) + { + return FR_NO_FILESYSTEM; + } + + #endif + #if !_FS_READONLY + if( chk_wp && (stat & STA_PROTECT) ) + { /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; + } + + #endif + + /* Search FAT partition on the drive */ + fmt = check_fs( fs, bsect = 0 ); /* Check sector 0 as an SFD format */ + if( fmt == 1 ) + { /* Not an FAT boot record, it may be patitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT( vol ) * 16]; /* Partition table */ + if( tbl[4] ) + { /* Is the partition existing? */ + bsect = LD_DWORD( &tbl[8] ); /* Partition offset in LBA */ + fmt = check_fs( fs, bsect ); /* Check the partition */ + } + } + + if( fmt == 3 ) + { + return FR_DISK_ERR; + } + + if( fmt || LD_WORD(fs->win + BPB_BytsPerSec) != SS(fs) ) + { /* No valid FAT patition is found */ + return FR_NO_FILESYSTEM; + } + + /* Initialize the file system object */ + fsize = LD_WORD( fs->win + BPB_FATSz16 ); /* Number of sectors per FAT */ + if( !fsize ) + { + fsize = LD_DWORD( fs->win + BPB_FATSz32 ); + } + + fs->sects_fat = fsize; + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + fsize *= fs->n_fats; /* (Number of sectors in FAT area) */ + fs->fatbase = bsect + LD_WORD( fs->win + BPB_RsvdSecCnt ); /* FAT start sector (lba) */ + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + fs->n_rootdir = LD_WORD( fs->win + BPB_RootEntCnt ); /* Nmuber of root directory entries */ + tsect = LD_WORD( fs->win + BPB_TotSec16 ); /* Number of sectors on the volume */ + if( !tsect ) + { + tsect = LD_DWORD( fs->win + BPB_TotSec32 ); + } + + fs->max_clust = mclst = + ( + tsect /* Last cluster# + 1 (Number of clusters + 2) */ - + LD_WORD(fs->win + BPB_RsvdSecCnt) - + fsize - + fs->n_rootdir / + (SS(fs) / 32) + ) / + fs->csize + + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if( mclst >= 0xFF7 ) + { + fmt = FS_FAT16; /* Number of clusters >= 0xFF5 */ + } + + if( mclst >= 0xFFF7 ) + { + fmt = FS_FAT32; /* Number of clusters >= 0xFFF5 */ + } + + if( fmt == FS_FAT32 ) + { + fs->dirbase = LD_DWORD( fs->win + BPB_RootClus ); /* Root directory start cluster */ + } + else + { + fs->dirbase = fs->fatbase + fsize; /* Root directory start sector (lba) */ + } + + fs->database = fs->fatbase + fsize + fs->n_rootdir / ( SS(fs) / 32 ); /* Data start sector (lba) */ + + #if !_FS_READONLY + + /* Initialize allocation information */ + fs->free_clust = 0xFFFFFFFF; + fs->wflag = 0; + + /* Get fsinfo if needed */ + if( fmt == FS_FAT32 ) + { + fs->fsi_flag = 0; + fs->fsi_sector = bsect + LD_WORD( fs->win + BPB_FSInfo ); + if + ( + disk_read(fs->drive, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(fs->win + BS_55AA) == 0xAA55 && + LD_DWORD(fs->win + FSI_LeadSig) == 0x41615252 && + LD_DWORD(fs->win + FSI_StrucSig) == 0x61417272 + ) + { + fs->last_clust = LD_DWORD( fs->win + FSI_Nxt_Free ); + fs->free_clust = LD_DWORD( fs->win + FSI_Free_Count ); + } + } + + #endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->winsect = 0; /* Invalidate sector cache */ + #if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ + #endif + fs->id = ++Fsid; /* File system mount ID */ + + return FR_OK; +} + +/*-----------------------------------------------------------------------*/ + +/* Check if the file/dir object is valid or not */ + +/*-----------------------------------------------------------------------*/ +static FRESULT validate + ( /* FR_OK(0): The object is valid, !=0: Invalid */ + FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ + ) +{ + if( !fs || !fs->fs_type || fs->id != id ) + { + return FR_INVALID_OBJECT; + } + + ENTER_FF( fs ); /* Lock file system */ + + if( disk_status(fs->drive) & STA_NOINIT ) + { + return FR_NOT_READY; + } + + return FR_OK; +} + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + +/*-----------------------------------------------------------------------*/ + +/* Mount/Unmount a Locical Drive */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_mount + ( + BYTE vol, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ + ) +{ + FATFS *rfs; + + if( vol >= _DRIVES ) + { /* Check if the drive number is valid */ + return FR_INVALID_DRIVE; + } + + rfs = FatFs[vol]; /* Get current fs object */ + + if( rfs ) + { + #if _FS_REENTRANT /* Discard sync object of the current volume */ + if( !ff_del_syncobj(rfs->sobj) ) + { + return FR_INT_ERR; + } + + #endif + rfs->fs_type = 0; /* Clear old fs object */ + } + + if( fs ) + { + fs->fs_type = 0; /* Clear new fs object */ + #if _FS_REENTRANT /* Create sync object for the new volume */ + if( !ff_cre_syncobj(vol, &fs->sobj) ) + { + return FR_INT_ERR; + } + + #endif + } + + FatFs[vol] = fs; /* Register new fs object */ + + return FR_OK; +} + +/*-----------------------------------------------------------------------*/ + +/* Open or Create a File */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_open + ( + FIL *fp, /* Pointer to the blank file object */ + const XCHAR *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ + ) +{ + FRESULT res; + DIR dj; + NAMEBUF( sfn, lfn ); + + BYTE *dir; + + fp->fs = NULL; /* Clear file object */ + #if !_FS_READONLY + mode &= ( FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW ); + res = chk_mounted( &path, &dj.fs, (BYTE) (mode & (FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) ); + #else + mode &= FA_READ; + res = chk_mounted( &path, &dj.fs, 0 ); + #endif + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + + #if !_FS_READONLY + + /* Create or Open a file */ + if( mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW) ) + { + DWORD ps, cl; + + if( res != FR_OK ) + { /* No file, create new */ + if( res == FR_NO_FILE ) + { /* There is no file to open, create a new entry */ + res = dir_register( &dj ); + } + + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + + mode |= FA_CREATE_ALWAYS; + dir = dj.dir; /* Created entry (SFN entry) */ + } + else + { /* Any object is already existing */ + if( mode & FA_CREATE_NEW ) + { /* Cannot create new */ + LEAVE_FF( dj.fs, FR_EXIST ); + } + + dir = dj.dir; + if( !dir || (dir[DIR_Attr] & (AM_RDO | AM_DIR)) ) + { /* Cannot overwrite it (R/O or DIR) */ + LEAVE_FF( dj.fs, FR_DENIED ); + } + + if( mode & FA_CREATE_ALWAYS ) + { /* Resize it to zero on over write mode */ + cl = ( (DWORD) LD_WORD(dir + DIR_FstClusHI) << 16 ) | LD_WORD( dir + DIR_FstClusLO ); /* Get start cluster */ + ST_WORD( dir + DIR_FstClusHI, 0 ); /* cluster = 0 */ + ST_WORD( dir + DIR_FstClusLO, 0 ); + ST_DWORD( dir + DIR_FileSize, 0 ); /* size = 0 */ + dj.fs->wflag = 1; + ps = dj.fs->winsect; /* Remove the cluster chain */ + if( cl ) + { + res = remove_chain( dj.fs, cl ); + if( res ) + { + LEAVE_FF( dj.fs, res ); + } + + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + } + + res = move_window( dj.fs, ps ); + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + } + } + + if( mode & FA_CREATE_ALWAYS ) + { + dir[DIR_Attr] = 0; /* Reset attribute */ + ps = get_fattime(); + ST_DWORD( dir + DIR_CrtTime, ps ); /* Created time */ + dj.fs->wflag = 1; + mode |= FA__WRITTEN; /* Set file changed flag */ + } + } + + /* Open an existing file */ + else + { + #endif /* !_FS_READONLY */ + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); /* Follow failed */ + } + + dir = dj.dir; + if( !dir || (dir[DIR_Attr] & AM_DIR) ) + { /* It is a directory */ + LEAVE_FF( dj.fs, FR_NO_FILE ); + } + + #if !_FS_READONLY + if( (mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO) ) + { /* R/O violation */ + LEAVE_FF( dj.fs, FR_DENIED ); + } + } + + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; + #endif + fp->flag = mode; /* File access mode */ + fp->org_clust = /* File start cluster */ + ( (DWORD) LD_WORD(dir + DIR_FstClusHI) << 16 ) | LD_WORD( dir + DIR_FstClusLO ); + fp->fsize = LD_DWORD( dir + DIR_FileSize ); /* File size */ + fp->fptr = 0; + fp->csect = 255; /* File pointer */ + fp->dsect = 0; + fp->fs = dj.fs; + fp->id = dj.fs->id; /* Owner file system object of the file */ + + LEAVE_FF( dj.fs, FR_OK ); +} + +/*-----------------------------------------------------------------------*/ + +/* Read File */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_read + ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ + ) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE *rbuff = buff; + + *br = 0; /* Initialize bytes read */ + + res = validate( fp->fs, fp->id ); /* Check validity of the object */ + if( res != FR_OK ) + { + LEAVE_FF( fp->fs, res ); + } + + if( fp->flag & FA__ERROR ) + { /* Check abort flag */ + LEAVE_FF( fp->fs, FR_INT_ERR ); + } + + if( !(fp->flag & FA_READ) ) + { /* Check access mode */ + LEAVE_FF( fp->fs, FR_DENIED ); + } + + remain = fp->fsize - fp->fptr; + if( btr > remain ) + { + btr = ( UINT ) remain; /* Truncate btr by remaining bytes */ + } + + for( ; btr; /* Repeat until all data transferred */ rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt ) + { + if( (fp->fptr % SS(fp->fs)) == 0 ) + { /* On the sector boundary? */ + if( fp->csect >= fp->fs->csize ) + { /* On the cluster boundary? */ + clst = ( fp->fptr == 0 ) ? /* On the top of the file? */ + fp->org_clust : get_fat( fp->fs, fp->curr_clust ); + if( clst <= 1 ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + if( clst == 0xFFFFFFFF ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector offset in the cluster */ + } + + sect = clust2sect( fp->fs, fp->curr_clust ); /* Get current sector */ + if( !sect ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + sect += fp->csect; + cc = btr / SS( fp->fs ); /* When remaining bytes >= sector size, */ + if( cc ) + { /* Read maximum contiguous sectors directly */ + if( fp->csect + cc > fp->fs->csize ) + { /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + } + + if( disk_read(fp->fs->drive, rbuff, sect, (BYTE) cc) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + #if !_FS_READONLY && _FS_MINIMIZE <= 2 + #if _FS_TINY + if( fp->fs->wflag && fp->fs->winsect - sect < cc ) + { /* Replace one of the read sectors with cached data if it contains a dirty sector */ + mem_cpy( rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs) ); + } + + #else + if( (fp->flag & FA__DIRTY) && fp->dsect - sect < cc ) + { /* Replace one of the read sectors with cached data if it contains a dirty sector */ + mem_cpy( rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs) ); + } + + #endif + #endif + fp->csect += ( BYTE ) cc; /* Next sector address in the cluster */ + rcnt = SS( fp->fs ) * cc; /* Number of bytes transferred */ + continue; + } + + #if !_FS_TINY + #if !_FS_READONLY + if( fp->flag & FA__DIRTY ) + { /* Write sector I/O buffer if needed */ + if( disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->flag &= ~FA__DIRTY; + } + + #endif + if( fp->dsect != sect ) + { /* Fill sector buffer with file data */ + if( disk_read(fp->fs->drive, fp->buf, sect, 1) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + } + + #endif + fp->dsect = sect; + fp->csect++; /* Next sector address in the cluster */ + } + + rcnt = SS( fp->fs ) - ( fp->fptr % SS(fp->fs) ); /* Get partial sector data from sector buffer */ + if( rcnt > btr ) + { + rcnt = btr; + } + + #if _FS_TINY + if( move_window(fp->fs, fp->dsect) ) + { /* Move sector window */ + ABORT( fp->fs, FR_DISK_ERR ); + } + + mem_cpy( rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt ); /* Pick partial sector */ + #else + mem_cpy( rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt ); /* Pick partial sector */ + #endif + } + + LEAVE_FF( fp->fs, FR_OK ); +} + +#if !_FS_READONLY + +/*-----------------------------------------------------------------------*/ + +/* Write File */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_write + ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ + ) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + + *bw = 0; /* Initialize bytes written */ + + res = validate( fp->fs, fp->id ); /* Check validity of the object */ + if( res != FR_OK ) + { + LEAVE_FF( fp->fs, res ); + } + + if( fp->flag & FA__ERROR ) + { /* Check abort flag */ + LEAVE_FF( fp->fs, FR_INT_ERR ); + } + + if( !(fp->flag & FA_WRITE) ) + { /* Check access mode */ + LEAVE_FF( fp->fs, FR_DENIED ); + } + + if( fp->fsize + btw < fp->fsize ) + { + btw = 0; /* File size cannot reach 4GB */ + } + + for( ; btw; /* Repeat until all data transferred */ wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt ) + { + if( (fp->fptr % SS(fp->fs)) == 0 ) + { /* On the sector boundary? */ + if( fp->csect >= fp->fs->csize ) + { /* On the cluster boundary? */ + if( fp->fptr == 0 ) + { /* On the top of the file? */ + clst = fp->org_clust; /* Follow from the origin */ + if( clst == 0 ) + { /* When there is no cluster chain, */ + fp->org_clust = clst = create_chain( fp->fs, 0 ); /* Create a new cluster chain */ + } + } + else + { /* Middle or end of the file */ + clst = create_chain( fp->fs, fp->curr_clust ); /* Follow or streach cluster chain */ + } + + if( clst == 0 ) + { + break; /* Could not allocate a new cluster (disk full) */ + } + + if( clst == 1 ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + if( clst == 0xFFFFFFFF ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + + #if _FS_TINY + if( fp->fs->winsect == fp->dsect && move_window(fp->fs, 0) ) + { /* Write back data buffer prior to following direct transfer */ + ABORT( fp->fs, FR_DISK_ERR ); + } + + #else + if( fp->flag & FA__DIRTY ) + { /* Write back data buffer prior to following direct transfer */ + if( disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->flag &= ~FA__DIRTY; + } + + #endif + sect = clust2sect( fp->fs, fp->curr_clust ); /* Get current sector */ + if( !sect ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + sect += fp->csect; + cc = btw / SS( fp->fs ); /* When remaining bytes >= sector size, */ + if( cc ) + { /* Write maximum contiguous sectors directly */ + if( fp->csect + cc > fp->fs->csize ) + { /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + } + + if( disk_write(fp->fs->drive, wbuff, sect, (BYTE) cc) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + #if _FS_TINY + if( fp->fs->winsect - sect < cc ) + { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy( fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs) ); + fp->fs->wflag = 0; + } + + #else + if( fp->dsect - sect < cc ) + { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy( fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs) ); + fp->flag &= ~FA__DIRTY; + } + + #endif + fp->csect += ( BYTE ) cc; /* Next sector address in the cluster */ + wcnt = SS( fp->fs ) * cc; /* Number of bytes transferred */ + continue; + } + + #if _FS_TINY + if( fp->fptr >= fp->fsize ) + { /* Avoid silly buffer filling at growing edge */ + if( move_window(fp->fs, 0) ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->fs->winsect = sect; + } + + #else + if( fp->dsect != sect ) + { /* Fill sector buffer with file data */ + if( fp->fptr < fp->fsize && disk_read(fp->fs->drive, fp->buf, sect, 1) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + } + + #endif + fp->dsect = sect; + fp->csect++; /* Next sector address in the cluster */ + } + + wcnt = SS( fp->fs ) - ( fp->fptr % SS(fp->fs) ); /* Put partial sector into file I/O buffer */ + if( wcnt > btw ) + { + wcnt = btw; + } + + #if _FS_TINY + if( move_window(fp->fs, fp->dsect) ) + { /* Move sector window */ + ABORT( fp->fs, FR_DISK_ERR ); + } + + mem_cpy( &fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt ); /* Fit partial sector */ + fp->fs->wflag = 1; + #else + mem_cpy( &fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt ); /* Fit partial sector */ + fp->flag |= FA__DIRTY; + #endif + } + + if( fp->fptr > fp->fsize ) + { + fp->fsize = fp->fptr; /* Update file size if needed */ + } + + fp->flag |= FA__WRITTEN; /* Set file changed flag */ + + LEAVE_FF( fp->fs, FR_OK ); +} + +/*-----------------------------------------------------------------------*/ + +/* Synchronize the File Object */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_sync( FIL *fp /* Pointer to the file object */ ) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + res = validate( fp->fs, fp->id ); /* Check validity of the object */ + if( res == FR_OK ) + { + if( fp->flag & FA__WRITTEN ) + { /* Has the file been written? */ + #if !_FS_TINY /* Write-back dirty buffer */ + if( fp->flag & FA__DIRTY ) + { + if( disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK ) + { + LEAVE_FF( fp->fs, FR_DISK_ERR ); + } + + fp->flag &= ~FA__DIRTY; + } + + #endif + + /* Update the directory entry */ + res = move_window( fp->fs, fp->dir_sect ); + if( res == FR_OK ) + { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD( dir + DIR_FileSize, fp->fsize ); /* Update file size */ + ST_WORD( dir + DIR_FstClusLO, fp->org_clust ); /* Update start cluster */ + ST_WORD( dir + DIR_FstClusHI, fp->org_clust >> 16 ); + tim = get_fattime(); /* Updated time */ + ST_DWORD( dir + DIR_WrtTime, tim ); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync( fp->fs ); + } + } + } + + LEAVE_FF( fp->fs, res ); +} + +#endif /* !_FS_READONLY */ + +/*-----------------------------------------------------------------------*/ + +/* Close File */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_close( FIL *fp /* Pointer to the file object to be closed */ ) +{ + FRESULT res; + + #if _FS_READONLY + res = validate( fp->fs, fp->id ); + if( res == FR_OK ) + { + fp->fs = NULL; + } + + LEAVE_FF( fp->fs, res ); + #else + res = f_sync( fp ); + if( res == FR_OK ) + { + fp->fs = NULL; + } + + return res; + #endif +} + +/*-----------------------------------------------------------------------*/ + +/* Change Current Drive/Directory */ + +/*-----------------------------------------------------------------------*/ +#if _FS_RPATH +FRESULT f_chdrive( BYTE drv /* Drive number */ ) +{ + if( drv >= _DRIVES ) + { + return FR_INVALID_DRIVE; + } + + Drive = drv; + + return FR_OK; +} + +FRESULT f_chdir( const XCHAR *path /* Pointer to the directory path */ ) +{ + FRESULT res; + DIR dj; + NAMEBUF( sfn, lfn ); + + BYTE *dir; + + res = chk_mounted( &path, &dj.fs, 0 ); + if( res == FR_OK ) + { + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + if( res == FR_OK ) + { /* Follow completed */ + dir = dj.dir; /* Pointer to the entry */ + if( !dir ) + { + dj.fs->cdir = 0; /* No entry (root dir) */ + } + else + { + if( dir[DIR_Attr] & AM_DIR ) + { /* Reached to the dir */ + dj.fs->cdir = ( (DWORD) LD_WORD(dir + DIR_FstClusHI) << 16 ) | LD_WORD( dir + DIR_FstClusLO ); + } + else + { + res = FR_NO_PATH; /* Could not reach the dir (it is a file) */ + } + } + } + + if( res == FR_NO_FILE ) + { + res = FR_NO_PATH; + } + } + + LEAVE_FF( dj.fs, res ); +} + +#endif +#if _FS_MINIMIZE <= 2 + +/*-----------------------------------------------------------------------*/ + +/* Seek File R/W Pointer */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_lseek( FIL *fp, /* Pointer to the file object */ DWORD ofs /* File pointer from top of file */ ) +{ + FRESULT res; + DWORD clst, bcs, nsect, ifptr; + + res = validate( fp->fs, fp->id ); /* Check validity of the object */ + if( res != FR_OK ) + { + LEAVE_FF( fp->fs, res ); + } + + if( fp->flag & FA__ERROR ) + { /* Check abort flag */ + LEAVE_FF( fp->fs, FR_INT_ERR ); + } + + if( ofs > fp->fsize /* In read-only mode, clip offset with the file size */ + #if !_FS_READONLY + && !(fp->flag & FA_WRITE) + #endif + ) + { + ofs = fp->fsize; + } + + ifptr = fp->fptr; + fp->fptr = nsect = 0; + fp->csect = 255; + if( ofs > 0 ) + { + bcs = ( DWORD ) fp->fs->csize * SS( fp->fs ); /* Cluster size (byte) */ + if( ifptr > 0 && (ofs - 1) / bcs >= (ifptr - 1) / bcs ) + { /* When seek to same or following cluster, */ + fp->fptr = ( ifptr - 1 ) &~( bcs - 1 ); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->curr_clust; + } + else + { /* When seek to back cluster, */ + clst = fp->org_clust; /* start from the first cluster */ + #if !_FS_READONLY + if( clst == 0 ) + { /* If no cluster chain, create a new chain */ + clst = create_chain( fp->fs, 0 ); + if( clst == 1 ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + if( clst == 0xFFFFFFFF ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->org_clust = clst; + } + + #endif + fp->curr_clust = clst; + } + + if( clst != 0 ) + { + while( ofs > bcs ) + { /* Cluster following loop */ + #if !_FS_READONLY + if( fp->flag & FA_WRITE ) + { /* Check if in write mode or not */ + clst = create_chain( fp->fs, clst ); /* Force streached if in write mode */ + if( clst == 0 ) + { /* When disk gets full, clip file size */ + ofs = bcs; + break; + } + } + else + #endif + clst = get_fat( fp->fs, clst ); /* Follow cluster chain if not in write mode */ + if( clst == 0xFFFFFFFF ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + if( clst <= 1 || clst >= fp->fs->max_clust ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + fp->curr_clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + + fp->fptr += ofs; + fp->csect = ( BYTE ) ( ofs / SS(fp->fs) ); /* Sector offset in the cluster */ + if( ofs % SS(fp->fs) ) + { + nsect = clust2sect( fp->fs, clst ); /* Current sector */ + if( !nsect ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + nsect += fp->csect; + fp->csect++; + } + } + } + + if( fp->fptr % SS(fp->fs) && nsect != fp->dsect ) + { + #if !_FS_TINY + #if !_FS_READONLY + if( fp->flag & FA__DIRTY ) + { /* Write-back dirty buffer if needed */ + if( disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->flag &= ~FA__DIRTY; + } + + #endif + if( disk_read(fp->fs->drive, fp->buf, nsect, 1) != RES_OK ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + #endif + fp->dsect = nsect; + } + + #if !_FS_READONLY + if( fp->fptr > fp->fsize ) + { /* Set changed flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } + + #endif + LEAVE_FF( fp->fs, res ); +} + + #if _FS_MINIMIZE <= 1 + +/*-----------------------------------------------------------------------*/ + +/* Create a Directroy Object */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_opendir( DIR *dj, /* Pointer to directory object to create */ const XCHAR *path /* Pointer to the directory path */ ) +{ + FRESULT res; + NAMEBUF( sfn, lfn ); + + BYTE *dir; + + res = chk_mounted( &path, &dj->fs, 0 ); + if( res == FR_OK ) + { + INITBUF( (*dj), sfn, lfn ); + res = follow_path( dj, path ); /* Follow the path to the directory */ + if( res == FR_OK ) + { /* Follow completed */ + dir = dj->dir; + if( dir ) + { /* It is not the root dir */ + if( dir[DIR_Attr] & AM_DIR ) + { /* The object is a directory */ + dj->sclust = ( (DWORD) LD_WORD(dir + DIR_FstClusHI) << 16 ) | LD_WORD( dir + DIR_FstClusLO ); + } + else + { /* The object is not a directory */ + res = FR_NO_PATH; + } + } + + if( res == FR_OK ) + { + dj->id = dj->fs->id; + res = dir_seek( dj, 0 ); /* Rewind dir */ + } + } + + if( res == FR_NO_FILE ) + { + res = FR_NO_PATH; + } + } + + LEAVE_FF( dj->fs, res ); +} + +/*-----------------------------------------------------------------------*/ + +/* Read Directory Entry in Sequense */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_readdir( DIR *dj, /* Pointer to the open directory object */ FILINFO *fno /* Pointer to file information to return */ ) +{ + FRESULT res; + NAMEBUF( sfn, lfn ); + + res = validate( dj->fs, dj->id ); /* Check validity of the object */ + if( res == FR_OK ) + { + INITBUF( (*dj), sfn, lfn ); + if( !fno ) + { + res = dir_seek( dj, 0 ); + } + else + { + res = dir_read( dj ); + if( res == FR_NO_FILE ) + { + dj->sect = 0; + res = FR_OK; + } + + if( res == FR_OK ) + { /* A valid entry is found */ + get_fileinfo( dj, fno ); /* Get the object information */ + res = dir_next( dj, FALSE ); /* Increment index for next */ + if( res == FR_NO_FILE ) + { + dj->sect = 0; + res = FR_OK; + } + } + } + } + + LEAVE_FF( dj->fs, res ); +} + + #if _FS_MINIMIZE == 0 + +/*-----------------------------------------------------------------------*/ + +/* Get File Status */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_stat( const XCHAR *path, /* Pointer to the file path */ FILINFO *fno /* Pointer to file information to return */ ) +{ + FRESULT res; + DIR dj; + NAMEBUF( sfn, lfn ); + + res = chk_mounted( &path, &dj.fs, 0 ); + if( res == FR_OK ) + { + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + if( res == FR_OK ) + { /* Follwo completed */ + if( dj.dir ) + { /* Found an object */ + get_fileinfo( &dj, fno ); + } + else + { /* It is root dir */ + res = FR_INVALID_NAME; + } + } + } + + LEAVE_FF( dj.fs, res ); +} + + #if !_FS_READONLY + +/*-----------------------------------------------------------------------*/ + +/* Get Number of Free Clusters */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_getfree + ( + const XCHAR *path, /* Pointer to the logical drive number (root dir) */ + DWORD *nclst, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ + ) +{ + FRESULT res; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + /* Get drive number */ + res = chk_mounted( &path, fatfs, 0 ); + if( res != FR_OK ) + { + LEAVE_FF( *fatfs, res ); + } + + /* If number of free cluster is valid, return it without cluster scan. */ + if( (*fatfs)->free_clust <= (*fatfs)->max_clust - 2 ) + { + *nclst = ( *fatfs )->free_clust; + LEAVE_FF( *fatfs, FR_OK ); + } + + /* Get number of free clusters */ + fat = ( *fatfs )->fs_type; + n = 0; + if( fat == FS_FAT12 ) + { + clst = 2; + do + { + stat = get_fat( *fatfs, clst ); + if( stat == 0xFFFFFFFF ) + { + LEAVE_FF( *fatfs, FR_DISK_ERR ); + } + + if( stat == 1 ) + { + LEAVE_FF( *fatfs, FR_INT_ERR ); + } + + if( stat == 0 ) + { + n++; + } + } while( ++clst < (*fatfs)->max_clust ); + } + else + { + clst = ( *fatfs )->max_clust; + sect = ( *fatfs )->fatbase; + i = 0; + p = 0; + do + { + if( !i ) + { + res = move_window( *fatfs, sect++ ); + if( res != FR_OK ) + { + LEAVE_FF( *fatfs, res ); + } + + p = ( *fatfs )->win; + i = SS( *fatfs ); + } + + if( fat == FS_FAT16 ) + { + if( LD_WORD(p) == 0 ) + { + n++; + } + + p += 2; + i -= 2; + } + else + { + if( (LD_DWORD(p) & 0x0FFFFFFF) == 0 ) + { + n++; + } + + p += 4; + i -= 4; + } + } while( --clst ); + } + + ( *fatfs )->free_clust = n; + if( fat == FS_FAT32 ) + { + ( *fatfs )->fsi_flag = 1; + } + + *nclst = n; + + LEAVE_FF( *fatfs, FR_OK ); +} + +/*-----------------------------------------------------------------------*/ + +/* Truncate File */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_truncate( FIL *fp /* Pointer to the file object */ ) +{ + FRESULT res; + DWORD ncl; + + res = validate( fp->fs, fp->id ); /* Check validity of the object */ + if( res != FR_OK ) + { + LEAVE_FF( fp->fs, res ); + } + + if( fp->flag & FA__ERROR ) + { /* Check abort flag */ + LEAVE_FF( fp->fs, FR_INT_ERR ); + } + + if( !(fp->flag & FA_WRITE) ) + { /* Check access mode */ + LEAVE_FF( fp->fs, FR_DENIED ); + } + + if( fp->fsize > fp->fptr ) + { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if( fp->fptr == 0 ) + { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain( fp->fs, fp->org_clust ); + fp->org_clust = 0; + } + else + { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat( fp->fs, fp->curr_clust ); + res = FR_OK; + if( ncl == 0xFFFFFFFF ) + { + res = FR_DISK_ERR; + } + + if( ncl == 1 ) + { + res = FR_INT_ERR; + } + + if( res == FR_OK && ncl < fp->fs->max_clust ) + { + res = put_fat( fp->fs, fp->curr_clust, 0x0FFFFFFF ); + if( res == FR_OK ) + { + res = remove_chain( fp->fs, ncl ); + } + } + } + } + + if( res != FR_OK ) + { + fp->flag |= FA__ERROR; + } + + LEAVE_FF( fp->fs, res ); +} + +/*-----------------------------------------------------------------------*/ + +/* Delete a File or Directory */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_unlink( const XCHAR *path /* Pointer to the file or directory path */ ) +{ + FRESULT res; + DIR dj, sdj; + NAMEBUF( sfn, lfn ); + + BYTE *dir; + DWORD dclst; + + res = chk_mounted( &path, &dj.fs, 1 ); + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + if( _FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT) ) + { + res = FR_INVALID_NAME; + } + + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); /* Follow failed */ + } + + dir = dj.dir; + if( !dir ) + { /* Is it the root directory? */ + LEAVE_FF( dj.fs, FR_INVALID_NAME ); + } + + if( dir[DIR_Attr] & AM_RDO ) + { /* Is it a R/O object? */ + LEAVE_FF( dj.fs, FR_DENIED ); + } + + dclst = ( (DWORD) LD_WORD(dir + DIR_FstClusHI) << 16 ) | LD_WORD( dir + DIR_FstClusLO ); + + if( dir[DIR_Attr] & AM_DIR ) + { /* It is a sub-directory */ + if( dclst < 2 ) + { + LEAVE_FF( dj.fs, FR_INT_ERR ); + } + + mem_cpy( &sdj, &dj, sizeof(DIR) ); /* Check if the sub-dir is empty or not */ + sdj.sclust = dclst; + res = dir_seek( &sdj, 2 ); + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + + res = dir_read( &sdj ); + if( res == FR_OK ) + { + res = FR_DENIED; /* Not empty sub-dir */ + } + + if( res != FR_NO_FILE ) + { + LEAVE_FF( dj.fs, res ); + } + } + + res = dir_remove( &dj ); /* Remove directory entry */ + if( res == FR_OK ) + { + if( dclst ) + { + res = remove_chain( dj.fs, dclst ); /* Remove the cluster chain */ + } + + if( res == FR_OK ) + { + res = sync( dj.fs ); + } + } + + LEAVE_FF( dj.fs, res ); +} + +/*-----------------------------------------------------------------------*/ + +/* Create a Directory */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_mkdir( const XCHAR *path /* Pointer to the directory path */ ) +{ + FRESULT res; + DIR dj; + NAMEBUF( sfn, lfn ); + + BYTE *dir, n; + DWORD dsect, dclst, pclst, tim; + + res = chk_mounted( &path, &dj.fs, 1 ); + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + if( res == FR_OK ) + { + res = FR_EXIST; /* Any file or directory is already existing */ + } + + if( _FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT) ) + { + res = FR_INVALID_NAME; + } + + if( res != FR_NO_FILE ) + { /* Any error occured */ + LEAVE_FF( dj.fs, res ); + } + + dclst = create_chain( dj.fs, 0 ); /* Allocate a new cluster for new directory table */ + res = FR_OK; + if( dclst == 0 ) + { + res = FR_DENIED; + } + + if( dclst == 1 ) + { + res = FR_INT_ERR; + } + + if( dclst == 0xFFFFFFFF ) + { + res = FR_DISK_ERR; + } + + if( res == FR_OK ) + { + res = move_window( dj.fs, 0 ); + } + + if( res != FR_OK ) + { + LEAVE_FF( dj.fs, res ); + } + + dsect = clust2sect( dj.fs, dclst ); + + dir = dj.fs->win; /* Initialize the new directory table */ + mem_set( dir, 0, SS(dj.fs) ); + mem_set( dir + DIR_Name, ' ', 8 + 3 ); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + tim = get_fattime(); + ST_DWORD( dir + DIR_WrtTime, tim ); + ST_WORD( dir + DIR_FstClusLO, dclst ); + ST_WORD( dir + DIR_FstClusHI, dclst >> 16 ); + mem_cpy( dir + 32, dir, 32 ); /* Create ".." entry */ + dir[33] = '.'; + pclst = dj.sclust; + if( dj.fs->fs_type == FS_FAT32 && pclst == dj.fs->dirbase ) + { + pclst = 0; + } + + ST_WORD( dir + 32 + DIR_FstClusLO, pclst ); + ST_WORD( dir + 32 + DIR_FstClusHI, pclst >> 16 ); + for( n = 0; n < dj.fs->csize; n++ ) + { /* Write dot entries and clear left sectors */ + dj.fs->winsect = dsect++; + dj.fs->wflag = 1; + res = move_window( dj.fs, 0 ); + if( res ) + { + LEAVE_FF( dj.fs, res ); + } + + mem_set( dir, 0, SS(dj.fs) ); + } + + res = dir_register( &dj ); + if( res != FR_OK ) + { + remove_chain( dj.fs, dclst ); + } + else + { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD( dir + DIR_WrtTime, tim ); /* Crated time */ + ST_WORD( dir + DIR_FstClusLO, dclst ); /* Table start cluster */ + ST_WORD( dir + DIR_FstClusHI, dclst >> 16 ); + dj.fs->wflag = 1; + res = sync( dj.fs ); + } + + LEAVE_FF( dj.fs, res ); +} + +/*-----------------------------------------------------------------------*/ + +/* Change File Attribute */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_chmod( const XCHAR *path, /* Pointer to the file path */ BYTE value, /* Attribute bits */ BYTE mask /* Attribute mask to change */ ) +{ + FRESULT res; + DIR dj; + NAMEBUF( sfn, lfn ); + + BYTE *dir; + + res = chk_mounted( &path, &dj.fs, 1 ); + if( res == FR_OK ) + { + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + if( _FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT) ) + { + res = FR_INVALID_NAME; + } + + if( res == FR_OK ) + { + dir = dj.dir; + if( !dir ) + { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } + else + { /* File or sub directory */ + mask &= AM_RDO | AM_HID | AM_SYS | AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = ( value & mask ) | ( dir[DIR_Attr] & (BYTE)~mask ); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync( dj.fs ); + } + } + } + + LEAVE_FF( dj.fs, res ); +} + +/*-----------------------------------------------------------------------*/ + +/* Change Timestamp */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_utime( const XCHAR *path, /* Pointer to the file/directory name */ const FILINFO *fno /* Pointer to the timestamp to be set */ ) +{ + FRESULT res; + DIR dj; + NAMEBUF( sfn, lfn ); + + BYTE *dir; + + res = chk_mounted( &path, &dj.fs, 1 ); + if( res == FR_OK ) + { + INITBUF( dj, sfn, lfn ); + res = follow_path( &dj, path ); /* Follow the file path */ + if( _FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT) ) + { + res = FR_INVALID_NAME; + } + + if( res == FR_OK ) + { + dir = dj.dir; + if( !dir ) + { /* Root directory */ + res = FR_INVALID_NAME; + } + else + { /* File or sub-directory */ + ST_WORD( dir + DIR_WrtTime, fno->ftime ); + ST_WORD( dir + DIR_WrtDate, fno->fdate ); + dj.fs->wflag = 1; + res = sync( dj.fs ); + } + } + } + + LEAVE_FF( dj.fs, res ); +} + +/*-----------------------------------------------------------------------*/ + +/* Rename File/Directory */ + +/*-----------------------------------------------------------------------*/ +FRESULT f_rename( const XCHAR *path_old, /* Pointer to the old name */ const XCHAR *path_new /* Pointer to the new name */ ) +{ + FRESULT res; + DIR dj_old, dj_new; + NAMEBUF( sfn, lfn ); + + BYTE buf[21], *dir; + DWORD dw; + + INITBUF( dj_old, sfn, lfn ); + res = chk_mounted( &path_old, &dj_old.fs, 1 ); + if( res == FR_OK ) + { + dj_new.fs = dj_old.fs; + res = follow_path( &dj_old, path_old ); /* Check old object */ + if( _FS_RPATH && res == FR_OK && (dj_old.fn[NS] & NS_DOT) ) + { + res = FR_INVALID_NAME; + } + } + + if( res != FR_OK ) + { + LEAVE_FF( dj_old.fs, res ); /* The old object is not found */ + } + + if( !dj_old.dir ) + { + LEAVE_FF( dj_old.fs, FR_NO_FILE ); /* Is root dir? */ + } + + mem_cpy( buf, dj_old.dir + DIR_Attr, 21 ); /* Save the object information */ + + mem_cpy( &dj_new, &dj_old, sizeof(DIR) ); + res = follow_path( &dj_new, path_new ); /* Check new object */ + if( res == FR_OK ) + { + res = FR_EXIST; /* The new object name is already existing */ + } + + if( res == FR_NO_FILE ) + { /* Is it a valid path and no name collision? */ + res = dir_register( &dj_new ); /* Register the new object */ + if( res == FR_OK ) + { + dir = dj_new.dir; /* Copy object information into new entry */ + mem_cpy( dir + 13, buf + 2, 19 ); + dir[DIR_Attr] = buf[0] | AM_ARC; + dj_old.fs->wflag = 1; + if( dir[DIR_Attr] & AM_DIR ) + { /* Update .. entry in the directory if needed */ + dw = clust2sect( dj_new.fs, (DWORD) LD_WORD(dir + DIR_FstClusHI) | LD_WORD(dir + DIR_FstClusLO) ); + if( !dw ) + { + res = FR_INT_ERR; + } + else + { + res = move_window( dj_new.fs, dw ); + dir = dj_new.fs->win + 32; + if( res == FR_OK && dir[1] == '.' ) + { + dw = ( dj_new.fs->fs_type == FS_FAT32 && dj_new.sclust == dj_new.fs->dirbase ) ? 0 : dj_new.sclust; + ST_WORD( dir + DIR_FstClusLO, dw ); + ST_WORD( dir + DIR_FstClusHI, dw >> 16 ); + dj_new.fs->wflag = 1; + } + } + } + + if( res == FR_OK ) + { + res = dir_remove( &dj_old ); /* Remove old entry */ + if( res == FR_OK ) + { + res = sync( dj_old.fs ); + } + } + } + } + + LEAVE_FF( dj_old.fs, res ); +} + + #endif /* !_FS_READONLY */ + #endif /* _FS_MINIMIZE == 0 */ + #endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + +/*-----------------------------------------------------------------------*/ + +/* Forward data to the stream directly (Available on only _FS_TINY cfg) */ + +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY +FRESULT f_forward + ( + FIL *fp, /* Pointer to the file object */ + UINT (*func) ( const BYTE *, UINT ), /* Pointer to the streaming function */ + UINT btr, /* Number of bytes to forward */ + UINT *bf /* Pointer to number of bytes forwarded */ + ) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + + *bf = 0; + + res = validate( fp->fs, fp->id ); /* Check validity of the object */ + if( res != FR_OK ) + { + LEAVE_FF( fp->fs, res ); + } + + if( fp->flag & FA__ERROR ) + { /* Check error flag */ + LEAVE_FF( fp->fs, FR_INT_ERR ); + } + + if( !(fp->flag & FA_READ) ) + { /* Check access mode */ + LEAVE_FF( fp->fs, FR_DENIED ); + } + + remain = fp->fsize - fp->fptr; + if( btr > remain ) + { + btr = ( UINT ) remain; /* Truncate btr by remaining bytes */ + } + + for + ( + ; + btr && (*func) (NULL, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btr -= rcnt + ) + { + if( (fp->fptr % SS(fp->fs)) == 0 ) + { /* On the sector boundary? */ + if( fp->csect >= fp->fs->csize ) + { /* On the cluster boundary? */ + clst = ( fp->fptr == 0 ) ? /* On the top of the file? */ + fp->org_clust : get_fat( fp->fs, fp->curr_clust ); + if( clst <= 1 ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + if( clst == 0xFFFFFFFF ) + { + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + + fp->csect++; /* Next sector address in the cluster */ + } + + sect = clust2sect( fp->fs, fp->curr_clust ); /* Get current data sector */ + if( !sect ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + + sect += fp->csect - 1; + if( move_window(fp->fs, sect) ) + { /* Move sector window */ + ABORT( fp->fs, FR_DISK_ERR ); + } + + fp->dsect = sect; + rcnt = SS( fp->fs ) - ( WORD ) ( fp->fptr % SS(fp->fs) ); /* Forward data from sector window */ + if( rcnt > btr ) + { + rcnt = btr; + } + + rcnt = ( *func ) ( &fp->fs->win[(WORD) fp->fptr % SS(fp->fs)], rcnt ); + if( !rcnt ) + { + ABORT( fp->fs, FR_INT_ERR ); + } + } + + LEAVE_FF( fp->fs, FR_OK ); +} + +#endif /* _USE_FORWARD */ + +#if _USE_MKFS && !_FS_READONLY + +/*-----------------------------------------------------------------------*/ + +/* Create File System on the Drive */ + +/*-----------------------------------------------------------------------*/ + #define N_ROOTDIR 512 /* Multiple of 32 and <= 2048 */ + #define N_FATS 1 /* 1 or 2 */ + #define MAX_SECTOR 131072000UL /* Maximum partition size */ + #define MIN_SECTOR 2000UL /* Minimum partition size */ + +FRESULT f_mkfs + ( + BYTE drv, /* Logical drive number */ + BYTE partition, /* Partitioning rule 0:FDISK, 1:SFD */ + WORD allocsize /* Allocation unit size [bytes] */ + ) +{ + static const DWORD sstbl[] = { 2048000, 1024000, 512000, 256000, 128000, 64000, 32000, 16000, 8000, 4000, 0 }; + static const WORD cstbl[] = { 32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512 }; + BYTE fmt, m, *tbl; + DWORD b_part, b_fat, b_dir, b_data; /* Area offset (LBA) */ + DWORD n_part, n_rsv, n_fat, n_dir; /* Area size */ + DWORD n_clst, d, n; + WORD as; + FATFS *fs; + DSTATUS stat; + + /* Check validity of the parameters */ + if( drv >= _DRIVES ) + { + return FR_INVALID_DRIVE; + } + + if( partition >= 2 ) + { + return FR_MKFS_ABORTED; + } + + /* Check mounted drive and clear work area */ + fs = FatFs[drv]; + if( !fs ) + { + return FR_NOT_ENABLED; + } + + fs->fs_type = 0; + drv = LD2PD( drv ); + + /* Get disk statics */ + stat = disk_initialize( drv ); + if( stat & STA_NOINIT ) + { + return FR_NOT_READY; + } + + if( stat & STA_PROTECT ) + { + return FR_WRITE_PROTECTED; + } + + #if _MAX_SS != 512 /* Get disk sector size */ + if( disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS ) + { + return FR_MKFS_ABORTED; + } + + #endif + if( disk_ioctl(drv, GET_SECTOR_COUNT, &n_part) != RES_OK || n_part < MIN_SECTOR ) + { + return FR_MKFS_ABORTED; + } + + if( n_part > MAX_SECTOR ) + { + n_part = MAX_SECTOR; + } + + b_part = ( !partition ) ? 63 : 0; /* Boot sector */ + n_part -= b_part; + for( d = 512; d <= 32768U && d != allocsize; d <<= 1 ); + + /* Check validity of the allocation unit size */ + if( d != allocsize ) + { + allocsize = 0; + } + + if( !allocsize ) + { /* Auto selection of cluster size */ + d = n_part; + for( as = SS(fs); as > 512U; as >>= 1 ) + { + d >>= 1; + } + + for( n = 0; d < sstbl[n]; n++ ); + allocsize = cstbl[n]; + } + + if( allocsize < SS(fs) ) + { + allocsize = SS( fs ); + } + + allocsize /= SS( fs ); /* Number of sectors per cluster */ + + /* Pre-compute number of clusters and FAT type */ + n_clst = n_part / allocsize; + fmt = FS_FAT12; + if( n_clst >= 0xFF5 ) + { + fmt = FS_FAT16; + } + + if( n_clst >= 0xFFF5 ) + { + fmt = FS_FAT32; + } + + /* Determine offset and size of FAT structure */ + switch( fmt ) + { + case FS_FAT12: + n_fat = ( (n_clst * 3 + 1) / 2 + 3 + SS(fs) - 1 ) / SS( fs ); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS( fs ); + break; + + case FS_FAT16: + n_fat = ( (n_clst * 2) + 4 + SS(fs) - 1 ) / SS( fs ); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS( fs ); + break; + + default: + n_fat = ( (n_clst * 4) + 8 + SS(fs) - 1 ) / SS( fs ); + n_rsv = 33 - partition; + n_dir = 0; + } + + b_fat = b_part + n_rsv; /* FATs start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory start sector */ + b_data = b_dir + n_dir; /* Data start sector */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if( disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK ) + { + return FR_MKFS_ABORTED; + } + + n = ( b_data + n - 1 ) &~( n - 1 ); + n_fat += ( n - b_data ) / N_FATS; + + /* b_dir and b_data are no longer used below */ + + /* Determine number of cluster and final check of validity of the FAT type */ + n_clst = ( n_part - n_rsv - n_fat * N_FATS - n_dir ) / allocsize; + if( (fmt == FS_FAT16 && n_clst < 0xFF5) || (fmt == FS_FAT32 && n_clst < 0xFFF5) ) + { + return FR_MKFS_ABORTED; + } + + /* Create partition table if needed */ + if( !partition ) + { + DWORD n_disk = b_part + n_part; + + mem_set( fs->win, 0, SS(fs) ); + tbl = fs->win + MBR_Table; + ST_DWORD( tbl, 0x00010180 ); /* Partition start in CHS */ + if( n_disk < 63UL * 255 * 1024 ) + { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = ( BYTE ) n_disk; + tbl[6] = ( BYTE ) ( (n_disk >> 2) | 63 ); + } + else + { + ST_WORD( &tbl[6], 0xFFFF ); + } + + tbl[5] = 254; + if( fmt != FS_FAT32 ) + { /* System ID */ + tbl[4] = ( n_part < 0x10000 ) ? 0x04 : 0x06; + } + else + { + tbl[4] = 0x0c; + } + + ST_DWORD( tbl + 8, 63 ); /* Partition start in LBA */ + ST_DWORD( tbl + 12, n_part ); /* Partition size in LBA */ + ST_WORD( tbl + 64, 0xAA55 ); /* Signature */ + if( disk_write(drv, fs->win, 0, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + + partition = 0xF8; + } + else + { + partition = 0xF0; + } + + /* Create boot record */ + tbl = fs->win; /* Clear buffer */ + mem_set( tbl, 0, SS(fs) ); + ST_DWORD( tbl + BS_jmpBoot, 0x90FEEB ); /* Boot code (jmp $, nop) */ + ST_WORD( tbl + BPB_BytsPerSec, SS(fs) ); /* Sector size */ + tbl[BPB_SecPerClus] = ( BYTE ) allocsize; /* Sectors per cluster */ + ST_WORD( tbl + BPB_RsvdSecCnt, n_rsv ); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + ST_WORD( tbl + BPB_RootEntCnt, SS(fs) / 32 * n_dir ); /* Number of rootdir entries */ + if( n_part < 0x10000 ) + { /* Number of total sectors */ + ST_WORD( tbl + BPB_TotSec16, n_part ); + } + else + { + ST_DWORD( tbl + BPB_TotSec32, n_part ); + } + + tbl[BPB_Media] = partition; /* Media descripter */ + ST_WORD( tbl + BPB_SecPerTrk, 63 ); /* Number of sectors per track */ + ST_WORD( tbl + BPB_NumHeads, 255 ); /* Number of heads */ + ST_DWORD( tbl + BPB_HiddSec, b_part ); /* Hidden sectors */ + n = get_fattime(); /* Use current time as a VSN */ + if( fmt != FS_FAT32 ) + { + ST_DWORD( tbl + BS_VolID, n ); /* Volume serial number */ + ST_WORD( tbl + BPB_FATSz16, n_fat ); /* Number of secters per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy( tbl + BS_VolLab, "NO NAME FAT ", 19 ); /* Volume lavel, FAT signature */ + } + else + { + ST_DWORD( tbl + BS_VolID32, n ); /* Volume serial number */ + ST_DWORD( tbl + BPB_FATSz32, n_fat ); /* Number of secters per FAT */ + ST_DWORD( tbl + BPB_RootClus, 2 ); /* Root directory cluster (2) */ + ST_WORD( tbl + BPB_FSInfo, 1 ); /* FSInfo record offset (bs+1) */ + ST_WORD( tbl + BPB_BkBootSec, 6 ); /* Backup boot record offset (bs+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy( tbl + BS_VolLab32, "NO NAME FAT32 ", 19 ); /* Volume lavel, FAT signature */ + } + + ST_WORD( tbl + BS_55AA, 0xAA55 ); /* Signature */ + if( SS(fs) > 512U ) + { + ST_WORD( tbl + SS(fs) - 2, 0xAA55 ); + } + + if( disk_write(drv, tbl, b_part + 0, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + + if( fmt == FS_FAT32 ) + { + disk_write( drv, tbl, b_part + 6, 1 ); + } + + /* Initialize FAT area */ + for( m = 0; m < N_FATS; m++ ) + { + mem_set( tbl, 0, SS(fs) ); /* 1st sector of the FAT */ + if( fmt != FS_FAT32 ) + { + n = ( fmt == FS_FAT12 ) ? 0x00FFFF00 : 0xFFFFFF00; + n |= partition; + ST_DWORD( tbl, n ); /* Reserve cluster #0-1 (FAT12/16) */ + } + else + { + ST_DWORD( tbl + 0, 0xFFFFFFF8 ); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD( tbl + 4, 0xFFFFFFFF ); + ST_DWORD( tbl + 8, 0x0FFFFFFF ); /* Reserve cluster #2 for root dir */ + } + + if( disk_write(drv, tbl, b_fat++, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + + mem_set( tbl, 0, SS(fs) ); /* Following FAT entries are filled by zero */ + for( n = 1; n < n_fat; n++ ) + { + if( disk_write(drv, tbl, b_fat++, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + } + } + + /* Initialize Root directory */ + m = ( BYTE ) ( (fmt == FS_FAT32) ? allocsize : n_dir ); + do + { + if( disk_write(drv, tbl, b_fat++, 1) != RES_OK ) + { + return FR_DISK_ERR; + } + } while( --m ); + + /* Create FSInfo record if needed */ + if( fmt == FS_FAT32 ) + { + ST_WORD( tbl + BS_55AA, 0xAA55 ); + ST_DWORD( tbl + FSI_LeadSig, 0x41615252 ); + ST_DWORD( tbl + FSI_StrucSig, 0x61417272 ); + ST_DWORD( tbl + FSI_Free_Count, n_clst - 1 ); + ST_DWORD( tbl + FSI_Nxt_Free, 0xFFFFFFFF ); + disk_write( drv, tbl, b_part + 1, 1 ); + disk_write( drv, tbl, b_part + 7, 1 ); + } + + return( disk_ioctl(drv, CTRL_SYNC, ( void * ) NULL) == RES_OK ) ? FR_OK : FR_DISK_ERR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + +#if _USE_STRFUNC + +/*-----------------------------------------------------------------------*/ + +/* Get a string from the file */ + +/*-----------------------------------------------------------------------*/ +char *f_gets + ( + char *buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer */ + FIL *fil /* Pointer to the file object */ + ) +{ + int i = 0; + char *p = buff; + UINT rc; + + while( i < len - 1 ) + { /* Read bytes until buffer gets filled */ + f_read( fil, p, 1, &rc ); + if( rc != 1 ) + { + break; /* Break when no data to read */ + } + + #if _USE_STRFUNC >= 2 + if( *p == '\r' ) + { + continue; /* Strip '\r' */ + } + + #endif + i++; + if( *p++ == '\n' ) + { + break; /* Break when reached end of line */ + } + } + + *p = 0; + return i ? buff : NULL; /* When no data read (eof or error), return with error. */ +} + + #if !_FS_READONLY + #include + +/*-----------------------------------------------------------------------*/ + +/* Put a character to the file */ + +/*-----------------------------------------------------------------------*/ +int f_putc( int chr, /* A character to be output */ FIL *fil /* Ponter to the file object */ ) +{ + UINT bw; + char c; + + #if _USE_STRFUNC >= 2 + if( chr == '\n' ) + { + f_putc( '\r', fil ); /* LF -> CRLF conversion */ + } + + #endif + if( !fil ) + { /* Special value may be used to switch the destination to any other device */ + /* put_console(chr); */ + return chr; + } + + c = ( char ) chr; + f_write( fil, &c, 1, &bw ); /* Write a byte to the file */ + return bw ? chr : EOF; /* Return the result */ +} + +/*-----------------------------------------------------------------------*/ + +/* Put a string to the file */ + +/*-----------------------------------------------------------------------*/ +int f_puts( const char *str, /* Pointer to the string to be output */ FIL *fil /* Pointer to the file object */ ) +{ + int n; + + for( n = 0; *str; str++, n++ ) + { + if( f_putc(*str, fil) == EOF ) + { + return EOF; + } + } + + return n; +} + +/*-----------------------------------------------------------------------*/ + +/* Put a formatted string to the file */ + +/*-----------------------------------------------------------------------*/ +int f_printf( FIL *fil, /* Pointer to the file object */ const char *str, /* Pointer to the format string */ ... /* Optional arguments... */ ) +{ + va_list arp; + UCHAR c, f, r; + ULONG val; + char s[16]; + int i, w, res, cc; + + va_start( arp, str ); + + for( cc = res = 0; cc != EOF; res += cc ) + { + c = *str++; + if( c == 0 ) + { + break; /* End of string */ + } + + if( c != '%' ) + { /* Non escape cahracter */ + cc = f_putc( c, fil ); + if( cc != EOF ) + { + cc = 1; + } + + continue; + } + + w = f = 0; + c = *str++; + if( c == '0' ) + { /* Flag: '0' padding */ + f = 1; + c = *str++; + } + + while( c >= '0' && c <= '9' ) + { /* Precision */ + w = w * 10 + ( c - '0' ); + c = *str++; + } + + if( c == 'l' ) + { /* Prefix: Size is long int */ + f |= 2; + c = *str++; + } + + if( c == 's' ) + { /* Type is string */ + cc = f_puts( va_arg(arp, char *), fil ); + continue; + } + + if( c == 'c' ) + { /* Type is character */ + cc = f_putc( va_arg(arp, int), fil ); + if( cc != EOF ) + { + cc = 1; + } + + continue; + } + + r = 0; + if( c == 'd' ) + { + r = 10; /* Type is signed decimal */ + } + + if( c == 'u' ) + { + r = 10; /* Type is unsigned decimal */ + } + + if( c == 'X' ) + { + r = 16; /* Type is unsigned hexdecimal */ + } + + if( r == 0 ) + { + break; /* Unknown type */ + } + + if( f & 2 ) + { /* Get the value */ + val = ( ULONG ) va_arg( arp, long ); + } + else + { + val = ( c == 'd' ) ? ( ULONG ) ( long ) va_arg( arp, int ) : ( ULONG ) va_arg( arp, unsigned int ); + } + + /* Put numeral string */ + if( c == 'd' ) + { + if( val & 0x80000000 ) + { + val = 0 - val; + f |= 4; + } + } + + i = sizeof( s ) - 1; + s[i] = 0; + do + { + c = ( UCHAR ) ( val % r + '0' ); + if( c > '9' ) + { + c += 7; + } + + s[--i] = c; + val /= r; + } while( i && val ); + if( i && (f & 4) ) + { + s[--i] = '-'; + } + + w = sizeof( s ) - 1 - w; + while( i && i > w ) + { + s[--i] = ( f & 1 ) ? '0' : ' '; + } + + cc = f_puts( &s[i], fil ); + } + + va_end( arp ); + return( cc == EOF ) ? cc : res; +} + + #endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/ff.h b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/ff.h new file mode 100644 index 0000000..0e2f212 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/ff.h @@ -0,0 +1,596 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.07e (C)ChaN, 2009 +/----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following trems. +/ +/ Copyright (C) 2009, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/----------------------------------------------------------------------------*/ + +#ifndef _FATFS +#define _FATFS 0x007E + +#include "fat_integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONFIG +#error Wrong configuration file (ffconf.h). +#endif + + +/* DBCS code ranges and SBCS extend char conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + + +/* Character code support macros */ + +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) + +#if _DF1S /* DBCS configuration */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* SBCS configuration */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + + +/* Definitions corresponds to multi partition */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ + +typedef struct _PARTITION { + BYTE pd; /* Physical drive# */ + BYTE pt; /* Partition # (0-3) */ +} PARTITION; + +extern +const PARTITION Drives[]; /* Logical drive# to physical location conversion table */ +#define LD2PD(drv) (Drives[drv].pd) /* Get physical drive# */ +#define LD2PT(drv) (Drives[drv].pt) /* Get partition# */ + +#else /* Single partition configuration */ + +#define LD2PD(drv) (drv) /* Physical drive# is equal to the logical drive# */ +#define LD2PT(drv) 0 /* Always mounts the 1st partition */ + +#endif + + + +/* Definitions corresponds to multiple sector size */ + +#if _MAX_SS == 512 /* Single sector size */ +#define SS(fs) 512U + +#elif _MAX_SS == 1024 || _MAX_SS == 2048 || _MAX_SS == 4096 /* Multiple sector size */ +#define SS(fs) ((fs)->s_size) + +#else +#error Sector size must be 512, 1024, 2048 or 4096. + +#endif + + + +/* Type of file name on FatFs API */ + +#if _LFN_UNICODE && _USE_LFN +typedef WCHAR XCHAR; /* Unicode */ +#else +typedef char XCHAR; /* SBCS, DBCS */ +#endif + + + +/* File system object structure */ + +typedef struct _FATFS_ { + BYTE fs_type; /* FAT sub type */ + BYTE drive; /* Physical drive number */ + BYTE csize; /* Number of sectors per cluster */ + BYTE n_fats; /* Number of FAT copies */ + BYTE wflag; /* win[] dirty flag (1:must be written back) */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (0 on FAT32) */ +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if _MAX_SS != 512 + WORD s_size; /* Sector size */ +#endif +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ + DWORD fsi_sector; /* fsinfo sector */ +#endif +#if _FS_RPATH + DWORD cdir; /* Current directory (0:root)*/ +#endif + DWORD sects_fat; /* Sectors per fat */ + DWORD max_clust; /* Maximum cluster# + 1. Number of clusters is max_clust - 2 */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (Cluster# on FAT32) */ + DWORD database; /* Data start sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS];/* Disk access window for Directory/FAT */ +} FATFS; + + + +/* Directory object structure */ + +typedef struct _DIR_ { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + WORD index; /* Current read/write index number */ + DWORD sclust; /* Table start cluster (0:Static table) */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the current SFN entry in the win[] */ + BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#if _USE_LFN + WCHAR* lfn; /* Pointer to the LFN working buffer */ + WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ +#endif +} DIR; + + + +/* File object structure */ + +typedef struct _FIL_ { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE csect; /* Sector address in the cluster */ + DWORD fptr; /* File R/W pointer */ + DWORD fsize; /* File size */ + DWORD org_clust; /* File start cluster */ + DWORD curr_clust; /* Current cluster */ + DWORD dsect; /* Current data sector */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Ponter to the directory entry in the window */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS];/* File R/W buffer */ +#endif +} FIL; + + + +/* File status structure */ + +typedef struct _FILINFO_ { + DWORD fsize; /* File size */ + WORD fdate; /* Last modified date */ + WORD ftime; /* Last modified time */ + BYTE fattrib; /* Attribute */ + char fname[13]; /* Short file name (8.3 format) */ +#if _USE_LFN + XCHAR* lfname; /* Pointer to the LFN buffer */ + int lfsize; /* Size of LFN buffer [chrs] */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* 0 */ + FR_DISK_ERR, /* 1 */ + FR_INT_ERR, /* 2 */ + FR_NOT_READY, /* 3 */ + FR_NO_FILE, /* 4 */ + FR_NO_PATH, /* 5 */ + FR_INVALID_NAME, /* 6 */ + FR_DENIED, /* 7 */ + FR_EXIST, /* 8 */ + FR_INVALID_OBJECT, /* 9 */ + FR_WRITE_PROTECTED, /* 10 */ + FR_INVALID_DRIVE, /* 11 */ + FR_NOT_ENABLED, /* 12 */ + FR_NO_FILESYSTEM, /* 13 */ + FR_MKFS_ABORTED, /* 14 */ + FR_TIMEOUT /* 15 */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const XCHAR*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ +FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const XCHAR*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const XCHAR*, FILINFO*); /* Get file status */ +FRESULT f_getfree (const XCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const XCHAR*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const XCHAR*); /* Create a new directory */ +FRESULT f_chmod (const XCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */ +FRESULT f_utime (const XCHAR*, const FILINFO*); /* Change timestamp of the file/dir */ +FRESULT f_rename (const XCHAR*, const XCHAR*); /* Rename/Move a file or directory */ +FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ +FRESULT f_mkfs (BYTE, BYTE, WORD); /* Create a file system on the drive */ +FRESULT f_chdir (const XCHAR*); /* Change current directory */ +FRESULT f_chdrive (BYTE); /* Change current drive */ + +#if _USE_STRFUNC +int f_putc (int, FIL*); /* Put a character to the file */ +int f_puts (const char*, FIL*); /* Put a string to the file */ +int f_printf (FIL*, const char*, ...); /* Put a formatted string to the file */ +char* f_gets (char*, int, FIL*); /* Get a string from the file */ +#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) +#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) +#ifndef EOF +#define EOF -1 +#endif +#endif + + + +/*--------------------------------------------------------------*/ +/* User defined functions */ + +/* Real time clock */ +#if !_FS_READONLY +DWORD get_fattime (void); /* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */ + /* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */ +#endif + +/* Unicode - OEM code conversion */ +#if _USE_LFN +WCHAR ff_convert (WCHAR, UINT); +WCHAR ff_wtoupper (WCHAR); +#endif + +/* Sync functions */ +#if _FS_REENTRANT +BOOL ff_cre_syncobj(BYTE, _SYNC_t*); +BOOL ff_del_syncobj(_SYNC_t); +BOOL ff_req_grant(_SYNC_t); +void ff_rel_grant(_SYNC_t); +#endif + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#if _FS_READONLY == 0 +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif +#define FA__ERROR 0x80 + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* FatFs refers the members in the FAT structures with byte offset instead +/ of structure member because there are incompatibility of the packing option +/ between various compilers. */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_55AA 510 + +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 + +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 + +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 + +#define MBR_Table 446 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 +#define LDIR_Ord 0 +#define LDIR_Attr 11 +#define LDIR_Type 12 +#define LDIR_Chksum 13 +#define LDIR_FstClusLO 26 + + + +/*--------------------------------*/ +/* Multi-byte word access macros */ + +#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#else /* Use byte-by-byte access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) +#endif + + +#endif /* _FATFS */ diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc932.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc932.c new file mode 100644 index 0000000..779ef68 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc932.c @@ -0,0 +1,3798 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2009 */ +/* */ +/* CP932 (Japanese Shift-JIS) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + +#define _TINY_TABLE 0 + +#if !_USE_LFN || _CODE_PAGE != 932 +#error This file is not needed in current configuration. +#endif + + +static +const WCHAR uni2sjis[] = { +/* Unicode - Sjis, Unicode - Sjis, Unicode - Sjis, Unicode - Sjis, */ + 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, + 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, + 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, + 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, + 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, + 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, + 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, + 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, + 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, + 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, + 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, + 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, + 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, + 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6, + 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, + 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447, + 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B, + 0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F, + 0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453, + 0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457, + 0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B, + 0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F, + 0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472, + 0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477, + 0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B, + 0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480, + 0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484, + 0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488, + 0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C, + 0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490, + 0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C, + 0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168, + 0x2020, 0x81F5, 0x2021, 0x81F6, 0x2025, 0x8164, 0x2026, 0x8163, + 0x2030, 0x81F1, 0x2032, 0x818C, 0x2033, 0x818D, 0x203B, 0x81A6, + 0x2103, 0x818E, 0x2116, 0x8782, 0x2121, 0x8784, 0x212B, 0x81F0, + 0x2160, 0x8754, 0x2161, 0x8755, 0x2162, 0x8756, 0x2163, 0x8757, + 0x2164, 0x8758, 0x2165, 0x8759, 0x2166, 0x875A, 0x2167, 0x875B, + 0x2168, 0x875C, 0x2169, 0x875D, 0x2170, 0xFA40, 0x2171, 0xFA41, + 0x2172, 0xFA42, 0x2173, 0xFA43, 0x2174, 0xFA44, 0x2175, 0xFA45, + 0x2176, 0xFA46, 0x2177, 0xFA47, 0x2178, 0xFA48, 0x2179, 0xFA49, + 0x2190, 0x81A9, 0x2191, 0x81AA, 0x2192, 0x81A8, 0x2193, 0x81AB, + 0x21D2, 0x81CB, 0x21D4, 0x81CC, 0x2200, 0x81CD, 0x2202, 0x81DD, + 0x2203, 0x81CE, 0x2207, 0x81DE, 0x2208, 0x81B8, 0x220B, 0x81B9, + 0x2211, 0x8794, 0x221A, 0x81E3, 0x221D, 0x81E5, 0x221E, 0x8187, + 0x221F, 0x8798, 0x2220, 0x81DA, 0x2225, 0x8161, 0x2227, 0x81C8, + 0x2228, 0x81C9, 0x2229, 0x81BF, 0x222A, 0x81BE, 0x222B, 0x81E7, + 0x222C, 0x81E8, 0x222E, 0x8793, 0x2234, 0x8188, 0x2235, 0x81E6, + 0x223D, 0x81E4, 0x2252, 0x81E0, 0x2260, 0x8182, 0x2261, 0x81DF, + 0x2266, 0x8185, 0x2267, 0x8186, 0x226A, 0x81E1, 0x226B, 0x81E2, + 0x2282, 0x81BC, 0x2283, 0x81BD, 0x2286, 0x81BA, 0x2287, 0x81BB, + 0x22A5, 0x81DB, 0x22BF, 0x8799, 0x2312, 0x81DC, 0x2460, 0x8740, + 0x2461, 0x8741, 0x2462, 0x8742, 0x2463, 0x8743, 0x2464, 0x8744, + 0x2465, 0x8745, 0x2466, 0x8746, 0x2467, 0x8747, 0x2468, 0x8748, + 0x2469, 0x8749, 0x246A, 0x874A, 0x246B, 0x874B, 0x246C, 0x874C, + 0x246D, 0x874D, 0x246E, 0x874E, 0x246F, 0x874F, 0x2470, 0x8750, + 0x2471, 0x8751, 0x2472, 0x8752, 0x2473, 0x8753, 0x2500, 0x849F, + 0x2501, 0x84AA, 0x2502, 0x84A0, 0x2503, 0x84AB, 0x250C, 0x84A1, + 0x250F, 0x84AC, 0x2510, 0x84A2, 0x2513, 0x84AD, 0x2514, 0x84A4, + 0x2517, 0x84AF, 0x2518, 0x84A3, 0x251B, 0x84AE, 0x251C, 0x84A5, + 0x251D, 0x84BA, 0x2520, 0x84B5, 0x2523, 0x84B0, 0x2524, 0x84A7, + 0x2525, 0x84BC, 0x2528, 0x84B7, 0x252B, 0x84B2, 0x252C, 0x84A6, + 0x252F, 0x84B6, 0x2530, 0x84BB, 0x2533, 0x84B1, 0x2534, 0x84A8, + 0x2537, 0x84B8, 0x2538, 0x84BD, 0x253B, 0x84B3, 0x253C, 0x84A9, + 0x253F, 0x84B9, 0x2542, 0x84BE, 0x254B, 0x84B4, 0x25A0, 0x81A1, + 0x25A1, 0x81A0, 0x25B2, 0x81A3, 0x25B3, 0x81A2, 0x25BC, 0x81A5, + 0x25BD, 0x81A4, 0x25C6, 0x819F, 0x25C7, 0x819E, 0x25CB, 0x819B, + 0x25CE, 0x819D, 0x25CF, 0x819C, 0x25EF, 0x81FC, 0x2605, 0x819A, + 0x2606, 0x8199, 0x2640, 0x818A, 0x2642, 0x8189, 0x266A, 0x81F4, + 0x266D, 0x81F3, 0x266F, 0x81F2, 0x3000, 0x8140, 0x3001, 0x8141, + 0x3002, 0x8142, 0x3003, 0x8156, 0x3005, 0x8158, 0x3006, 0x8159, + 0x3007, 0x815A, 0x3008, 0x8171, 0x3009, 0x8172, 0x300A, 0x8173, + 0x300B, 0x8174, 0x300C, 0x8175, 0x300D, 0x8176, 0x300E, 0x8177, + 0x300F, 0x8178, 0x3010, 0x8179, 0x3011, 0x817A, 0x3012, 0x81A7, + 0x3013, 0x81AC, 0x3014, 0x816B, 0x3015, 0x816C, 0x301D, 0x8780, + 0x301F, 0x8781, 0x3041, 0x829F, 0x3042, 0x82A0, 0x3043, 0x82A1, + 0x3044, 0x82A2, 0x3045, 0x82A3, 0x3046, 0x82A4, 0x3047, 0x82A5, + 0x3048, 0x82A6, 0x3049, 0x82A7, 0x304A, 0x82A8, 0x304B, 0x82A9, + 0x304C, 0x82AA, 0x304D, 0x82AB, 0x304E, 0x82AC, 0x304F, 0x82AD, + 0x3050, 0x82AE, 0x3051, 0x82AF, 0x3052, 0x82B0, 0x3053, 0x82B1, + 0x3054, 0x82B2, 0x3055, 0x82B3, 0x3056, 0x82B4, 0x3057, 0x82B5, + 0x3058, 0x82B6, 0x3059, 0x82B7, 0x305A, 0x82B8, 0x305B, 0x82B9, + 0x305C, 0x82BA, 0x305D, 0x82BB, 0x305E, 0x82BC, 0x305F, 0x82BD, + 0x3060, 0x82BE, 0x3061, 0x82BF, 0x3062, 0x82C0, 0x3063, 0x82C1, + 0x3064, 0x82C2, 0x3065, 0x82C3, 0x3066, 0x82C4, 0x3067, 0x82C5, + 0x3068, 0x82C6, 0x3069, 0x82C7, 0x306A, 0x82C8, 0x306B, 0x82C9, + 0x306C, 0x82CA, 0x306D, 0x82CB, 0x306E, 0x82CC, 0x306F, 0x82CD, + 0x3070, 0x82CE, 0x3071, 0x82CF, 0x3072, 0x82D0, 0x3073, 0x82D1, + 0x3074, 0x82D2, 0x3075, 0x82D3, 0x3076, 0x82D4, 0x3077, 0x82D5, + 0x3078, 0x82D6, 0x3079, 0x82D7, 0x307A, 0x82D8, 0x307B, 0x82D9, + 0x307C, 0x82DA, 0x307D, 0x82DB, 0x307E, 0x82DC, 0x307F, 0x82DD, + 0x3080, 0x82DE, 0x3081, 0x82DF, 0x3082, 0x82E0, 0x3083, 0x82E1, + 0x3084, 0x82E2, 0x3085, 0x82E3, 0x3086, 0x82E4, 0x3087, 0x82E5, + 0x3088, 0x82E6, 0x3089, 0x82E7, 0x308A, 0x82E8, 0x308B, 0x82E9, + 0x308C, 0x82EA, 0x308D, 0x82EB, 0x308E, 0x82EC, 0x308F, 0x82ED, + 0x3090, 0x82EE, 0x3091, 0x82EF, 0x3092, 0x82F0, 0x3093, 0x82F1, + 0x3094, 0x8394, 0x309B, 0x814A, 0x309C, 0x814B, 0x309D, 0x8154, + 0x309E, 0x8155, 0x30A1, 0x8340, 0x30A2, 0x8341, 0x30A3, 0x8342, + 0x30A4, 0x8343, 0x30A5, 0x8344, 0x30A6, 0x8345, 0x30A7, 0x8346, + 0x30A8, 0x8347, 0x30A9, 0x8348, 0x30AA, 0x8349, 0x30AB, 0x834A, + 0x30AC, 0x834B, 0x30AD, 0x834C, 0x30AE, 0x834D, 0x30AF, 0x834E, + 0x30B0, 0x834F, 0x30B1, 0x8350, 0x30B2, 0x8351, 0x30B3, 0x8352, + 0x30B4, 0x8353, 0x30B5, 0x8354, 0x30B6, 0x8355, 0x30B7, 0x8356, + 0x30B8, 0x8357, 0x30B9, 0x8358, 0x30BA, 0x8359, 0x30BB, 0x835A, + 0x30BC, 0x835B, 0x30BD, 0x835C, 0x30BE, 0x835D, 0x30BF, 0x835E, + 0x30C0, 0x835F, 0x30C1, 0x8360, 0x30C2, 0x8361, 0x30C3, 0x8362, + 0x30C4, 0x8363, 0x30C5, 0x8364, 0x30C6, 0x8365, 0x30C7, 0x8366, + 0x30C8, 0x8367, 0x30C9, 0x8368, 0x30CA, 0x8369, 0x30CB, 0x836A, + 0x30CC, 0x836B, 0x30CD, 0x836C, 0x30CE, 0x836D, 0x30CF, 0x836E, + 0x30D0, 0x836F, 0x30D1, 0x8370, 0x30D2, 0x8371, 0x30D3, 0x8372, + 0x30D4, 0x8373, 0x30D5, 0x8374, 0x30D6, 0x8375, 0x30D7, 0x8376, + 0x30D8, 0x8377, 0x30D9, 0x8378, 0x30DA, 0x8379, 0x30DB, 0x837A, + 0x30DC, 0x837B, 0x30DD, 0x837C, 0x30DE, 0x837D, 0x30DF, 0x837E, + 0x30E0, 0x8380, 0x30E1, 0x8381, 0x30E2, 0x8382, 0x30E3, 0x8383, + 0x30E4, 0x8384, 0x30E5, 0x8385, 0x30E6, 0x8386, 0x30E7, 0x8387, + 0x30E8, 0x8388, 0x30E9, 0x8389, 0x30EA, 0x838A, 0x30EB, 0x838B, + 0x30EC, 0x838C, 0x30ED, 0x838D, 0x30EE, 0x838E, 0x30EF, 0x838F, + 0x30F0, 0x8390, 0x30F1, 0x8391, 0x30F2, 0x8392, 0x30F3, 0x8393, + 0x30F4, 0x8394, 0x30F5, 0x8395, 0x30F6, 0x8396, 0x30FB, 0x8145, + 0x30FC, 0x815B, 0x30FD, 0x8152, 0x30FE, 0x8153, 0x3231, 0x878A, + 0x3232, 0x878B, 0x3239, 0x878C, 0x32A4, 0x8785, 0x32A5, 0x8786, + 0x32A6, 0x8787, 0x32A7, 0x8788, 0x32A8, 0x8789, 0x3303, 0x8765, + 0x330D, 0x8769, 0x3314, 0x8760, 0x3318, 0x8763, 0x3322, 0x8761, + 0x3323, 0x876B, 0x3326, 0x876A, 0x3327, 0x8764, 0x332B, 0x876C, + 0x3336, 0x8766, 0x333B, 0x876E, 0x3349, 0x875F, 0x334A, 0x876D, + 0x334D, 0x8762, 0x3351, 0x8767, 0x3357, 0x8768, 0x337B, 0x877E, + 0x337C, 0x878F, 0x337D, 0x878E, 0x337E, 0x878D, 0x338E, 0x8772, + 0x338F, 0x8773, 0x339C, 0x876F, 0x339D, 0x8770, 0x339E, 0x8771, + 0x33A1, 0x8775, 0x33C4, 0x8774, 0x33CD, 0x8783, 0x4E00, 0x88EA, + 0x4E01, 0x929A, 0x4E03, 0x8EB5, 0x4E07, 0x969C, 0x4E08, 0x8FE4, + 0x4E09, 0x8E4F, 0x4E0A, 0x8FE3, 0x4E0B, 0x89BA, 0x4E0D, 0x9573, + 0x4E0E, 0x975E, 0x4E10, 0x98A0, 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0x9D44, 0xE9F5, 0x9D46, 0xE9FB, 0x9D48, 0xE9FC, 0x9D50, 0xEA44, + 0x9D51, 0xEA43, 0x9D59, 0xEA45, 0x9D5C, 0x894C, 0x9D5D, 0xEA40, + 0x9D5E, 0xEA41, 0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, + 0x9D6B, 0xFC48, 0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, + 0x9D72, 0xEA46, 0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, + 0x9D8F, 0x8C7B, 0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, + 0x9DAB, 0xEA49, 0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, + 0x9DB8, 0xEA53, 0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, + 0x9DC2, 0xEA57, 0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, + 0x9DD3, 0xEA59, 0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, + 0x9DEF, 0xEA5D, 0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, + 0x9DFA, 0x8DEB, 0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, + 0x9E1B, 0xEA60, 0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, + 0x9E79, 0xEA63, 0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, + 0x9E88, 0xEA66, 0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, + 0x9E92, 0xEA69, 0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, + 0x9E9D, 0xEA6C, 0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, + 0x9EA9, 0xEA6E, 0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, + 0x9EB9, 0x8D8D, 0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, + 0x9EBE, 0x9F80, 0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, + 0x9ECD, 0x8B6F, 0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, + 0x9ED1, 0xFC4B, 0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, + 0x9ED9, 0x96D9, 0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, + 0x9EDE, 0xEA79, 0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, + 0x9EEF, 0xEA7E, 0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, + 0x9EF9, 0xEA83, 0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, + 0x9F07, 0xEA87, 0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, + 0x9F15, 0xEA8A, 0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, + 0x9F3B, 0x9540, 0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, + 0x9F4E, 0xE6D8, 0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, + 0x9F5F, 0xEA92, 0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, + 0x9F63, 0xEA91, 0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, + 0x9F6C, 0xEA97, 0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, + 0x9F8D, 0x97B4, 0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, + 0x9FA0, 0xEA9E, 0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, + 0xFA0F, 0xFA9B, 0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, + 0xFA13, 0xFAE8, 0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, + 0xFA17, 0xFB75, 0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, + 0xFA1B, 0xFB82, 0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, + 0xFA1F, 0xFB9D, 0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, + 0xFA23, 0xFBB1, 0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, + 0xFA27, 0xFBD3, 0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, + 0xFA2B, 0xFBF7, 0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, + 0xFF02, 0xFA57, 0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, + 0xFF06, 0x8195, 0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, + 0xFF0A, 0x8196, 0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, + 0xFF0E, 0x8144, 0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, + 0xFF12, 0x8251, 0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, + 0xFF16, 0x8255, 0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, + 0xFF1A, 0x8146, 0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, + 0xFF1E, 0x8184, 0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, + 0xFF22, 0x8261, 0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, + 0xFF26, 0x8265, 0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, + 0xFF2A, 0x8269, 0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, + 0xFF2E, 0x826D, 0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, + 0xFF32, 0x8271, 0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, + 0xFF36, 0x8275, 0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, + 0xFF3A, 0x8279, 0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, + 0xFF3E, 0x814F, 0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, + 0xFF42, 0x8282, 0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, + 0xFF46, 0x8286, 0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, + 0xFF4A, 0x828A, 0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, + 0xFF4E, 0x828E, 0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, + 0xFF52, 0x8292, 0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, + 0xFF56, 0x8296, 0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, + 0xFF5A, 0x829A, 0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, + 0xFF5E, 0x8160, 0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, + 0xFF64, 0x00A4, 0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, + 0xFF68, 0x00A8, 0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, + 0xFF6C, 0x00AC, 0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, + 0xFF70, 0x00B0, 0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, + 0xFF74, 0x00B4, 0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, + 0xFF78, 0x00B8, 0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, + 0xFF7C, 0x00BC, 0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, + 0xFF80, 0x00C0, 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, + 0xFF84, 0x00C4, 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, + 0xFF88, 0x00C8, 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, + 0xFF8C, 0x00CC, 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, + 0xFF90, 0x00D0, 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, + 0xFF94, 0x00D4, 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, + 0xFF98, 0x00D8, 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, + 0xFF9C, 0x00DC, 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, + 0xFFE0, 0x8191, 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, + 0xFFE4, 0xFA55, 0xFFE5, 0x818F, 0, 0 +}; + +#if !_TINY_TABLE +static +const WCHAR sjis2uni[] = { +/* SJIS - Unicode, SJIS - Unicode, SJIS - Unicode, SJIS - Unicode, */ + 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, + 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, + 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, + 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, + 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, + 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, + 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, + 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, + 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, + 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, + 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, + 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, + 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, + 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98, + 0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C, + 0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000, + 0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E, + 0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F, + 0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4, + 0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3, + 0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D, + 0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005, + 0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015, + 0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E, + 0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025, + 0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D, + 0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015, + 0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D, + 0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B, + 0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F, + 0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D, + 0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D, + 0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266, + 0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642, + 0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033, + 0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0, + 0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06, + 0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606, + 0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE, + 0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0, + 0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC, + 0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190, + 0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208, + 0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282, + 0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227, + 0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4, + 0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5, + 0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261, + 0x81E0, 0x2252, 0x81E1, 0x226A, 0x81E2, 0x226B, 0x81E3, 0x221A, + 0x81E4, 0x223D, 0x81E5, 0x221D, 0x81E6, 0x2235, 0x81E7, 0x222B, + 0x81E8, 0x222C, 0x81F0, 0x212B, 0x81F1, 0x2030, 0x81F2, 0x266F, + 0x81F3, 0x266D, 0x81F4, 0x266A, 0x81F5, 0x2020, 0x81F6, 0x2021, + 0x81F7, 0x00B6, 0x81FC, 0x25EF, 0x824F, 0xFF10, 0x8250, 0xFF11, + 0x8251, 0xFF12, 0x8252, 0xFF13, 0x8253, 0xFF14, 0x8254, 0xFF15, + 0x8255, 0xFF16, 0x8256, 0xFF17, 0x8257, 0xFF18, 0x8258, 0xFF19, + 0x8260, 0xFF21, 0x8261, 0xFF22, 0x8262, 0xFF23, 0x8263, 0xFF24, + 0x8264, 0xFF25, 0x8265, 0xFF26, 0x8266, 0xFF27, 0x8267, 0xFF28, + 0x8268, 0xFF29, 0x8269, 0xFF2A, 0x826A, 0xFF2B, 0x826B, 0xFF2C, + 0x826C, 0xFF2D, 0x826D, 0xFF2E, 0x826E, 0xFF2F, 0x826F, 0xFF30, + 0x8270, 0xFF31, 0x8271, 0xFF32, 0x8272, 0xFF33, 0x8273, 0xFF34, + 0x8274, 0xFF35, 0x8275, 0xFF36, 0x8276, 0xFF37, 0x8277, 0xFF38, + 0x8278, 0xFF39, 0x8279, 0xFF3A, 0x8281, 0xFF41, 0x8282, 0xFF42, + 0x8283, 0xFF43, 0x8284, 0xFF44, 0x8285, 0xFF45, 0x8286, 0xFF46, + 0x8287, 0xFF47, 0x8288, 0xFF48, 0x8289, 0xFF49, 0x828A, 0xFF4A, + 0x828B, 0xFF4B, 0x828C, 0xFF4C, 0x828D, 0xFF4D, 0x828E, 0xFF4E, + 0x828F, 0xFF4F, 0x8290, 0xFF50, 0x8291, 0xFF51, 0x8292, 0xFF52, + 0x8293, 0xFF53, 0x8294, 0xFF54, 0x8295, 0xFF55, 0x8296, 0xFF56, + 0x8297, 0xFF57, 0x8298, 0xFF58, 0x8299, 0xFF59, 0x829A, 0xFF5A, + 0x829F, 0x3041, 0x82A0, 0x3042, 0x82A1, 0x3043, 0x82A2, 0x3044, + 0x82A3, 0x3045, 0x82A4, 0x3046, 0x82A5, 0x3047, 0x82A6, 0x3048, + 0x82A7, 0x3049, 0x82A8, 0x304A, 0x82A9, 0x304B, 0x82AA, 0x304C, + 0x82AB, 0x304D, 0x82AC, 0x304E, 0x82AD, 0x304F, 0x82AE, 0x3050, + 0x82AF, 0x3051, 0x82B0, 0x3052, 0x82B1, 0x3053, 0x82B2, 0x3054, + 0x82B3, 0x3055, 0x82B4, 0x3056, 0x82B5, 0x3057, 0x82B6, 0x3058, + 0x82B7, 0x3059, 0x82B8, 0x305A, 0x82B9, 0x305B, 0x82BA, 0x305C, + 0x82BB, 0x305D, 0x82BC, 0x305E, 0x82BD, 0x305F, 0x82BE, 0x3060, + 0x82BF, 0x3061, 0x82C0, 0x3062, 0x82C1, 0x3063, 0x82C2, 0x3064, + 0x82C3, 0x3065, 0x82C4, 0x3066, 0x82C5, 0x3067, 0x82C6, 0x3068, + 0x82C7, 0x3069, 0x82C8, 0x306A, 0x82C9, 0x306B, 0x82CA, 0x306C, + 0x82CB, 0x306D, 0x82CC, 0x306E, 0x82CD, 0x306F, 0x82CE, 0x3070, + 0x82CF, 0x3071, 0x82D0, 0x3072, 0x82D1, 0x3073, 0x82D2, 0x3074, + 0x82D3, 0x3075, 0x82D4, 0x3076, 0x82D5, 0x3077, 0x82D6, 0x3078, + 0x82D7, 0x3079, 0x82D8, 0x307A, 0x82D9, 0x307B, 0x82DA, 0x307C, + 0x82DB, 0x307D, 0x82DC, 0x307E, 0x82DD, 0x307F, 0x82DE, 0x3080, + 0x82DF, 0x3081, 0x82E0, 0x3082, 0x82E1, 0x3083, 0x82E2, 0x3084, + 0x82E3, 0x3085, 0x82E4, 0x3086, 0x82E5, 0x3087, 0x82E6, 0x3088, + 0x82E7, 0x3089, 0x82E8, 0x308A, 0x82E9, 0x308B, 0x82EA, 0x308C, + 0x82EB, 0x308D, 0x82EC, 0x308E, 0x82ED, 0x308F, 0x82EE, 0x3090, + 0x82EF, 0x3091, 0x82F0, 0x3092, 0x82F1, 0x3093, 0x8340, 0x30A1, + 0x8341, 0x30A2, 0x8342, 0x30A3, 0x8343, 0x30A4, 0x8344, 0x30A5, + 0x8345, 0x30A6, 0x8346, 0x30A7, 0x8347, 0x30A8, 0x8348, 0x30A9, + 0x8349, 0x30AA, 0x834A, 0x30AB, 0x834B, 0x30AC, 0x834C, 0x30AD, + 0x834D, 0x30AE, 0x834E, 0x30AF, 0x834F, 0x30B0, 0x8350, 0x30B1, + 0x8351, 0x30B2, 0x8352, 0x30B3, 0x8353, 0x30B4, 0x8354, 0x30B5, + 0x8355, 0x30B6, 0x8356, 0x30B7, 0x8357, 0x30B8, 0x8358, 0x30B9, + 0x8359, 0x30BA, 0x835A, 0x30BB, 0x835B, 0x30BC, 0x835C, 0x30BD, + 0x835D, 0x30BE, 0x835E, 0x30BF, 0x835F, 0x30C0, 0x8360, 0x30C1, + 0x8361, 0x30C2, 0x8362, 0x30C3, 0x8363, 0x30C4, 0x8364, 0x30C5, + 0x8365, 0x30C6, 0x8366, 0x30C7, 0x8367, 0x30C8, 0x8368, 0x30C9, + 0x8369, 0x30CA, 0x836A, 0x30CB, 0x836B, 0x30CC, 0x836C, 0x30CD, + 0x836D, 0x30CE, 0x836E, 0x30CF, 0x836F, 0x30D0, 0x8370, 0x30D1, + 0x8371, 0x30D2, 0x8372, 0x30D3, 0x8373, 0x30D4, 0x8374, 0x30D5, + 0x8375, 0x30D6, 0x8376, 0x30D7, 0x8377, 0x30D8, 0x8378, 0x30D9, + 0x8379, 0x30DA, 0x837A, 0x30DB, 0x837B, 0x30DC, 0x837C, 0x30DD, + 0x837D, 0x30DE, 0x837E, 0x30DF, 0x8380, 0x30E0, 0x8381, 0x30E1, + 0x8382, 0x30E2, 0x8383, 0x30E3, 0x8384, 0x30E4, 0x8385, 0x30E5, + 0x8386, 0x30E6, 0x8387, 0x30E7, 0x8388, 0x30E8, 0x8389, 0x30E9, + 0x838A, 0x30EA, 0x838B, 0x30EB, 0x838C, 0x30EC, 0x838D, 0x30ED, + 0x838E, 0x30EE, 0x838F, 0x30EF, 0x8390, 0x30F0, 0x8391, 0x30F1, + 0x8392, 0x30F2, 0x8393, 0x30F3, 0x8394, 0x3094, 0x8394, 0x30F4, + 0x8395, 0x30F5, 0x8396, 0x30F6, 0x839F, 0x0391, 0x83A0, 0x0392, + 0x83A1, 0x0393, 0x83A2, 0x0394, 0x83A3, 0x0395, 0x83A4, 0x0396, + 0x83A5, 0x0397, 0x83A6, 0x0398, 0x83A7, 0x0399, 0x83A8, 0x039A, + 0x83A9, 0x039B, 0x83AA, 0x039C, 0x83AB, 0x039D, 0x83AC, 0x039E, + 0x83AD, 0x039F, 0x83AE, 0x03A0, 0x83AF, 0x03A1, 0x83B0, 0x03A3, + 0x83B1, 0x03A4, 0x83B2, 0x03A5, 0x83B3, 0x03A6, 0x83B4, 0x03A7, + 0x83B5, 0x03A8, 0x83B6, 0x03A9, 0x83BF, 0x03B1, 0x83C0, 0x03B2, + 0x83C1, 0x03B3, 0x83C2, 0x03B4, 0x83C3, 0x03B5, 0x83C4, 0x03B6, + 0x83C5, 0x03B7, 0x83C6, 0x03B8, 0x83C7, 0x03B9, 0x83C8, 0x03BA, + 0x83C9, 0x03BB, 0x83CA, 0x03BC, 0x83CB, 0x03BD, 0x83CC, 0x03BE, + 0x83CD, 0x03BF, 0x83CE, 0x03C0, 0x83CF, 0x03C1, 0x83D0, 0x03C3, + 0x83D1, 0x03C4, 0x83D2, 0x03C5, 0x83D3, 0x03C6, 0x83D4, 0x03C7, + 0x83D5, 0x03C8, 0x83D6, 0x03C9, 0x8440, 0x0410, 0x8441, 0x0411, + 0x8442, 0x0412, 0x8443, 0x0413, 0x8444, 0x0414, 0x8445, 0x0415, + 0x8446, 0x0401, 0x8447, 0x0416, 0x8448, 0x0417, 0x8449, 0x0418, + 0x844A, 0x0419, 0x844B, 0x041A, 0x844C, 0x041B, 0x844D, 0x041C, + 0x844E, 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0xFB5E, 0xFA16, 0xFB5F, 0x7377, 0xFB60, 0x73BD, 0xFB61, 0x73C9, + 0xFB62, 0x73D6, 0xFB63, 0x73E3, 0xFB64, 0x73D2, 0xFB65, 0x7407, + 0xFB66, 0x73F5, 0xFB67, 0x7426, 0xFB68, 0x742A, 0xFB69, 0x7429, + 0xFB6A, 0x742E, 0xFB6B, 0x7462, 0xFB6C, 0x7489, 0xFB6D, 0x749F, + 0xFB6E, 0x7501, 0xFB6F, 0x756F, 0xFB70, 0x7682, 0xFB71, 0x769C, + 0xFB72, 0x769E, 0xFB73, 0x769B, 0xFB74, 0x76A6, 0xFB75, 0xFA17, + 0xFB76, 0x7746, 0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, + 0xFB7A, 0x7864, 0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, + 0xFB7E, 0xFA19, 0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, + 0xFB83, 0x799B, 0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, + 0xFB87, 0x7AEB, 0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, + 0xFB8B, 0x7D5C, 0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, + 0xFB8F, 0x7E52, 0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, + 0xFB93, 0x8301, 0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, + 0xFB97, 0x83F6, 0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, + 0xFB9B, 0x8559, 0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, + 0xFB9F, 0xFA20, 0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, + 0xFBA3, 0x8A12, 0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, + 0xFBA7, 0x8ABE, 0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, + 0xFBAB, 0x8B53, 0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, + 0xFBAF, 0x8D12, 0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, + 0xFBB3, 0xFA24, 0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, + 0xFBB7, 0xFA26, 0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, + 0xFBBB, 0x91D7, 0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, + 0xFBBF, 0x91E4, 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, + 0xFBC3, 0x920A, 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, + 0xFBC7, 0x924E, 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, + 0xFBCB, 0x9267, 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, + 0xFBCF, 0x92E7, 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, + 0xFBD3, 0xFA27, 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, + 0xFBD7, 0x9325, 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, + 0xFBDB, 0x931E, 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, + 0xFBDF, 0x9370, 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, + 0xFBE3, 0x93DE, 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, + 0xFBE7, 0x9448, 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, + 0xFBEB, 0x969D, 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, + 0xFBEF, 0x9743, 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, + 0xFBF3, 0x9755, 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, + 0xFBF7, 0xFA2B, 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, + 0xFBFB, 0x9A4E, 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, + 0xFC42, 0x9B72, 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, + 0xFC46, 0x9C00, 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, + 0xFC4A, 0x9E19, 0xFC4B, 0x9ED1, 0, 0 +}; +#endif + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (src <= 0x80) { /* ASCII */ + c = src; + } else { +#if !_TINY_TABLE + if (dir) { /* OEMCP to unicode */ + p = sjis2uni; + hi = sizeof(sjis2uni) / 4 - 1; + } else { /* Unicode to OEMCP */ + p = uni2sjis; + hi = sizeof(uni2sjis) / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (src == p[i * 2]) break; + if (src > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; +#else + if (dir) { /* OEMCP to unicode (Incremental search)*/ + p = &uni2sjis[1]; + do { + c = *p; + p += 2; + p -= 3; + c = *p; + } while (c && c != src); + } else { /* Unicode to OEMCP */ + li = 0; hi = sizeof(uni2sjis) / 4 - 1; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (src == uni2sjis[i * 2]) break; + if (src > uni2sjis[i * 2]) + li = i; + else + hi = i; + } + c = n ? uni2sjis[i * 2 + 1] : 0; + } +#endif + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc936.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc936.c new file mode 100644 index 0000000..276a83f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc936.c @@ -0,0 +1,10973 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2009 */ +/* */ +/* CP936 (Simplified Chinese GBK) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + + +#if !_USE_LFN || _CODE_PAGE != 936 +#error This file is not needed in current configuration. +#endif + +static +const WCHAR uni2oem[] = { +/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ + 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, + 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, + 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, + 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, + 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, + 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, + 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, + 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, + 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, + 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, + 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, + 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, + 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, + 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, + 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, + 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, + 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, + 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, + 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, + 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, + 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, + 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, + 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, + 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, + 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, + 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, + 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, + 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, + 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, + 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, + 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, + 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, + 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, + 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, + 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, + 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, + 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, + 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, + 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, + 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, + 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, + 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD, + 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, + 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847, + 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, + 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5, + 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, + 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1, + 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, + 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9, + 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, + 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B, + 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, + 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE, + 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, + 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8, + 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, + 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6, + 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, + 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852, + 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, + 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9, + 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, + 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1, + 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, + 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB, + 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, + 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3, + 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7, + 0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 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0xFD80, 0x9F7A, 0xFD81, + 0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85, + 0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87, + 0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6, + 0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA, + 0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89, + 0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D, + 0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91, + 0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8, + 0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96, + 0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98, + 0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C, + 0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0, + 0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43, + 0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47, + 0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B, + 0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F, + 0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5, + 0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1, + 0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF, + 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5, + 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, + 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B, + 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, + 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973, + 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, + 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B, + 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, + 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, + 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, + 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, + 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, + 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, + 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, + 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, + 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, + 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, + 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, + 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, + 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, + 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, + 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, + 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, + 0, 0 +}; + +static +const WCHAR oem2uni[] = { +/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ + 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, + 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, + 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, + 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F, + 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, + 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42, + 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, + 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B, + 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, + 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B, + 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, + 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76, + 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, + 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F, + 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, + 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A, + 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, + 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3, + 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, + 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8, + 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, + 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0, + 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, + 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7, + 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, + 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9, + 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, + 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05, + 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, + 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14, + 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, + 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29, + 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, + 0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39, + 0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40, + 0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45, + 0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A, + 0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54, + 0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66, + 0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D, + 0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75, + 0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A, + 0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82, + 0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A, + 0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92, + 0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98, + 0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E, + 0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4, + 0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1, + 0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6, + 0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA, + 0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE, + 0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6, + 0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB, + 0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3, + 0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9, + 0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4, + 0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC, + 0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5, + 0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB, + 0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000, + 0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004, + 0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008, + 0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E, + 0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015, + 0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D, + 0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023, + 0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F, + 0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033, + 0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037, + 0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D, + 0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042, + 0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 0x82A5, 0x5049, + 0x82A6, 0x504A, 0x82A7, 0x504B, 0x82A8, 0x504D, 0x82A9, 0x5050, + 0x82AA, 0x5051, 0x82AB, 0x5052, 0x82AC, 0x5053, 0x82AD, 0x5054, + 0x82AE, 0x5056, 0x82AF, 0x5057, 0x82B0, 0x5058, 0x82B1, 0x5059, + 0x82B2, 0x505B, 0x82B3, 0x505D, 0x82B4, 0x505E, 0x82B5, 0x505F, + 0x82B6, 0x5060, 0x82B7, 0x5061, 0x82B8, 0x5062, 0x82B9, 0x5063, + 0x82BA, 0x5064, 0x82BB, 0x5066, 0x82BC, 0x5067, 0x82BD, 0x5068, + 0x82BE, 0x5069, 0x82BF, 0x506A, 0x82C0, 0x506B, 0x82C1, 0x506D, + 0x82C2, 0x506E, 0x82C3, 0x506F, 0x82C4, 0x5070, 0x82C5, 0x5071, + 0x82C6, 0x5072, 0x82C7, 0x5073, 0x82C8, 0x5074, 0x82C9, 0x5075, + 0x82CA, 0x5078, 0x82CB, 0x5079, 0x82CC, 0x507A, 0x82CD, 0x507C, + 0x82CE, 0x507D, 0x82CF, 0x5081, 0x82D0, 0x5082, 0x82D1, 0x5083, + 0x82D2, 0x5084, 0x82D3, 0x5086, 0x82D4, 0x5087, 0x82D5, 0x5089, + 0x82D6, 0x508A, 0x82D7, 0x508B, 0x82D8, 0x508C, 0x82D9, 0x508E, + 0x82DA, 0x508F, 0x82DB, 0x5090, 0x82DC, 0x5091, 0x82DD, 0x5092, + 0x82DE, 0x5093, 0x82DF, 0x5094, 0x82E0, 0x5095, 0x82E1, 0x5096, + 0x82E2, 0x5097, 0x82E3, 0x5098, 0x82E4, 0x5099, 0x82E5, 0x509A, + 0x82E6, 0x509B, 0x82E7, 0x509C, 0x82E8, 0x509D, 0x82E9, 0x509E, + 0x82EA, 0x509F, 0x82EB, 0x50A0, 0x82EC, 0x50A1, 0x82ED, 0x50A2, + 0x82EE, 0x50A4, 0x82EF, 0x50A6, 0x82F0, 0x50AA, 0x82F1, 0x50AB, + 0x82F2, 0x50AD, 0x82F3, 0x50AE, 0x82F4, 0x50AF, 0x82F5, 0x50B0, + 0x82F6, 0x50B1, 0x82F7, 0x50B3, 0x82F8, 0x50B4, 0x82F9, 0x50B5, + 0x82FA, 0x50B6, 0x82FB, 0x50B7, 0x82FC, 0x50B8, 0x82FD, 0x50B9, + 0x82FE, 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0x72C7, + 0xA0F2, 0x72C9, 0xA0F3, 0x72CA, 0xA0F4, 0x72CB, 0xA0F5, 0x72CC, + 0xA0F6, 0x72CF, 0xA0F7, 0x72D1, 0xA0F8, 0x72D3, 0xA0F9, 0x72D4, + 0xA0FA, 0x72D5, 0xA0FB, 0x72D6, 0xA0FC, 0x72D8, 0xA0FD, 0x72DA, + 0xA0FE, 0x72DB, 0xA1A1, 0x3000, 0xA1A2, 0x3001, 0xA1A3, 0x3002, + 0xA1A4, 0x00B7, 0xA1A5, 0x02C9, 0xA1A6, 0x02C7, 0xA1A7, 0x00A8, + 0xA1A8, 0x3003, 0xA1A9, 0x3005, 0xA1AA, 0x2014, 0xA1AB, 0xFF5E, + 0xA1AC, 0x2016, 0xA1AD, 0x2026, 0xA1AE, 0x2018, 0xA1AF, 0x2019, + 0xA1B0, 0x201C, 0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015, + 0xA1B4, 0x3008, 0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B, + 0xA1B8, 0x300C, 0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F, + 0xA1BC, 0x3016, 0xA1BD, 0x3017, 0xA1BE, 0x3010, 0xA1BF, 0x3011, + 0xA1C0, 0x00B1, 0xA1C1, 0x00D7, 0xA1C2, 0x00F7, 0xA1C3, 0x2236, + 0xA1C4, 0x2227, 0xA1C5, 0x2228, 0xA1C6, 0x2211, 0xA1C7, 0x220F, + 0xA1C8, 0x222A, 0xA1C9, 0x2229, 0xA1CA, 0x2208, 0xA1CB, 0x2237, + 0xA1CC, 0x221A, 0xA1CD, 0x22A5, 0xA1CE, 0x2225, 0xA1CF, 0x2220, + 0xA1D0, 0x2312, 0xA1D1, 0x2299, 0xA1D2, 0x222B, 0xA1D3, 0x222E, + 0xA1D4, 0x2261, 0xA1D5, 0x224C, 0xA1D6, 0x2248, 0xA1D7, 0x223D, + 0xA1D8, 0x221D, 0xA1D9, 0x2260, 0xA1DA, 0x226E, 0xA1DB, 0x226F, + 0xA1DC, 0x2264, 0xA1DD, 0x2265, 0xA1DE, 0x221E, 0xA1DF, 0x2235, + 0xA1E0, 0x2234, 0xA1E1, 0x2642, 0xA1E2, 0x2640, 0xA1E3, 0x00B0, + 0xA1E4, 0x2032, 0xA1E5, 0x2033, 0xA1E6, 0x2103, 0xA1E7, 0xFF04, + 0xA1E8, 0x00A4, 0xA1E9, 0xFFE0, 0xA1EA, 0xFFE1, 0xA1EB, 0x2030, + 0xA1EC, 0x00A7, 0xA1ED, 0x2116, 0xA1EE, 0x2606, 0xA1EF, 0x2605, + 0xA1F0, 0x25CB, 0xA1F1, 0x25CF, 0xA1F2, 0x25CE, 0xA1F3, 0x25C7, + 0xA1F4, 0x25C6, 0xA1F5, 0x25A1, 0xA1F6, 0x25A0, 0xA1F7, 0x25B3, + 0xA1F8, 0x25B2, 0xA1F9, 0x203B, 0xA1FA, 0x2192, 0xA1FB, 0x2190, + 0xA1FC, 0x2191, 0xA1FD, 0x2193, 0xA1FE, 0x3013, 0xA2A1, 0x2170, + 0xA2A2, 0x2171, 0xA2A3, 0x2172, 0xA2A4, 0x2173, 0xA2A5, 0x2174, + 0xA2A6, 0x2175, 0xA2A7, 0x2176, 0xA2A8, 0x2177, 0xA2A9, 0x2178, + 0xA2AA, 0x2179, 0xA2B1, 0x2488, 0xA2B2, 0x2489, 0xA2B3, 0x248A, + 0xA2B4, 0x248B, 0xA2B5, 0x248C, 0xA2B6, 0x248D, 0xA2B7, 0x248E, + 0xA2B8, 0x248F, 0xA2B9, 0x2490, 0xA2BA, 0x2491, 0xA2BB, 0x2492, + 0xA2BC, 0x2493, 0xA2BD, 0x2494, 0xA2BE, 0x2495, 0xA2BF, 0x2496, + 0xA2C0, 0x2497, 0xA2C1, 0x2498, 0xA2C2, 0x2499, 0xA2C3, 0x249A, + 0xA2C4, 0x249B, 0xA2C5, 0x2474, 0xA2C6, 0x2475, 0xA2C7, 0x2476, + 0xA2C8, 0x2477, 0xA2C9, 0x2478, 0xA2CA, 0x2479, 0xA2CB, 0x247A, + 0xA2CC, 0x247B, 0xA2CD, 0x247C, 0xA2CE, 0x247D, 0xA2CF, 0x247E, + 0xA2D0, 0x247F, 0xA2D1, 0x2480, 0xA2D2, 0x2481, 0xA2D3, 0x2482, + 0xA2D4, 0x2483, 0xA2D5, 0x2484, 0xA2D6, 0x2485, 0xA2D7, 0x2486, + 0xA2D8, 0x2487, 0xA2D9, 0x2460, 0xA2DA, 0x2461, 0xA2DB, 0x2462, + 0xA2DC, 0x2463, 0xA2DD, 0x2464, 0xA2DE, 0x2465, 0xA2DF, 0x2466, + 0xA2E0, 0x2467, 0xA2E1, 0x2468, 0xA2E2, 0x2469, 0xA2E5, 0x3220, + 0xA2E6, 0x3221, 0xA2E7, 0x3222, 0xA2E8, 0x3223, 0xA2E9, 0x3224, + 0xA2EA, 0x3225, 0xA2EB, 0x3226, 0xA2EC, 0x3227, 0xA2ED, 0x3228, + 0xA2EE, 0x3229, 0xA2F1, 0x2160, 0xA2F2, 0x2161, 0xA2F3, 0x2162, + 0xA2F4, 0x2163, 0xA2F5, 0x2164, 0xA2F6, 0x2165, 0xA2F7, 0x2166, + 0xA2F8, 0x2167, 0xA2F9, 0x2168, 0xA2FA, 0x2169, 0xA2FB, 0x216A, + 0xA2FC, 0x216B, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03, + 0xA3A4, 0xFFE5, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07, + 0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B, + 0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F, + 0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13, + 0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17, + 0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B, + 0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F, + 0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23, + 0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27, + 0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B, + 0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F, + 0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33, + 0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37, + 0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B, + 0xA3DC, 0xFF3C, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F, + 0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43, + 0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47, + 0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B, + 0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F, + 0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53, + 0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57, + 0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B, + 0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA4A1, 0x3041, + 0xA4A2, 0x3042, 0xA4A3, 0x3043, 0xA4A4, 0x3044, 0xA4A5, 0x3045, + 0xA4A6, 0x3046, 0xA4A7, 0x3047, 0xA4A8, 0x3048, 0xA4A9, 0x3049, + 0xA4AA, 0x304A, 0xA4AB, 0x304B, 0xA4AC, 0x304C, 0xA4AD, 0x304D, + 0xA4AE, 0x304E, 0xA4AF, 0x304F, 0xA4B0, 0x3050, 0xA4B1, 0x3051, + 0xA4B2, 0x3052, 0xA4B3, 0x3053, 0xA4B4, 0x3054, 0xA4B5, 0x3055, + 0xA4B6, 0x3056, 0xA4B7, 0x3057, 0xA4B8, 0x3058, 0xA4B9, 0x3059, + 0xA4BA, 0x305A, 0xA4BB, 0x305B, 0xA4BC, 0x305C, 0xA4BD, 0x305D, + 0xA4BE, 0x305E, 0xA4BF, 0x305F, 0xA4C0, 0x3060, 0xA4C1, 0x3061, + 0xA4C2, 0x3062, 0xA4C3, 0x3063, 0xA4C4, 0x3064, 0xA4C5, 0x3065, + 0xA4C6, 0x3066, 0xA4C7, 0x3067, 0xA4C8, 0x3068, 0xA4C9, 0x3069, + 0xA4CA, 0x306A, 0xA4CB, 0x306B, 0xA4CC, 0x306C, 0xA4CD, 0x306D, + 0xA4CE, 0x306E, 0xA4CF, 0x306F, 0xA4D0, 0x3070, 0xA4D1, 0x3071, + 0xA4D2, 0x3072, 0xA4D3, 0x3073, 0xA4D4, 0x3074, 0xA4D5, 0x3075, + 0xA4D6, 0x3076, 0xA4D7, 0x3077, 0xA4D8, 0x3078, 0xA4D9, 0x3079, + 0xA4DA, 0x307A, 0xA4DB, 0x307B, 0xA4DC, 0x307C, 0xA4DD, 0x307D, + 0xA4DE, 0x307E, 0xA4DF, 0x307F, 0xA4E0, 0x3080, 0xA4E1, 0x3081, + 0xA4E2, 0x3082, 0xA4E3, 0x3083, 0xA4E4, 0x3084, 0xA4E5, 0x3085, + 0xA4E6, 0x3086, 0xA4E7, 0x3087, 0xA4E8, 0x3088, 0xA4E9, 0x3089, + 0xA4EA, 0x308A, 0xA4EB, 0x308B, 0xA4EC, 0x308C, 0xA4ED, 0x308D, + 0xA4EE, 0x308E, 0xA4EF, 0x308F, 0xA4F0, 0x3090, 0xA4F1, 0x3091, + 0xA4F2, 0x3092, 0xA4F3, 0x3093, 0xA5A1, 0x30A1, 0xA5A2, 0x30A2, + 0xA5A3, 0x30A3, 0xA5A4, 0x30A4, 0xA5A5, 0x30A5, 0xA5A6, 0x30A6, + 0xA5A7, 0x30A7, 0xA5A8, 0x30A8, 0xA5A9, 0x30A9, 0xA5AA, 0x30AA, + 0xA5AB, 0x30AB, 0xA5AC, 0x30AC, 0xA5AD, 0x30AD, 0xA5AE, 0x30AE, + 0xA5AF, 0x30AF, 0xA5B0, 0x30B0, 0xA5B1, 0x30B1, 0xA5B2, 0x30B2, + 0xA5B3, 0x30B3, 0xA5B4, 0x30B4, 0xA5B5, 0x30B5, 0xA5B6, 0x30B6, + 0xA5B7, 0x30B7, 0xA5B8, 0x30B8, 0xA5B9, 0x30B9, 0xA5BA, 0x30BA, + 0xA5BB, 0x30BB, 0xA5BC, 0x30BC, 0xA5BD, 0x30BD, 0xA5BE, 0x30BE, + 0xA5BF, 0x30BF, 0xA5C0, 0x30C0, 0xA5C1, 0x30C1, 0xA5C2, 0x30C2, + 0xA5C3, 0x30C3, 0xA5C4, 0x30C4, 0xA5C5, 0x30C5, 0xA5C6, 0x30C6, + 0xA5C7, 0x30C7, 0xA5C8, 0x30C8, 0xA5C9, 0x30C9, 0xA5CA, 0x30CA, + 0xA5CB, 0x30CB, 0xA5CC, 0x30CC, 0xA5CD, 0x30CD, 0xA5CE, 0x30CE, + 0xA5CF, 0x30CF, 0xA5D0, 0x30D0, 0xA5D1, 0x30D1, 0xA5D2, 0x30D2, + 0xA5D3, 0x30D3, 0xA5D4, 0x30D4, 0xA5D5, 0x30D5, 0xA5D6, 0x30D6, + 0xA5D7, 0x30D7, 0xA5D8, 0x30D8, 0xA5D9, 0x30D9, 0xA5DA, 0x30DA, + 0xA5DB, 0x30DB, 0xA5DC, 0x30DC, 0xA5DD, 0x30DD, 0xA5DE, 0x30DE, + 0xA5DF, 0x30DF, 0xA5E0, 0x30E0, 0xA5E1, 0x30E1, 0xA5E2, 0x30E2, + 0xA5E3, 0x30E3, 0xA5E4, 0x30E4, 0xA5E5, 0x30E5, 0xA5E6, 0x30E6, + 0xA5E7, 0x30E7, 0xA5E8, 0x30E8, 0xA5E9, 0x30E9, 0xA5EA, 0x30EA, + 0xA5EB, 0x30EB, 0xA5EC, 0x30EC, 0xA5ED, 0x30ED, 0xA5EE, 0x30EE, + 0xA5EF, 0x30EF, 0xA5F0, 0x30F0, 0xA5F1, 0x30F1, 0xA5F2, 0x30F2, + 0xA5F3, 0x30F3, 0xA5F4, 0x30F4, 0xA5F5, 0x30F5, 0xA5F6, 0x30F6, + 0xA6A1, 0x0391, 0xA6A2, 0x0392, 0xA6A3, 0x0393, 0xA6A4, 0x0394, + 0xA6A5, 0x0395, 0xA6A6, 0x0396, 0xA6A7, 0x0397, 0xA6A8, 0x0398, + 0xA6A9, 0x0399, 0xA6AA, 0x039A, 0xA6AB, 0x039B, 0xA6AC, 0x039C, + 0xA6AD, 0x039D, 0xA6AE, 0x039E, 0xA6AF, 0x039F, 0xA6B0, 0x03A0, + 0xA6B1, 0x03A1, 0xA6B2, 0x03A3, 0xA6B3, 0x03A4, 0xA6B4, 0x03A5, + 0xA6B5, 0x03A6, 0xA6B6, 0x03A7, 0xA6B7, 0x03A8, 0xA6B8, 0x03A9, + 0xA6C1, 0x03B1, 0xA6C2, 0x03B2, 0xA6C3, 0x03B3, 0xA6C4, 0x03B4, + 0xA6C5, 0x03B5, 0xA6C6, 0x03B6, 0xA6C7, 0x03B7, 0xA6C8, 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0xF875, 0x9D18, 0xF876, 0x9D19, 0xF877, 0x9D1A, + 0xF878, 0x9D1B, 0xF879, 0x9D1C, 0xF87A, 0x9D1D, 0xF87B, 0x9D1E, + 0xF87C, 0x9D1F, 0xF87D, 0x9D20, 0xF87E, 0x9D21, 0xF880, 0x9D22, + 0xF881, 0x9D23, 0xF882, 0x9D24, 0xF883, 0x9D25, 0xF884, 0x9D26, + 0xF885, 0x9D27, 0xF886, 0x9D28, 0xF887, 0x9D29, 0xF888, 0x9D2A, + 0xF889, 0x9D2B, 0xF88A, 0x9D2C, 0xF88B, 0x9D2D, 0xF88C, 0x9D2E, + 0xF88D, 0x9D2F, 0xF88E, 0x9D30, 0xF88F, 0x9D31, 0xF890, 0x9D32, + 0xF891, 0x9D33, 0xF892, 0x9D34, 0xF893, 0x9D35, 0xF894, 0x9D36, + 0xF895, 0x9D37, 0xF896, 0x9D38, 0xF897, 0x9D39, 0xF898, 0x9D3A, + 0xF899, 0x9D3B, 0xF89A, 0x9D3C, 0xF89B, 0x9D3D, 0xF89C, 0x9D3E, + 0xF89D, 0x9D3F, 0xF89E, 0x9D40, 0xF89F, 0x9D41, 0xF8A0, 0x9D42, + 0xF940, 0x9D43, 0xF941, 0x9D44, 0xF942, 0x9D45, 0xF943, 0x9D46, + 0xF944, 0x9D47, 0xF945, 0x9D48, 0xF946, 0x9D49, 0xF947, 0x9D4A, + 0xF948, 0x9D4B, 0xF949, 0x9D4C, 0xF94A, 0x9D4D, 0xF94B, 0x9D4E, + 0xF94C, 0x9D4F, 0xF94D, 0x9D50, 0xF94E, 0x9D51, 0xF94F, 0x9D52, + 0xF950, 0x9D53, 0xF951, 0x9D54, 0xF952, 0x9D55, 0xF953, 0x9D56, + 0xF954, 0x9D57, 0xF955, 0x9D58, 0xF956, 0x9D59, 0xF957, 0x9D5A, + 0xF958, 0x9D5B, 0xF959, 0x9D5C, 0xF95A, 0x9D5D, 0xF95B, 0x9D5E, + 0xF95C, 0x9D5F, 0xF95D, 0x9D60, 0xF95E, 0x9D61, 0xF95F, 0x9D62, + 0xF960, 0x9D63, 0xF961, 0x9D64, 0xF962, 0x9D65, 0xF963, 0x9D66, + 0xF964, 0x9D67, 0xF965, 0x9D68, 0xF966, 0x9D69, 0xF967, 0x9D6A, + 0xF968, 0x9D6B, 0xF969, 0x9D6C, 0xF96A, 0x9D6D, 0xF96B, 0x9D6E, + 0xF96C, 0x9D6F, 0xF96D, 0x9D70, 0xF96E, 0x9D71, 0xF96F, 0x9D72, + 0xF970, 0x9D73, 0xF971, 0x9D74, 0xF972, 0x9D75, 0xF973, 0x9D76, + 0xF974, 0x9D77, 0xF975, 0x9D78, 0xF976, 0x9D79, 0xF977, 0x9D7A, + 0xF978, 0x9D7B, 0xF979, 0x9D7C, 0xF97A, 0x9D7D, 0xF97B, 0x9D7E, + 0xF97C, 0x9D7F, 0xF97D, 0x9D80, 0xF97E, 0x9D81, 0xF980, 0x9D82, + 0xF981, 0x9D83, 0xF982, 0x9D84, 0xF983, 0x9D85, 0xF984, 0x9D86, + 0xF985, 0x9D87, 0xF986, 0x9D88, 0xF987, 0x9D89, 0xF988, 0x9D8A, + 0xF989, 0x9D8B, 0xF98A, 0x9D8C, 0xF98B, 0x9D8D, 0xF98C, 0x9D8E, + 0xF98D, 0x9D8F, 0xF98E, 0x9D90, 0xF98F, 0x9D91, 0xF990, 0x9D92, + 0xF991, 0x9D93, 0xF992, 0x9D94, 0xF993, 0x9D95, 0xF994, 0x9D96, + 0xF995, 0x9D97, 0xF996, 0x9D98, 0xF997, 0x9D99, 0xF998, 0x9D9A, + 0xF999, 0x9D9B, 0xF99A, 0x9D9C, 0xF99B, 0x9D9D, 0xF99C, 0x9D9E, + 0xF99D, 0x9D9F, 0xF99E, 0x9DA0, 0xF99F, 0x9DA1, 0xF9A0, 0x9DA2, + 0xFA40, 0x9DA3, 0xFA41, 0x9DA4, 0xFA42, 0x9DA5, 0xFA43, 0x9DA6, + 0xFA44, 0x9DA7, 0xFA45, 0x9DA8, 0xFA46, 0x9DA9, 0xFA47, 0x9DAA, + 0xFA48, 0x9DAB, 0xFA49, 0x9DAC, 0xFA4A, 0x9DAD, 0xFA4B, 0x9DAE, + 0xFA4C, 0x9DAF, 0xFA4D, 0x9DB0, 0xFA4E, 0x9DB1, 0xFA4F, 0x9DB2, + 0xFA50, 0x9DB3, 0xFA51, 0x9DB4, 0xFA52, 0x9DB5, 0xFA53, 0x9DB6, + 0xFA54, 0x9DB7, 0xFA55, 0x9DB8, 0xFA56, 0x9DB9, 0xFA57, 0x9DBA, + 0xFA58, 0x9DBB, 0xFA59, 0x9DBC, 0xFA5A, 0x9DBD, 0xFA5B, 0x9DBE, + 0xFA5C, 0x9DBF, 0xFA5D, 0x9DC0, 0xFA5E, 0x9DC1, 0xFA5F, 0x9DC2, + 0xFA60, 0x9DC3, 0xFA61, 0x9DC4, 0xFA62, 0x9DC5, 0xFA63, 0x9DC6, + 0xFA64, 0x9DC7, 0xFA65, 0x9DC8, 0xFA66, 0x9DC9, 0xFA67, 0x9DCA, + 0xFA68, 0x9DCB, 0xFA69, 0x9DCC, 0xFA6A, 0x9DCD, 0xFA6B, 0x9DCE, + 0xFA6C, 0x9DCF, 0xFA6D, 0x9DD0, 0xFA6E, 0x9DD1, 0xFA6F, 0x9DD2, + 0xFA70, 0x9DD3, 0xFA71, 0x9DD4, 0xFA72, 0x9DD5, 0xFA73, 0x9DD6, + 0xFA74, 0x9DD7, 0xFA75, 0x9DD8, 0xFA76, 0x9DD9, 0xFA77, 0x9DDA, + 0xFA78, 0x9DDB, 0xFA79, 0x9DDC, 0xFA7A, 0x9DDD, 0xFA7B, 0x9DDE, + 0xFA7C, 0x9DDF, 0xFA7D, 0x9DE0, 0xFA7E, 0x9DE1, 0xFA80, 0x9DE2, + 0xFA81, 0x9DE3, 0xFA82, 0x9DE4, 0xFA83, 0x9DE5, 0xFA84, 0x9DE6, + 0xFA85, 0x9DE7, 0xFA86, 0x9DE8, 0xFA87, 0x9DE9, 0xFA88, 0x9DEA, + 0xFA89, 0x9DEB, 0xFA8A, 0x9DEC, 0xFA8B, 0x9DED, 0xFA8C, 0x9DEE, + 0xFA8D, 0x9DEF, 0xFA8E, 0x9DF0, 0xFA8F, 0x9DF1, 0xFA90, 0x9DF2, + 0xFA91, 0x9DF3, 0xFA92, 0x9DF4, 0xFA93, 0x9DF5, 0xFA94, 0x9DF6, + 0xFA95, 0x9DF7, 0xFA96, 0x9DF8, 0xFA97, 0x9DF9, 0xFA98, 0x9DFA, + 0xFA99, 0x9DFB, 0xFA9A, 0x9DFC, 0xFA9B, 0x9DFD, 0xFA9C, 0x9DFE, + 0xFA9D, 0x9DFF, 0xFA9E, 0x9E00, 0xFA9F, 0x9E01, 0xFAA0, 0x9E02, + 0xFB40, 0x9E03, 0xFB41, 0x9E04, 0xFB42, 0x9E05, 0xFB43, 0x9E06, + 0xFB44, 0x9E07, 0xFB45, 0x9E08, 0xFB46, 0x9E09, 0xFB47, 0x9E0A, + 0xFB48, 0x9E0B, 0xFB49, 0x9E0C, 0xFB4A, 0x9E0D, 0xFB4B, 0x9E0E, + 0xFB4C, 0x9E0F, 0xFB4D, 0x9E10, 0xFB4E, 0x9E11, 0xFB4F, 0x9E12, + 0xFB50, 0x9E13, 0xFB51, 0x9E14, 0xFB52, 0x9E15, 0xFB53, 0x9E16, + 0xFB54, 0x9E17, 0xFB55, 0x9E18, 0xFB56, 0x9E19, 0xFB57, 0x9E1A, + 0xFB58, 0x9E1B, 0xFB59, 0x9E1C, 0xFB5A, 0x9E1D, 0xFB5B, 0x9E1E, + 0xFB5C, 0x9E24, 0xFB5D, 0x9E27, 0xFB5E, 0x9E2E, 0xFB5F, 0x9E30, + 0xFB60, 0x9E34, 0xFB61, 0x9E3B, 0xFB62, 0x9E3C, 0xFB63, 0x9E40, + 0xFB64, 0x9E4D, 0xFB65, 0x9E50, 0xFB66, 0x9E52, 0xFB67, 0x9E53, + 0xFB68, 0x9E54, 0xFB69, 0x9E56, 0xFB6A, 0x9E59, 0xFB6B, 0x9E5D, + 0xFB6C, 0x9E5F, 0xFB6D, 0x9E60, 0xFB6E, 0x9E61, 0xFB6F, 0x9E62, + 0xFB70, 0x9E65, 0xFB71, 0x9E6E, 0xFB72, 0x9E6F, 0xFB73, 0x9E72, + 0xFB74, 0x9E74, 0xFB75, 0x9E75, 0xFB76, 0x9E76, 0xFB77, 0x9E77, + 0xFB78, 0x9E78, 0xFB79, 0x9E79, 0xFB7A, 0x9E7A, 0xFB7B, 0x9E7B, + 0xFB7C, 0x9E7C, 0xFB7D, 0x9E7D, 0xFB7E, 0x9E80, 0xFB80, 0x9E81, + 0xFB81, 0x9E83, 0xFB82, 0x9E84, 0xFB83, 0x9E85, 0xFB84, 0x9E86, + 0xFB85, 0x9E89, 0xFB86, 0x9E8A, 0xFB87, 0x9E8C, 0xFB88, 0x9E8D, + 0xFB89, 0x9E8E, 0xFB8A, 0x9E8F, 0xFB8B, 0x9E90, 0xFB8C, 0x9E91, + 0xFB8D, 0x9E94, 0xFB8E, 0x9E95, 0xFB8F, 0x9E96, 0xFB90, 0x9E97, + 0xFB91, 0x9E98, 0xFB92, 0x9E99, 0xFB93, 0x9E9A, 0xFB94, 0x9E9B, + 0xFB95, 0x9E9C, 0xFB96, 0x9E9E, 0xFB97, 0x9EA0, 0xFB98, 0x9EA1, + 0xFB99, 0x9EA2, 0xFB9A, 0x9EA3, 0xFB9B, 0x9EA4, 0xFB9C, 0x9EA5, + 0xFB9D, 0x9EA7, 0xFB9E, 0x9EA8, 0xFB9F, 0x9EA9, 0xFBA0, 0x9EAA, + 0xFC40, 0x9EAB, 0xFC41, 0x9EAC, 0xFC42, 0x9EAD, 0xFC43, 0x9EAE, + 0xFC44, 0x9EAF, 0xFC45, 0x9EB0, 0xFC46, 0x9EB1, 0xFC47, 0x9EB2, + 0xFC48, 0x9EB3, 0xFC49, 0x9EB5, 0xFC4A, 0x9EB6, 0xFC4B, 0x9EB7, + 0xFC4C, 0x9EB9, 0xFC4D, 0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF, + 0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3, + 0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8, + 0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0, + 0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6, + 0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE, + 0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6, + 0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED, + 0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2, + 0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6, + 0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD, + 0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02, + 0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06, + 0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A, + 0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12, + 0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18, + 0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D, + 0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23, + 0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27, + 0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B, + 0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31, + 0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35, + 0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C, + 0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42, + 0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47, + 0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B, + 0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F, + 0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55, + 0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59, + 0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, + 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61, + 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, + 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69, + 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, + 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71, + 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, + 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79, + 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, + 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D, + 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, + 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95, + 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, + 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2, + 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, + 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1, + 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, + 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18, + 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, + 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29, + 0, 0 +}; + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (src < 0x80) { /* ASCII */ + c = src; + } else { + if (dir) { /* OEMCP to unicode */ + p = oem2uni; + hi = sizeof(oem2uni) / 4 - 1; + } else { /* Unicode to OEMCP */ + p = uni2oem; + hi = sizeof(uni2oem) / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (src == p[i * 2]) break; + if (src > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; + } + + return c; +} + + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc949.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc949.c new file mode 100644 index 0000000..5dcb0a8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc949.c @@ -0,0 +1,8603 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2009 */ +/* */ +/* CP949 (Korean) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + + +#if !_USE_LFN || _CODE_PAGE != 949 +#error This file is not needed in current configuration. +#endif + + +static +const WCHAR uni2oem[] = { +/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ + 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, + 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, + 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, + 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, + 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, + 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, + 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, + 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, + 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, + 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, + 0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0, + 0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB, + 0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0, + 0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD, + 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, + 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7, + 0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB, + 0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF, + 0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3, + 0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7, + 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, + 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7, + 0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB, + 0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF, + 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, + 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7, + 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, + 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6, + 0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB, + 0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF, + 0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3, + 0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7, + 0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB, + 0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF, + 0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2, + 0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6, + 0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB, + 0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF, + 0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3, + 0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7, + 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, + 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF, + 0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA, + 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, + 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, + 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8, + 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, + 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9, + 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, + 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7, + 0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD, + 0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2, + 0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6, + 0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1, + 0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5, + 0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9, + 0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6, + 0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8, + 0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1, + 0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4, + 0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3, + 0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4, + 0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD, + 0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3, + 0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD, + 0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5, + 0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED, + 0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7, + 0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7, + 0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB, + 0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF, + 0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3, + 0x246D, 0xA8F4, 0x246E, 0xA8F5, 0x2474, 0xA9E7, 0x2475, 0xA9E8, + 0x2476, 0xA9E9, 0x2477, 0xA9EA, 0x2478, 0xA9EB, 0x2479, 0xA9EC, + 0x247A, 0xA9ED, 0x247B, 0xA9EE, 0x247C, 0xA9EF, 0x247D, 0xA9F0, + 0x247E, 0xA9F1, 0x247F, 0xA9F2, 0x2480, 0xA9F3, 0x2481, 0xA9F4, + 0x2482, 0xA9F5, 0x249C, 0xA9CD, 0x249D, 0xA9CE, 0x249E, 0xA9CF, + 0x249F, 0xA9D0, 0x24A0, 0xA9D1, 0x24A1, 0xA9D2, 0x24A2, 0xA9D3, + 0x24A3, 0xA9D4, 0x24A4, 0xA9D5, 0x24A5, 0xA9D6, 0x24A6, 0xA9D7, + 0x24A7, 0xA9D8, 0x24A8, 0xA9D9, 0x24A9, 0xA9DA, 0x24AA, 0xA9DB, + 0x24AB, 0xA9DC, 0x24AC, 0xA9DD, 0x24AD, 0xA9DE, 0x24AE, 0xA9DF, + 0x24AF, 0xA9E0, 0x24B0, 0xA9E1, 0x24B1, 0xA9E2, 0x24B2, 0xA9E3, + 0x24B3, 0xA9E4, 0x24B4, 0xA9E5, 0x24B5, 0xA9E6, 0x24D0, 0xA8CD, + 0x24D1, 0xA8CE, 0x24D2, 0xA8CF, 0x24D3, 0xA8D0, 0x24D4, 0xA8D1, + 0x24D5, 0xA8D2, 0x24D6, 0xA8D3, 0x24D7, 0xA8D4, 0x24D8, 0xA8D5, + 0x24D9, 0xA8D6, 0x24DA, 0xA8D7, 0x24DB, 0xA8D8, 0x24DC, 0xA8D9, + 0x24DD, 0xA8DA, 0x24DE, 0xA8DB, 0x24DF, 0xA8DC, 0x24E0, 0xA8DD, + 0x24E1, 0xA8DE, 0x24E2, 0xA8DF, 0x24E3, 0xA8E0, 0x24E4, 0xA8E1, + 0x24E5, 0xA8E2, 0x24E6, 0xA8E3, 0x24E7, 0xA8E4, 0x24E8, 0xA8E5, + 0x24E9, 0xA8E6, 0x2500, 0xA6A1, 0x2501, 0xA6AC, 0x2502, 0xA6A2, + 0x2503, 0xA6AD, 0x250C, 0xA6A3, 0x250D, 0xA6C8, 0x250E, 0xA6C7, + 0x250F, 0xA6AE, 0x2510, 0xA6A4, 0x2511, 0xA6C2, 0x2512, 0xA6C1, + 0x2513, 0xA6AF, 0x2514, 0xA6A6, 0x2515, 0xA6C6, 0x2516, 0xA6C5, + 0x2517, 0xA6B1, 0x2518, 0xA6A5, 0x2519, 0xA6C4, 0x251A, 0xA6C3, + 0x251B, 0xA6B0, 0x251C, 0xA6A7, 0x251D, 0xA6BC, 0x251E, 0xA6C9, + 0x251F, 0xA6CA, 0x2520, 0xA6B7, 0x2521, 0xA6CB, 0x2522, 0xA6CC, + 0x2523, 0xA6B2, 0x2524, 0xA6A9, 0x2525, 0xA6BE, 0x2526, 0xA6CD, + 0x2527, 0xA6CE, 0x2528, 0xA6B9, 0x2529, 0xA6CF, 0x252A, 0xA6D0, + 0x252B, 0xA6B4, 0x252C, 0xA6A8, 0x252D, 0xA6D1, 0x252E, 0xA6D2, + 0x252F, 0xA6B8, 0x2530, 0xA6BD, 0x2531, 0xA6D3, 0x2532, 0xA6D4, + 0x2533, 0xA6B3, 0x2534, 0xA6AA, 0x2535, 0xA6D5, 0x2536, 0xA6D6, + 0x2537, 0xA6BA, 0x2538, 0xA6BF, 0x2539, 0xA6D7, 0x253A, 0xA6D8, + 0x253B, 0xA6B5, 0x253C, 0xA6AB, 0x253D, 0xA6D9, 0x253E, 0xA6DA, + 0x253F, 0xA6BB, 0x2540, 0xA6DB, 0x2541, 0xA6DC, 0x2542, 0xA6C0, + 0x2543, 0xA6DD, 0x2544, 0xA6DE, 0x2545, 0xA6DF, 0x2546, 0xA6E0, + 0x2547, 0xA6E1, 0x2548, 0xA6E2, 0x2549, 0xA6E3, 0x254A, 0xA6E4, + 0x254B, 0xA6B6, 0x2592, 0xA2C6, 0x25A0, 0xA1E1, 0x25A1, 0xA1E0, + 0x25A3, 0xA2C3, 0x25A4, 0xA2C7, 0x25A5, 0xA2C8, 0x25A6, 0xA2CB, + 0x25A7, 0xA2CA, 0x25A8, 0xA2C9, 0x25A9, 0xA2CC, 0x25B2, 0xA1E3, + 0x25B3, 0xA1E2, 0x25B6, 0xA2BA, 0x25B7, 0xA2B9, 0x25BC, 0xA1E5, + 0x25BD, 0xA1E4, 0x25C0, 0xA2B8, 0x25C1, 0xA2B7, 0x25C6, 0xA1DF, + 0x25C7, 0xA1DE, 0x25C8, 0xA2C2, 0x25CB, 0xA1DB, 0x25CE, 0xA1DD, + 0x25CF, 0xA1DC, 0x25D0, 0xA2C4, 0x25D1, 0xA2C5, 0x2605, 0xA1DA, + 0x2606, 0xA1D9, 0x260E, 0xA2CF, 0x260F, 0xA2CE, 0x261C, 0xA2D0, + 0x261E, 0xA2D1, 0x2640, 0xA1CF, 0x2642, 0xA1CE, 0x2660, 0xA2BC, + 0x2661, 0xA2BD, 0x2663, 0xA2C0, 0x2664, 0xA2BB, 0x2665, 0xA2BE, + 0x2667, 0xA2BF, 0x2668, 0xA2CD, 0x2669, 0xA2DB, 0x266A, 0xA2DC, + 0x266C, 0xA2DD, 0x266D, 0xA2DA, 0x3000, 0xA1A1, 0x3001, 0xA1A2, + 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3008, 0xA1B4, 0x3009, 0xA1B5, + 0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9, + 0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BC, 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0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595, + 0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597, + 0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A, + 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, + 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0, + 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, + 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646, + 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, + 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD, + 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, + 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652, + 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, + 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2, + 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, + 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC, + 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, + 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5, + 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, + 0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0, + 0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC, + 0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3, + 0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA, + 0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE, + 0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6, + 0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA, + 0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF, + 0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3, + 0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7, + 0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF, + 0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5, + 0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9, + 0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1, + 0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5, + 0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC, + 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8, + 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, + 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5, + 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, + 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD, + 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, + 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9, + 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, + 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA, + 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, + 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF, + 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, + 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6, + 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, + 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1, + 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, + 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF, + 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, + 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6, + 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, + 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6, + 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, + 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4, + 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, + 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9, + 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, + 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5, + 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, + 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA, + 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, + 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC, + 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, + 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA, + 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, + 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0, + 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, + 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE, + 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, + 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1, + 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, + 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7, + 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, + 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0, + 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, + 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, + 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, + 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, + 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, + 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, + 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, + 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, + 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, + 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, + 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, + 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, + 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, + 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, + 0, 0 +}; + +static +const WCHAR oem2uni[] = { +/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ + 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, + 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, + 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, + 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, + 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, + 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, + 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, + 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, + 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, + 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, + 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, + 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, + 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, + 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, + 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, + 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, + 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, + 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, + 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, + 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, + 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, + 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, + 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, + 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, + 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, + 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, + 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, + 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, + 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, + 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, + 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, + 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, + 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, + 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, + 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, + 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, + 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, + 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, + 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, + 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, + 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, + 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, + 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, + 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, + 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, + 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, + 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, + 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, + 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, + 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, + 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, + 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, + 0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F, + 0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43, + 0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B, + 0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F, + 0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55, + 0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A, + 0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E, + 0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 0xAD64, + 0x828B, 0xAD65, 0x828C, 0xAD66, 0x828D, 0xAD67, 0x828E, 0xAD68, + 0x828F, 0xAD69, 0x8290, 0xAD6A, 0x8291, 0xAD6B, 0x8292, 0xAD6E, + 0x8293, 0xAD6F, 0x8294, 0xAD71, 0x8295, 0xAD72, 0x8296, 0xAD77, + 0x8297, 0xAD78, 0x8298, 0xAD79, 0x8299, 0xAD7A, 0x829A, 0xAD7E, + 0x829B, 0xAD80, 0x829C, 0xAD83, 0x829D, 0xAD84, 0x829E, 0xAD85, + 0x829F, 0xAD86, 0x82A0, 0xAD87, 0x82A1, 0xAD8A, 0x82A2, 0xAD8B, + 0x82A3, 0xAD8D, 0x82A4, 0xAD8E, 0x82A5, 0xAD8F, 0x82A6, 0xAD91, + 0x82A7, 0xAD92, 0x82A8, 0xAD93, 0x82A9, 0xAD94, 0x82AA, 0xAD95, + 0x82AB, 0xAD96, 0x82AC, 0xAD97, 0x82AD, 0xAD98, 0x82AE, 0xAD99, + 0x82AF, 0xAD9A, 0x82B0, 0xAD9B, 0x82B1, 0xAD9E, 0x82B2, 0xAD9F, + 0x82B3, 0xADA0, 0x82B4, 0xADA1, 0x82B5, 0xADA2, 0x82B6, 0xADA3, + 0x82B7, 0xADA5, 0x82B8, 0xADA6, 0x82B9, 0xADA7, 0x82BA, 0xADA8, + 0x82BB, 0xADA9, 0x82BC, 0xADAA, 0x82BD, 0xADAB, 0x82BE, 0xADAC, + 0x82BF, 0xADAD, 0x82C0, 0xADAE, 0x82C1, 0xADAF, 0x82C2, 0xADB0, + 0x82C3, 0xADB1, 0x82C4, 0xADB2, 0x82C5, 0xADB3, 0x82C6, 0xADB4, + 0x82C7, 0xADB5, 0x82C8, 0xADB6, 0x82C9, 0xADB8, 0x82CA, 0xADB9, + 0x82CB, 0xADBA, 0x82CC, 0xADBB, 0x82CD, 0xADBC, 0x82CE, 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0xD0EB, 0xB58E, 0xD0EE, + 0xB58F, 0xD0F2, 0xB590, 0xD0F3, 0xB591, 0xD0F4, 0xB592, 0xD0F5, + 0xB593, 0xD0F6, 0xB594, 0xD0F7, 0xB595, 0xD0F9, 0xB596, 0xD0FA, + 0xB597, 0xD0FB, 0xB598, 0xD0FC, 0xB599, 0xD0FD, 0xB59A, 0xD0FE, + 0xB59B, 0xD0FF, 0xB59C, 0xD100, 0xB59D, 0xD101, 0xB59E, 0xD102, + 0xB59F, 0xD103, 0xB5A0, 0xD104, 0xB5A1, 0xB367, 0xB5A2, 0xB369, + 0xB5A3, 0xB36B, 0xB5A4, 0xB36E, 0xB5A5, 0xB370, 0xB5A6, 0xB371, + 0xB5A7, 0xB374, 0xB5A8, 0xB378, 0xB5A9, 0xB380, 0xB5AA, 0xB381, + 0xB5AB, 0xB383, 0xB5AC, 0xB384, 0xB5AD, 0xB385, 0xB5AE, 0xB38C, + 0xB5AF, 0xB390, 0xB5B0, 0xB394, 0xB5B1, 0xB3A0, 0xB5B2, 0xB3A1, + 0xB5B3, 0xB3A8, 0xB5B4, 0xB3AC, 0xB5B5, 0xB3C4, 0xB5B6, 0xB3C5, + 0xB5B7, 0xB3C8, 0xB5B8, 0xB3CB, 0xB5B9, 0xB3CC, 0xB5BA, 0xB3CE, + 0xB5BB, 0xB3D0, 0xB5BC, 0xB3D4, 0xB5BD, 0xB3D5, 0xB5BE, 0xB3D7, + 0xB5BF, 0xB3D9, 0xB5C0, 0xB3DB, 0xB5C1, 0xB3DD, 0xB5C2, 0xB3E0, + 0xB5C3, 0xB3E4, 0xB5C4, 0xB3E8, 0xB5C5, 0xB3FC, 0xB5C6, 0xB410, + 0xB5C7, 0xB418, 0xB5C8, 0xB41C, 0xB5C9, 0xB420, 0xB5CA, 0xB428, + 0xB5CB, 0xB429, 0xB5CC, 0xB42B, 0xB5CD, 0xB434, 0xB5CE, 0xB450, + 0xB5CF, 0xB451, 0xB5D0, 0xB454, 0xB5D1, 0xB458, 0xB5D2, 0xB460, + 0xB5D3, 0xB461, 0xB5D4, 0xB463, 0xB5D5, 0xB465, 0xB5D6, 0xB46C, + 0xB5D7, 0xB480, 0xB5D8, 0xB488, 0xB5D9, 0xB49D, 0xB5DA, 0xB4A4, + 0xB5DB, 0xB4A8, 0xB5DC, 0xB4AC, 0xB5DD, 0xB4B5, 0xB5DE, 0xB4B7, + 0xB5DF, 0xB4B9, 0xB5E0, 0xB4C0, 0xB5E1, 0xB4C4, 0xB5E2, 0xB4C8, + 0xB5E3, 0xB4D0, 0xB5E4, 0xB4D5, 0xB5E5, 0xB4DC, 0xB5E6, 0xB4DD, + 0xB5E7, 0xB4E0, 0xB5E8, 0xB4E3, 0xB5E9, 0xB4E4, 0xB5EA, 0xB4E6, + 0xB5EB, 0xB4EC, 0xB5EC, 0xB4ED, 0xB5ED, 0xB4EF, 0xB5EE, 0xB4F1, + 0xB5EF, 0xB4F8, 0xB5F0, 0xB514, 0xB5F1, 0xB515, 0xB5F2, 0xB518, + 0xB5F3, 0xB51B, 0xB5F4, 0xB51C, 0xB5F5, 0xB524, 0xB5F6, 0xB525, + 0xB5F7, 0xB527, 0xB5F8, 0xB528, 0xB5F9, 0xB529, 0xB5FA, 0xB52A, + 0xB5FB, 0xB530, 0xB5FC, 0xB531, 0xB5FD, 0xB534, 0xB5FE, 0xB538, + 0xB641, 0xD105, 0xB642, 0xD106, 0xB643, 0xD107, 0xB644, 0xD108, + 0xB645, 0xD109, 0xB646, 0xD10A, 0xB647, 0xD10B, 0xB648, 0xD10C, + 0xB649, 0xD10E, 0xB64A, 0xD10F, 0xB64B, 0xD110, 0xB64C, 0xD111, + 0xB64D, 0xD112, 0xB64E, 0xD113, 0xB64F, 0xD114, 0xB650, 0xD115, + 0xB651, 0xD116, 0xB652, 0xD117, 0xB653, 0xD118, 0xB654, 0xD119, + 0xB655, 0xD11A, 0xB656, 0xD11B, 0xB657, 0xD11C, 0xB658, 0xD11D, + 0xB659, 0xD11E, 0xB65A, 0xD11F, 0xB661, 0xD120, 0xB662, 0xD121, + 0xB663, 0xD122, 0xB664, 0xD123, 0xB665, 0xD124, 0xB666, 0xD125, + 0xB667, 0xD126, 0xB668, 0xD127, 0xB669, 0xD128, 0xB66A, 0xD129, + 0xB66B, 0xD12A, 0xB66C, 0xD12B, 0xB66D, 0xD12C, 0xB66E, 0xD12D, + 0xB66F, 0xD12E, 0xB670, 0xD12F, 0xB671, 0xD132, 0xB672, 0xD133, + 0xB673, 0xD135, 0xB674, 0xD136, 0xB675, 0xD137, 0xB676, 0xD139, + 0xB677, 0xD13B, 0xB678, 0xD13C, 0xB679, 0xD13D, 0xB67A, 0xD13E, + 0xB681, 0xD13F, 0xB682, 0xD142, 0xB683, 0xD146, 0xB684, 0xD147, + 0xB685, 0xD148, 0xB686, 0xD149, 0xB687, 0xD14A, 0xB688, 0xD14B, + 0xB689, 0xD14E, 0xB68A, 0xD14F, 0xB68B, 0xD151, 0xB68C, 0xD152, + 0xB68D, 0xD153, 0xB68E, 0xD155, 0xB68F, 0xD156, 0xB690, 0xD157, + 0xB691, 0xD158, 0xB692, 0xD159, 0xB693, 0xD15A, 0xB694, 0xD15B, + 0xB695, 0xD15E, 0xB696, 0xD160, 0xB697, 0xD162, 0xB698, 0xD163, + 0xB699, 0xD164, 0xB69A, 0xD165, 0xB69B, 0xD166, 0xB69C, 0xD167, + 0xB69D, 0xD169, 0xB69E, 0xD16A, 0xB69F, 0xD16B, 0xB6A0, 0xD16D, + 0xB6A1, 0xB540, 0xB6A2, 0xB541, 0xB6A3, 0xB543, 0xB6A4, 0xB544, + 0xB6A5, 0xB545, 0xB6A6, 0xB54B, 0xB6A7, 0xB54C, 0xB6A8, 0xB54D, + 0xB6A9, 0xB550, 0xB6AA, 0xB554, 0xB6AB, 0xB55C, 0xB6AC, 0xB55D, + 0xB6AD, 0xB55F, 0xB6AE, 0xB560, 0xB6AF, 0xB561, 0xB6B0, 0xB5A0, + 0xB6B1, 0xB5A1, 0xB6B2, 0xB5A4, 0xB6B3, 0xB5A8, 0xB6B4, 0xB5AA, + 0xB6B5, 0xB5AB, 0xB6B6, 0xB5B0, 0xB6B7, 0xB5B1, 0xB6B8, 0xB5B3, + 0xB6B9, 0xB5B4, 0xB6BA, 0xB5B5, 0xB6BB, 0xB5BB, 0xB6BC, 0xB5BC, + 0xB6BD, 0xB5BD, 0xB6BE, 0xB5C0, 0xB6BF, 0xB5C4, 0xB6C0, 0xB5CC, + 0xB6C1, 0xB5CD, 0xB6C2, 0xB5CF, 0xB6C3, 0xB5D0, 0xB6C4, 0xB5D1, + 0xB6C5, 0xB5D8, 0xB6C6, 0xB5EC, 0xB6C7, 0xB610, 0xB6C8, 0xB611, + 0xB6C9, 0xB614, 0xB6CA, 0xB618, 0xB6CB, 0xB625, 0xB6CC, 0xB62C, + 0xB6CD, 0xB634, 0xB6CE, 0xB648, 0xB6CF, 0xB664, 0xB6D0, 0xB668, + 0xB6D1, 0xB69C, 0xB6D2, 0xB69D, 0xB6D3, 0xB6A0, 0xB6D4, 0xB6A4, + 0xB6D5, 0xB6AB, 0xB6D6, 0xB6AC, 0xB6D7, 0xB6B1, 0xB6D8, 0xB6D4, + 0xB6D9, 0xB6F0, 0xB6DA, 0xB6F4, 0xB6DB, 0xB6F8, 0xB6DC, 0xB700, + 0xB6DD, 0xB701, 0xB6DE, 0xB705, 0xB6DF, 0xB728, 0xB6E0, 0xB729, + 0xB6E1, 0xB72C, 0xB6E2, 0xB72F, 0xB6E3, 0xB730, 0xB6E4, 0xB738, + 0xB6E5, 0xB739, 0xB6E6, 0xB73B, 0xB6E7, 0xB744, 0xB6E8, 0xB748, + 0xB6E9, 0xB74C, 0xB6EA, 0xB754, 0xB6EB, 0xB755, 0xB6EC, 0xB760, + 0xB6ED, 0xB764, 0xB6EE, 0xB768, 0xB6EF, 0xB770, 0xB6F0, 0xB771, + 0xB6F1, 0xB773, 0xB6F2, 0xB775, 0xB6F3, 0xB77C, 0xB6F4, 0xB77D, + 0xB6F5, 0xB780, 0xB6F6, 0xB784, 0xB6F7, 0xB78C, 0xB6F8, 0xB78D, + 0xB6F9, 0xB78F, 0xB6FA, 0xB790, 0xB6FB, 0xB791, 0xB6FC, 0xB792, + 0xB6FD, 0xB796, 0xB6FE, 0xB797, 0xB741, 0xD16E, 0xB742, 0xD16F, + 0xB743, 0xD170, 0xB744, 0xD171, 0xB745, 0xD172, 0xB746, 0xD173, + 0xB747, 0xD174, 0xB748, 0xD175, 0xB749, 0xD176, 0xB74A, 0xD177, + 0xB74B, 0xD178, 0xB74C, 0xD179, 0xB74D, 0xD17A, 0xB74E, 0xD17B, + 0xB74F, 0xD17D, 0xB750, 0xD17E, 0xB751, 0xD17F, 0xB752, 0xD180, + 0xB753, 0xD181, 0xB754, 0xD182, 0xB755, 0xD183, 0xB756, 0xD185, + 0xB757, 0xD186, 0xB758, 0xD187, 0xB759, 0xD189, 0xB75A, 0xD18A, + 0xB761, 0xD18B, 0xB762, 0xD18C, 0xB763, 0xD18D, 0xB764, 0xD18E, + 0xB765, 0xD18F, 0xB766, 0xD190, 0xB767, 0xD191, 0xB768, 0xD192, + 0xB769, 0xD193, 0xB76A, 0xD194, 0xB76B, 0xD195, 0xB76C, 0xD196, + 0xB76D, 0xD197, 0xB76E, 0xD198, 0xB76F, 0xD199, 0xB770, 0xD19A, + 0xB771, 0xD19B, 0xB772, 0xD19C, 0xB773, 0xD19D, 0xB774, 0xD19E, + 0xB775, 0xD19F, 0xB776, 0xD1A2, 0xB777, 0xD1A3, 0xB778, 0xD1A5, + 0xB779, 0xD1A6, 0xB77A, 0xD1A7, 0xB781, 0xD1A9, 0xB782, 0xD1AA, + 0xB783, 0xD1AB, 0xB784, 0xD1AC, 0xB785, 0xD1AD, 0xB786, 0xD1AE, + 0xB787, 0xD1AF, 0xB788, 0xD1B2, 0xB789, 0xD1B4, 0xB78A, 0xD1B6, + 0xB78B, 0xD1B7, 0xB78C, 0xD1B8, 0xB78D, 0xD1B9, 0xB78E, 0xD1BB, + 0xB78F, 0xD1BD, 0xB790, 0xD1BE, 0xB791, 0xD1BF, 0xB792, 0xD1C1, + 0xB793, 0xD1C2, 0xB794, 0xD1C3, 0xB795, 0xD1C4, 0xB796, 0xD1C5, + 0xB797, 0xD1C6, 0xB798, 0xD1C7, 0xB799, 0xD1C8, 0xB79A, 0xD1C9, + 0xB79B, 0xD1CA, 0xB79C, 0xD1CB, 0xB79D, 0xD1CC, 0xB79E, 0xD1CD, + 0xB79F, 0xD1CE, 0xB7A0, 0xD1CF, 0xB7A1, 0xB798, 0xB7A2, 0xB799, + 0xB7A3, 0xB79C, 0xB7A4, 0xB7A0, 0xB7A5, 0xB7A8, 0xB7A6, 0xB7A9, + 0xB7A7, 0xB7AB, 0xB7A8, 0xB7AC, 0xB7A9, 0xB7AD, 0xB7AA, 0xB7B4, + 0xB7AB, 0xB7B5, 0xB7AC, 0xB7B8, 0xB7AD, 0xB7C7, 0xB7AE, 0xB7C9, + 0xB7AF, 0xB7EC, 0xB7B0, 0xB7ED, 0xB7B1, 0xB7F0, 0xB7B2, 0xB7F4, + 0xB7B3, 0xB7FC, 0xB7B4, 0xB7FD, 0xB7B5, 0xB7FF, 0xB7B6, 0xB800, + 0xB7B7, 0xB801, 0xB7B8, 0xB807, 0xB7B9, 0xB808, 0xB7BA, 0xB809, + 0xB7BB, 0xB80C, 0xB7BC, 0xB810, 0xB7BD, 0xB818, 0xB7BE, 0xB819, + 0xB7BF, 0xB81B, 0xB7C0, 0xB81D, 0xB7C1, 0xB824, 0xB7C2, 0xB825, + 0xB7C3, 0xB828, 0xB7C4, 0xB82C, 0xB7C5, 0xB834, 0xB7C6, 0xB835, + 0xB7C7, 0xB837, 0xB7C8, 0xB838, 0xB7C9, 0xB839, 0xB7CA, 0xB840, + 0xB7CB, 0xB844, 0xB7CC, 0xB851, 0xB7CD, 0xB853, 0xB7CE, 0xB85C, + 0xB7CF, 0xB85D, 0xB7D0, 0xB860, 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0xF7E8, 0x5A46, 0xF7E9, 0x5DF4, 0xF7EA, 0x628A, + 0xF7EB, 0x64AD, 0xF7EC, 0x64FA, 0xF7ED, 0x6777, 0xF7EE, 0x6CE2, + 0xF7EF, 0x6D3E, 0xF7F0, 0x722C, 0xF7F1, 0x7436, 0xF7F2, 0x7834, + 0xF7F3, 0x7F77, 0xF7F4, 0x82AD, 0xF7F5, 0x8DDB, 0xF7F6, 0x9817, + 0xF7F7, 0x5224, 0xF7F8, 0x5742, 0xF7F9, 0x677F, 0xF7FA, 0x7248, + 0xF7FB, 0x74E3, 0xF7FC, 0x8CA9, 0xF7FD, 0x8FA6, 0xF7FE, 0x9211, + 0xF8A1, 0x962A, 0xF8A2, 0x516B, 0xF8A3, 0x53ED, 0xF8A4, 0x634C, + 0xF8A5, 0x4F69, 0xF8A6, 0x5504, 0xF8A7, 0x6096, 0xF8A8, 0x6557, + 0xF8A9, 0x6C9B, 0xF8AA, 0x6D7F, 0xF8AB, 0x724C, 0xF8AC, 0x72FD, + 0xF8AD, 0x7A17, 0xF8AE, 0x8987, 0xF8AF, 0x8C9D, 0xF8B0, 0x5F6D, + 0xF8B1, 0x6F8E, 0xF8B2, 0x70F9, 0xF8B3, 0x81A8, 0xF8B4, 0x610E, + 0xF8B5, 0x4FBF, 0xF8B6, 0x504F, 0xF8B7, 0x6241, 0xF8B8, 0x7247, + 0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D, + 0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A, + 0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55, + 0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2, + 0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D, + 0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305, + 0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA, + 0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B, + 0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1, + 0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE, + 0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2, + 0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA, + 0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4, + 0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07, + 0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153, + 0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2, + 0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7, + 0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F, + 0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8, + 0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2, + 0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642, + 0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC, + 0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46, + 0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C, + 0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F, + 0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455, + 0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050, + 0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78, + 0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2, + 0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57, + 0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55, + 0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650, + 0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD, + 0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A, + 0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266, + 0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408, + 0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4, + 0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09, + 0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052, + 0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86, + 0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A, + 0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5, + 0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A, + 0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977, + 0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3, + 0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED, + 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, + 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, + 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, + 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, + 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, + 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, + 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, + 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, + 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, + 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, + 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, + 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, + 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, + 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, + 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, + 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, + 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, + 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, + 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, + 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, + 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, + 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, + 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, + 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, + 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, + 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, + 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, + 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, + 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, + 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, + 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, + 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, + 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, + 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, + 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, + 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, + 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, + 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, + 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, + 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, + 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, + 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, + 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, + 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, + 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, + 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, + 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, + 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, + 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, + 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, + 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, + 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, + 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, + 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, + 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, + 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, + 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, + 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, + 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, + 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, + 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, + 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, + 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, + 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, + 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, + 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, + 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, + 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, + 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, + 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, + 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, + 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, + 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, + 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, + 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, + 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, + 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, + 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, + 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, + 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, + 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, + 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, + 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, + 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, + 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, + 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, + 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, + 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, + 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, + 0, 0 +}; + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (src < 0x80) { /* ASCII */ + c = src; + } else { + if (dir) { /* OEMCP to unicode */ + p = oem2uni; + hi = sizeof(oem2uni) / 4 - 1; + } else { /* Unicode to OEMCP */ + p = uni2oem; + hi = sizeof(uni2oem) / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (src == p[i * 2]) break; + if (src > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; + } + + return c; +} + + + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc950.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc950.c new file mode 100644 index 0000000..aa02a75 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/cc950.c @@ -0,0 +1,6829 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - OEM code bidirectional converter (C)ChaN, 2009 */ +/* */ +/* CP950 (Traditional Chinese Big5) */ +/*------------------------------------------------------------------------*/ + +#include "../ff.h" + + +#if !_USE_LFN || _CODE_PAGE != 950 +#error This file is not needed in current configuration. +#endif + + +static +const WCHAR uni2oem[] = { +/* Unicode - OEM, Unicode - OEM, Unicode - OEM, Unicode - OEM */ + 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, + 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, + 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, + 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, + 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, + 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, + 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, + 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, + 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, + 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, + 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, + 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, + 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, + 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, + 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, + 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, + 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, + 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, + 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, + 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, + 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, + 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, + 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, + 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, + 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, + 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, + 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, + 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, + 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, + 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, + 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, + 0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271, + 0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6, + 0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1, + 0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3, + 0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5, + 0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7, + 0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7, + 0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6, + 0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3, + 0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1, + 0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2, + 0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE, + 0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264, + 0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268, + 0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E, + 0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A, + 0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD, + 0x25A1, 0xA1BC, 0x25B2, 0xA1B6, 0x25B3, 0xA1B5, 0x25BC, 0xA1BF, + 0x25BD, 0xA1BE, 0x25C6, 0xA1BB, 0x25C7, 0xA1BA, 0x25CB, 0xA1B3, + 0x25CE, 0xA1B7, 0x25CF, 0xA1B4, 0x25E2, 0xA2A8, 0x25E3, 0xA2A9, + 0x25E4, 0xA2AB, 0x25E5, 0xA2AA, 0x2605, 0xA1B9, 0x2606, 0xA1B8, + 0x2640, 0xA1F0, 0x2642, 0xA1F1, 0x3000, 0xA140, 0x3001, 0xA142, + 0x3002, 0xA143, 0x3003, 0xA1B2, 0x3008, 0xA171, 0x3009, 0xA172, + 0x300A, 0xA16D, 0x300B, 0xA16E, 0x300C, 0xA175, 0x300D, 0xA176, + 0x300E, 0xA179, 0x300F, 0xA17A, 0x3010, 0xA169, 0x3011, 0xA16A, + 0x3012, 0xA245, 0x3014, 0xA165, 0x3015, 0xA166, 0x301D, 0xA1A9, + 0x301E, 0xA1AA, 0x3021, 0xA2C3, 0x3022, 0xA2C4, 0x3023, 0xA2C5, + 0x3024, 0xA2C6, 0x3025, 0xA2C7, 0x3026, 0xA2C8, 0x3027, 0xA2C9, + 0x3028, 0xA2CA, 0x3029, 0xA2CB, 0x3105, 0xA374, 0x3106, 0xA375, + 0x3107, 0xA376, 0x3108, 0xA377, 0x3109, 0xA378, 0x310A, 0xA379, + 0x310B, 0xA37A, 0x310C, 0xA37B, 0x310D, 0xA37C, 0x310E, 0xA37D, + 0x310F, 0xA37E, 0x3110, 0xA3A1, 0x3111, 0xA3A2, 0x3112, 0xA3A3, + 0x3113, 0xA3A4, 0x3114, 0xA3A5, 0x3115, 0xA3A6, 0x3116, 0xA3A7, + 0x3117, 0xA3A8, 0x3118, 0xA3A9, 0x3119, 0xA3AA, 0x311A, 0xA3AB, + 0x311B, 0xA3AC, 0x311C, 0xA3AD, 0x311D, 0xA3AE, 0x311E, 0xA3AF, + 0x311F, 0xA3B0, 0x3120, 0xA3B1, 0x3121, 0xA3B2, 0x3122, 0xA3B3, + 0x3123, 0xA3B4, 0x3124, 0xA3B5, 0x3125, 0xA3B6, 0x3126, 0xA3B7, + 0x3127, 0xA3B8, 0x3128, 0xA3B9, 0x3129, 0xA3BA, 0x32A3, 0xA1C0, + 0x338E, 0xA255, 0x338F, 0xA256, 0x339C, 0xA250, 0x339D, 0xA251, + 0x339E, 0xA252, 0x33A1, 0xA254, 0x33C4, 0xA257, 0x33CE, 0xA253, + 0x33D1, 0xA1EB, 0x33D2, 0xA1EA, 0x33D5, 0xA24F, 0x4E00, 0xA440, + 0x4E01, 0xA442, 0x4E03, 0xA443, 0x4E07, 0xC945, 0x4E08, 0xA456, + 0x4E09, 0xA454, 0x4E0A, 0xA457, 0x4E0B, 0xA455, 0x4E0C, 0xC946, + 0x4E0D, 0xA4A3, 0x4E0E, 0xC94F, 0x4E0F, 0xC94D, 0x4E10, 0xA4A2, + 0x4E11, 0xA4A1, 0x4E14, 0xA542, 0x4E15, 0xA541, 0x4E16, 0xA540, + 0x4E18, 0xA543, 0x4E19, 0xA4FE, 0x4E1E, 0xA5E0, 0x4E1F, 0xA5E1, + 0x4E26, 0xA8C3, 0x4E2B, 0xA458, 0x4E2D, 0xA4A4, 0x4E2E, 0xC950, + 0x4E30, 0xA4A5, 0x4E31, 0xC963, 0x4E32, 0xA6EA, 0x4E33, 0xCBB1, + 0x4E38, 0xA459, 0x4E39, 0xA4A6, 0x4E3B, 0xA544, 0x4E3C, 0xC964, + 0x4E42, 0xC940, 0x4E43, 0xA444, 0x4E45, 0xA45B, 0x4E47, 0xC947, + 0x4E48, 0xA45C, 0x4E4B, 0xA4A7, 0x4E4D, 0xA545, 0x4E4E, 0xA547, + 0x4E4F, 0xA546, 0x4E52, 0xA5E2, 0x4E53, 0xA5E3, 0x4E56, 0xA8C4, + 0x4E58, 0xADBC, 0x4E59, 0xA441, 0x4E5C, 0xC941, 0x4E5D, 0xA445, + 0x4E5E, 0xA45E, 0x4E5F, 0xA45D, 0x4E69, 0xA5E4, 0x4E73, 0xA8C5, + 0x4E7E, 0xB0AE, 0x4E7F, 0xD44B, 0x4E82, 0xB6C3, 0x4E83, 0xDCB1, + 0x4E84, 0xDCB2, 0x4E86, 0xA446, 0x4E88, 0xA4A9, 0x4E8B, 0xA8C6, + 0x4E8C, 0xA447, 0x4E8D, 0xC948, 0x4E8E, 0xA45F, 0x4E91, 0xA4AA, + 0x4E92, 0xA4AC, 0x4E93, 0xC951, 0x4E94, 0xA4AD, 0x4E95, 0xA4AB, + 0x4E99, 0xA5E5, 0x4E9B, 0xA8C7, 0x4E9E, 0xA8C8, 0x4E9F, 0xAB45, + 0x4EA1, 0xA460, 0x4EA2, 0xA4AE, 0x4EA4, 0xA5E6, 0x4EA5, 0xA5E8, + 0x4EA6, 0xA5E7, 0x4EA8, 0xA6EB, 0x4EAB, 0xA8C9, 0x4EAC, 0xA8CA, + 0x4EAD, 0xAB46, 0x4EAE, 0xAB47, 0x4EB3, 0xADBD, 0x4EB6, 0xDCB3, + 0x4EB9, 0xF6D6, 0x4EBA, 0xA448, 0x4EC0, 0xA4B0, 0x4EC1, 0xA4AF, + 0x4EC2, 0xC952, 0x4EC3, 0xA4B1, 0x4EC4, 0xA4B7, 0x4EC6, 0xA4B2, + 0x4EC7, 0xA4B3, 0x4EC8, 0xC954, 0x4EC9, 0xC953, 0x4ECA, 0xA4B5, + 0x4ECB, 0xA4B6, 0x4ECD, 0xA4B4, 0x4ED4, 0xA54A, 0x4ED5, 0xA54B, + 0x4ED6, 0xA54C, 0x4ED7, 0xA54D, 0x4ED8, 0xA549, 0x4ED9, 0xA550, + 0x4EDA, 0xC96A, 0x4EDC, 0xC966, 0x4EDD, 0xC969, 0x4EDE, 0xA551, + 0x4EDF, 0xA561, 0x4EE1, 0xC968, 0x4EE3, 0xA54E, 0x4EE4, 0xA54F, + 0x4EE5, 0xA548, 0x4EE8, 0xC965, 0x4EE9, 0xC967, 0x4EF0, 0xA5F5, + 0x4EF1, 0xC9B0, 0x4EF2, 0xA5F2, 0x4EF3, 0xA5F6, 0x4EF4, 0xC9BA, + 0x4EF5, 0xC9AE, 0x4EF6, 0xA5F3, 0x4EF7, 0xC9B2, 0x4EFB, 0xA5F4, + 0x4EFD, 0xA5F7, 0x4EFF, 0xA5E9, 0x4F00, 0xC9B1, 0x4F01, 0xA5F8, + 0x4F02, 0xC9B5, 0x4F04, 0xC9B9, 0x4F05, 0xC9B6, 0x4F08, 0xC9B3, + 0x4F09, 0xA5EA, 0x4F0A, 0xA5EC, 0x4F0B, 0xA5F9, 0x4F0D, 0xA5EE, + 0x4F0E, 0xC9AB, 0x4F0F, 0xA5F1, 0x4F10, 0xA5EF, 0x4F11, 0xA5F0, + 0x4F12, 0xC9BB, 0x4F13, 0xC9B8, 0x4F14, 0xC9AF, 0x4F15, 0xA5ED, + 0x4F18, 0xC9AC, 0x4F19, 0xA5EB, 0x4F1D, 0xC9B4, 0x4F22, 0xC9B7, + 0x4F2C, 0xC9AD, 0x4F2D, 0xCA66, 0x4F2F, 0xA742, 0x4F30, 0xA6F4, + 0x4F33, 0xCA67, 0x4F34, 0xA6F1, 0x4F36, 0xA744, 0x4F38, 0xA6F9, + 0x4F3A, 0xA6F8, 0x4F3B, 0xCA5B, 0x4F3C, 0xA6FC, 0x4F3D, 0xA6F7, + 0x4F3E, 0xCA60, 0x4F3F, 0xCA68, 0x4F41, 0xCA64, 0x4F43, 0xA6FA, + 0x4F46, 0xA6FD, 0x4F47, 0xA6EE, 0x4F48, 0xA747, 0x4F49, 0xCA5D, + 0x4F4C, 0xCBBD, 0x4F4D, 0xA6EC, 0x4F4E, 0xA743, 0x4F4F, 0xA6ED, + 0x4F50, 0xA6F5, 0x4F51, 0xA6F6, 0x4F52, 0xCA62, 0x4F53, 0xCA5E, + 0x4F54, 0xA6FB, 0x4F55, 0xA6F3, 0x4F56, 0xCA5A, 0x4F57, 0xA6EF, + 0x4F58, 0xCA65, 0x4F59, 0xA745, 0x4F5A, 0xA748, 0x4F5B, 0xA6F2, + 0x4F5C, 0xA740, 0x4F5D, 0xA746, 0x4F5E, 0xA6F0, 0x4F5F, 0xCA63, + 0x4F60, 0xA741, 0x4F61, 0xCA69, 0x4F62, 0xCA5C, 0x4F63, 0xA6FE, + 0x4F64, 0xCA5F, 0x4F67, 0xCA61, 0x4F69, 0xA8D8, 0x4F6A, 0xCBBF, + 0x4F6B, 0xCBCB, 0x4F6C, 0xA8D0, 0x4F6E, 0xCBCC, 0x4F6F, 0xA8CB, + 0x4F70, 0xA8D5, 0x4F73, 0xA8CE, 0x4F74, 0xCBB9, 0x4F75, 0xA8D6, + 0x4F76, 0xCBB8, 0x4F77, 0xCBBC, 0x4F78, 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0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, + 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, + 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, + 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, + 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, + 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, + 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, + 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, + 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, + 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, + 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, + 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, + 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, + 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, + 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, + 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, + 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, + 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, + 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, + 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, + 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, + 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, + 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, + 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, + 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, + 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, + 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, + 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, + 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, + 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, + 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, + 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, + 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, + 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, + 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, + 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, + 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, + 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, + 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, + 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, + 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, + 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, + 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, + 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, + 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, + 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, + 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, + 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, + 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, + 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, + 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, + 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, + 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, + 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, + 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, + 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, + 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, + 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, + 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, + 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, + 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 +}; + +static +const WCHAR oem2uni[] = { +/* OEM - Unicode, OEM - Unicode, OEM - Unicode, OEM - Unicode */ + 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, + 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, + 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, + 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, + 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, + 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, + 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, + 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, + 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, + 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, + 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, + 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, + 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, + 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, + 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, + 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, + 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, + 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, + 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, + 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, + 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, + 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, + 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, + 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, + 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, + 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, + 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, + 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, + 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, + 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, + 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, + 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, + 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, + 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, + 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, + 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, + 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, + 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, + 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, + 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, + 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, + 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, + 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, + 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, + 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, + 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, + 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, + 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, + 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, + 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, + 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, + 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, + 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, + 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C, + 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, + 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550, + 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, + 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571, + 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, + 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15, + 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, + 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163, + 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, + 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022, + 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, + 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341, + 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, + 0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26, + 0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A, + 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E, + 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, + 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36, + 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, + 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44, + 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, + 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C, + 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, + 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54, + 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, + 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392, + 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, + 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A, + 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, + 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3, + 0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7, + 0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2, + 0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6, + 0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA, + 0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE, + 0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3, + 0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7, + 0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106, + 0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A, + 0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E, + 0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112, + 0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116, + 0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A, + 0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E, + 0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122, + 0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126, + 0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9, + 0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB, + 0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01, + 0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86, + 0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165, + 0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201, + 0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C, + 0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08, + 0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1, + 0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E, + 0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203, + 0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3, + 0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927, + 0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 0x5B51, 0xA46E, 0x5B53, + 0xA46F, 0x5BF8, 0xA470, 0x5C0F, 0xA471, 0x5C22, 0xA472, 0x5C38, + 0xA473, 0x5C71, 0xA474, 0x5DDD, 0xA475, 0x5DE5, 0xA476, 0x5DF1, + 0xA477, 0x5DF2, 0xA478, 0x5DF3, 0xA479, 0x5DFE, 0xA47A, 0x5E72, + 0xA47B, 0x5EFE, 0xA47C, 0x5F0B, 0xA47D, 0x5F13, 0xA47E, 0x624D, + 0xA4A1, 0x4E11, 0xA4A2, 0x4E10, 0xA4A3, 0x4E0D, 0xA4A4, 0x4E2D, + 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0xF6A2, 0x9ACD, + 0xF6A3, 0x9B15, 0xF6A4, 0x9B17, 0xF6A5, 0x9B18, 0xF6A6, 0x9B16, + 0xF6A7, 0x9B3A, 0xF6A8, 0x9B52, 0xF6A9, 0x9C2B, 0xF6AA, 0x9C1D, + 0xF6AB, 0x9C1C, 0xF6AC, 0x9C2C, 0xF6AD, 0x9C23, 0xF6AE, 0x9C28, + 0xF6AF, 0x9C29, 0xF6B0, 0x9C24, 0xF6B1, 0x9C21, 0xF6B2, 0x9DB7, + 0xF6B3, 0x9DB6, 0xF6B4, 0x9DBC, 0xF6B5, 0x9DC1, 0xF6B6, 0x9DC7, + 0xF6B7, 0x9DCA, 0xF6B8, 0x9DCF, 0xF6B9, 0x9DBE, 0xF6BA, 0x9DC5, + 0xF6BB, 0x9DC3, 0xF6BC, 0x9DBB, 0xF6BD, 0x9DB5, 0xF6BE, 0x9DCE, + 0xF6BF, 0x9DB9, 0xF6C0, 0x9DBA, 0xF6C1, 0x9DAC, 0xF6C2, 0x9DC8, + 0xF6C3, 0x9DB1, 0xF6C4, 0x9DAD, 0xF6C5, 0x9DCC, 0xF6C6, 0x9DB3, + 0xF6C7, 0x9DCD, 0xF6C8, 0x9DB2, 0xF6C9, 0x9E7A, 0xF6CA, 0x9E9C, + 0xF6CB, 0x9EEB, 0xF6CC, 0x9EEE, 0xF6CD, 0x9EED, 0xF6CE, 0x9F1B, + 0xF6CF, 0x9F18, 0xF6D0, 0x9F1A, 0xF6D1, 0x9F31, 0xF6D2, 0x9F4E, + 0xF6D3, 0x9F65, 0xF6D4, 0x9F64, 0xF6D5, 0x9F92, 0xF6D6, 0x4EB9, + 0xF6D7, 0x56C6, 0xF6D8, 0x56C5, 0xF6D9, 0x56CB, 0xF6DA, 0x5971, + 0xF6DB, 0x5B4B, 0xF6DC, 0x5B4C, 0xF6DD, 0x5DD5, 0xF6DE, 0x5DD1, + 0xF6DF, 0x5EF2, 0xF6E0, 0x6521, 0xF6E1, 0x6520, 0xF6E2, 0x6526, + 0xF6E3, 0x6522, 0xF6E4, 0x6B0B, 0xF6E5, 0x6B08, 0xF6E6, 0x6B09, + 0xF6E7, 0x6C0D, 0xF6E8, 0x7055, 0xF6E9, 0x7056, 0xF6EA, 0x7057, + 0xF6EB, 0x7052, 0xF6EC, 0x721E, 0xF6ED, 0x721F, 0xF6EE, 0x72A9, + 0xF6EF, 0x737F, 0xF6F0, 0x74D8, 0xF6F1, 0x74D5, 0xF6F2, 0x74D9, + 0xF6F3, 0x74D7, 0xF6F4, 0x766D, 0xF6F5, 0x76AD, 0xF6F6, 0x7935, + 0xF6F7, 0x79B4, 0xF6F8, 0x7A70, 0xF6F9, 0x7A71, 0xF6FA, 0x7C57, + 0xF6FB, 0x7C5C, 0xF6FC, 0x7C59, 0xF6FD, 0x7C5B, 0xF6FE, 0x7C5A, + 0xF740, 0x7CF4, 0xF741, 0x7CF1, 0xF742, 0x7E91, 0xF743, 0x7F4F, + 0xF744, 0x7F87, 0xF745, 0x81DE, 0xF746, 0x826B, 0xF747, 0x8634, + 0xF748, 0x8635, 0xF749, 0x8633, 0xF74A, 0x862C, 0xF74B, 0x8632, + 0xF74C, 0x8636, 0xF74D, 0x882C, 0xF74E, 0x8828, 0xF74F, 0x8826, + 0xF750, 0x882A, 0xF751, 0x8825, 0xF752, 0x8971, 0xF753, 0x89BF, + 0xF754, 0x89BE, 0xF755, 0x89FB, 0xF756, 0x8B7E, 0xF757, 0x8B84, + 0xF758, 0x8B82, 0xF759, 0x8B86, 0xF75A, 0x8B85, 0xF75B, 0x8B7F, + 0xF75C, 0x8D15, 0xF75D, 0x8E95, 0xF75E, 0x8E94, 0xF75F, 0x8E9A, + 0xF760, 0x8E92, 0xF761, 0x8E90, 0xF762, 0x8E96, 0xF763, 0x8E97, + 0xF764, 0x8F60, 0xF765, 0x8F62, 0xF766, 0x9147, 0xF767, 0x944C, + 0xF768, 0x9450, 0xF769, 0x944A, 0xF76A, 0x944B, 0xF76B, 0x944F, + 0xF76C, 0x9447, 0xF76D, 0x9445, 0xF76E, 0x9448, 0xF76F, 0x9449, + 0xF770, 0x9446, 0xF771, 0x973F, 0xF772, 0x97E3, 0xF773, 0x986A, + 0xF774, 0x9869, 0xF775, 0x98CB, 0xF776, 0x9954, 0xF777, 0x995B, + 0xF778, 0x9A4E, 0xF779, 0x9A53, 0xF77A, 0x9A54, 0xF77B, 0x9A4C, + 0xF77C, 0x9A4F, 0xF77D, 0x9A48, 0xF77E, 0x9A4A, 0xF7A1, 0x9A49, + 0xF7A2, 0x9A52, 0xF7A3, 0x9A50, 0xF7A4, 0x9AD0, 0xF7A5, 0x9B19, + 0xF7A6, 0x9B2B, 0xF7A7, 0x9B3B, 0xF7A8, 0x9B56, 0xF7A9, 0x9B55, + 0xF7AA, 0x9C46, 0xF7AB, 0x9C48, 0xF7AC, 0x9C3F, 0xF7AD, 0x9C44, + 0xF7AE, 0x9C39, 0xF7AF, 0x9C33, 0xF7B0, 0x9C41, 0xF7B1, 0x9C3C, + 0xF7B2, 0x9C37, 0xF7B3, 0x9C34, 0xF7B4, 0x9C32, 0xF7B5, 0x9C3D, + 0xF7B6, 0x9C36, 0xF7B7, 0x9DDB, 0xF7B8, 0x9DD2, 0xF7B9, 0x9DDE, + 0xF7BA, 0x9DDA, 0xF7BB, 0x9DCB, 0xF7BC, 0x9DD0, 0xF7BD, 0x9DDC, + 0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9, + 0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5, + 0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35, + 0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B, + 0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299, + 0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D, + 0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201, + 0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525, + 0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12, + 0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A, + 0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383, + 0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66, + 0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640, + 0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B, + 0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E, + 0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973, + 0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B, + 0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98, + 0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462, + 0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E, + 0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56, + 0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20, + 0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A, + 0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59, + 0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7, + 0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8, + 0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE, + 0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, + 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8, + 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, + 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38, + 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, + 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F, + 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, + 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13, + 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, + 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5, + 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, + 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643, + 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, + 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, + 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, + 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, + 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, + 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, + 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, + 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, + 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, + 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, + 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, + 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, + 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, + 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, + 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, + 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, + 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, + 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, + 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, + 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, + 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, + 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, + 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, + 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, + 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, + 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, + 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, + 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, + 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, + 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, + 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, + 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, + 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, + 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, + 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, + 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, + 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, + 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, + 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, + 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, + 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, + 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, + 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, + 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, + 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, + 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, + 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, + 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, + 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, + 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, + 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, + 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, + 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, + 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, + 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, + 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 +}; + + + +WCHAR ff_convert ( /* Converted code, 0 means conversion error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + const WCHAR *p; + WCHAR c; + int i, n, li, hi; + + + if (src < 0x80) { /* ASCII */ + c = src; + } else { + if (dir) { /* OEMCP to unicode */ + p = oem2uni; + hi = sizeof(oem2uni) / 4 - 1; + } else { /* Unicode to OEMCP */ + p = uni2oem; + hi = sizeof(uni2oem) / 4 - 1; + } + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (src == p[i * 2]) break; + if (src > p[i * 2]) + li = i; + else + hi = i; + } + c = n ? p[i * 2 + 1] : 0; + } + + return c; +} + + + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/ccsbcs.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/ccsbcs.c new file mode 100644 index 0000000..359755a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/ccsbcs.c @@ -0,0 +1,540 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. (OEM) +/ 720 Arabic (OEM) +/ 1256 Arabic (Windows) +/ 737 Greek (OEM) +/ 1253 Greek (Windows) +/ 1250 Central Europe (Windows) +/ 775 Baltic (OEM) +/ 1257 Baltic (Windows) +/ 850 Multilingual Latin 1 (OEM) +/ 852 Latin 2 (OEM) +/ 1252 Latin 1 (Windows) +/ 855 Cyrillic (OEM) +/ 1251 Cyrillic (Windows) +/ 866 Russian (OEM) +/ 857 Turkish (OEM) +/ 1254 Turkish (Windows) +/ 858 Multilingual Latin 1 + Euro (OEM) +/ 862 Hebrew (OEM) +/ 1255 Hebrew (Windows) +/ 874 Thai (OEM, Windows) +/ 1258 Vietnam (OEM, Windows) +*/ + +#include "../ff.h" + + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, + 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, + 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, + 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, + 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, + 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, + 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, + 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, + 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, + 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, + 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, + 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, + 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, + 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, + 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, + 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, + 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, + 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, + 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, + 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, + 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, + 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, + 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, + 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, + 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, + 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 858 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 874 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, + 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, + 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, + 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, + 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, + 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, + 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, + 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, + 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, + 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, + 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, + 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +#elif _CODE_PAGE == 1250 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, + 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, + 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, + 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, + 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, + 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, + 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, + 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, + 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, + 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, + 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 +}; + +#elif _CODE_PAGE == 1251 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ + 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, + 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, + 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, + 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, + 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, + 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, + 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042D, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F +}; + +#elif _CODE_PAGE == 1252 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x00DD, 0x00DE, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF +}; + +#elif _CODE_PAGE == 1253 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, + 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, + 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, + 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, + 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, + 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, + 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, + 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 +}; + +#elif _CODE_PAGE == 1254 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF +}; + +#elif _CODE_PAGE == 1255 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, + 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, + 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 +}; + +#elif _CODE_PAGE == 1256 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, + 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, + 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, + 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, + 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, + 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, + 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, + 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 +} + +#elif _CODE_PAGE == 1257 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, + 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, + 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, + 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, + 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, + 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, + 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, + 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, + 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, + 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, + 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 +}; + +#elif _CODE_PAGE == 1258 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, + 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, + 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed in current configuration +#endif + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (src < 0x80) { /* ASCII */ + c = src; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (src >= 0x100) ? 0 : Tbl[src - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (src == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/syncobj.c b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/syncobj.c new file mode 100644 index 0000000..6d8ad28 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/FileSystem/FatFs-0.7e/src/option/syncobj.c @@ -0,0 +1,111 @@ +/*------------------------------------------------------------------------*/ +/* Sample code of OS dependent synchronization object controls */ +/* for FatFs R0.07d (C)ChaN, 2009 */ +/*------------------------------------------------------------------------*/ + +#include +#include + +#include "../ff.h" + +#if _FS_REENTRANT + +/*------------------------------------------------------------------------*/ +/* Create a Synchronization Object for a Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount function to create a new +/ synchronization object, such as semaphore and mutex. When a FALSE is +/ returned, the f_mount function fails with FR_INT_ERR. +*/ + +BOOL ff_cre_syncobj ( /* TRUE:Function succeeded, FALSE:Could not create due to any error */ + BYTE vol, /* Corresponding logical drive being processed */ + _SYNC_t *sobj /* Pointer to return the created sync object */ +) +{ + BOOL ret; + + *sobj = xSemaphoreCreateMutex(); + + if( *sobj == NULL ) + { + ret = FALSE; + } + else + { + ret = TRUE; + } + + return ret; +} + + + +/*------------------------------------------------------------------------*/ +/* Delete a Synchronization Object */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount function to delete a synchronization +/ object that created with ff_cre_syncobj function. When a FALSE is +/ returned, the f_mount function fails with FR_INT_ERR. +*/ + +BOOL ff_del_syncobj ( /* TRUE:Function succeeded, FALSE:Could not delete due to any error */ + _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ +) +{ + BOOL ret; + + if( sobj != NULL ) + { + vQueueDelete( sobj ); + ret = TRUE; + } + else + { + ret = FALSE; + } + + return ret; +} + + + +/*------------------------------------------------------------------------*/ +/* Request Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on entering file functions to lock the volume. +/ When a FALSE is returned, the file function fails with FR_TIMEOUT. +*/ + +BOOL ff_req_grant ( /* TRUE:Got a grant to access the volume, FALSE:Could not get a grant */ + _SYNC_t sobj /* Sync object to wait */ +) +{ + BOOL ret; + + ret = xSemaphoreTake( sobj, _FS_TIMEOUT ); + + return ret; +} + + + +/*------------------------------------------------------------------------*/ +/* Release Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on leaving file functions to unlock the volume. +*/ + +void ff_rel_grant ( + _SYNC_t sobj /* Sync object to be signaled */ +) +{ + xSemaphoreGive( sobj ); +} + + +#else + +#error This file is not needed in this configuration. + +#endif diff --git a/third_party/FreeRTOS/Demo/Common/Full/BlockQ.c b/third_party/FreeRTOS/Demo/Common/Full/BlockQ.c new file mode 100644 index 0000000..89119ea --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/BlockQ.c @@ -0,0 +1,346 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + * \page BlockQC blockQ.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + Reversed the priority and block times of the second two demo tasks so + they operate as per the description above. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. + +Changes from V4.0.2 + + + The second set of tasks were created the wrong way around. This has been + corrected. +*/ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" +#include "print.h" + +#define blckqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE ) +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile short *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static void vBlockingQueueProducer( void *pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static void vBlockingQueueConsumer( void *pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueProducer( void *pvParameters ) +{ +unsigned short usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +const char * const pcTaskStartMsg = "Blocking queue producer started.\r\n"; +const char * const pcTaskErrorMsg = "Could not post on blocking queue\r\n"; +short sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueConsumer( void *pvParameters ) +{ +unsigned short usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +const char * const pcTaskStartMsg = "Blocking queue consumer started.\r\n"; +const char * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n"; +short sErrorEverOccurred = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ +static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; +static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Full/PollQ.c b/third_party/FreeRTOS/Demo/Common/Full/PollQ.c new file mode 100644 index 0000000..47dc140 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/PollQ.c @@ -0,0 +1,258 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/** + * This is a very simple queue test. See the BlockQ. c documentation for a more + * comprehensive version. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + * + * \page PollQC pollQ.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "print.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE ) + +/* The task that posts the incrementing number onto the queue. */ +static void vPolledQueueProducer( void *pvParameters ); + +/* The task that empties the queue. */ +static void vPolledQueueConsumer( void *pvParameters ); + +/* Variables that are used to check that the tasks are still running with no errors. */ +static volatile short sPollingConsumerCount = 0, sPollingProducerCount = 0; +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; +const unsigned portBASE_TYPE uxQueueSize = 10; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); + xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueProducer( void *pvParameters ) +{ +unsigned short usValue = 0, usLoop; +xQueueHandle *pxQueue; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; +const unsigned short usNumToProduce = 3; +const char * const pcTaskStartMsg = "Polled queue producer started.\r\n"; +const char * const pcTaskErrorMsg = "Could not post on polled queue.\r\n"; +short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + for( usLoop = 0; usLoop < usNumToProduce; ++usLoop ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( portTickType ) 0 ) != pdPASS ) + { + /* We should never find the queue full - this is an error. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + } + else + { + if( sError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + ++sPollingProducerCount; + } + + /* Update the value we are going to post next time around. */ + ++usValue; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueConsumer( void *pvParameters ) +{ +unsigned short usData, usExpectedValue = 0; +xQueueHandle *pxQueue; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; +const char * const pcTaskStartMsg = "Polled queue consumer started.\r\n"; +const char * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n"; +short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *pxQueue ) ) + { + if( xQueueReceive( *pxQueue, &usData, ( portTickType ) 0 ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + /* Catch-up to the value we received so our next expected value + should again be correct. */ + usExpectedValue = usData; + } + else + { + if( sError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + ++sPollingConsumerCount; + } + } + ++usExpectedValue; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ +static short sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0; +portBASE_TYPE xReturn; + + if( ( sLastPollingConsumerCount == sPollingConsumerCount ) || + ( sLastPollingProducerCount == sPollingProducerCount ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastPollingConsumerCount = sPollingConsumerCount; + sLastPollingProducerCount = sPollingProducerCount; + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Full/comtest.c b/third_party/FreeRTOS/Demo/Common/Full/comtest.c new file mode 100644 index 0000000..dfd3459 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/comtest.c @@ -0,0 +1,384 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Creates two tasks that operate on an interrupt driven serial port. A loopback + * connector should be used so that everything that is transmitted is also received. + * The serial port does not use any flow control. On a standard 9way 'D' connector + * pins two and three should be connected together. + * + * The first task repeatedly sends a string to a queue, character at a time. The + * serial port interrupt will empty the queue and transmit the characters. The + * task blocks for a pseudo random period before resending the string. + * + * The second task blocks on a queue waiting for a character to be received. + * Characters received by the serial port interrupt routine are posted onto the + * queue - unblocking the task making it ready to execute. If this is then the + * highest priority task ready to run it will run immediately - with a context + * switch occurring at the end of the interrupt service routine. The task + * receiving characters is spawned with a higher priority than the task + * transmitting the characters. + * + * With the loop back connector in place, one task will transmit a string and the + * other will immediately receive it. The receiving task knows the string it + * expects to receive so can detect an error. + * + * This also creates a third task. This is used to test semaphore usage from an + * ISR and does nothing interesting. + * + * \page ComTestC comtest.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + The priority of the Rx task has been lowered. Received characters are + now processed (read from the queue) at the idle priority, allowing low + priority tasks to run evenly at times of a high communications overhead. + +Changes from V1.01: + + + The Tx task now waits a pseudo random time between transissions. + Previously a fixed period was used but this was not such a good test as + interrupts fired at regular intervals. + +Changes From V1.2.0: + + + Use vSerialPutString() instead of single character puts. + + Only stop the check variable incrementing after two consecutive errors. + +Changed from V1.2.5 + + + Made the Rx task 2 priorities higher than the Tx task. Previously it was + only 1. This is done to tie in better with the other demo application + tasks. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. + + Slight modification to task priorities. + +*/ + + +/* Scheduler include files. */ +#include +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "print.h" + +/* The Tx task will transmit the sequence of characters at a pseudo random +interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x15e ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0xc8 ) + +#define comMAX_CONSECUTIVE_ERRORS ( 2 ) + +#define comSTACK_SIZE ( ( unsigned short ) 256 ) + +#define comRX_RELATIVE_PRIORITY ( 1 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort; + +/* The transmit function as described at the top of the file. */ +static void vComTxTask( void *pvParameters ); + +/* The receive function as described at the top of the file. */ +static void vComRxTask( void *pvParameters ); + +/* The semaphore test function as described at the top of the file. */ +static void vSemTestTask( void * pvParameters ); + +/* The string that is repeatedly transmitted. */ +const char * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. " + "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n"; + +/* Variables that are incremented on each cycle of each task. These are used to +check that both tasks are still executing. */ +volatile short sTxCount = 0, sRxCount = 0, sSemCount = 0; + +/* The handle to the semaphore test task. */ +static xTaskHandle xSemTestTaskHandle = NULL; + +/*-----------------------------------------------------------*/ + +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ) +{ +const unsigned portBASE_TYPE uxBufferLength = 255; + + /* Initialise the com port then spawn both tasks. */ + xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength ); + xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL ); + xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL ); + xTaskCreate( vSemTestTask, "ISRSem", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xSemTestTaskHandle ); +} +/*-----------------------------------------------------------*/ + +static void vComTxTask( void *pvParameters ) +{ +const char * const pcTaskStartMsg = "COM Tx task started.\r\n"; +portTickType xTimeToWait; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Send the string to the serial port. */ + vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) ); + + /* We have posted all the characters in the string - increment the variable + used to check that this task is still running, then wait before re-sending + the string. */ + sTxCount++; + + xTimeToWait = xTaskGetTickCount(); + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vComRxTask( void *pvParameters ) +{ +const char * const pcTaskStartMsg = "COM Rx task started.\r\n"; +const char * const pcTaskErrorMsg = "COM read error\r\n"; +const char * const pcTaskRestartMsg = "COM resynced\r\n"; +const char * const pcTaskTimeoutMsg = "COM Rx timed out\r\n"; +const portTickType xBlockTime = ( portTickType ) 0xffff / portTICK_RATE_MS; +const char *pcExpectedChar; +portBASE_TYPE xGotChar; +char cRxedChar; +short sResyncRequired, sConsecutiveErrors, sLatchedError; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The first expected character is the first character in the string. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + sConsecutiveErrors = 0; + sLatchedError = pdFALSE; + + for( ;; ) + { + /* Receive a message from the com port interrupt routine. If a message is + not yet available the call will block the task. */ + xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime ); + if( xGotChar == pdTRUE ) + { + if( sResyncRequired == pdTRUE ) + { + /* We got out of sequence and are waiting for the start of the next + transmission of the string. */ + if( cRxedChar == '\n' ) + { + /* This is the end of the message so we can start again - with + the first character in the string being the next thing we expect + to receive. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + + /* Queue a message for printing to say that we are going to try + again. */ + vPrintDisplayMessage( &pcTaskRestartMsg ); + + /* Stop incrementing the check variable, if consecutive errors occur. */ + sConsecutiveErrors++; + if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS ) + { + sLatchedError = pdTRUE; + } + } + } + else + { + /* We have received a character, but is it the expected character? */ + if( cRxedChar != *pcExpectedChar ) + { + /* This was not the expected character so post a message for + printing to say that an error has occurred. We will then wait + to resynchronise. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sResyncRequired = pdTRUE; + } + else + { + /* This was the expected character so next time we will expect + the next character in the string. Wrap back to the beginning + of the string when the null terminator has been reached. */ + pcExpectedChar++; + if( *pcExpectedChar == '\0' ) + { + pcExpectedChar = pcMessageToExchange; + + /* We have got through the entire string without error. */ + sConsecutiveErrors = 0; + } + } + } + + /* Increment the count that is used to check that this task is still + running. This is only done if an error has never occurred. */ + if( sLatchedError == pdFALSE ) + { + sRxCount++; + } + } + else + { + vPrintDisplayMessage( &pcTaskTimeoutMsg ); + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vSemTestTask( void * pvParameters ) +{ +const char * const pcTaskStartMsg = "ISR Semaphore test started.\r\n"; +portBASE_TYPE xError = pdFALSE; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + if( xSerialWaitForSemaphore( xPort ) ) + { + if( xError == pdFALSE ) + { + sSemCount++; + } + } + else + { + xError = pdTRUE; + } + } +} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +static short sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0; +portBASE_TYPE xReturn; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. */ + + if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastTxCount = sTxCount; + sLastRxCount = sRxCount; + sLastSemCount = sSemCount; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vComTestUnsuspendTask( void ) +{ + /* The task that is suspended on the semaphore will be referenced from the + Suspended list as it is blocking indefinitely. This call just checks that + the kernel correctly detects this and does not attempt to unsuspend the + task. */ + xTaskResumeFromISR( xSemTestTaskHandle ); +} diff --git a/third_party/FreeRTOS/Demo/Common/Full/death.c b/third_party/FreeRTOS/Demo/Common/Full/death.c new file mode 100644 index 0000000..2142f7a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/death.c @@ -0,0 +1,241 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Create a single persistent task which periodically dynamically creates another + * four tasks. The original task is called the creator task, the four tasks it + * creates are called suicidal tasks. + * + * Two of the created suicidal tasks kill one other suicidal task before killing + * themselves - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" +#include "print.h" + +#define deathSTACK_SIZE ( ( unsigned short ) 512 ) + +/* The task originally created which is responsible for periodically dynamically +creating another four tasks. */ +static void vCreateTasks( void *pvParameters ); + +/* The task function of the dynamically created tasks. */ +static void vSuicidalTask( void *pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This +is used to check that the task is still running. */ +static volatile short sCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator +task can tell if any of the suicidal tasks have failed to die. */ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5; + +/* Used to store a handle to the tasks that should be killed by a suicidal task, +before it kills itself. */ +xTaskHandle xCreatedTask1, xCreatedTask2; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE *puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = uxTaskGetNumberOfTasks(); +} +/*-----------------------------------------------------------*/ + +static void vSuicidalTask( void *pvParameters ) +{ +portDOUBLE d1, d2; +xTaskHandle xTaskToKill; +const portTickType xDelay = ( portTickType ) 500 / portTICK_RATE_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Tow created tasks are + passed a handle to the other task so it can kill it before killing itself. + The other task is passed in null. */ + xTaskToKill = *( xTaskHandle* )pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ;; ) + { + /* Do something random just to use some stack and registers. */ + d1 = 2.4; + d2 = 89.2; + d2 *= d1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( portTickType ) 0 ); + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static void vCreateTasks( void *pvParameters ) +{ +const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; +unsigned portBASE_TYPE uxPriority; +const char * const pcTaskStartMsg = "Create task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ;; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); + + ++sCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there +are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ +static short sLastCreationCount = 0; +short sReturn = pdTRUE; +unsigned portBASE_TYPE uxTasksRunningNow; + + if( sLastCreationCount == sCreationCount ) + { + sReturn = pdFALSE; + } + + uxTasksRunningNow = uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + sReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + sReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return sReturn; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Full/dynamic.c b/third_party/FreeRTOS/Demo/Common/Full/dynamic.c new file mode 100644 index 0000000..b9c4b18 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/dynamic.c @@ -0,0 +1,616 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises it's priority above that of the controller task before each + * increment, lowering it again to it's original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of it's loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume (). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from it's suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + * + * The final set of two tasks implements a third test. This simply raises the + * priority of a task while the scheduler is suspended. Again this test was + * added to exercise parts of the code not covered by the first test. + * + * \page Priorities dynamic.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. + + Added a second, simple test that uses the functions + vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask(). + +Changes from V3.1.1 + + + Added a third simple test that uses the vTaskPrioritySet() function + while the scheduler is suspended. + + Modified the controller task slightly to test the calling of + vTaskResumeAll() while the scheduler is suspended. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" +#include "print.h" + +/* Function that implements the "limited count" task as described above. */ +static void vLimitedIncrementTask( void * pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static void vContinuousIncrementTask( void * pvParameters ); + +/* Function that implements the controller task as described above. */ +static void vCounterControlTask( void * pvParameters ); + +/* The simple test functions that check sending and receiving while the +scheduler is suspended. */ +static void vQueueReceiveWhenSuspendedTask( void *pvParameters ); +static void vQueueSendWhenSuspendedTask( void *pvParameters ); + +/* The simple test functions that check raising and lowering of task priorities +while the scheduler is suspended. */ +static void prvChangePriorityWhenSuspendedTask( void *pvParameters ); +static void prvChangePriorityHelperTask( void *pvParameters ); + + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE ) +#define priSLEEP_TIME ( ( portTickType ) 50 ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned long ) 0xff ) +#define priNO_BLOCK ( ( portTickType ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters +to the controller task to prevent them having to be file scope. */ +static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle; + +/* The shared counter variable. This is passed in as a parameter to the two +counter variables for demonstration purposes. */ +static unsigned long ulCounter; + +/* Variable used in a similar way by the test that checks the raising and +lowering of task priorities while the scheduler is suspended. */ +static unsigned long ulPrioritySetCounter; + +/* Variables used to check that the tasks are still operating without error. +Each complete iteration of the controller task increments this variable +provided no errors have been found. The variable maintaining the same value +is therefore indication of an error. */ +static unsigned short usCheckVariable = ( unsigned short ) 0; +static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; +static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE; + +/* Queue used by the second test. */ +xQueueHandle xSuspendedTestQueue; + +/*-----------------------------------------------------------*/ +/* + * Start the seven tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) ); + xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static void vLimitedIncrementTask( void * pvParameters ) +{ +unsigned long *pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned long * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ;; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static void vContinuousIncrementTask( void * pvParameters ) +{ +unsigned long *pulCounter; +unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned long * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ;; ) + { + /* Raise our priority above the controller task to ensure a context + switch does not occur while we are accessing this variable. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + ( *pulCounter )++; + vTaskPrioritySet( NULL, uxOurPriority ); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static void vCounterControlTask( void * pvParameters ) +{ +unsigned long ulLastCounter; +short sLoops; +short sError = pdFALSE; +const char * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n"; +const char * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned long ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + shared variable without risk of corruption. */ + vTaskSuspend( xContinuousIncrementHandle ); + ulLastCounter = ulCounter; + vTaskResume( xContinuousIncrementHandle ); + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + exclusion the whole scheduler will be locked. This is just for + demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + with the continuous count task so flag an error. */ + sError = pdTRUE; + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + } + xTaskResumeAll(); + } + + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared variable. */ + vTaskSuspend( xContinuousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned long ) 0; + + /* Resume the limited count task which has a higher priority than us. + We should therefore not return from this call until the limited count + task has suspended itself with a known value in the counter variable. + The scheduler suspension is not necessary but is included for test + purposes. */ + vTaskSuspendAll(); + vTaskResume( xLimitedIncrementHandle ); + xTaskResumeAll(); + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinuousIncrementHandle ); + } +} +/*-----------------------------------------------------------*/ + +static void vQueueSendWhenSuspendedTask( void *pvParameters ) +{ +static unsigned long ulValueToSend = ( unsigned long ) 0; +const char * const pcTaskStartMsg = "Queue send while suspended task started.\r\n"; +const char * const pcTaskFailMsg = "Queue send while suspended failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + if( xSuspendedQueueSendError == pdFALSE ) + { + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static void vQueueReceiveWhenSuspendedTask( void *pvParameters ) +{ +static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue; +const char * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n"; +const char * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n"; +portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + undesirable for a normal application. It is done here purely + to test the scheduler. The inner xTaskResumeAll() should + never return pdTRUE as the scheduler is still locked by the + outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + if( xTaskResumeAll() ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + if( xSuspendedQueueReceiveError == pdFALSE ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + } + xSuspendedQueueReceiveError = pdTRUE; + } + + ++ulExpectedValue; + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityWhenSuspendedTask( void *pvParameters ) +{ +const char * const pcTaskStartMsg = "Priority change when suspended task started.\r\n"; +const char * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Start with the counter at 0 so we know what the counter should be + when we check it next. */ + ulPrioritySetCounter = ( unsigned long ) 0; + + /* Resume the helper task. At this time it has a priority lower than + ours so no context switch should occur. */ + vTaskResume( xChangePriorityWhenSuspendedHandle ); + + /* Check to ensure the task just resumed has not executed. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned long ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Now try raising the priority while the scheduler is suspended. */ + vTaskSuspendAll(); + { + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) ); + + /* Again, even though the helper task has a priority greater than + ours, it should not have executed yet because the scheduler is + suspended. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned long ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + } + xTaskResumeAll(); + + /* Now the scheduler has been resumed the helper task should + immediately preempt us and execute. When it executes it will increment + the ulPrioritySetCounter exactly once before suspending itself. + + We should now always find the counter set to 1. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned long ) 1 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Delay until we try this again. */ + vTaskDelay( priSLEEP_TIME * 2 ); + + /* Set the priority of the helper task back ready for the next + execution of this task. */ + vTaskSuspendAll(); + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY ); + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityHelperTask( void *pvParameters ) +{ + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + /* This is the helper task for prvChangePriorityWhenSuspendedTask(). + It has it's priority raised and lowered. When it runs it simply + increments the counter then suspends itself again. This allows + prvChangePriorityWhenSuspendedTask() to know how many times it has + executed. */ + ulPrioritySetCounter++; + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented +since the last call. */ +static unsigned short usLastTaskCheck = ( unsigned short ) 0; +portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xPriorityRaiseWhenSuspendedError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + return xReturn; +} + + + + diff --git a/third_party/FreeRTOS/Demo/Common/Full/events.c b/third_party/FreeRTOS/Demo/Common/Full/events.c new file mode 100644 index 0000000..8ff96a9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/events.c @@ -0,0 +1,406 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * This file exercises the event mechanism whereby more than one task is + * blocked waiting for the same event. + * + * The demo creates five tasks - four 'event' tasks, and a controlling task. + * The event tasks have various different priorities and all block on reading + * the same queue. The controlling task writes data to the queue, then checks + * to see which of the event tasks read the data from the queue. The + * controlling task has the lowest priority of all the tasks so is guaranteed + * to always get preempted immediately upon writing to the queue. + * + * By selectively suspending and resuming the event tasks the controlling task + * can check that the highest priority task that is blocked on the queue is the + * task that reads the posted data from the queue. + * + * Two of the event tasks share the same priority. When neither of these tasks + * are suspended they should alternate - one reading one message from the queue, + * the other the next message, etc. + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "mevents.h" +#include "print.h" + +/* Demo specific constants. */ +#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE ) +#define evtNUM_TASKS ( 4 ) +#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 ) +#define evtNO_DELAY 0 + +/* Just indexes used to uniquely identify the tasks. Note that two tasks are +'highest' priority. */ +#define evtHIGHEST_PRIORITY_INDEX_2 3 +#define evtHIGHEST_PRIORITY_INDEX_1 2 +#define evtMEDIUM_PRIORITY_INDEX 1 +#define evtLOWEST_PRIORITY_INDEX 0 + +/* Each event task increments one of these counters each time it reads data +from the queue. */ +static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Each time the controlling task posts onto the queue it increments the +expected count of the task that it expected to read the data from the queue +(i.e. the task with the highest priority that should be blocked on the queue). + +xExpectedTaskCounters are incremented from the controlling task, and +xTaskCounters are incremented from the individual event tasks - therefore +comparing xTaskCounters to xExpectedTaskCounters shows whether or not the +correct task was unblocked by the post. */ +static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Handles to the four event tasks. These are required to suspend and resume +the tasks. */ +static xTaskHandle xCreatedTasks[ evtNUM_TASKS ]; + +/* The single queue onto which the controlling task posts, and the four event +tasks block. */ +static xQueueHandle xQueue; + +/* Flag used to indicate whether or not an error has occurred at any time. +An error is either the queue being full when not expected, or an unexpected +task reading data from the queue. */ +static portBASE_TYPE xHealthStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* Function that implements the event task. This is created four times. */ +static void prvMultiEventTask( void *pvParameters ); + +/* Function that implements the controlling task. */ +static void prvEventControllerTask( void *pvParameters ); + +/* This is a utility function that posts data to the queue, then compares +xExpectedTaskCounters with xTaskCounters to ensure everything worked as +expected. + +The event tasks all have higher priorities the controlling task. Therefore +the controlling task will always get preempted between writhing to the queue +and checking the task counters. + +@param xExpectedTask The index to the task that the controlling task thinks + should be the highest priority task waiting for data, and + therefore the task that will unblock. + +@param xIncrement The number of items that should be written to the queue. +*/ +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ); + +/* This is just incremented each cycle of the controlling tasks function so +the main application can ensure the test is still running. */ +static portBASE_TYPE xCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartMultiEventTasks( void ) +{ + /* Create the queue to be used for all the communications. */ + xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + /* Start the controlling task. This has the idle priority to ensure it is + always preempted by the event tasks. */ + xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the four event tasks. Note that two have priority 3, one + priority 2 and the other priority 1. */ + xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) ); + xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) ); +} +/*-----------------------------------------------------------*/ + +static void prvMultiEventTask( void *pvParameters ) +{ +portBASE_TYPE *pxCounter; +unsigned portBASE_TYPE uxDummy; +const char * const pcTaskStartMsg = "Multi event task started.\r\n"; + + /* The variable this task will increment is passed in as a parameter. */ + pxCounter = ( portBASE_TYPE * ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Block on the queue. */ + if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) ) + { + /* We unblocked by reading the queue - so simply increment + the counter specific to this task instance. */ + ( *pxCounter )++; + } + else + { + xHealthStatus = pdFAIL; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvEventControllerTask( void *pvParameters ) +{ +const char * const pcTaskStartMsg = "Multi event controller task started.\r\n"; +portBASE_TYPE xDummy = 0; + + /* Just to stop warnings. */ + ( void ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* All tasks are blocked on the queue. When a message is posted one of + the two tasks that share the highest priority should unblock to read + the queue. The next message written should unblock the other task with + the same high priority, and so on in order. No other task should + unblock to read data as they have lower priorities. */ + + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* For the rest of these tests we don't need the second 'highest' + priority task - so it is suspended. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + + + /* Now suspend the other highest priority task. The medium priority + task will then be the task with the highest priority that remains + blocked on the queue. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + /* This time, when we post onto the queue we will expect the medium + priority task to unblock and preempt us. */ + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + /* Now try resuming the highest priority task while the scheduler is + suspended. The task should start executing as soon as the scheduler + is resumed - therefore when we post to the queue again, the highest + priority task should again preempt us. */ + vTaskSuspendAll(); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now we are going to suspend the high and medium priority tasks. The + low priority task should then preempt us. Again the task suspension is + done with the whole scheduler suspended just for test purposes. */ + vTaskSuspendAll(); + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + /* Do the same basic test another few times - selectively suspending + and resuming tasks and each time calling prvCheckTaskCounters() passing + to the function the number of the task we expected to be unblocked by + the post. */ + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for even more test. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + xTaskResumeAll(); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now a slight change, first suspend all tasks. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* Now when we resume the low priority task and write to the queue 3 + times. We expect the low priority task to service the queue three + times. */ + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH ); + + /* Again suspend all tasks (only the low priority task is not suspended + already). */ + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* This time we are going to suspend the scheduler, resume the low + priority task, then resume the high priority task. In this state we + will write to the queue three times. When the scheduler is resumed + we expect the high priority task to service all three messages. */ + vTaskSuspendAll(); + { + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + xHealthStatus = pdFAIL; + } + } + + /* The queue should not have been serviced yet!. The scheduler + is still suspended. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + } + xTaskResumeAll(); + + /* We should have been preempted by resuming the scheduler - so by the + time we are running again we expect the high priority task to have + removed three items from the queue. */ + xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH; + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + + /* The medium priority and second high priority tasks are still + suspended. Make sure to resume them before starting again. */ + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + /* Just keep incrementing to show the task is still executing. */ + xCheckVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ) +{ +portBASE_TYPE xDummy = 0; + + /* Write to the queue the requested number of times. The data written is + not important. */ + for( xDummy = 0; xDummy < xIncrement; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + /* Did not expect to ever find the queue full. */ + xHealthStatus = pdFAIL; + } + } + + /* All the tasks blocked on the queue have a priority higher than the + controlling task. Writing to the queue will therefore have caused this + task to be preempted. By the time this line executes the event task will + have executed and incremented its counter. Increment the expected counter + to the same value. */ + ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement; + + /* Check the actual counts and expected counts really are the same. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + /* The counters were not the same. This means a task we did not expect + to unblock actually did unblock. */ + xHealthStatus = pdFAIL; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreMultiEventTasksStillRunning( void ) +{ +static portBASE_TYPE xPreviousCheckVariable = 0; + + /* Called externally to periodically check that this test is still + operational. */ + + if( xPreviousCheckVariable == xCheckVariable ) + { + xHealthStatus = pdFAIL; + } + + xPreviousCheckVariable = xCheckVariable; + + return xHealthStatus; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Full/flash.c b/third_party/FreeRTOS/Demo/Common/Full/flash.c new file mode 100644 index 0000000..05e1e90 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/flash.c @@ -0,0 +1,166 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/** + * Creates eight tasks, each of which flash an LED at a different rate. The first + * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + * The PC port uses the standard parallel port for outputs, the Flashlite 186 port + * uses IO port F. + * + * \page flashC flash.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. + +Changes from V2.1.1 + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" +#include "print.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE + +/* Structure used to pass parameters to the LED tasks. */ +typedef struct LED_PARAMETERS +{ + unsigned portBASE_TYPE uxLED; /*< The output the task should use. */ + portTickType xFlashRate; /*< The rate at which the LED should flash. */ +} xLEDParameters; + +/* The task that is created eight times - each time with a different xLEDParaemtes +structure passed in as the parameter. */ +static void vLEDFlashTask( void *pvParameters ); + +/* String to print if USE_STDIO is defined. */ +const char * const pcTaskStartMsg = "LED flash task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE uxLEDTask; +xLEDParameters *pxLEDParameters; +const unsigned portBASE_TYPE uxNumOfLEDs = 8; +const portTickType xFlashRate = 125; + + /* Create the eight tasks. */ + for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask ) + { + /* Create and complete the structure used to pass parameters to the next + created task. */ + pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) ); + pxLEDParameters->uxLED = uxLEDTask; + pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( portTickType ) uxLEDTask ) ); + pxLEDParameters->xFlashRate /= portTICK_RATE_MS; + + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void vLEDFlashTask( void *pvParameters ) +{ +xLEDParameters *pxParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxParameters = ( xLEDParameters * ) pvParameters; + + for(;;) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + } +} + diff --git a/third_party/FreeRTOS/Demo/Common/Full/flop.c b/third_party/FreeRTOS/Demo/Common/Full/flop.c new file mode 100644 index 0000000..af15049 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/flop.c @@ -0,0 +1,369 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* +Changes from V1.2.3 + + + The created tasks now include calls to tskYIELD(), allowing them to be used + with the cooperative scheduler. +*/ + +/** + * Creates eight tasks, each of which loops continuously performing an (emulated) + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + * + * \page FlopC flop.c + * \ingroup DemoFiles + *
+ */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE ( ( unsigned short ) 512 ) +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static void vCompetingMathTask1( void *pvParameters ); +static void vCompetingMathTask2( void *pvParameters ); +static void vCompetingMathTask3( void *pvParameters ); +static void vCompetingMathTask4( void *pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will +stop incrementing its check variable. */ +static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask1( void *pvParameters ) +{ +portDOUBLE d1, d2, d3, d4; +volatile unsigned short *pusTaskCheckVariable; +const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222; +const char * const pcTaskStartMsg = "Math task 1 started.\r\n"; +const char * const pcTaskFailMsg = "Math task 1 failed.\r\n"; +short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask2( void *pvParameters ) +{ +portDOUBLE d1, d2, d3, d4; +volatile unsigned short *pusTaskCheckVariable; +const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001; +const char * const pcTaskStartMsg = "Math task 2 started.\r\n"; +const char * const pcTaskFailMsg = "Math task 2 failed.\r\n"; +short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask3( void *pvParameters ) +{ +portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned short *pusTaskCheckVariable; +const unsigned short usArraySize = 250; +unsigned short usPosition; +const char * const pcTaskStartMsg = "Math task 3 started.\r\n"; +const char * const pcTaskFailMsg = "Math task 3 failed.\r\n"; +short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5; + dTotal1 += ( portDOUBLE ) usPosition + 5.5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask4( void *pvParameters ) +{ +portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned short *pusTaskCheckVariable; +const unsigned short usArraySize = 250; +unsigned short usPosition; +const char * const pcTaskStartMsg = "Math task 4 started.\r\n"; +const char * const pcTaskFailMsg = "Math task 4 failed.\r\n"; +short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123; + dTotal1 += ( portDOUBLE ) usPosition * 12.123; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/third_party/FreeRTOS/Demo/Common/Full/integer.c b/third_party/FreeRTOS/Demo/Common/Full/integer.c new file mode 100644 index 0000000..9c69570 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/integer.c @@ -0,0 +1,365 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* +Changes from V1.2.3 + + + The created tasks now include calls to tskYIELD(), allowing them to be used + with the cooperative scheduler. +*/ + +/** + * This does the same as flop. c, but uses variables of type long instead of + * type double. + * + * As with flop. c, the tasks created in this file are a good test of the + * scheduler context switch mechanism. The processor has to access 32bit + * variables in two or four chunks (depending on the processor). The low + * priority of these tasks means there is a high probability that a context + * switch will occur mid calculation. See the flop. c documentation for + * more information. + * + * \page IntegerC integer.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.2.1 + + + The constants used in the calculations are larger to ensure the + optimiser does not truncate them to 16 bits. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "integer.h" + +#define intgSTACK_SIZE ( ( unsigned short ) 256 ) +#define intgNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different calculation on four byte +variables. Each of the four is created twice. */ +static void vCompeteingIntMathTask1( void *pvParameters ); +static void vCompeteingIntMathTask2( void *pvParameters ); +static void vCompeteingIntMathTask3( void *pvParameters ); +static void vCompeteingIntMathTask4( void *pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will stop incrementing its check variable. */ +static volatile unsigned short usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask1( void *pvParameters ) +{ +long l1, l2, l3, l4; +short sError = pdFALSE; +volatile unsigned short *pusTaskCheckVariable; +const long lAnswer = ( ( long ) 74565L + ( long ) 1234567L ) * ( long ) -918L; +const char * const pcTaskStartMsg = "Integer math task 1 started.\r\n"; +const char * const pcTaskFailMsg = "Integer math task 1 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + l1 = ( long ) 74565L; + l2 = ( long ) 1234567L; + l3 = ( long ) -918L; + + l4 = ( l1 + l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask2( void *pvParameters ) +{ +long l1, l2, l3, l4; +short sError = pdFALSE; +volatile unsigned short *pusTaskCheckVariable; +const long lAnswer = ( ( long ) -389000L / ( long ) 329999L ) * ( long ) -89L; +const char * const pcTaskStartMsg = "Integer math task 2 started.\r\n"; +const char * const pcTaskFailMsg = "Integer math task 2 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + l1 = -389000L; + l2 = 329999L; + l3 = -89L; + + l4 = ( l1 / l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask3( void *pvParameters ) +{ +long *plArray, lTotal1, lTotal2; +short sError = pdFALSE; +volatile unsigned short *pusTaskCheckVariable; +const unsigned short usArraySize = ( unsigned short ) 250; +unsigned short usPosition; +const char * const pcTaskStartMsg = "Integer math task 3 started.\r\n"; +const char * const pcTaskFailMsg = "Integer math task 3 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + lTotal1 = ( long ) 0; + lTotal2 = ( long ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( long ) usPosition + ( long ) 5; + lTotal1 += ( long ) usPosition + ( long ) 5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask4( void *pvParameters ) +{ +long *plArray, lTotal1, lTotal2; +short sError = pdFALSE; +volatile unsigned short *pusTaskCheckVariable; +const unsigned short usArraySize = 250; +unsigned short usPosition; +const char * const pcTaskStartMsg = "Integer math task 4 started.\r\n"; +const char * const pcTaskFailMsg = "Integer math task 4 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + lTotal1 = ( long ) 0; + lTotal2 = ( long ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( long ) usPosition * ( long ) 12; + lTotal1 += ( long ) usPosition * ( long ) 12; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned short usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Full/print.c b/third_party/FreeRTOS/Demo/Common/Full/print.c new file mode 100644 index 0000000..14944d8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/print.c @@ -0,0 +1,144 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Manages a queue of strings that are waiting to be displayed. This is used to + * ensure mutual exclusion of console output. + * + * A task wishing to display a message will call vPrintDisplayMessage (), with a + * pointer to the string as the parameter. The pointer is posted onto the + * xPrintQueue queue. + * + * The task spawned in main. c blocks on xPrintQueue. When a message becomes + * available it calls pcPrintGetNextMessage () to obtain a pointer to the next + * string, then uses the functions defined in the portable layer FileIO. c to + * display the message. + * + * NOTE: + * Using console IO can disrupt real time performance - depending on the port. + * Standard C IO routines are not designed for real time applications. While + * standard IO is useful for demonstration and debugging an alternative method + * should be used if you actually require console IO as part of your application. + * + * \page PrintC print.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo program include files. */ +#include "print.h" + +static xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +void vPrintInitialise( void ) +{ +const unsigned portBASE_TYPE uxQueueSize = 20; + + /* Create the queue on which errors will be reported. */ + xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( char * ) ); +} +/*-----------------------------------------------------------*/ + +void vPrintDisplayMessage( const char * const * ppcMessageToSend ) +{ + #ifdef USE_STDIO + xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( portTickType ) 0 ); + #else + /* Stop warnings. */ + ( void ) ppcMessageToSend; + #endif +} +/*-----------------------------------------------------------*/ + +const char *pcPrintGetNextMessage( portTickType xPrintRate ) +{ +char *pcMessage; + + if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS ) + { + return pcMessage; + } + else + { + return NULL; + } +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Full/semtest.c b/third_party/FreeRTOS/Demo/Common/Full/semtest.c new file mode 100644 index 0000000..4d6ee72 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Full/semtest.c @@ -0,0 +1,323 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + * \page SemTestC semtest.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.2.0: + + + The tasks that operate at the idle priority now use a lower expected + count than those running at a higher priority. This prevents the low + priority tasks from signaling an error because they have not been + scheduled enough time for each of them to count the shared variable to + the high value. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. + +Changes from V2.1.1 + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" +#include "print.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) + +/* The task function as described at the top of the file. */ +static void prvSemaphoreTest( void *pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + xSemaphoreHandle xSemaphore; + volatile unsigned long *pulSharedVariable; + portTickType xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile short sNextCheckVariable = 0; + +/* Strings to print if USE_STDIO is defined. */ +const char * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n"; +const char * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ +xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; +const portTickType xBlockTime = ( portTickType ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + if( pxSecondSemaphoreParameters != NULL ) + { + vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; + + xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSemaphoreTest( void *pvParameters ) +{ +xSemaphoreParameters *pxParameters; +volatile unsigned long *pulSharedVariable, ulExpectedValue; +unsigned long ulCounter; +short sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcSemaphoreTaskStart ); + + /* A structure is passed in as the parameter. This contains the shared + variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + switches occur during the count. */ + if( pxParameters->xBlockTime > ( portTickType ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ;; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + shared variable to have left it in the state we expect to find + it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + before releasing the semaphore. Would expect a context switch or + two during this time. */ + for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + if( *pulSharedVariable != ulCounter ) + { + if( sError == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + } + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + than the idle priority. This task takes a long time to complete + a cycle (deliberately so to test the guarding) so will be starving + out lower priority tasks. Block for some time to allow give lower + priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( portTickType ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + processor. We are not blocking when attempting to obtain the + semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) +{ +static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; +portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/AltBlckQ.c b/third_party/FreeRTOS/Demo/Common/Minimal/AltBlckQ.c new file mode 100644 index 0000000..aff7d32 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/AltBlckQ.c @@ -0,0 +1,332 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This is a version of BlockQ.c that uses the alternative (Alt) API. + * + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "AltBlckQ.h" + +#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartAltBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt blocking queue producer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueAltSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt blocking queue consumer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueAltReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreAltBlockingQueuesStillRunning( void ) +{ +static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable to and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/AltBlock.c b/third_party/FreeRTOS/Demo/Common/Minimal/AltBlock.c new file mode 100644 index 0000000..93c8472 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/AltBlock.c @@ -0,0 +1,549 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This is a version of BlockTim.c that uses the light weight API. + * + * This file contains some test scenarios that ensure tasks do not exit queue + * send or receive functions prematurely. A description of the tests is + * included within the code. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "AltBlock.h" + +/* Task priorities. */ +#define bktPRIMARY_PRIORITY ( 3 ) +#define bktSECONDARY_PRIORITY ( 2 ) + +/* Task behaviour. */ +#define bktQUEUE_LENGTH ( 5 ) +#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS ) +#define bktPRIMARY_BLOCK_TIME ( 10 ) +#define bktALLOWABLE_MARGIN ( 12 ) +#define bktTIME_TO_BLOCK ( 175 ) +#define bktDONT_BLOCK ( ( portTickType ) 0 ) +#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 ) + +/* The queue on which the tasks block. */ +static xQueueHandle xTestQueue; + +/* Handle to the secondary task is required by the primary task for calls +to vTaskSuspend/Resume(). */ +static xTaskHandle xSecondary; + +/* Used to ensure that tasks are still executing without error. */ +static portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0; +static portBASE_TYPE xErrorOccurred = pdFALSE; + +/* Provides a simple mechanism for the primary task to know when the +secondary task has executed. */ +static volatile unsigned portBASE_TYPE xRunIndicator; + +/* The two test tasks. Their behaviour is commented within the files. */ +static void vPrimaryBlockTimeTestTask( void *pvParameters ); +static void vSecondaryBlockTimeTestTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +void vCreateAltBlockTimeTasks( void ) +{ + /* Create the queue on which the two tasks block. */ + xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xTestQueue, ( signed portCHAR * ) "AltBlockQueue" ); + + + /* Create the two test tasks. */ + xTaskCreate( vPrimaryBlockTimeTestTask, ( signed portCHAR * )"FBTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL ); + xTaskCreate( vSecondaryBlockTimeTestTask, ( signed portCHAR * )"FBTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary ); +} +/*-----------------------------------------------------------*/ + +static void vPrimaryBlockTimeTestTask( void *pvParameters ) +{ +portBASE_TYPE xItem, xData; +portTickType xTimeWhenBlocking; +portTickType xTimeToBlock, xBlockedTime; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt primary block time test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 + + Simple block time wakeup test on queue receives. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is empty. Attempt to read from the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; + + /* A critical section is used to minimise the jitter in the time + measurements. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueAltReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /********************************************************************* + Test 2 + + Simple block time wakeup test on queue sends. + + First fill the queue. It should be empty so all sends should pass. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is full. Attempt to write to the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; + + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueAltSendToBack( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /********************************************************************* + Test 3 + + Wake the other task, it will block attempting to post to the queue. + When we read from the queue the other task will wake, but before it + can run we will post to the queue again. When the other task runs it + will find the queue still full, even though it was woken. It should + recognise that its block time has not expired and return to block for + the remains of its block time. + + Wake the other task so it blocks attempting to post to the already + full queue. */ + xRunIndicator = 0; + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + /* The other task has not yet executed. */ + vTaskDelay( bktSHORT_WAIT ); + } + /* Make sure the other task is blocked on the queue. */ + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we make space on the queue the other task should wake + but not execute as this task has higher priority. */ + if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now fill the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + full ourselves, and the other task have set xRunIndicator. */ + if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + + /* Set the priority back down. */ + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /********************************************************************* + Test 4 + + As per test 3 - but with the send and receive the other way around. + The other task blocks attempting to read from the queue. + + Empty the queue. We should find that it is full. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Wake the other task so it blocks attempting to read from the + already empty queue. */ + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we place an item on the queue the other task should + wake but not execute as this task has higher priority. */ + if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now empty the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + empty ourselves, and the other task would be suspended. */ + if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + + xPrimaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void vSecondaryBlockTimeTestTask( void *pvParameters ) +{ +portTickType xTimeWhenBlocking, xBlockedTime; +portBASE_TYPE xData; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt secondary block time test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 and 2 + + This task does does not participate in these tests. */ + vTaskSuspend( NULL ); + + /********************************************************************* + Test 3 + + The first thing we do is attempt to read from the queue. It should be + full so we block. Note the time before we block so we can check the + wake time is as per that expected. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xData = 0; + xRunIndicator = bktRUN_INDICATOR; + if( xQueueAltSendToBack( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we inside the send function? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as + soon as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Suspend ready for test 3. */ + xRunIndicator = bktRUN_INDICATOR; + vTaskSuspend( NULL ); + + /********************************************************************* + Test 4 + + As per test three, but with the send and receive reversed. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xRunIndicator = bktRUN_INDICATOR; + if( xQueueAltReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as soon + as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + xRunIndicator = bktRUN_INDICATOR; + + xSecondaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreAltBlockTimeTestTasksStillRunning( void ) +{ +static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0; +portBASE_TYPE xReturn = pdPASS; + + /* Have both tasks performed at least one cycle since this function was + last called? */ + if( xPrimaryCycles == xLastPrimaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xSecondaryCycles == xLastSecondaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + + xLastSecondaryCycleCount = xSecondaryCycles; + xLastPrimaryCycleCount = xPrimaryCycles; + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/AltPollQ.c b/third_party/FreeRTOS/Demo/Common/Minimal/AltPollQ.c new file mode 100644 index 0000000..25949ea --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/AltPollQ.c @@ -0,0 +1,275 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This is a version of PollQ.c that uses the alternative (Alt) API. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "AltPollQ.h" + +#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE +#define pollqQUEUE_SIZE ( 10 ) +#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS ) +#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) ) +#define pollqNO_DELAY ( ( portTickType ) 0 ) +#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 ) +#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 ) + +/* The task that posts the incrementing number onto the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); + +/* The task that empties the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); + +/* Variables that are used to check that the tasks are still running with no +errors. */ +static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; + +/*-----------------------------------------------------------*/ + +void vStartAltPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xPolledQueue, ( signed portCHAR * ) "AltPollQueue" ); + + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, ( signed portCHAR * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( vPolledQueueProducer, ( signed portCHAR * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE, xLoop; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt polling queue producer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + for( ;; ) + { + for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueAltSendToBack( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) + { + /* We should never find the queue full so if we get here there + has been an error. */ + xError = pdTRUE; + } + else + { + if( xError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + portENTER_CRITICAL(); + xPollingProducerCount++; + portEXIT_CRITICAL(); + } + + /* Update the value we are going to post next time around. */ + usValue++; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( pollqPRODUCER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt blocking queue consumer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) ) + { + if( xQueueAltReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + xError = pdTRUE; + + /* Catch-up to the value we received so our next expected + value should again be correct. */ + usExpectedValue = usData; + } + else + { + if( xError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + portENTER_CRITICAL(); + xPollingConsumerCount++; + portEXIT_CRITICAL(); + } + } + + /* Next time round we would expect the number to be one higher. */ + usExpectedValue++; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( pollqCONSUMER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xAreAltPollingQueuesStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* Check both the consumer and producer poll count to check they have both + been changed since out last trip round. We do not need a critical section + around the check variables as this is called from a higher priority than + the other tasks that access the same variables. */ + if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || + ( xPollingProducerCount == pollqINITIAL_VALUE ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Set the check variables back down so we know if they have been + incremented the next time around. */ + xPollingConsumerCount = pollqINITIAL_VALUE; + xPollingProducerCount = pollqINITIAL_VALUE; + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/AltQTest.c b/third_party/FreeRTOS/Demo/Common/Minimal/AltQTest.c new file mode 100644 index 0000000..9710336 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/AltQTest.c @@ -0,0 +1,587 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This file implements the same demo and test as GenQTest.c, but uses the + * light weight API in place of the fully featured API. + * + * See the comments at the top of GenQTest.c for a description. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "AltQTest.h" + +#define genqQUEUE_LENGTH ( 5 ) +#define genqNO_BLOCK ( 0 ) + +#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY ) +#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * Tests the behaviour of the xQueueAltSendToFront() and xQueueAltSendToBack() + * macros by using both to fill a queue, then reading from the queue to + * check the resultant queue order is as expected. Queue data is also + * peeked. + */ +static void prvSendFrontAndBackTest( void *pvParameters ); + +/* + * The following three tasks are used to demonstrate the mutex behaviour. + * Each task is given a different priority to demonstrate the priority + * inheritance mechanism. + * + * The low priority task obtains a mutex. After this a high priority task + * attempts to obtain the same mutex, causing its priority to be inherited + * by the low priority task. The task with the inherited high priority then + * resumes a medium priority task to ensure it is not blocked by the medium + * priority task while it holds the inherited high priority. Once the mutex + * is returned the task with the inherited priority returns to its original + * low priority, and is therefore immediately preempted by first the high + * priority task and then the medium prioroity task before it can continue. + */ +static void prvLowPriorityMutexTask( void *pvParameters ); +static void prvMediumPriorityMutexTask( void *pvParameters ); +static void prvHighPriorityMutexTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static portBASE_TYPE xErrorDetected = pdFALSE; + +/* Counters that are incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned portLONG ulLoopCounter = 0; +static volatile unsigned portLONG ulLoopCounter2 = 0; + +/* The variable that is guarded by the mutex in the mutex demo tasks. */ +static volatile unsigned portLONG ulGuardedVariable = 0; + +/* Handles used in the mutext test to suspend and resume the high and medium +priority mutex test tasks. */ +static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask; + +/*-----------------------------------------------------------*/ + +void vStartAltGenericQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xQueueHandle xQueue; +xSemaphoreHandle xMutex; + + /* Create the queue that we are going to use for the + prvSendFrontAndBackTest demo. */ + xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xQueue, ( signed portCHAR * ) "Alt_Gen_Test_Queue" ); + + /* Create the demo task and pass it the queue just created. We are + passing the queue handle by value so it does not matter that it is + declared on the stack here. */ + xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * ) "FGenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL ); + + /* Create the mutex used by the prvMutexTest task. */ + xMutex = xSemaphoreCreateMutex(); + + /* vQueueAddToRegistry() adds the mutex to the registry, if one is + in use. The registry is provided as a means for kernel aware + debuggers to locate mutex and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( ( xQueueHandle ) xMutex, ( signed portCHAR * ) "Alt_Q_Mutex" ); + + /* Create the mutex demo tasks and pass it the mutex just created. We are + passing the mutex handle by value so it does not matter that it is declared + on the stack here. */ + xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * ) "FMuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * ) "FMuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask ); + xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * ) "FMuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask ); +} +/*-----------------------------------------------------------*/ + +static void prvSendFrontAndBackTest( void *pvParameters ) +{ +unsigned portLONG ulData, ulData2; +xQueueHandle xQueue; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt queue SendToFront/SendToBack/Peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + xQueue = ( xQueueHandle ) pvParameters; + + for( ;; ) + { + /* The queue is empty, so sending an item to the back of the queue + should have the same efect as sending it to the front of the queue. + + First send to the front and check everything is as expected. */ + xQueueAltSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + /* Then do the same, sending the data to the back, checking everything + is as expected. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + xQueueAltSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + + /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */ + for( ulData = 2; ulData < 5; ulData++ ) + { + xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + } + + /* Now the order in the queue should be 2, 3, 4, with 2 being the first + thing to be read out. Now add 1 then 0 to the front of the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 3 ) + { + xErrorDetected = pdTRUE; + } + ulData = 1; + xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + ulData = 0; + xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + + /* Now the queue should be full, and when we read the data out we + should receive 0, 1, 2, 3, 4. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ ) + { + /* Try peeking the data first. */ + if( xQueueAltPeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + + + /* Now try receiving the data for real. The value should be the + same. Clobber the value first so we know we really received it. */ + ulData2 = ~ulData2; + if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + /* The queue should now be empty again. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /* Our queue is empty once more, add 10, 11 to the back. */ + ulData = 10; + if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + ulData = 11; + if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 2 ) + { + xErrorDetected = pdTRUE; + } + + /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the + front. */ + for( ulData = 9; ulData >= 7; ulData-- ) + { + if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } + + /* Now check that the queue is full, and that receiving data provides + the expected sequence of 7, 8, 9, 10, 11. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ ) + { + if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Fast mutex with priority inheritance test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + ( void ) pvParameters; + + + for( ;; ) + { + /* Take the mutex. It should be available now. */ + if( xSemaphoreAltTake( xMutex, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Set our guarded variable to a known start value. */ + ulGuardedVariable = 0; + + /* Our priority should be as per that assigned when the task was + created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + /* We should now have inherited the prioritoy of the high priority task, + as by now it will have attempted to get the mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* We can attempt to set our priority to the test priority - between the + idle priority and the medium/high test priorities, but our actual + prioroity should remain at the high priority. */ + vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY ); + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the medium priority task. This should not run as our + inherited priority is above that of the medium priority task. */ + vTaskResume( xMediumPriorityMutexTask ); + + /* If the did run then it will have incremented our guarded variable. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* When we give back the semaphore our priority should be disinherited + back to the priority to which we attempted to set ourselves. This means + that when the high priority task next blocks, the medium priority task + should execute and increment the guarded variable. When we next run + both the high and medium priority tasks will have been suspended again. */ + if( xSemaphoreAltGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Check that the guarded variable did indeed increment... */ + if( ulGuardedVariable != 1 ) + { + xErrorDetected = pdTRUE; + } + + /* ... and that our priority has been disinherited to + genqMUTEX_TEST_PRIORITY. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Set our priority back to our original priority ready for the next + loop around this test. */ + vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY ); + + /* Just to show we are still running. */ + ulLoopCounter2++; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityMutexTask( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + /* The medium priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is increment the guarded + variable, this is so the low priority task knows that it has + executed. */ + ulGuardedVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + ( void ) pvParameters; + + for( ;; ) + { + /* The high priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is attempt to obtain + the mutex. It should find the mutex is not available so a + block time is specified. */ + if( xSemaphoreAltTake( xMutex, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* When we eventually obtain the mutex we just give it back then + return to suspend ready for the next test. */ + if( xSemaphoreAltGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreAltGenericQueueTasksStillRunning( void ) +{ +static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0; + + /* If the demo task is still running then we expect the loopcounters to + have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + if( ulLastLoopCounter2 == ulLoopCounter2 ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + ulLastLoopCounter2 = ulLoopCounter2; + + /* Errors detected in the task itself will have latched xErrorDetected + to true. */ + + return !xErrorDetected; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/BlockQ.c b/third_party/FreeRTOS/Demo/Common/Minimal/BlockQ.c new file mode 100644 index 0000000..be19050 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/BlockQ.c @@ -0,0 +1,324 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" + +#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile short *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, ( signed char * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed char * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueConsumer, ( signed char * ) "QConsB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed char * ) "QProdB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, ( signed char * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, ( signed char * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) +{ +unsigned short usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +short sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) +{ +unsigned short usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +short sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + + #if configUSE_PREEMPTION == 0 + { + if( pxQueueParameters->xBlockTime == 0 ) + { + taskYIELD(); + } + } + #endif + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ +static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 }; +static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable to and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/GenQTest.c b/third_party/FreeRTOS/Demo/Common/Minimal/GenQTest.c new file mode 100644 index 0000000..90dac35 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/GenQTest.c @@ -0,0 +1,600 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Tests the extra queue functionality introduced in FreeRTOS.org V4.5.0 - + * including xQueueSendToFront(), xQueueSendToBack(), xQueuePeek() and + * mutex behaviour. + * + * See the comments above the prvSendFrontAndBackTest() and + * prvLowPriorityMutexTask() prototypes below for more information. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "GenQTest.h" + +#define genqQUEUE_LENGTH ( 5 ) +#define genqNO_BLOCK ( 0 ) + +#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY ) +#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * Tests the behaviour of the xQueueSendToFront() and xQueueSendToBack() + * macros by using both to fill a queue, then reading from the queue to + * check the resultant queue order is as expected. Queue data is also + * peeked. + */ +static void prvSendFrontAndBackTest( void *pvParameters ); + +/* + * The following three tasks are used to demonstrate the mutex behaviour. + * Each task is given a different priority to demonstrate the priority + * inheritance mechanism. + * + * The low priority task obtains a mutex. After this a high priority task + * attempts to obtain the same mutex, causing its priority to be inherited + * by the low priority task. The task with the inherited high priority then + * resumes a medium priority task to ensure it is not blocked by the medium + * priority task while it holds the inherited high priority. Once the mutex + * is returned the task with the inherited priority returns to its original + * low priority, and is therefore immediately preempted by first the high + * priority task and then the medium prioroity task before it can continue. + */ +static void prvLowPriorityMutexTask( void *pvParameters ); +static void prvMediumPriorityMutexTask( void *pvParameters ); +static void prvHighPriorityMutexTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static volatile portBASE_TYPE xErrorDetected = pdFALSE; + +/* Counters that are incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned portLONG ulLoopCounter = 0; +static volatile unsigned portLONG ulLoopCounter2 = 0; + +/* The variable that is guarded by the mutex in the mutex demo tasks. */ +static volatile unsigned portLONG ulGuardedVariable = 0; + +/* Handles used in the mutext test to suspend and resume the high and medium +priority mutex test tasks. */ +static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask; + +/*-----------------------------------------------------------*/ + +void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xQueueHandle xQueue; +xSemaphoreHandle xMutex; + + /* Create the queue that we are going to use for the + prvSendFrontAndBackTest demo. */ + xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xQueue, ( signed portCHAR * ) "Gen_Queue_Test" ); + + /* Create the demo task and pass it the queue just created. We are + passing the queue handle by value so it does not matter that it is + declared on the stack here. */ + xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * )"GenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL ); + + /* Create the mutex used by the prvMutexTest task. */ + xMutex = xSemaphoreCreateMutex(); + + /* vQueueAddToRegistry() adds the mutex to the registry, if one is + in use. The registry is provided as a means for kernel aware + debuggers to locate mutexes and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( ( xQueueHandle ) xMutex, ( signed portCHAR * ) "Gen_Queue_Mutex" ); + + /* Create the mutex demo tasks and pass it the mutex just created. We are + passing the mutex handle by value so it does not matter that it is declared + on the stack here. */ + xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * )"MuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * )"MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask ); + xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * )"MuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask ); +} +/*-----------------------------------------------------------*/ + +static void prvSendFrontAndBackTest( void *pvParameters ) +{ +unsigned portLONG ulData, ulData2; +xQueueHandle xQueue; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + xQueue = ( xQueueHandle ) pvParameters; + + for( ;; ) + { + /* The queue is empty, so sending an item to the back of the queue + should have the same efect as sending it to the front of the queue. + + First send to the front and check everything is as expected. */ + xQueueSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + /* Then do the same, sending the data to the back, checking everything + is as expected. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + xQueueSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + + /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */ + for( ulData = 2; ulData < 5; ulData++ ) + { + xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + } + + /* Now the order in the queue should be 2, 3, 4, with 2 being the first + thing to be read out. Now add 1 then 0 to the front of the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 3 ) + { + xErrorDetected = pdTRUE; + } + ulData = 1; + xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + ulData = 0; + xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + + /* Now the queue should be full, and when we read the data out we + should receive 0, 1, 2, 3, 4. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ ) + { + /* Try peeking the data first. */ + if( xQueuePeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + + + /* Now try receiving the data for real. The value should be the + same. Clobber the value first so we know we really received it. */ + ulData2 = ~ulData2; + if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + /* The queue should now be empty again. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /* Our queue is empty once more, add 10, 11 to the back. */ + ulData = 10; + if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + ulData = 11; + if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 2 ) + { + xErrorDetected = pdTRUE; + } + + /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the + front. */ + for( ulData = 9; ulData >= 7; ulData-- ) + { + if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } + + /* Now check that the queue is full, and that receiving data provides + the expected sequence of 7, 8, 9, 10, 11. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ ) + { + if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + for( ;; ) + { + /* Take the mutex. It should be available now. */ + if( xSemaphoreTake( xMutex, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Set our guarded variable to a known start value. */ + ulGuardedVariable = 0; + + /* Our priority should be as per that assigned when the task was + created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Ensure the task is reporting it priority as blocked and not + suspended (as it would have done in versions up to V7.5.3). */ + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* We should now have inherited the prioritoy of the high priority task, + as by now it will have attempted to get the mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* We can attempt to set our priority to the test priority - between the + idle priority and the medium/high test priorities, but our actual + prioroity should remain at the high priority. */ + vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY ); + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the medium priority task. This should not run as our + inherited priority is above that of the medium priority task. */ + vTaskResume( xMediumPriorityMutexTask ); + + /* If the did run then it will have incremented our guarded variable. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* When we give back the semaphore our priority should be disinherited + back to the priority to which we attempted to set ourselves. This means + that when the high priority task next blocks, the medium priority task + should execute and increment the guarded variable. When we next run + both the high and medium priority tasks will have been suspended again. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check that the guarded variable did indeed increment... */ + if( ulGuardedVariable != 1 ) + { + xErrorDetected = pdTRUE; + } + + /* ... and that our priority has been disinherited to + genqMUTEX_TEST_PRIORITY. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Set our priority back to our original priority ready for the next + loop around this test. */ + vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY ); + + /* Just to show we are still running. */ + ulLoopCounter2++; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityMutexTask( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + /* The medium priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is increment the guarded + variable, this is so the low priority task knows that it has + executed. */ + ulGuardedVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + for( ;; ) + { + /* The high priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is attempt to obtain + the mutex. It should find the mutex is not available so a + block time is specified. */ + if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* When we eventually obtain the mutex we just give it back then + return to suspend ready for the next test. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreGenericQueueTasksStillRunning( void ) +{ +static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0; + + /* If the demo task is still running then we expect the loopcounters to + have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + if( ulLastLoopCounter2 == ulLoopCounter2 ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + ulLastLoopCounter2 = ulLoopCounter2; + + /* Errors detected in the task itself will have latched xErrorDetected + to true. */ + + return ( portBASE_TYPE ) !xErrorDetected; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/IntQueue.c b/third_party/FreeRTOS/Demo/Common/Minimal/IntQueue.c new file mode 100644 index 0000000..42d2103 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/IntQueue.c @@ -0,0 +1,756 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file defines one of the more complex set of demo/test tasks. They are + * designed to stress test the queue implementation though pseudo simultaneous + * multiple reads and multiple writes from both tasks of varying priority and + * interrupts. The interrupts are prioritised such to ensure that nesting + * occurs (for those ports that support it). + * + * The test ensures that, while being accessed from three tasks and two + * interrupts, all the data sent to the queues is also received from + * the same queue, and that no duplicate items are either sent or received. + * The tests also ensure that a low priority task is never able to successfully + * read from or write to a queue when a task of higher priority is attempting + * the same operation. + */ + +/* Standard includes. */ +#include + +/* SafeRTOS includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo app includes. */ +#include "IntQueue.h" +#include "IntQueueTimer.h" + +/* Priorities used by test tasks. */ +#ifndef intqHIGHER_PRIORITY + #define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 2 ) +#endif +#define intqLOWER_PRIORITY ( tskIDLE_PRIORITY ) + +/* The number of values to send/receive before checking that all values were +processed as expected. */ +#define intqNUM_VALUES_TO_LOG ( 200 ) +#define intqSHORT_DELAY ( 140 ) + +/* The value by which the value being sent to or received from a queue should +increment past intqNUM_VALUES_TO_LOG before we check that all values have been +sent/received correctly. This is done to ensure that all tasks and interrupts +accessing the queue have completed their accesses with the +intqNUM_VALUES_TO_LOG range. */ +#define intqVALUE_OVERRUN ( 50 ) + +/* The delay used by the polling task. A short delay is used for code +coverage. */ +#define intqONE_TICK_DELAY ( 1 ) + +/* Each task and interrupt is given a unique identifier. This value is used to +identify which task sent or received each value. The identifier is also used +to distinguish between two tasks that are running the same task function. */ +#define intqHIGH_PRIORITY_TASK1 ( ( unsigned portBASE_TYPE ) 1 ) +#define intqHIGH_PRIORITY_TASK2 ( ( unsigned portBASE_TYPE ) 2 ) +#define intqLOW_PRIORITY_TASK ( ( unsigned portBASE_TYPE ) 3 ) +#define intqFIRST_INTERRUPT ( ( unsigned portBASE_TYPE ) 4 ) +#define intqSECOND_INTERRUPT ( ( unsigned portBASE_TYPE ) 5 ) +#define intqQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 ) + +/* At least intqMIN_ACCEPTABLE_TASK_COUNT values should be sent to/received +from each queue by each task, otherwise an error is detected. */ +#define intqMIN_ACCEPTABLE_TASK_COUNT ( 5 ) + +/* Send the next value to the queue that is normally empty. This is called +from within the interrupts. */ +#define timerNORMALLY_EMPTY_TX() \ + if( xQueueIsQueueFullFromISR( xNormallyEmptyQueue ) != pdTRUE ) \ + { \ + unsigned portBASE_TYPE uxSavedInterruptStatus; \ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + uxValueForNormallyEmptyQueue++; \ + xQueueSendFromISR( xNormallyEmptyQueue, ( void * ) &uxValueForNormallyEmptyQueue, &xHigherPriorityTaskWoken ); \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } \ + +/* Send the next value to the queue that is normally full. This is called +from within the interrupts. */ +#define timerNORMALLY_FULL_TX() \ + if( xQueueIsQueueFullFromISR( xNormallyFullQueue ) != pdTRUE ) \ + { \ + unsigned portBASE_TYPE uxSavedInterruptStatus; \ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + uxValueForNormallyFullQueue++; \ + xQueueSendFromISR( xNormallyFullQueue, ( void * ) &uxValueForNormallyFullQueue, &xHigherPriorityTaskWoken ); \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } \ + +/* Receive a value from the normally empty queue. This is called from within +an interrupt. */ +#define timerNORMALLY_EMPTY_RX() \ + if( xQueueReceiveFromISR( xNormallyEmptyQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) != pdPASS ) \ + { \ + prvQueueAccessLogError( __LINE__ ); \ + } \ + else \ + { \ + prvRecordValue_NormallyEmpty( uxRxedValue, intqSECOND_INTERRUPT ); \ + } + +/* Receive a value from the normally full queue. This is called from within +an interrupt. */ +#define timerNORMALLY_FULL_RX() \ + if( xQueueReceiveFromISR( xNormallyFullQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) == pdPASS ) \ + { \ + prvRecordValue_NormallyFull( uxRxedValue, intqSECOND_INTERRUPT ); \ + } \ + + +/*-----------------------------------------------------------*/ + +/* The two queues used by the test. */ +static xQueueHandle xNormallyEmptyQueue, xNormallyFullQueue; + +/* Variables used to detect a stall in one of the tasks. */ +static unsigned portBASE_TYPE uxHighPriorityLoops1 = 0, uxHighPriorityLoops2 = 0, uxLowPriorityLoops1 = 0, uxLowPriorityLoops2 = 0; + +/* Any unexpected behaviour sets xErrorStatus to fail and log the line that +caused the error in xErrorLine. */ +static portBASE_TYPE xErrorStatus = pdPASS; +static volatile unsigned portBASE_TYPE xErrorLine = ( unsigned portBASE_TYPE ) 0; + +/* Used for sequencing between tasks. */ +static portBASE_TYPE xWasSuspended = pdFALSE; + +/* The values that are sent to the queues. An incremented value is sent each +time to each queue. */ +volatile unsigned portBASE_TYPE uxValueForNormallyEmptyQueue = 0, uxValueForNormallyFullQueue = 0; + +/* A handle to some of the tasks is required so they can be suspended/resumed. */ +xTaskHandle xHighPriorityNormallyEmptyTask1, xHighPriorityNormallyEmptyTask2, xHighPriorityNormallyFullTask1, xHighPriorityNormallyFullTask2; + +/* When a value is received in a queue the value is ticked off in the array +the array position of the value is set to a the identifier of the task or +interrupt that accessed the queue. This way missing or duplicate values can be +detected. */ +static unsigned portCHAR ucNormallyEmptyReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 }; +static unsigned portCHAR ucNormallyFullReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 }; + +/* The test tasks themselves. */ +static void prvLowerPriorityNormallyEmptyTask( void *pvParameters ); +static void prvLowerPriorityNormallyFullTask( void *pvParameters ); +static void prvHigherPriorityNormallyEmptyTask( void *pvParameters ); +static void prv1stHigherPriorityNormallyFullTask( void *pvParameters ); +static void prv2ndHigherPriorityNormallyFullTask( void *pvParameters ); + +/* Used to mark the positions within the ucNormallyEmptyReceivedValues and +ucNormallyFullReceivedValues arrays, while checking for duplicates. */ +static void prvRecordValue_NormallyEmpty( unsigned portBASE_TYPE uxValue, unsigned portBASE_TYPE uxSource ); +static void prvRecordValue_NormallyFull( unsigned portBASE_TYPE uxValue, unsigned portBASE_TYPE uxSource ); + +/* Logs the line on which an error occurred. */ +static void prvQueueAccessLogError( unsigned portBASE_TYPE uxLine ); + +/*-----------------------------------------------------------*/ + +void vStartInterruptQueueTasks( void ) +{ + /* Start the test tasks. */ + xTaskCreate( prvHigherPriorityNormallyEmptyTask, ( signed portCHAR * ) "H1QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask1 ); + xTaskCreate( prvHigherPriorityNormallyEmptyTask, ( signed portCHAR * ) "H2QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask2 ); + xTaskCreate( prvLowerPriorityNormallyEmptyTask, ( signed portCHAR * ) "L1QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL ); + xTaskCreate( prv1stHigherPriorityNormallyFullTask, ( signed portCHAR * ) "H1QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask1 ); + xTaskCreate( prv2ndHigherPriorityNormallyFullTask, ( signed portCHAR * ) "H2QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask2 ); + xTaskCreate( prvLowerPriorityNormallyFullTask, ( signed portCHAR * ) "L2QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL ); + + /* Create the queues that are accessed by multiple tasks and multiple + interrupts. */ + xNormallyFullQueue = xQueueCreate( intqQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + xNormallyEmptyQueue = xQueueCreate( intqQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xNormallyFullQueue, ( signed portCHAR * ) "NormallyFull" ); + vQueueAddToRegistry( xNormallyEmptyQueue, ( signed portCHAR * ) "NormallyEmpty" ); +} +/*-----------------------------------------------------------*/ + +static void prvRecordValue_NormallyFull( unsigned portBASE_TYPE uxValue, unsigned portBASE_TYPE uxSource ) +{ + if( uxValue < intqNUM_VALUES_TO_LOG ) + { + /* We don't expect to receive the same value twice, so if the value + has already been marked as received an error has occurred. */ + if( ucNormallyFullReceivedValues[ uxValue ] != 0x00 ) + { + prvQueueAccessLogError( __LINE__ ); + } + + /* Log that this value has been received. */ + ucNormallyFullReceivedValues[ uxValue ] = uxSource; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecordValue_NormallyEmpty( unsigned portBASE_TYPE uxValue, unsigned portBASE_TYPE uxSource ) +{ + if( uxValue < intqNUM_VALUES_TO_LOG ) + { + /* We don't expect to receive the same value twice, so if the value + has already been marked as received an error has occurred. */ + if( ucNormallyEmptyReceivedValues[ uxValue ] != 0x00 ) + { + prvQueueAccessLogError( __LINE__ ); + } + + /* Log that this value has been received. */ + ucNormallyEmptyReceivedValues[ uxValue ] = uxSource; + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueAccessLogError( unsigned portBASE_TYPE uxLine ) +{ + /* Latch the line number that caused the error. */ + xErrorLine = uxLine; + xErrorStatus = pdFAIL; +} +/*-----------------------------------------------------------*/ + +static void prvHigherPriorityNormallyEmptyTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxRxed, ux, uxTask1, uxTask2, uxInterrupts, uxErrorCount1 = 0, uxErrorCount2 = 0; + + /* The timer should not be started until after the scheduler has started. + More than one task is running this code so we check the parameter value + to determine which task should start the timer. */ + if( ( unsigned portBASE_TYPE ) pvParameters == intqHIGH_PRIORITY_TASK1 ) + { + vInitialiseTimerForIntQueueTest(); + } + + for( ;; ) + { + /* Block waiting to receive a value from the normally empty queue. + Interrupts will write to the queue so we should receive a value. */ + if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqSHORT_DELAY ) != pdPASS ) + { + prvQueueAccessLogError( __LINE__ ); + } + else + { + /* Note which value was received so we can check all expected + values are received and no values are duplicated. */ + prvRecordValue_NormallyEmpty( uxRxed, ( unsigned portBASE_TYPE ) pvParameters ); + } + + /* Ensure the other task running this code gets a chance to execute. */ + taskYIELD(); + + if( ( unsigned portBASE_TYPE ) pvParameters == intqHIGH_PRIORITY_TASK1 ) + { + /* Have we received all the expected values? */ + if( uxValueForNormallyEmptyQueue > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) ) + { + vTaskSuspend( xHighPriorityNormallyEmptyTask2 ); + + uxTask1 = 0; + uxTask2 = 0; + uxInterrupts = 0; + + /* Loop through the array, checking that both tasks have + placed values into the array, and that no values are missing. + Start at 1 as we expect position 0 to be unused. */ + for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ ) + { + if( ucNormallyEmptyReceivedValues[ ux ] == 0 ) + { + /* A value is missing. */ + prvQueueAccessLogError( __LINE__ ); + } + else + { + if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK1 ) + { + /* Value was placed into the array by task 1. */ + uxTask1++; + } + else if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK2 ) + { + /* Value was placed into the array by task 2. */ + uxTask2++; + } + else if( ucNormallyEmptyReceivedValues[ ux ] == intqSECOND_INTERRUPT ) + { + uxInterrupts++; + } + } + } + + if( uxTask1 < intqMIN_ACCEPTABLE_TASK_COUNT ) + { + /* Only task 2 seemed to log any values. */ + uxErrorCount1++; + if( uxErrorCount1 > 2 ) + { + prvQueueAccessLogError( __LINE__ ); + } + } + else + { + uxErrorCount1 = 0; + } + + if( uxTask2 < intqMIN_ACCEPTABLE_TASK_COUNT ) + { + /* Only task 1 seemed to log any values. */ + uxErrorCount2++; + if( uxErrorCount2 > 2 ) + { + prvQueueAccessLogError( __LINE__ ); + } + } + else + { + uxErrorCount2 = 0; + } + + if( uxInterrupts == 0 ) + { + prvQueueAccessLogError( __LINE__ ); + } + + /* Clear the array again, ready to start a new cycle. */ + memset( ucNormallyEmptyReceivedValues, 0x00, sizeof( ucNormallyEmptyReceivedValues ) ); + + uxHighPriorityLoops1++; + uxValueForNormallyEmptyQueue = 0; + + /* Suspend ourselves, allowing the lower priority task to + actually receive something from the queue. Until now it + will have been prevented from doing so by the higher + priority tasks. The lower priority task will resume us + if it receives something. We will then resume the other + higher priority task. */ + vTaskSuspend( NULL ); + vTaskResume( xHighPriorityNormallyEmptyTask2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvLowerPriorityNormallyEmptyTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxValue, uxRxed; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqONE_TICK_DELAY ) != errQUEUE_EMPTY ) + { + /* We should only obtain a value when the high priority task is + suspended. */ + if( xTaskIsTaskSuspended( xHighPriorityNormallyEmptyTask1 ) == pdFALSE ) + { + prvQueueAccessLogError( __LINE__ ); + } + + prvRecordValue_NormallyEmpty( uxRxed, intqLOW_PRIORITY_TASK ); + + /* Wake the higher priority task again. */ + vTaskResume( xHighPriorityNormallyEmptyTask1 ); + uxLowPriorityLoops1++; + } + else + { + /* Raise our priority while we send so we can preempt the higher + priority task, and ensure we get the Tx value into the queue. */ + vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 ); + + portENTER_CRITICAL(); + { + uxValueForNormallyEmptyQueue++; + uxValue = uxValueForNormallyEmptyQueue; + } + portEXIT_CRITICAL(); + + if( xQueueSend( xNormallyEmptyQueue, &uxValue, portMAX_DELAY ) != pdPASS ) + { + prvQueueAccessLogError( __LINE__ ); + } + + vTaskPrioritySet( NULL, intqLOWER_PRIORITY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prv1stHigherPriorityNormallyFullTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxValueToTx, ux, uxInterrupts; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + /* Make sure the queue starts full or near full. >> 1 as there are two + high priority tasks. */ + for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ); + } + + for( ;; ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS ) + { + /* intqHIGH_PRIORITY_TASK2 is never suspended so we would not + expect it to ever time out. */ + prvQueueAccessLogError( __LINE__ ); + } + + /* Allow the other task running this code to run. */ + taskYIELD(); + + /* Have all the expected values been sent to the queue? */ + if( uxValueToTx > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) ) + { + /* Make sure the other high priority task completes its send of + any values below intqNUM_VALUE_TO_LOG. */ + vTaskDelay( intqSHORT_DELAY ); + + vTaskSuspend( xHighPriorityNormallyFullTask2 ); + + if( xWasSuspended == pdTRUE ) + { + /* We would have expected the other high priority task to have + set this back to false by now. */ + prvQueueAccessLogError( __LINE__ ); + } + + /* Set the suspended flag so an error is not logged if the other + task recognises a time out when it is unsuspended. */ + xWasSuspended = pdTRUE; + + /* Check interrupts are also sending. */ + uxInterrupts = 0U; + + /* Start at 1 as we expect position 0 to be unused. */ + for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ ) + { + if( ucNormallyFullReceivedValues[ ux ] == 0 ) + { + /* A value was missing. */ + prvQueueAccessLogError( __LINE__ ); + } + else if( ucNormallyFullReceivedValues[ ux ] == intqSECOND_INTERRUPT ) + { + uxInterrupts++; + } + } + + if( uxInterrupts == 0 ) + { + /* No writes from interrupts were found. Are interrupts + actually running? */ + prvQueueAccessLogError( __LINE__ ); + } + + /* Reset the array ready for the next cycle. */ + memset( ucNormallyFullReceivedValues, 0x00, sizeof( ucNormallyFullReceivedValues ) ); + + uxHighPriorityLoops2++; + uxValueForNormallyFullQueue = 0; + + /* Suspend ourselves, allowing the lower priority task to + actually receive something from the queue. Until now it + will have been prevented from doing so by the higher + priority tasks. The lower priority task will resume us + if it receives something. We will then resume the other + higher priority task. */ + vTaskSuspend( NULL ); + vTaskResume( xHighPriorityNormallyFullTask2 ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prv2ndHigherPriorityNormallyFullTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxValueToTx, ux; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + /* Make sure the queue starts full or near full. >> 1 as there are two + high priority tasks. */ + for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ); + } + + for( ;; ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS ) + { + if( xWasSuspended != pdTRUE ) + { + /* It is ok to time out if the task has been suspended. */ + prvQueueAccessLogError( __LINE__ ); + } + } + + xWasSuspended = pdFALSE; + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void prvLowerPriorityNormallyFullTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxValue, uxTxed = 9999; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + if( xQueueSend( xNormallyFullQueue, &uxTxed, intqONE_TICK_DELAY ) != errQUEUE_FULL ) + { + /* We would only expect to succeed when the higher priority task + is suspended. */ + if( xTaskIsTaskSuspended( xHighPriorityNormallyFullTask1 ) == pdFALSE ) + { + prvQueueAccessLogError( __LINE__ ); + } + + vTaskResume( xHighPriorityNormallyFullTask1 ); + uxLowPriorityLoops2++; + } + else + { + /* Raise our priority while we receive so we can preempt the higher + priority task, and ensure we get the value from the queue. */ + vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 ); + + if( xQueueReceive( xNormallyFullQueue, &uxValue, portMAX_DELAY ) != pdPASS ) + { + prvQueueAccessLogError( __LINE__ ); + } + else + { + prvRecordValue_NormallyFull( uxValue, intqLOW_PRIORITY_TASK ); + } + + vTaskPrioritySet( NULL, intqLOWER_PRIORITY ); + } + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xFirstTimerHandler( void ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, uxRxedValue; +static unsigned portBASE_TYPE uxNextOperation = 0; + + /* Called from a timer interrupt. Perform various read and write + accesses on the queues. */ + + uxNextOperation++; + + if( uxNextOperation & ( unsigned portBASE_TYPE ) 0x01 ) + { + timerNORMALLY_EMPTY_TX(); + timerNORMALLY_EMPTY_TX(); + timerNORMALLY_EMPTY_TX(); + } + else + { + timerNORMALLY_FULL_RX(); + timerNORMALLY_FULL_RX(); + timerNORMALLY_FULL_RX(); + } + + return xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSecondTimerHandler( void ) +{ +unsigned portBASE_TYPE uxRxedValue; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; +static unsigned portBASE_TYPE uxNextOperation = 0; + + /* Called from a timer interrupt. Perform various read and write + accesses on the queues. */ + + uxNextOperation++; + + if( uxNextOperation & ( unsigned portBASE_TYPE ) 0x01 ) + { + timerNORMALLY_EMPTY_TX(); + timerNORMALLY_EMPTY_TX(); + + timerNORMALLY_EMPTY_RX(); + timerNORMALLY_EMPTY_RX(); + } + else + { + timerNORMALLY_FULL_RX(); + timerNORMALLY_FULL_TX(); + timerNORMALLY_FULL_TX(); + timerNORMALLY_FULL_TX(); + timerNORMALLY_FULL_TX(); + } + + return xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + + +portBASE_TYPE xAreIntQueueTasksStillRunning( void ) +{ +static unsigned portBASE_TYPE uxLastHighPriorityLoops1 = 0, uxLastHighPriorityLoops2 = 0, uxLastLowPriorityLoops1 = 0, uxLastLowPriorityLoops2 = 0; + + /* xErrorStatus can be set outside of this function. This function just + checks that all the tasks are still cycling. */ + + if( uxHighPriorityLoops1 == uxLastHighPriorityLoops1 ) + { + /* The high priority 1 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastHighPriorityLoops1 = uxHighPriorityLoops1; + + if( uxHighPriorityLoops2 == uxLastHighPriorityLoops2 ) + { + /* The high priority 2 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastHighPriorityLoops2 = uxHighPriorityLoops2; + + if( uxLowPriorityLoops1 == uxLastLowPriorityLoops1 ) + { + /* The low priority 1 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastLowPriorityLoops1 = uxLowPriorityLoops1; + + if( uxLowPriorityLoops2 == uxLastLowPriorityLoops2 ) + { + /* The low priority 2 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastLowPriorityLoops2 = uxLowPriorityLoops2; + + return xErrorStatus; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/PollQ.c b/third_party/FreeRTOS/Demo/Common/Minimal/PollQ.c new file mode 100644 index 0000000..e3a3cb3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/PollQ.c @@ -0,0 +1,258 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This version of PollQ. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned long. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE +#define pollqQUEUE_SIZE ( 10 ) +#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS ) +#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) ) +#define pollqNO_DELAY ( ( portTickType ) 0 ) +#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 ) +#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 ) + +/* The task that posts the incrementing number onto the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); + +/* The task that empties the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); + +/* Variables that are used to check that the tasks are still running with no +errors. */ +static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; + +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xPolledQueue, ( signed char * ) "Poll_Test_Queue" ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, ( signed char * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( vPolledQueueProducer, ( signed char * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) +{ +unsigned short usValue = ( unsigned short ) 0; +signed portBASE_TYPE xError = pdFALSE, xLoop; + + for( ;; ) + { + for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) + { + /* We should never find the queue full so if we get here there + has been an error. */ + xError = pdTRUE; + } + else + { + if( xError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + portENTER_CRITICAL(); + xPollingProducerCount++; + portEXIT_CRITICAL(); + } + + /* Update the value we are going to post next time around. */ + usValue++; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( pollqPRODUCER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) +{ +unsigned short usData, usExpectedValue = ( unsigned short ) 0; +signed portBASE_TYPE xError = pdFALSE; + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) ) + { + if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + xError = pdTRUE; + + /* Catch-up to the value we received so our next expected + value should again be correct. */ + usExpectedValue = usData; + } + else + { + if( xError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + portENTER_CRITICAL(); + xPollingConsumerCount++; + portEXIT_CRITICAL(); + } + } + + /* Next time round we would expect the number to be one higher. */ + usExpectedValue++; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( pollqCONSUMER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* Check both the consumer and producer poll count to check they have both + been changed since out last trip round. We do not need a critical section + around the check variables as this is called from a higher priority than + the other tasks that access the same variables. */ + if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || + ( xPollingProducerCount == pollqINITIAL_VALUE ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Set the check variables back down so we know if they have been + incremented the next time around. */ + xPollingConsumerCount = pollqINITIAL_VALUE; + xPollingProducerCount = pollqINITIAL_VALUE; + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/QPeek.c b/third_party/FreeRTOS/Demo/Common/Minimal/QPeek.c new file mode 100644 index 0000000..942155c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/QPeek.c @@ -0,0 +1,474 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Tests the behaviour when data is peeked from a queue when there are + * multiple tasks blocked on the queue. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "QPeek.h" + +#define qpeekQUEUE_LENGTH ( 5 ) +#define qpeekNO_BLOCK ( 0 ) +#define qpeekSHORT_DELAY ( 10 ) + +#define qpeekLOW_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define qpeekMEDIUM_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define qpeekHIGH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define qpeekHIGHEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * The following three tasks are used to demonstrate the peeking behaviour. + * Each task is given a different priority to demonstrate the order in which + * tasks are woken as data is peeked from a queue. + */ +static void prvLowPriorityPeekTask( void *pvParameters ); +static void prvMediumPriorityPeekTask( void *pvParameters ); +static void prvHighPriorityPeekTask( void *pvParameters ); +static void prvHighestPriorityPeekTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static volatile portBASE_TYPE xErrorDetected = pdFALSE; + +/* Counter that is incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned portLONG ulLoopCounter = 0; + +/* Handles to the test tasks. */ +xTaskHandle xMediumPriorityTask, xHighPriorityTask, xHighestPriorityTask; +/*-----------------------------------------------------------*/ + +void vStartQueuePeekTasks( void ) +{ +xQueueHandle xQueue; + + /* Create the queue that we are going to use for the test/demo. */ + xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( unsigned portLONG ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xQueue, ( signed portCHAR * ) "QPeek_Test_Queue" ); + + /* Create the demo tasks and pass it the queue just created. We are + passing the queue handle by value so it does not matter that it is declared + on the stack here. */ + xTaskCreate( prvLowPriorityPeekTask, ( signed portCHAR * )"PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityPeekTask, ( signed portCHAR * )"PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask ); + xTaskCreate( prvHighPriorityPeekTask, ( signed portCHAR * )"PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask ); + xTaskCreate( prvHighestPriorityPeekTask, ( signed portCHAR * )"PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask ); +} +/*-----------------------------------------------------------*/ + +static void prvHighestPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + #ifdef USE_STDIO + { + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Queue peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + } + #endif + + for( ;; ) + { + /* Try peeking from the queue. The queue should be empty so we will + block, allowing the high priority task to execute. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we reach here the high and medium priority tasks should still + be blocked on the queue. We unblocked because the low priority task + wrote a value to the queue, which we should have peeked. Peeking the + data (rather than receiving it) will leave the data on the queue, so + the high priority task should then have also been unblocked, but not + yet executed. */ + if( ulValue != 0x11223344 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* Now we are going to actually receive the data, so when the high + priority task runs it will find the queue empty and return to the + blocked state. */ + ulValue = 0; + if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We expected to receive the value. */ + xErrorDetected = pdTRUE; + } + + if( ulValue != 0x11223344 ) + { + /* We did not receive the expected value - which should have been + the same value as was peeked. */ + xErrorDetected = pdTRUE; + } + + /* Now we will block again as the queue is once more empty. The low + priority task can then execute again. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the low priority task should have again written to the + queue. */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* We only peeked the data, so suspending ourselves now should enable + the high priority task to also peek the data. The high priority task + will have been unblocked when we peeked the data as we left the data + in the queue. */ + vTaskSuspend( NULL ); + + + + /* This time we are going to do the same as the above test, but the + high priority task is going to receive the data, rather than peek it. + This means that the medium priority task should never peek the value. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulValue != 0xaabbaabb ) + { + xErrorDetected = pdTRUE; + } + + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + for( ;; ) + { + /* Try peeking from the queue. The queue should be empty so we will + block, allowing the medium priority task to execute. Both the high + and highest priority tasks will then be blocked on the queue. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the highest priority task should have peeked the data + (unblocking this task) then suspended (allowing this task to also peek + the data). */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* We only peeked the data, so suspending ourselves now should enable + the medium priority task to also peek the data. The medium priority task + will have been unblocked when we peeked the data as we left the data + in the queue. */ + vTaskSuspend( NULL ); + + + /* This time we are going actually receive the value, so the medium + priority task will never peek the data - we removed it from the queue. */ + if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulValue != 0xaabbaabb ) + { + xErrorDetected = pdTRUE; + } + + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + for( ;; ) + { + /* Try peeking from the queue. The queue should be empty so we will + block, allowing the low priority task to execute. The highest, high + and medium priority tasks will then all be blocked on the queue. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the high priority task should have peeked the data + (unblocking this task) then suspended (allowing this task to also peek + the data). */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* Just so we know the test is still running. */ + ulLoopCounter++; + + /* Now we can suspend ourselves so the low priority task can execute + again. */ + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + for( ;; ) + { + /* Write some data to the queue. This should unblock the highest + priority task that is waiting to peek data from the queue. */ + ulValue = 0x11223344; + if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* By the time we get here the data should have been removed from + the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* Write another value to the queue, again waking the highest priority + task that is blocked on the queue. */ + ulValue = 0x01234567; + if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* All the other tasks should now have successfully peeked the data. + The data is still in the queue so we should be able to receive it. */ + ulValue = 0; + if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We expected to receive the data. */ + xErrorDetected = pdTRUE; + } + + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + } + + /* Lets just delay a while as this is an intensive test as we don't + want to starve other tests of processing time. */ + vTaskDelay( qpeekSHORT_DELAY ); + + /* Unsuspend the other tasks so we can repeat the test - this time + however not all the other tasks will peek the data as the high + priority task is actually going to remove it from the queue. Send + to front is used just to be different. As the queue is empty it + makes no difference to the result. */ + vTaskResume( xMediumPriorityTask ); + vTaskResume( xHighPriorityTask ); + vTaskResume( xHighestPriorityTask ); + + #if( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + ulValue = 0xaabbaabb; + if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* This time we should find that the queue is empty. The high priority + task actually removed the data rather than just peeking it. */ + if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY ) + { + /* We expected to receive the data. */ + xErrorDetected = pdTRUE; + } + + /* Unsuspend the highest and high priority tasks so we can go back + and repeat the whole thing. The medium priority task should not be + suspended as it was not able to peek the data in this last case. */ + vTaskResume( xHighPriorityTask ); + vTaskResume( xHighestPriorityTask ); + + /* Lets just delay a while as this is an intensive test as we don't + want to starve other tests of processing time. */ + vTaskDelay( qpeekSHORT_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreQueuePeekTasksStillRunning( void ) +{ +static unsigned portLONG ulLastLoopCounter = 0; + + /* If the demo task is still running then we expect the loopcounter to + have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + + /* Errors detected in the task itself will have latched xErrorDetected + to true. */ + + return !xErrorDetected; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/TimerDemo.c b/third_party/FreeRTOS/Demo/Common/Minimal/TimerDemo.c new file mode 100644 index 0000000..509c690 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/TimerDemo.c @@ -0,0 +1,1060 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Tests the behaviour of timers. Some timers are created before the scheduler + * is started, and some after. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Demo program include files. */ +#include "TimerDemo.h" + +#if ( configTIMER_TASK_PRIORITY < 1 ) + #error configTIMER_TASK_PRIORITY must be set to at least 1 for this test/demo to function correctly. +#endif + +#define tmrdemoDONT_BLOCK ( ( portTickType ) 0 ) +#define tmrdemoONE_SHOT_TIMER_PERIOD ( xBasePeriod * ( portTickType ) 3 ) +#define trmdemoNUM_TIMER_RESETS ( ( unsigned char ) 10 ) + +/*-----------------------------------------------------------*/ + +/* The callback functions used by the timers. These each increment a counter +to indicate which timer has expired. The auto-reload timers that are used by +the test task (as opposed to being used from an ISR) all share the same +prvAutoReloadTimerCallback() callback function, and use the ID of the +pxExpiredTimer parameter passed into that function to know which counter to +increment. The other timers all have their own unique callback function and +simply increment their counters without using the callback function parameter. */ +static void prvAutoReloadTimerCallback( xTimerHandle pxExpiredTimer ); +static void prvOneShotTimerCallback( xTimerHandle pxExpiredTimer ); +static void prvTimerTestTask( void *pvParameters ); +static void prvISRAutoReloadTimerCallback( xTimerHandle pxExpiredTimer ); +static void prvISROneShotTimerCallback( xTimerHandle pxExpiredTimer ); + +/* The test functions used by the timer test task. These manipulate the auto +reload and one shot timers in various ways, then delay, then inspect the timers +to ensure they have behaved as expected. */ +static void prvTest1_CreateTimersWithoutSchedulerRunning( void ); +static void prvTest2_CheckTaskAndTimersInitialState( void ); +static void prvTest3_CheckAutoReloadExpireRates( void ); +static void prvTest4_CheckAutoReloadTimersCanBeStopped( void ); +static void prvTest5_CheckBasicOneShotTimerBehaviour( void ); +static void prvTest6_CheckAutoReloadResetBehaviour( void ); +static void prvResetStartConditionsForNextIteration( void ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdFAIL should any unexpected behaviour be +detected in any of the demo tests. */ +static volatile portBASE_TYPE xTestStatus = pdPASS; + +/* Counter that is incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned long ulLoopCounter = 0; + +/* A set of auto reload timers - each of which use the same callback function. +The callback function uses the timer ID to index into, and then increment, a +counter in the ucAutoReloadTimerCounters[] array. The auto reload timers +referenced from xAutoReloadTimers[] are used by the prvTimerTestTask task. */ +static xTimerHandle xAutoReloadTimers[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 }; +static unsigned char ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 }; + +/* The one shot timer is configured to use a callback function that increments +ucOneShotTimerCounter each time it gets called. */ +static xTimerHandle xOneShotTimer = NULL; +static unsigned char ucOneShotTimerCounter = ( unsigned char ) 0; + +/* The ISR reload timer is controlled from the tick hook to exercise the timer +API functions that can be used from an ISR. It is configured to increment +ucISRReloadTimerCounter each time its callback function is executed. */ +static xTimerHandle xISRAutoReloadTimer = NULL; +static unsigned char ucISRAutoReloadTimerCounter = ( unsigned char ) 0; + +/* The ISR one shot timer is controlled from the tick hook to exercise the timer +API functions that can be used from an ISR. It is configured to increment +ucISRReloadTimerCounter each time its callback function is executed. */ +static xTimerHandle xISROneShotTimer = NULL; +static unsigned char ucISROneShotTimerCounter = ( unsigned char ) 0; + +/* The period of all the timers are a multiple of the base period. The base +period is configured by the parameter to vStartTimerDemoTask(). */ +static portTickType xBasePeriod = 0; + +/*-----------------------------------------------------------*/ + +void vStartTimerDemoTask( portTickType xBasePeriodIn ) +{ + /* Start with the timer and counter arrays clear - this is only necessary + where the compiler does not clear them automatically on start up. */ + memset( ucAutoReloadTimerCounters, 0x00, sizeof( ucAutoReloadTimerCounters ) ); + memset( xAutoReloadTimers, 0x00, sizeof( xAutoReloadTimers ) ); + + /* Store the period from which all the timer periods will be generated from + (multiples of). */ + xBasePeriod = xBasePeriodIn; + + /* Create a set of timers for use by this demo/test. */ + prvTest1_CreateTimersWithoutSchedulerRunning(); + + /* Create the task that will control and monitor the timers. This is + created at a lower priority than the timer service task to ensure, as + far as it is concerned, commands on timers are actioned immediately + (sending a command to the timer service task will unblock the timer service + task, which will then preempt this task). */ + if( xTestStatus != pdFAIL ) + { + xTaskCreate( prvTimerTestTask, ( signed portCHAR * ) "Tmr Tst", configMINIMAL_STACK_SIZE, NULL, configTIMER_TASK_PRIORITY - 1, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTimerTestTask( void *pvParameters ) +{ + ( void ) pvParameters; + + /* Create a one-shot timer for use later on in this test. */ + xOneShotTimer = xTimerCreate( ( const signed char * ) "Oneshot Timer",/* Text name to facilitate debugging. The kernel does not use this itself. */ + tmrdemoONE_SHOT_TIMER_PERIOD, /* The period for the timer. */ + pdFALSE, /* Don't auto-reload - hence a one shot timer. */ + ( void * ) 0, /* The timer identifier. In this case this is not used as the timer has its own callback. */ + prvOneShotTimerCallback ); /* The callback to be called when the timer expires. */ + + if( xOneShotTimer == NULL ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + + /* Ensure all the timers are in their expected initial state. This + depends on the timer service task having a higher priority than this task. */ + prvTest2_CheckTaskAndTimersInitialState(); + + for( ;; ) + { + /* Check the auto reload timers expire at the expected/correct rates. */ + prvTest3_CheckAutoReloadExpireRates(); + + /* Check the auto reload timers can be stopped correctly, and correctly + report their state. */ + prvTest4_CheckAutoReloadTimersCanBeStopped(); + + /* Check the one shot timer only calls its callback once after it has been + started, and that it reports its state correctly. */ + prvTest5_CheckBasicOneShotTimerBehaviour(); + + /* Check timer reset behaviour. */ + prvTest6_CheckAutoReloadResetBehaviour(); + + /* Start the timers again to restart all the tests over again. */ + prvResetStartConditionsForNextIteration(); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the created task is still running and has not +detected any errors. */ +portBASE_TYPE xAreTimerDemoTasksStillRunning( portTickType xCycleFrequency ) +{ +static unsigned long ulLastLoopCounter = 0UL; +portTickType xMaxBlockTimeUsedByTheseTests, xLoopCounterIncrementTimeMax; +static portTickType xIterationsWithoutCounterIncrement = ( portTickType ) 0, xLastCycleFrequency; + + if( xLastCycleFrequency != xCycleFrequency ) + { + /* The cycle frequency has probably become much faster due to an error + elsewhere. Start counting Iterations again. */ + xIterationsWithoutCounterIncrement = ( portTickType ) 0; + xLastCycleFrequency = xCycleFrequency; + } + + /* Calculate the maximum number of times that it is permissible for this + function to be called without ulLoopCounter being incremented. This is + necessary because the tests in this file block for extended periods, and the + block period might be longer than the time between calls to this function. */ + xMaxBlockTimeUsedByTheseTests = ( ( portTickType ) configTIMER_QUEUE_LENGTH ) * xBasePeriod; + xLoopCounterIncrementTimeMax = xMaxBlockTimeUsedByTheseTests / xCycleFrequency; + + /* If the demo task is still running then we expect the loopcounter to + have incremented every xLoopCounterIncrementTimeMax calls. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xIterationsWithoutCounterIncrement++; + if( xIterationsWithoutCounterIncrement > xLoopCounterIncrementTimeMax ) + { + /* The tests appear to be no longer running (stalled). */ + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else + { + /* ulLoopCounter changed, so the count of times this function was called + without a change can be reset to zero. */ + xIterationsWithoutCounterIncrement = ( portTickType ) 0; + } + + ulLastLoopCounter = ulLoopCounter; + + /* Errors detected in the task itself will have latched xTestStatus + to pdFAIL. */ + + return xTestStatus; +} +/*-----------------------------------------------------------*/ + +static void prvTest1_CreateTimersWithoutSchedulerRunning( void ) +{ +unsigned portBASE_TYPE xTimer; + + for( xTimer = 0; xTimer < configTIMER_QUEUE_LENGTH; xTimer++ ) + { + /* As the timer queue is not yet full, it should be possible to both create + and start a timer. These timers are being started before the scheduler has + been started, so their block times should get set to zero within the timer + API itself. */ + xAutoReloadTimers[ xTimer ] = xTimerCreate( ( const signed char * )"FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */ + ( ( xTimer + ( portTickType ) 1 ) * xBasePeriod ),/* The period for the timer. The plus 1 ensures a period of zero is not specified. */ + pdTRUE, /* Auto-reload is set to true. */ + ( void * ) xTimer, /* An identifier for the timer as all the auto reload timers use the same callback. */ + prvAutoReloadTimerCallback ); /* The callback to be called when the timer expires. */ + + if( xAutoReloadTimers[ xTimer ] == NULL ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + else + { + /* The scheduler has not yet started, so the block period of + portMAX_DELAY should just get set to zero in xTimerStart(). Also, + the timer queue is not yet full so xTimerStart() should return + pdPASS. */ + if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) != pdPASS ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + } + + /* The timers queue should now be full, so it should be possible to create + another timer, but not possible to start it (the timer queue will not get + drained until the scheduler has been started. */ + xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] = xTimerCreate( ( const signed char * ) "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */ + ( configTIMER_QUEUE_LENGTH * xBasePeriod ), /* The period for the timer. */ + pdTRUE, /* Auto-reload is set to true. */ + ( void * ) xTimer, /* An identifier for the timer as all the auto reload timers use the same callback. */ + prvAutoReloadTimerCallback ); /* The callback executed when the timer expires. */ + + if( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] == NULL ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + else + { + if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) == pdPASS ) + { + /* This time it would not be expected that the timer could be + started at this point. */ + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + /* Create the timers that are used from the tick interrupt to test the timer + API functions that can be called from an ISR. */ + xISRAutoReloadTimer = xTimerCreate( ( const signed char * ) "ISR AR", /* The text name given to the timer. */ + 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */ + pdTRUE, /* This is an auto reload timer. */ + ( void * ) NULL, /* The identifier is not required. */ + prvISRAutoReloadTimerCallback ); /* The callback that is executed when the timer expires. */ + + xISROneShotTimer = xTimerCreate( ( const signed char * ) "ISR OS", /* The text name given to the timer. */ + 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */ + pdFALSE, /* This is a one shot timer. */ + ( void * ) NULL, /* The identifier is not required. */ + prvISROneShotTimerCallback ); /* The callback that is executed when the timer expires. */ + + if( ( xISRAutoReloadTimer == NULL ) || ( xISROneShotTimer == NULL ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTest2_CheckTaskAndTimersInitialState( void ) +{ +unsigned char ucTimer; + + /* Ensure all the timers are in their expected initial state. This depends + on the timer service task having a higher priority than this task. + + auto reload timers 0 to ( configTIMER_QUEUE_LENGTH - 1 ) should now be active, + and auto reload timer configTIMER_QUEUE_LENGTH should not yet be active (it + could not be started prior to the scheduler being started when it was + created). */ + for( ucTimer = 0; ucTimer < ( unsigned char ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTest3_CheckAutoReloadExpireRates( void ) +{ +unsigned char ucMaxAllowableValue, ucMinAllowableValue, ucTimer; +portTickType xBlockPeriod, xTimerPeriod, xExpectedNumber; + + /* Check the auto reload timers expire at the expected rates. */ + + + /* Delaying for configTIMER_QUEUE_LENGTH * xBasePeriod ticks should allow + all the auto reload timers to expire at least once. */ + xBlockPeriod = ( ( portTickType ) configTIMER_QUEUE_LENGTH ) * xBasePeriod; + vTaskDelay( xBlockPeriod ); + + /* Check that all the auto reload timers have called their callback + function the expected number of times. */ + for( ucTimer = 0; ucTimer < ( unsigned char ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + /* The expected number of expiries is equal to the block period divided + by the timer period. */ + xTimerPeriod = ( ( ( portTickType ) ucTimer + ( portTickType ) 1 ) * xBasePeriod ); + xExpectedNumber = xBlockPeriod / xTimerPeriod; + + ucMaxAllowableValue = ( ( unsigned char ) xExpectedNumber ) ; + ucMinAllowableValue = ( ( unsigned char ) xExpectedNumber - ( unsigned char ) 1 ); + + if( ( ucAutoReloadTimerCounters[ ucTimer ] < ucMinAllowableValue ) || + ( ucAutoReloadTimerCounters[ ucTimer ] > ucMaxAllowableValue ) + ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the + check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest4_CheckAutoReloadTimersCanBeStopped( void ) +{ +unsigned char ucTimer; + + /* Check the auto reload timers can be stopped correctly, and correctly + report their state. */ + + /* Stop all the active timers. */ + for( ucTimer = 0; ucTimer < ( unsigned char ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + /* The timer has not been stopped yet! */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now stop the timer. This will appear to happen immediately to + this task because this task is running at a priority below the + timer service task. */ + xTimerStop( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK ); + + /* The timer should now be inactive. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + taskENTER_CRITICAL(); + { + /* The timer in array position configTIMER_QUEUE_LENGTH should not + be active. The critical section is used to ensure the timer does + not call its callback between the next line running and the array + being cleared back to zero, as that would mask an error condition. */ + if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH ] != ( unsigned char ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Clear the timer callback count. */ + memset( ( void * ) ucAutoReloadTimerCounters, 0, sizeof( ucAutoReloadTimerCounters ) ); + } + taskEXIT_CRITICAL(); + + /* The timers are now all inactive, so this time, after delaying, none + of the callback counters should have incremented. */ + vTaskDelay( ( ( portTickType ) configTIMER_QUEUE_LENGTH ) * xBasePeriod ); + for( ucTimer = 0; ucTimer < ( unsigned char ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + if( ucAutoReloadTimerCounters[ ucTimer ] != ( unsigned char ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so + the check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest5_CheckBasicOneShotTimerBehaviour( void ) +{ + /* Check the one shot timer only calls its callback once after it has been + started, and that it reports its state correctly. */ + + /* The one shot timer should not be active yet. */ + if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucOneShotTimerCounter != ( unsigned char ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Start the one shot timer and check that it reports its state correctly. */ + xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK ); + if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Delay for three times as long as the one shot timer period, then check + to ensure it has only called its callback once, and is now not in the + active state. */ + vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD * ( portTickType ) 3 ); + + if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucOneShotTimerCounter != ( unsigned char ) 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + else + { + /* Reset the one shot timer callback count. */ + ucOneShotTimerCounter = ( unsigned char ) 0; + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the + check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest6_CheckAutoReloadResetBehaviour( void ) +{ +unsigned char ucTimer; + + /* Check timer reset behaviour. */ + + /* Restart the one shot timer and check it reports its status correctly. */ + xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK ); + if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Restart one of the auto reload timers and check that it reports its + status correctly. */ + xTimerStart( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK ); + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + for( ucTimer = 0; ucTimer < trmdemoNUM_TIMER_RESETS; ucTimer++ ) + { + /* Delay for half as long as the one shot timer period, then reset it. + It should never expire while this is done, so its callback count should + never increment. */ + vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD / 2 ); + + /* Check both running timers are still active, but have not called their + callback functions. */ + if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucOneShotTimerCounter != ( unsigned char ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] != ( unsigned char ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Reset both running timers. */ + xTimerReset( xOneShotTimer, tmrdemoDONT_BLOCK ); + xTimerReset( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK ); + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so + the check task knows this task is still running. */ + ulLoopCounter++; + } + } + + /* Finally delay long enough for both running timers to expire. */ + vTaskDelay( ( ( portTickType ) configTIMER_QUEUE_LENGTH ) * xBasePeriod ); + + /* The timers were not reset during the above delay period so should now + both have called their callback functions. */ + if( ucOneShotTimerCounter != ( unsigned char ) 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] == 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* The one shot timer should no longer be active, while the auto reload + timer should still be active. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( xTimerIsTimerActive( xOneShotTimer ) == pdTRUE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Stop the auto reload timer again. */ + xTimerStop( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK ); + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Clear the timer callback counts, ready for another iteration of these + tests. */ + ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] = ( unsigned char ) 0; + ucOneShotTimerCounter = ( unsigned char ) 0; + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the check + task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvResetStartConditionsForNextIteration( void ) +{ +unsigned char ucTimer; + + /* Start the timers again to start all the tests over again. */ + + /* Start the timers again. */ + for( ucTimer = 0; ucTimer < ( unsigned char ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + /* The timer has not been started yet! */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now start the timer. This will appear to happen immediately to + this task because this task is running at a priority below the timer + service task. */ + xTimerStart( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK ); + + /* The timer should now be active. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the + check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +void vTimerPeriodicISRTests( void ) +{ +static portTickType uxTick = ( portTickType ) -1; + +/* The xHigherPriorityTaskWoken parameter is not used in this case as this +function is called from the tick hook anyway. However the API required it +to be present. */ +signed portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; +portTickType xMargin; + + if( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) ) + { + /* The timer service task is not the highest priority task, so it cannot + be assumed that timings will be exact. Timers should never call their + callback before their expiry time, but a margin is permissible for calling + their callback after their expiry time. If exact timing is required then + configTIMER_TASK_PRIORITY must be set to ensure the timer service task + is the highest priority task in the system. */ + xMargin = 5; + } + else + { + xMargin = 1; + } + + /* This test is called from the tick ISR even when the scheduler is suspended. + Therefore, it is possible for the xTickCount to be temporarily less than the + uxTicks count maintained in this function. That can result in calculated + unblock times being too short, as this function is not called as missed ticks + (ticks that occur while the scheduler is suspended) are unwound to re-instate + the real tick value. Therefore, if this happens, just abandon the test + and start again. */ + if( xTaskGetSchedulerState() != taskSCHEDULER_RUNNING ) + { + uxTick = ( portTickType ) -1; + } + else + { + uxTick++; + } + + if( uxTick == 0 ) + { + /* The timers will have been created, but not started. Start them + now by setting their period. */ + ucISRAutoReloadTimerCounter = 0; + ucISROneShotTimerCounter = 0; + xTimerChangePeriodFromISR( xISRAutoReloadTimer, xBasePeriod, &xHigherPriorityTaskWoken ); + xTimerChangePeriodFromISR( xISROneShotTimer, xBasePeriod, &xHigherPriorityTaskWoken ); + } + else if( uxTick == xBasePeriod ) + { + /* Neither timer should have expired yet. */ + if( ( ucISRAutoReloadTimerCounter != 0 ) || ( ucISROneShotTimerCounter != 0 ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( xBasePeriod + xMargin ) ) + { + /* Both timers should now have expired once. The auto reload timer will + still be active, but the one shot timer should now have stopped. */ + if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( 2 * xBasePeriod ) ) + { + /* The auto reload timer will still be active, but the one shot timer + should now have stopped - however, at this time neither of the timers + should have expired again since the last test. */ + if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 2 * xBasePeriod ) + xMargin ) ) + { + /* The auto reload timer will still be active, but the one shot timer + should now have stopped. At this time the auto reload timer should have + expired again, but the one shot timer count should not have changed. */ + if( ucISRAutoReloadTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 2 * xBasePeriod ) + ( xBasePeriod >> ( portTickType ) 2U ) ) ) + { + /* The auto reload timer will still be active, but the one shot timer + should now have stopped. Again though, at this time, neither timer call + back should have been called since the last test. */ + if( ucISRAutoReloadTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( 3 * xBasePeriod ) ) + { + /* Start the one shot timer again. */ + xTimerStartFromISR( xISROneShotTimer, &xHigherPriorityTaskWoken ); + } + else if( uxTick == ( ( 3 * xBasePeriod ) + xMargin ) ) + { + /* The auto reload timer and one shot timer will be active. At + this time the auto reload timer should have expired again, but the one + shot timer count should not have changed yet. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now stop the auto reload timer. The one shot timer was started + a few ticks ago. */ + xTimerStopFromISR( xISRAutoReloadTimer, &xHigherPriorityTaskWoken ); + } + else if( uxTick == ( 4 * xBasePeriod ) ) + { + /* The auto reload timer is now stopped, and the one shot timer is + active, but at this time neither timer should have expired since the + last test. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 4 * xBasePeriod ) + xMargin ) ) + { + /* The auto reload timer is now stopped, and the one shot timer is + active. The one shot timer should have expired again, but the auto + reload timer should not have executed its callback. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 8 * xBasePeriod ) + xMargin ) ) + { + /* The auto reload timer is now stopped, and the one shot timer has + already expired and then stopped itself. Both callback counters should + not have incremented since the last test. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now reset the one shot timer. */ + xTimerResetFromISR( xISROneShotTimer, &xHigherPriorityTaskWoken ); + } + else if( uxTick == ( 9 * xBasePeriod ) ) + { + /* Only the one shot timer should be running, but it should not have + expired since the last test. Check the callback counters have not + incremented, then reset the one shot timer again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + xTimerResetFromISR( xISROneShotTimer, &xHigherPriorityTaskWoken ); + } + else if( uxTick == ( 10 * xBasePeriod ) ) + { + /* Only the one shot timer should be running, but it should not have + expired since the last test. Check the callback counters have not + incremented, then reset the one shot timer again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + xTimerResetFromISR( xISROneShotTimer, &xHigherPriorityTaskWoken ); + } + else if( uxTick == ( 11 * xBasePeriod ) ) + { + /* Only the one shot timer should be running, but it should not have + expired since the last test. Check the callback counters have not + incremented, then reset the one shot timer once again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + xTimerResetFromISR( xISROneShotTimer, &xHigherPriorityTaskWoken ); + } + else if( uxTick == ( ( 12 * xBasePeriod ) + xMargin ) ) + { + /* Only the one shot timer should have been running and this time it + should have expired. Check its callback count has been incremented. + The auto reload timer is still not running so should still have the same + count value. This time the one shot timer is not reset so should not + restart from its expiry period again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( 15 * xBasePeriod ) ) + { + /* Neither timer should be running now. Check neither callback count + has incremented, then go back to the start to run these tests all + over again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + uxTick = ( portTickType ) -1; + } +} +/*-----------------------------------------------------------*/ + +/*** Timer callback functions are defined below here. ***/ + +static void prvAutoReloadTimerCallback( xTimerHandle pxExpiredTimer ) +{ +unsigned long ulTimerID; + + ulTimerID = ( unsigned long ) pvTimerGetTimerID( pxExpiredTimer ); + if( ulTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) ) + { + ( ucAutoReloadTimerCounters[ ulTimerID ] )++; + } + else + { + /* The timer ID appears to be unexpected (invalid). */ + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } +} +/*-----------------------------------------------------------*/ + +static void prvOneShotTimerCallback( xTimerHandle pxExpiredTimer ) +{ + /* The parameter is not used in this case as only one timer uses this + callback function. */ + ( void ) pxExpiredTimer; + + ucOneShotTimerCounter++; +} +/*-----------------------------------------------------------*/ + +static void prvISRAutoReloadTimerCallback( xTimerHandle pxExpiredTimer ) +{ + /* The parameter is not used in this case as only one timer uses this + callback function. */ + ( void ) pxExpiredTimer; + + ucISRAutoReloadTimerCounter++; +} +/*-----------------------------------------------------------*/ + +static void prvISROneShotTimerCallback( xTimerHandle pxExpiredTimer ) +{ + /* The parameter is not used in this case as only one timer uses this + callback function. */ + ( void ) pxExpiredTimer; + + ucISROneShotTimerCounter++; +} +/*-----------------------------------------------------------*/ + + + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/blocktim.c b/third_party/FreeRTOS/Demo/Common/Minimal/blocktim.c new file mode 100644 index 0000000..cef2ba6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/blocktim.c @@ -0,0 +1,505 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains some test scenarios that ensure tasks do not exit queue + * send or receive functions prematurely. A description of the tests is + * included within the code. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "blocktim.h" + +/* Task priorities. Allow these to be overridden. */ +#ifndef bktPRIMARY_PRIORITY + #define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#endif + +#ifndef bktSECONDARY_PRIORITY + #define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#endif + +/* Task behaviour. */ +#define bktQUEUE_LENGTH ( 5 ) +#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS ) +#define bktPRIMARY_BLOCK_TIME ( 10 ) +#define bktALLOWABLE_MARGIN ( 15 ) +#define bktTIME_TO_BLOCK ( 175 ) +#define bktDONT_BLOCK ( ( portTickType ) 0 ) +#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 ) + +/* The queue on which the tasks block. */ +static xQueueHandle xTestQueue; + +/* Handle to the secondary task is required by the primary task for calls +to vTaskSuspend/Resume(). */ +static xTaskHandle xSecondary; + +/* Used to ensure that tasks are still executing without error. */ +static volatile portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0; +static volatile portBASE_TYPE xErrorOccurred = pdFALSE; + +/* Provides a simple mechanism for the primary task to know when the +secondary task has executed. */ +static volatile unsigned portBASE_TYPE xRunIndicator; + +/* The two test tasks. Their behaviour is commented within the files. */ +static void vPrimaryBlockTimeTestTask( void *pvParameters ); +static void vSecondaryBlockTimeTestTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +void vCreateBlockTimeTasks( void ) +{ + /* Create the queue on which the two tasks block. */ + xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xTestQueue, ( signed char * ) "Block_Time_Queue" ); + + /* Create the two test tasks. */ + xTaskCreate( vPrimaryBlockTimeTestTask, ( signed char * )"BTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL ); + xTaskCreate( vSecondaryBlockTimeTestTask, ( signed char * )"BTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary ); +} +/*-----------------------------------------------------------*/ + +static void vPrimaryBlockTimeTestTask( void *pvParameters ) +{ +portBASE_TYPE xItem, xData; +portTickType xTimeWhenBlocking; +portTickType xTimeToBlock, xBlockedTime; + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 + + Simple block time wakeup test on queue receives. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is empty. Attempt to read from the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = ( portTickType ) ( bktPRIMARY_BLOCK_TIME << xItem ); + + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + /********************************************************************* + Test 2 + + Simple block time wakeup test on queue sends. + + First fill the queue. It should be empty so all sends should pass. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is full. Attempt to write to the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = ( portTickType ) ( bktPRIMARY_BLOCK_TIME << xItem ); + + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + /********************************************************************* + Test 3 + + Wake the other task, it will block attempting to post to the queue. + When we read from the queue the other task will wake, but before it + can run we will post to the queue again. When the other task runs it + will find the queue still full, even though it was woken. It should + recognise that its block time has not expired and return to block for + the remains of its block time. + + Wake the other task so it blocks attempting to post to the already + full queue. */ + xRunIndicator = 0; + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + /* The other task has not yet executed. */ + vTaskDelay( bktSHORT_WAIT ); + } + /* Make sure the other task is blocked on the queue. */ + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we make space on the queue the other task should wake + but not execute as this task has higher priority. */ + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now fill the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + full ourselves, and the other task have set xRunIndicator. */ + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + + /* Set the priority back down. */ + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + + /********************************************************************* + Test 4 + + As per test 3 - but with the send and receive the other way around. + The other task blocks attempting to read from the queue. + + Empty the queue. We should find that it is full. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Wake the other task so it blocks attempting to read from the + already empty queue. */ + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we place an item on the queue the other task should + wake but not execute as this task has higher priority. */ + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now empty the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + empty ourselves, and the other task would be suspended. */ + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + + xPrimaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void vSecondaryBlockTimeTestTask( void *pvParameters ) +{ +portTickType xTimeWhenBlocking, xBlockedTime; +portBASE_TYPE xData; + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 and 2 + + This task does does not participate in these tests. */ + vTaskSuspend( NULL ); + + /********************************************************************* + Test 3 + + The first thing we do is attempt to read from the queue. It should be + full so we block. Note the time before we block so we can check the + wake time is as per that expected. */ + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not sent + anything to the queue. */ + xData = 0; + xRunIndicator = bktRUN_INDICATOR; + if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we inside the send function? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as + soon as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Suspend ready for test 3. */ + xRunIndicator = bktRUN_INDICATOR; + vTaskSuspend( NULL ); + + /********************************************************************* + Test 4 + + As per test three, but with the send and receive reversed. */ + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xRunIndicator = bktRUN_INDICATOR; + if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as soon + as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + xRunIndicator = bktRUN_INDICATOR; + + xSecondaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void ) +{ +static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0; +portBASE_TYPE xReturn = pdPASS; + + /* Have both tasks performed at least one cycle since this function was + last called? */ + if( xPrimaryCycles == xLastPrimaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xSecondaryCycles == xLastSecondaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + + xLastSecondaryCycleCount = xSecondaryCycles; + xLastPrimaryCycleCount = xPrimaryCycles; + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/comtest.c b/third_party/FreeRTOS/Demo/Common/Minimal/comtest.c new file mode 100644 index 0000000..3295535 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/comtest.c @@ -0,0 +1,303 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This version of comtest. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that operate on an interrupt driven serial port. A + * loopback connector should be used so that everything that is transmitted is + * also received. The serial port does not use any flow control. On a + * standard 9way 'D' connector pins two and three should be connected together. + * + * The first task posts a sequence of characters to the Tx queue, toggling an + * LED on each successful post. At the end of the sequence it sleeps for a + * pseudo-random period before resending the same sequence. + * + * The UART Tx end interrupt is enabled whenever data is available in the Tx + * queue. The Tx end ISR removes a single character from the Tx queue and + * passes it to the UART for transmission. + * + * The second task blocks on the Rx queue waiting for a character to become + * available. When the UART Rx end interrupt receives a character it places + * it in the Rx queue, waking the second task. The second task checks that the + * characters removed from the Rx queue form the same sequence as those posted + * to the Tx queue, and toggles an LED for each correct character. + * + * The receiving task is spawned with a higher priority than the transmitting + * task. The receiver will therefore wake every time a character is + * transmitted so neither the Tx or Rx queue should ever hold more than a few + * characters. + * + */ + +/* Scheduler include files. */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "partest.h" + +#define comSTACK_SIZE configMINIMAL_STACK_SIZE +#define comTX_LED_OFFSET ( 0 ) +#define comRX_LED_OFFSET ( 1 ) +#define comTOTAL_PERMISSIBLE_ERRORS ( 2 ) + +/* The Tx task will transmit the sequence of characters at a pseudo random +interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 ) +#define comOFFSET_TIME ( ( portTickType ) 3 ) + +/* We should find that each character can be queued for Tx immediately and we +don't have to block to send. */ +#define comNO_BLOCK ( ( portTickType ) 0 ) + +/* The Rx task will block on the Rx queue for a long period. */ +#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff ) + +/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */ +#define comFIRST_BYTE ( 'A' ) +#define comLAST_BYTE ( 'X' ) + +#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 ) +#define comINITIAL_RX_COUNT_VALUE ( 0 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort = NULL; + +/* The transmit task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters ); + +/* The receive task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters ); + +/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will +toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED +( uxBaseLED + comTX_LED_OFFSET ). */ +static unsigned portBASE_TYPE uxBaseLED = 0; + +/* Check variable used to ensure no error have occurred. The Rx task will +increment this variable after every successfully received sequence. If at any +time the sequence is incorrect the the variable will stop being incremented. */ +static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE; + +/*-----------------------------------------------------------*/ + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED ) +{ + /* Initialise the com port then spawn the Rx and Tx tasks. */ + uxBaseLED = uxLED; + xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN ); + + /* The Tx task is spawned with a lower priority than the Rx task. */ + xTaskCreate( vComTxTask, ( signed char * ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL ); + xTaskCreate( vComRxTask, ( signed char * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComTxTask, pvParameters ) +{ +signed char cByteToSend; +portTickType xTimeToWait; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Simply transmit a sequence of characters from comFIRST_BYTE to + comLAST_BYTE. */ + for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ ) + { + if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS ) + { + vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE ); + + /* We have posted all the characters in the string - wait before + re-sending. Wait a pseudo-random time as this will provide a better + test. */ + xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComRxTask, pvParameters ) +{ +signed char cExpectedByte, cByteRxed; +portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* We expect to receive the characters from comFIRST_BYTE to + comLAST_BYTE in an incrementing order. Loop to receive each byte. */ + for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ ) + { + /* Block on the queue that contains received bytes until a byte is + available. */ + if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) ) + { + /* Was this the byte we were expecting? If so, toggle the LED, + otherwise we are out on sync and should break out of the loop + until the expected character sequence is about to restart. */ + if( cByteRxed == cExpectedByte ) + { + vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); + } + else + { + xResyncRequired = pdTRUE; + break; /*lint !e960 Non-switch break allowed. */ + } + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE ); + + /* Did we break out of the loop because the characters were received in + an unexpected order? If so wait here until the character sequence is + about to restart. */ + if( xResyncRequired == pdTRUE ) + { + while( cByteRxed != comLAST_BYTE ) + { + /* Block until the next char is available. */ + xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ); + } + + /* Note that an error occurred which caused us to have to resync. + We use this to stop incrementing the loop counter so + sAreComTestTasksStillRunning() will return false - indicating an + error. */ + xErrorOccurred++; + + /* We have now resynced with the Tx task and can continue. */ + xResyncRequired = pdFALSE; + } + else + { + if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS ) + { + /* Increment the count of successful loops. As error + occurring (i.e. an unexpected character being received) will + prevent this counter being incremented for the rest of the + execution. Don't worry about mutual exclusion on this + variable - it doesn't really matter as we just want it + to change. */ + uxRxLoops++; + } + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* If the count of successful reception loops has not changed than at + some time an error occurred (i.e. a character was received out of sequence) + and we will return false. */ + if( uxRxLoops == comINITIAL_RX_COUNT_VALUE ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Reset the count of successful Rx loops. When this function is called + again we expect this to have been incremented. */ + uxRxLoops = comINITIAL_RX_COUNT_VALUE; + + return xReturn; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/comtest_strings.c b/third_party/FreeRTOS/Demo/Common/Minimal/comtest_strings.c new file mode 100644 index 0000000..11b80c4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/comtest_strings.c @@ -0,0 +1,349 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Creates a task and a timer that operate on an interrupt driven serial port. + * This demo assumes that the characters transmitted on a port will also be + * received on the same port. Therefore, the UART must either be connected to + * an echo server, or the uart connector must have a loopback connector fitted. + * See http://www.serialporttool.com/CommEcho.htm for a suitable echo server + * for Windows hosts. + * + * The timer sends a string to the UART, toggles an LED, then resets itself by + * changing its own period. The period is calculated as a pseudo random number + * between comTX_MAX_BLOCK_TIME and comTX_MIN_BLOCK_TIME. + * + * The task blocks on an Rx queue waiting for a character to become available. + * Received characters are checked to ensure they match those transmitted by the + * Tx timer. An error is latched if characters are missing, incorrect, or + * arrive too slowly. + * + * How characters are actually transmitted and received is port specific. Demos + * that include this test/demo file will provide example drivers. The Tx timer + * executes in the context of the timer service (daemon) task, and must + * therefore never attempt to block. + * + */ + +/* Scheduler include files. */ +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +#ifndef configUSE_TIMERS + #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h. +#endif + +#if configUSE_TIMERS != 1 + #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h. +#endif + + +/* Demo program include files. */ +#include "serial.h" +#include "comtest_strings.h" +#include "partest.h" + +/* The size of the stack given to the Rx task. */ +#define comSTACK_SIZE configMINIMAL_STACK_SIZE + +/* See the comment above the declaraction of the uxBaseLED variable. */ +#define comTX_LED_OFFSET ( 0 ) +#define comRX_LED_OFFSET ( 1 ) + +/* The Tx timer transmits the sequence of characters at a pseudo random +interval that is capped between comTX_MAX_BLOCK_TIME and +comTX_MIN_BLOCK_TIME. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 ) +#define comOFFSET_TIME ( ( portTickType ) 3 ) + +/* States for the simple state machine implemented in the Rx task. */ +#define comtstWAITING_START_OF_STRING 0 +#define comtstWAITING_END_OF_STRING 1 + +/* A short delay in ticks - this delay is used to allow the Rx queue to fill up +a bit so more than one character can be processed at a time. This is relative +to comTX_MIN_BLOCK_TIME to ensure it is never longer than the shortest gap +between transmissions. It could be worked out more scientifically from the +baud rate being used. */ +#define comSHORT_DELAY ( comTX_MIN_BLOCK_TIME >> ( portTickType ) 2 ) + +/* The string that is transmitted and received. */ +#define comTRANSACTED_STRING "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ1234567890" + +/* A block time of 0 simply means "don't block". */ +#define comtstDONT_BLOCK ( portTickType ) 0 + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort = NULL; + +/* The callback function allocated to the transmit timer, as described in the +comments at the top of this file. */ +static void prvComTxTimerCallback( xTimerHandle xTimer ); + +/* The receive task as described in the comments at the top of this file. */ +static void vComRxTask( void *pvParameters ); + +/* The Rx task will toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task +will toggle LED ( uxBaseLED + comTX_LED_OFFSET ). */ +static unsigned portBASE_TYPE uxBaseLED = 0; + +/* The Rx task toggles uxRxLoops on each successful iteration of its defined +function - provided no errors have ever been latched. If this variable stops +incrementing, then an error has occurred. */ +static volatile unsigned portBASE_TYPE uxRxLoops = 0UL; + +/* The timer used to periodically transmit the string. This is the timer that +has prvComTxTimerCallback allocated to it as its callback function. */ +static xTimerHandle xTxTimer = NULL; + +/* The string length is held at file scope so the Tx timer does not need to +calculate it each time it executes. */ +static size_t xStringLength = 0U; + +/*-----------------------------------------------------------*/ + +void vStartComTestStringsTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED ) +{ + /* Store values that are used at run time. */ + uxBaseLED = uxLED; + + /* Calculate the string length here, rather than each time the Tx timer + executes. */ + xStringLength = strlen( comTRANSACTED_STRING ); + + /* Include the null terminator in the string length as this is used to + detect the end of the string in the Rx task. */ + xStringLength++; + + /* Initialise the com port, then spawn the Rx task and create the Tx + timer. */ + xSerialPortInitMinimal( ulBaudRate, ( xStringLength * 2U ) ); + + /* Create the Rx task and the Tx timer. The timer is started from the + Rx task. */ + xTaskCreate( vComRxTask, ( signed char * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); + xTxTimer = xTimerCreate( ( const signed char * ) "TxTimer", comTX_MIN_BLOCK_TIME, pdFALSE, NULL, prvComTxTimerCallback ); + configASSERT( xTxTimer ); +} +/*-----------------------------------------------------------*/ + +static void prvComTxTimerCallback( xTimerHandle xTimer ) +{ +portTickType xTimeToWait; + + /* The parameter is not used in this case. */ + ( void ) xTimer; + + /* Send the string. How this is actually performed depends on the + sample driver provided with this demo. However - as this is a timer, + it executes in the context of the timer task and therefore must not + block. */ + vSerialPutString( xPort, ( const signed char * const ) comTRANSACTED_STRING, xStringLength ); + + /* Toggle an LED to give a visible indication that another transmission + has been performed. */ + vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); + + /* Wait a pseudo random time before sending the string again. */ + xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; + + /* Ensure the time to wait is not greater than comTX_MAX_BLOCK_TIME. */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* Ensure the time to wait is not less than comTX_MIN_BLOCK_TIME. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + /* Reset the timer to run again xTimeToWait ticks from now. This function + is called from the context of the timer task, so the block time must not + be anything other than zero. */ + xTimerChangePeriod( xTxTimer, xTimeToWait, comtstDONT_BLOCK ); +} +/*-----------------------------------------------------------*/ + +static void vComRxTask( void *pvParameters ) +{ +portBASE_TYPE xState = comtstWAITING_START_OF_STRING, xErrorOccurred = pdFALSE; +signed char *pcExpectedByte, cRxedChar; +const xComPortHandle xPort = NULL; + + /* The parameter is not used in this example. */ + ( void ) pvParameters; + + /* Start the Tx timer. This only needs to be started once, as it will + reset itself thereafter. */ + xTimerStart( xTxTimer, portMAX_DELAY ); + + /* The first expected Rx character is the first in the string that is + transmitted. */ + pcExpectedByte = ( signed char * ) comTRANSACTED_STRING; + + for( ;; ) + { + /* Wait for the next character. */ + if( xSerialGetChar( xPort, &cRxedChar, ( comTX_MAX_BLOCK_TIME * 2 ) ) == pdFALSE ) + { + /* A character definitely should have been received by now. As a + character was not received an error must have occurred (which might + just be that the loopback connector is not fitted). */ + xErrorOccurred = pdTRUE; + } + + switch( xState ) + { + case comtstWAITING_START_OF_STRING: + if( cRxedChar == *pcExpectedByte ) + { + /* The received character was the first character of the + string. Move to the next state to check each character + as it comes in until the entire string has been received. */ + xState = comtstWAITING_END_OF_STRING; + pcExpectedByte++; + + /* Block for a short period. This just allows the Rx queue + to contain more than one character, and therefore prevent + thrashing reads to the queue, and repetitive context + switches as each character is received. */ + vTaskDelay( comSHORT_DELAY ); + } + break; + + case comtstWAITING_END_OF_STRING: + if( cRxedChar == *pcExpectedByte ) + { + /* The received character was the expected character. Was + it the last character in the string - i.e. the null + terminator? */ + if( cRxedChar == 0x00 ) + { + /* The entire string has been received. If no errors + have been latched, then increment the loop counter to + show this task is still healthy. */ + if( xErrorOccurred == pdFALSE ) + { + uxRxLoops++; + + /* Toggle an LED to give a visible sign that a + complete string has been received. */ + vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); + } + + /* Go back to wait for the start of the next string. */ + pcExpectedByte = ( signed char * ) comTRANSACTED_STRING; + xState = comtstWAITING_START_OF_STRING; + } + else + { + /* Wait for the next character in the string. */ + pcExpectedByte++; + } + } + else + { + /* The character received was not that expected. */ + xErrorOccurred = pdTRUE; + } + break; + + default: + /* Should not get here. Stop the Rx loop counter from + incrementing to latch the error. */ + xErrorOccurred = pdTRUE; + break; + } + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* If the count of successful reception loops has not changed than at + some time an error occurred (i.e. a character was received out of sequence) + and false is returned. */ + if( uxRxLoops == 0UL ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Reset the count of successful Rx loops. When this function is called + again it should have been incremented again. */ + uxRxLoops = 0UL; + + return xReturn; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/countsem.c b/third_party/FreeRTOS/Demo/Common/Minimal/countsem.c new file mode 100644 index 0000000..d38e4f4 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/countsem.c @@ -0,0 +1,322 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * Simple demonstration of the usage of counting semaphore. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "countsem.h" + +/* The maximum count value that the semaphore used for the demo can hold. */ +#define countMAX_COUNT_VALUE ( 200 ) + +/* Constants used to indicate whether or not the semaphore should have been +created with its maximum count value, or its minimum count value. These +numbers are used to ensure that the pointers passed in as the task parameters +are valid. */ +#define countSTART_AT_MAX_COUNT ( 0xaa ) +#define countSTART_AT_ZERO ( 0x55 ) + +/* Two tasks are created for the test. One uses a semaphore created with its +count value set to the maximum, and one with the count value set to zero. */ +#define countNUM_TEST_TASKS ( 2 ) +#define countDONT_BLOCK ( 0 ) + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static volatile portBASE_TYPE xErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* + * The demo task. This simply counts the semaphore up to its maximum value, + * the counts it back down again. The result of each semaphore 'give' and + * 'take' is inspected, with an error being flagged if it is found not to be + * the expected result. + */ +static void prvCountingSemaphoreTask( void *pvParameters ); + +/* + * Utility function to increment the semaphore count value up from zero to + * countMAX_COUNT_VALUE. + */ +static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ); + +/* + * Utility function to decrement the semaphore count value up from + * countMAX_COUNT_VALUE to zero. + */ +static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ); + +/*-----------------------------------------------------------*/ + +/* The structure that is passed into the task as the task parameter. */ +typedef struct COUNT_SEM_STRUCT +{ + /* The semaphore to be used for the demo. */ + xSemaphoreHandle xSemaphore; + + /* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with + its count value set to its max count value, or countSTART_AT_ZERO if it + should have been created with its count value set to 0. */ + unsigned portBASE_TYPE uxExpectedStartCount; + + /* Incremented on each cycle of the demo task. Used to detect a stalled + task. */ + unsigned portBASE_TYPE uxLoopCounter; +} xCountSemStruct; + +/* Two structures are defined, one is passed to each test task. */ +static volatile xCountSemStruct xParameters[ countNUM_TEST_TASKS ]; + +/*-----------------------------------------------------------*/ + +void vStartCountingSemaphoreTasks( void ) +{ + /* Create the semaphores that we are going to use for the test/demo. The + first should be created such that it starts at its maximum count value, + the second should be created such that it starts with a count value of zero. */ + xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE ); + xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT; + xParameters[ 0 ].uxLoopCounter = 0; + + xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 ); + xParameters[ 1 ].uxExpectedStartCount = 0; + xParameters[ 1 ].uxLoopCounter = 0; + + /* vQueueAddToRegistry() adds the semaphore to the registry, if one is + in use. The registry is provided as a means for kernel aware + debuggers to locate semaphores and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( ( xQueueHandle ) xParameters[ 0 ].xSemaphore, ( signed portCHAR * ) "Counting_Sem_1" ); + vQueueAddToRegistry( ( xQueueHandle ) xParameters[ 1 ].xSemaphore, ( signed portCHAR * ) "Counting_Sem_2" ); + + + /* Were the semaphores created? */ + if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) ) + { + /* Create the demo tasks, passing in the semaphore to use as the parameter. */ + xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ) +{ +unsigned portBASE_TYPE ux; + + /* If the semaphore count is at its maximum then we should not be able to + 'give' the semaphore. */ + if( xSemaphoreGive( xSemaphore ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */ + for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ ) + { + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS ) + { + /* We expected to be able to take the semaphore. */ + xErrorDetected = pdTRUE; + } + + ( *puxLoopCounter )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the semaphore count is zero then we should not be able to 'take' + the semaphore. */ + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ) +{ +unsigned portBASE_TYPE ux; + + /* If the semaphore count is zero then we should not be able to 'take' + the semaphore. */ + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */ + for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ ) + { + if( xSemaphoreGive( xSemaphore ) != pdPASS ) + { + /* We expected to be able to take the semaphore. */ + xErrorDetected = pdTRUE; + } + + ( *puxLoopCounter )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the semaphore count is at its maximum then we should not be able to + 'give' the semaphore. */ + if( xSemaphoreGive( xSemaphore ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvCountingSemaphoreTask( void *pvParameters ) +{ +xCountSemStruct *pxParameter; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Counting semaphore demo started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + /* The semaphore to be used was passed as the parameter. */ + pxParameter = ( xCountSemStruct * ) pvParameters; + + /* Did we expect to find the semaphore already at its max count value, or + at zero? */ + if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT ) + { + prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + } + + /* Now we expect the semaphore count to be 0, so this time there is an + error if we can take the semaphore. */ + if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + for( ;; ) + { + prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void ) +{ +static unsigned portBASE_TYPE uxLastCount0 = 0, uxLastCount1 = 0; +portBASE_TYPE xReturn = pdPASS; + + /* Return fail if any 'give' or 'take' did not result in the expected + behaviour. */ + if( xErrorDetected != pdFALSE ) + { + xReturn = pdFAIL; + } + + /* Return fail if either task is not still incrementing its loop counter. */ + if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter ) + { + xReturn = pdFAIL; + } + else + { + uxLastCount0 = xParameters[ 0 ].uxLoopCounter; + } + + if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter ) + { + xReturn = pdFAIL; + } + else + { + uxLastCount1 = xParameters[ 1 ].uxLoopCounter; + } + + return xReturn; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/crflash.c b/third_party/FreeRTOS/Demo/Common/Minimal/crflash.c new file mode 100644 index 0000000..9f0a1a8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/crflash.c @@ -0,0 +1,246 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo application file demonstrates the use of queues to pass data + * between co-routines. + * + * N represents the number of 'fixed delay' co-routines that are created and + * is set during initialisation. + * + * N 'fixed delay' co-routines are created that just block for a fixed + * period then post the number of an LED onto a queue. Each such co-routine + * uses a different block period. A single 'flash' co-routine is also created + * that blocks on the same queue, waiting for the number of the next LED it + * should flash. Upon receiving a number it simply toggle the instructed LED + * then blocks on the queue once more. In this manner each LED from LED 0 to + * LED N-1 is caused to flash at a different rate. + * + * The 'fixed delay' co-routines are created with co-routine priority 0. The + * flash co-routine is created with co-routine priority 1. This means that + * the queue should never contain more than a single item. This is because + * posting to the queue will unblock the 'flash' co-routine, and as this has + * a priority greater than the tasks posting to the queue it is guaranteed to + * have emptied the queue and blocked once again before the queue can contain + * any more date. An error is indicated if an attempt to post data to the + * queue fails - indicating that the queue is already full. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "crflash.h" + +/* The queue should only need to be of length 1. See the description at the +top of the file. */ +#define crfQUEUE_LENGTH 1 + +#define crfFIXED_DELAY_PRIORITY 0 +#define crfFLASH_PRIORITY 1 + +/* Only one flash co-routine is created so the index is not significant. */ +#define crfFLASH_INDEX 0 + +/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be +created. */ +#define crfMAX_FLASH_TASKS 8 + +/* We don't want to block when posting to the queue. */ +#define crfPOSTING_BLOCK_TIME 0 + +/* + * The 'fixed delay' co-routine as described at the top of the file. + */ +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The 'flash' co-routine as described at the top of the file. + */ +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* The queue used to pass data between the 'fixed delay' co-routines and the +'flash' co-routine. */ +static xQueueHandle xFlashQueue; + +/* This will be set to pdFALSE if we detect an error. */ +static portBASE_TYPE xCoRoutineFlashStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* + * See the header file for details. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate ) +{ +unsigned portBASE_TYPE uxIndex; + + if( uxNumberToCreate > crfMAX_FLASH_TASKS ) + { + uxNumberToCreate = crfMAX_FLASH_TASKS; + } + + /* Create the queue used to pass data between the co-routines. */ + xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + if( xFlashQueue ) + { + /* Create uxNumberToCreate 'fixed delay' co-routines. */ + for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ ) + { + xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex ); + } + + /* Create the 'flash' co-routine. */ + xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX ); + } +} +/*-----------------------------------------------------------*/ + +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the xResult variable does not need to be +static as we do not need it to maintain its state between blocks. */ +signed portBASE_TYPE xResult; +/* The uxIndex parameter of the co-routine function is used as an index into +the xFlashRates array to obtain the delay period to use. */ +static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS, + 200 / portTICK_RATE_MS, + 250 / portTICK_RATE_MS, + 300 / portTICK_RATE_MS, + 350 / portTICK_RATE_MS, + 400 / portTICK_RATE_MS, + 450 / portTICK_RATE_MS, + 500 / portTICK_RATE_MS }; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ;; ) + { + /* Post our uxIndex value onto the queue. This is used as the LED to + flash. */ + crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult ); + + if( xResult != pdPASS ) + { + /* For the reasons stated at the top of the file we should always + find that we can post to the queue. If we could not then an error + has occurred. */ + xCoRoutineFlashStatus = pdFAIL; + } + + crDELAY( xHandle, xFlashRates[ uxIndex ] ); + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the variable do not need to be +static as we do not need it to maintain their state between blocks. */ +signed portBASE_TYPE xResult; +unsigned portBASE_TYPE uxLEDToFlash; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + ( void ) uxIndex; + + for( ;; ) + { + /* Block to wait for the number of the LED to flash. */ + crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + + if( xResult != pdPASS ) + { + /* We would not expect to wake unless we received something. */ + xCoRoutineFlashStatus = pdFAIL; + } + else + { + /* We received the number of an LED to flash - flash it! */ + vParTestToggleLED( uxLEDToFlash ); + } + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ) +{ + /* Return pdPASS or pdFAIL depending on whether an error has been detected + or not. */ + return xCoRoutineFlashStatus; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/crhook.c b/third_party/FreeRTOS/Demo/Common/Minimal/crhook.c new file mode 100644 index 0000000..0eaba7d --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/crhook.c @@ -0,0 +1,270 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This demo file demonstrates how to send data between an ISR and a + * co-routine. A tick hook function is used to periodically pass data between + * the RTOS tick and a set of 'hook' co-routines. + * + * hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks + * to wait for a character to be received on a queue from the tick ISR, checks + * to ensure the character received was that expected, then sends the number + * back to the tick ISR on a different queue. + * + * The tick ISR checks the numbers received back from the 'hook' co-routines + * matches the number previously sent. + * + * If at any time a queue function returns unexpectedly, or an incorrect value + * is received either by the tick hook or a co-routine then an error is + * latched. + * + * This demo relies on each 'hook' co-routine to execute between each + * hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of + * queues from within an interrupt may result in an error being detected on + * slower targets simply due to timing. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "crhook.h" + +/* The number of 'hook' co-routines that are to be created. */ +#define hookNUM_HOOK_CO_ROUTINES ( 4 ) + +/* The number of times the tick hook should be called before a character is +posted to the 'hook' co-routines. */ +#define hookTICK_CALLS_BEFORE_POST ( 500 ) + +/* There should never be more than one item in any queue at any time. */ +#define hookHOOK_QUEUE_LENGTH ( 1 ) + +/* Don't block when initially posting to the queue. */ +#define hookNO_BLOCK_TIME ( 0 ) + +/* The priority relative to other co-routines (rather than tasks) that the +'hook' co-routines should take. */ +#define mainHOOK_CR_PRIORITY ( 1 ) +/*-----------------------------------------------------------*/ + +/* + * The co-routine function itself. + */ +static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + + +/* + * The tick hook function. This receives a number from each 'hook' co-routine + * then sends a number to each co-routine. An error is flagged if a send or + * receive fails, or an unexpected number is received. + */ +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* Queues used to send data FROM a co-routine TO the tick hook function. +The hook functions received (Rx's) on these queues. One queue per +'hook' co-routine. */ +static xQueueHandle xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Queues used to send data FROM the tick hook TO a co-routine function. +The hood function transmits (Tx's) on these queues. One queue per +'hook' co-routine. */ +static xQueueHandle xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Set to true if an error is detected at any time. */ +static portBASE_TYPE xCoRoutineErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartHookCoRoutines( void ) +{ +unsigned portBASE_TYPE uxIndex, uxValueToPost = 0; + + for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ ) + { + /* Create a queue to transmit to and receive from each 'hook' + co-routine. */ + xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + /* To start things off the tick hook function expects the queue it + uses to receive data to contain a value. */ + xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME ); + + /* Create the 'hook' co-routine itself. */ + xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex ); + } +} +/*-----------------------------------------------------------*/ + +static unsigned portBASE_TYPE uxCallCounter = 0, uxNumberToPost = 0; +void vApplicationTickHook( void ) +{ +unsigned portBASE_TYPE uxReceivedNumber; +signed portBASE_TYPE xIndex, xCoRoutineWoken; + + /* Is it time to talk to the 'hook' co-routines again? */ + uxCallCounter++; + if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST ) + { + uxCallCounter = 0; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + xCoRoutineWoken = pdFALSE; + if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS ) + { + /* There is no reason why we would not expect the queue to + contain a value. */ + xCoRoutineErrorDetected = pdTRUE; + } + else + { + /* Each queue used to receive data from the 'hook' co-routines + should contain the number we last posted to the same co-routine. */ + if( uxReceivedNumber != uxNumberToPost ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Nothing should be blocked waiting to post to the queue. */ + if( xCoRoutineWoken != pdFALSE ) + { + xCoRoutineErrorDetected = pdTRUE; + } + } + } + + /* Start the next cycle by posting the next number onto each Tx queue. */ + uxNumberToPost++; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE ) + { + /* Posting to the queue should have woken the co-routine that + was blocked on the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static unsigned portBASE_TYPE uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ]; +portBASE_TYPE xResult; + + /* Each co-routine MUST start with a call to crSTART(); */ + crSTART( xHandle ); + + for( ;; ) + { + /* Wait to receive a value from the tick hook. */ + xResult = pdFAIL; + crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult ); + + /* There is no reason why we should not have received something on + the queue. */ + if( xResult != pdPASS ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Send the same number back to the idle hook so it can verify it. */ + xResult = pdFAIL; + crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult ); + if( xResult != pdPASS ) + { + /* There is no reason why we should not have been able to post to + the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + + /* Each co-routine MUST end with a call to crEND(). */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreHookCoRoutinesStillRunning( void ) +{ + if( xCoRoutineErrorDetected ) + { + return pdFALSE; + } + else + { + return pdTRUE; + } +} + + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/death.c b/third_party/FreeRTOS/Demo/Common/Minimal/death.c new file mode 100644 index 0000000..d6a9110 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/death.c @@ -0,0 +1,267 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Create a single persistent task which periodically dynamically creates another + * two tasks. The original task is called the creator task, the two tasks it + * creates are called suicidal tasks. + * + * One of the created suicidal tasks kill one other suicidal task before killing + * itself - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V3.0.0 + + CreationCount sizes changed from unsigned portBASE_TYPE to + unsigned short to minimize the risk of overflowing. + + + Reset of usLastCreationCount added + +Changes from V3.1.0 + + Changed the dummy calculation to use variables of type long, rather than + float. This allows the file to be used with ports that do not support + floating point. + +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" + +#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 ) + +/* The task originally created which is responsible for periodically dynamically +creating another four tasks. */ +static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters ); + +/* The task function of the dynamically created tasks. */ +static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This +is used to check that the task is still running. */ +static volatile unsigned short usCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator +task can tell if any of the suicidal tasks have failed to die. +*/ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; + +/* Tasks are deleted by the idle task. Under heavy load the idle task might +not get much processing time, so it would be legitimate for several tasks to +remain undeleted for a short period. */ +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 3; + +/* Used to store a handle to the task that should be killed by a suicidal task, +before it kills itself. */ +xTaskHandle xCreatedTask; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE *puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, ( signed char * ) "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); + + /* FreeRTOS.org versions before V3.0 started the idle-task as the very + first task. The idle task was then already included in uxTasksRunningAtStart. + From FreeRTOS V3.0 on, the idle task is started when the scheduler is + started. Therefore the idle task is not yet accounted for. We correct + this by increasing uxTasksRunningAtStart by 1. */ + uxTasksRunningAtStart++; + + /* From FreeRTOS version 7.0.0 can optionally create a timer service task. + If this is done, then uxTasksRunningAtStart needs incrementing again as that + too is created when the scheduler is started. */ + #if configUSE_TIMERS == 1 + uxTasksRunningAtStart++; + #endif +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vSuicidalTask, pvParameters ) +{ +volatile long l1, l2; +xTaskHandle xTaskToKill; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Two created tasks are + passed a handle to the other task so it can kill it before killing itself. + The other task is passed in null. */ + xTaskToKill = *( xTaskHandle* )pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ;; ) + { + /* Do something random just to use some stack and registers. */ + l1 = 2; + l2 = 89; + l2 *= l1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( portTickType ) 0 ); + + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCreateTasks, pvParameters ) +{ +const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; +unsigned portBASE_TYPE uxPriority; + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ;; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xCreatedTask = NULL; + + xTaskCreate( vSuicidalTask, ( signed char * ) "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask ); + xTaskCreate( vSuicidalTask, ( signed char * ) "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL ); + + ++usCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there +are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ +static unsigned short usLastCreationCount = 0xfff; +portBASE_TYPE xReturn = pdTRUE; +static unsigned portBASE_TYPE uxTasksRunningNow; + + if( usLastCreationCount == usCreationCount ) + { + xReturn = pdFALSE; + } + else + { + usLastCreationCount = usCreationCount; + } + + uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + xReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + xReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return xReturn; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/dynamic.c b/third_party/FreeRTOS/Demo/Common/Minimal/dynamic.c new file mode 100644 index 0000000..2a900af --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/dynamic.c @@ -0,0 +1,511 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises its priority above that of the controller task before each + * increment, lowering it again to its original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of its loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume(). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from its suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" + +/* Function that implements the "limited count" task as described above. */ +static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters ); + +/* Function that implements the controller task as described above. */ +static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters ); + +static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters ); +static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters ); + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE ) +#define priSLEEP_TIME ( ( portTickType ) 128 / portTICK_RATE_MS ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned long ) 0xff ) +#define priNO_BLOCK ( ( portTickType ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters +to the controller task to prevent them having to be file scope. */ +static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle; + +/* The shared counter variable. This is passed in as a parameter to the two +counter variables for demonstration purposes. */ +static volatile unsigned long ulCounter; + +/* Variables used to check that the tasks are still operating without error. +Each complete iteration of the controller task increments this variable +provided no errors have been found. The variable maintaining the same value +is therefore indication of an error. */ +static volatile unsigned short usCheckVariable = ( unsigned short ) 0; +static volatile portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static volatile portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; + +/* Queue used by the second test. */ +xQueueHandle xSuspendedTestQueue; + +/* The value the queue receive task expects to receive next. This is file +scope so xAreDynamicPriorityTasksStillRunning() can ensure it is still +incrementing. */ +static unsigned long ulExpectedValue = ( unsigned long ) 0; + +/*-----------------------------------------------------------*/ +/* + * Start the three tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + in use. The queue registry is provided as a means for kernel aware + debuggers to locate queues and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( xSuspendedTestQueue, ( signed char * ) "Suspended_Test_Queue" ); + + xTaskCreate( vContinuousIncrementTask, ( signed char * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, ( signed char * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, ( signed char * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, ( signed char * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed char * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters ) +{ +unsigned long *pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned long * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ;; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters ) +{ +volatile unsigned long *pulCounter; +unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned long * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ;; ) + { + /* Raise the priority above the controller task to ensure a context + switch does not occur while the variable is being accessed. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + { + configASSERT( ( uxTaskPriorityGet( NULL ) == ( uxOurPriority + 1 ) ) ); + ( *pulCounter )++; + } + vTaskPrioritySet( NULL, uxOurPriority ); + + #if( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + configASSERT( ( uxTaskPriorityGet( NULL ) == uxOurPriority ) ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static portTASK_FUNCTION( vCounterControlTask, pvParameters ) +{ +unsigned long ulLastCounter; +short sLoops; +short sError = pdFALSE; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned long ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + shared variable without risk of corruption. This is not really + needed as the other task raises its priority above this task's + priority. */ + vTaskSuspend( xContinuousIncrementHandle ); + { + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + ulLastCounter = ulCounter; + } + vTaskResume( xContinuousIncrementHandle ); + + #if( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eReady ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + exclusion the whole scheduler will be locked. This is just for + demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + with the continuous count task so flag an error. */ + sError = pdTRUE; + } + } + xTaskResumeAll(); + } + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared + variable. */ + vTaskSuspend( xContinuousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned long ) 0; + + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Resume the limited count task which has a higher priority than us. + We should therefore not return from this call until the limited count + task has suspended itself with a known value in the counter variable. */ + vTaskResume( xLimitedIncrementHandle ); + + #if( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + /* This task should not run again until xLimitedIncrementHandle has + suspended itself. */ + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinuousIncrementHandle ); + + #if( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters ) +{ +static unsigned long ulValueToSend = ( unsigned long ) 0; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters ) +{ +unsigned long ulReceivedValue; +portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + undesirable for a normal application. It is done here purely + to test the scheduler. The inner xTaskResumeAll() should + never return pdTRUE as the scheduler is still locked by the + outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + if( xTaskResumeAll() != pdFALSE ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + + if( xSuspendedQueueReceiveError != pdTRUE ) + { + /* Only increment the variable if an error has not occurred. This + allows xAreDynamicPriorityTasksStillRunning() to check for stalled + tasks as well as explicit errors. */ + ++ulExpectedValue; + } + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented +since the last call. */ +static unsigned short usLastTaskCheck = ( unsigned short ) 0; +static unsigned long ulLastExpectedValue = ( unsigned long ) 0U; +portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( ulExpectedValue == ulLastExpectedValue ) + { + /* The value being received by the queue receive task has not + incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + ulLastExpectedValue = ulExpectedValue; + + return xReturn; +} diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/flash.c b/third_party/FreeRTOS/Demo/Common/Minimal/flash.c new file mode 100644 index 0000000..fda5870 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/flash.c @@ -0,0 +1,157 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * This version of flash .c is for use on systems that have limited stack space + * and no display facilities. The complete version can be found in the + * Demo/Common/Full directory. + * + * Three tasks are created, each of which flash an LED at a different rate. The first + * LED flashes every 200ms, the second every 400ms, the third every 600ms. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE +#define ledNUMBER_OF_LEDS ( 3 ) +#define ledFLASH_RATE_BASE ( ( portTickType ) 333 ) + +/* Variable used by the created tasks to calculate the LED number to use, and +the rate at which they should flash the LED. */ +static volatile unsigned portBASE_TYPE uxFlashTaskNumber = 0; + +/* The task that is created three times. */ +static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters ); + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ +signed portBASE_TYPE xLEDTask; + + /* Create the three tasks. */ + for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask ) + { + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, ( signed char * ) "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vLEDFlashTask, pvParameters ) +{ +portTickType xFlashRate, xLastFlashTime; +unsigned portBASE_TYPE uxLED; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Calculate the LED and flash rate. */ + portENTER_CRITICAL(); + { + /* See which of the eight LED's we should use. */ + uxLED = uxFlashTaskNumber; + + /* Update so the next task uses the next LED. */ + uxFlashTaskNumber++; + } + portEXIT_CRITICAL(); + + xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( portTickType ) uxLED ); + xFlashRate /= portTICK_RATE_MS; + + /* We will turn the LED on and off again in the delay period, so each + delay is only half the total period. */ + xFlashRate /= ( portTickType ) 2; + + /* We need to initialise xLastFlashTime prior to the first call to + vTaskDelayUntil(). */ + xLastFlashTime = xTaskGetTickCount(); + + for(;;) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + } +} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */ + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/flash_timer.c b/third_party/FreeRTOS/Demo/Common/Minimal/flash_timer.c new file mode 100644 index 0000000..a5985ff --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/flash_timer.c @@ -0,0 +1,136 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/** + * Repeatedly toggles one or more LEDs using software timers - one timer per + * LED. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "timers.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash_timer.h" + +/* The toggle rates are all a multple of ledFLASH_RATE_BASE. */ +#define ledFLASH_RATE_BASE ( ( ( portTickType ) 333 ) / portTICK_RATE_MS ) + +/* A block time of zero simple means "don't block". */ +#define ledDONT_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* + * The callback function used by each LED flashing timer. All the timers use + * this function, and the timer ID is used within the function to determine + * which timer has actually expired. + */ +static void prvLEDTimerCallback( xTimerHandle xTimer ); + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTimers( unsigned portBASE_TYPE uxNumberOfLEDs ) +{ +unsigned portBASE_TYPE uxLEDTimer; +xTimerHandle xTimer; + + /* Create and start the requested number of timers. */ + for( uxLEDTimer = 0; uxLEDTimer < uxNumberOfLEDs; ++uxLEDTimer ) + { + /* Create the timer. */ + xTimer = xTimerCreate( ( const signed char * const ) "Flasher",/* A text name, purely to help debugging. */ + ledFLASH_RATE_BASE * ( uxLEDTimer + 1 ), /* The timer period, which is a multiple of ledFLASH_RATE_BASE. */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) uxLEDTimer, /* The ID is used to identify the timer within the timer callback function, as each timer uses the same callback. */ + prvLEDTimerCallback /* Each timer uses the same callback. */ + ); + + /* If the timer was created successfully, attempt to start it. If the + scheduler has not yet been started then the timer command queue must + be long enough to hold each command sent to it until such time that the + scheduler is started. The timer command queue length is set by + configTIMER_QUEUE_LENGTH in FreeRTOSConfig.h. */ + if( xTimer != NULL ) + { + xTimerStart( xTimer, ledDONT_BLOCK ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvLEDTimerCallback( xTimerHandle xTimer ) +{ +portBASE_TYPE xTimerID; + + /* The timer ID is used to identify the timer that has actually expired as + each timer uses the same callback. The ID is then also used as the number + of the LED that is to be toggled. */ + xTimerID = ( portBASE_TYPE ) pvTimerGetTimerID( xTimer ); + vParTestToggleLED( xTimerID ); +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/flop.c b/third_party/FreeRTOS/Demo/Common/Minimal/flop.c new file mode 100644 index 0000000..e45ec64 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/flop.c @@ -0,0 +1,383 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * Creates eight tasks, each of which loops continuously performing a floating + * point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle + * priority means that these tasks will get pre-empted any time another task is + * ready to run or a time slice occurs. More often than not the pre-emption + * will occur mid calculation, creating a good test of the schedulers context + * switch mechanism - a calculation producing an unexpected result could be a + * symptom of a corruption in the context of a task. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 4 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will stop setting its check variable. */ +static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ +volatile portDOUBLE d1, d2, d3, d4; +volatile unsigned short *pusTaskCheckVariable; +volatile portDOUBLE dAnswer; +short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + tell the kernel that they require a floating point context before any + floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + dAnswer = ( d1 + d2 ) * d3; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + variable. The check variable will get set to pdFALSE each time + xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ +volatile portDOUBLE d1, d2, d3, d4; +volatile unsigned short *pusTaskCheckVariable; +volatile portDOUBLE dAnswer; +short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + tell the kernel that they require a floating point context before any + floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + dAnswer = ( d1 / d2 ) * d3; + + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + variable. The check variable will get set to pdFALSE each time + xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ +volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned short *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + tell the kernel that they require a floating point context before any + floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5; + dTotal1 += ( portDOUBLE ) xPosition + 5.5; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + variable. The check variable will get set to pdFALSE each time + xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ +volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned short *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + tell the kernel that they require a floating point context before any + floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123; + dTotal1 += ( portDOUBLE ) xPosition * 12.123; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + variable. The check variable will get set to pdFALSE each time + xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +portBASE_TYPE xReturn = pdPASS, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + have been set to pdPASS. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] != pdTRUE ) + { + /* The check has not been set so the associated task has either + stalled or detected an error. */ + xReturn = pdFAIL; + } + else + { + /* Reset the variable so it can be checked again the next time this + function is executed. */ + usTaskCheck[ xTask ] = pdFALSE; + } + } + + return xReturn; +} + + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/integer.c b/third_party/FreeRTOS/Demo/Common/Minimal/integer.c new file mode 100644 index 0000000..76ea423 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/integer.c @@ -0,0 +1,201 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * Creates one or more tasks that repeatedly perform a set of integer + * calculations. The result of each run-time calculation is compared to the + * known expected result - with a mismatch being indicative of an error in the + * context switch mechanism. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "integer.h" + +/* The constants used in the calculation. */ +#define intgCONST1 ( ( long ) 123 ) +#define intgCONST2 ( ( long ) 234567 ) +#define intgCONST3 ( ( long ) -3 ) +#define intgCONST4 ( ( long ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + +#define intgSTACK_SIZE configMINIMAL_STACK_SIZE + +/* As this is the minimal version, we will only create one task. */ +#define intgNUMBER_OF_TASKS ( 1 ) + +/* The task function. Repeatedly performs a 32 bit calculation, checking the +result against the expected result. If the result is incorrect then the +context switch must have caused some corruption. */ +static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters ); + +/* Variables that are set to true within the calculation task to indicate +that the task is still executing. The check task sets the variable back to +false, flagging an error if the variable is still false the next time it +is called. */ +static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE }; + +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ +short sTask; + + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + xTaskCreate( vCompeteingIntMathTask, ( signed char * ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters ) +{ +/* These variables are all effectively set to constants so they are volatile to +ensure the compiler does not just get rid of them. */ +volatile long lValue; +short sError = pdFALSE; +volatile signed portBASE_TYPE *pxTaskHasExecuted; + + /* Set a pointer to the variable we are going to set to true each + iteration. This is also a good test of the parameter passing mechanism + within each port. */ + pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + + /* Finish off the calculation. */ + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* If the calculation is found to be incorrect we stop setting the + TaskHasExecuted variable so the check task can see an error has + occurred. */ + if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */ + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* We have not encountered any errors, so set the flag that show + we are still executing. This will be periodically cleared by + the check task. */ + portENTER_CRITICAL(); + *pxTaskHasExecuted = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +portBASE_TYPE xReturn = pdTRUE; +short sTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still being set to true. */ + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + if( xTaskCheck[ sTask ] == pdFALSE ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + /* Reset the check variable so we can tell if it has been set by + the next time around. */ + xTaskCheck[ sTask ] = pdFALSE; + } + + return xReturn; +} + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/recmutex.c b/third_party/FreeRTOS/Demo/Common/Minimal/recmutex.c new file mode 100644 index 0000000..760233c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/recmutex.c @@ -0,0 +1,440 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + The tasks defined on this page demonstrate the use of recursive mutexes. + + For recursive mutex functionality the created mutex should be created using + xSemaphoreCreateRecursiveMutex(), then be manipulated + using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API + functions. + + This demo creates three tasks all of which access the same recursive mutex: + + prvRecursiveMutexControllingTask() has the highest priority so executes + first and grabs the mutex. It then performs some recursive accesses - + between each of which it sleeps for a short period to let the lower + priority tasks execute. When it has completed its demo functionality + it gives the mutex back before suspending itself. + + prvRecursiveMutexBlockingTask() attempts to access the mutex by performing + a blocking 'take'. The blocking task has a lower priority than the + controlling task so by the time it executes the mutex has already been + taken by the controlling task, causing the blocking task to block. It + does not unblock until the controlling task has given the mutex back, + and it does not actually run until the controlling task has suspended + itself (due to the relative priorities). When it eventually does obtain + the mutex all it does is give the mutex back prior to also suspending + itself. At this point both the controlling task and the blocking task are + suspended. + + prvRecursiveMutexPollingTask() runs at the idle priority. It spins round + a tight loop attempting to obtain the mutex with a non-blocking call. As + the lowest priority task it will not successfully obtain the mutex until + both the controlling and blocking tasks are suspended. Once it eventually + does obtain the mutex it first unsuspends both the controlling task and + blocking task prior to giving the mutex back - resulting in the polling + task temporarily inheriting the controlling tasks priority. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "recmutex.h" + +/* Priorities assigned to the three tasks. recmuCONTROLLING_TASK_PRIORITY can +be overridden by a definition in FreeRTOSConfig.h. */ +#ifndef recmuCONTROLLING_TASK_PRIORITY + #define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#endif +#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) + +/* The recursive call depth. */ +#define recmuMAX_COUNT ( 10 ) + +/* Misc. */ +#define recmuSHORT_DELAY ( 20 / portTICK_RATE_MS ) +#define recmuNO_DELAY ( ( portTickType ) 0 ) +#define recmuFIVE_TICK_DELAY ( ( portTickType ) 5 ) + +/* The three tasks as described at the top of this file. */ +static void prvRecursiveMutexControllingTask( void *pvParameters ); +static void prvRecursiveMutexBlockingTask( void *pvParameters ); +static void prvRecursiveMutexPollingTask( void *pvParameters ); + +/* The mutex used by the demo. */ +static xSemaphoreHandle xMutex; + +/* Variables used to detect and latch errors. */ +static volatile portBASE_TYPE xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE; +static volatile unsigned portBASE_TYPE uxControllingCycles = 0, uxBlockingCycles = 0, uxPollingCycles = 0; + +/* Handles of the two higher priority tasks, required so they can be resumed +(unsuspended). */ +static xTaskHandle xControllingTaskHandle, xBlockingTaskHandle; + +/*-----------------------------------------------------------*/ + +void vStartRecursiveMutexTasks( void ) +{ + /* Just creates the mutex and the three tasks. */ + + xMutex = xSemaphoreCreateRecursiveMutex(); + + /* vQueueAddToRegistry() adds the mutex to the registry, if one is + in use. The registry is provided as a means for kernel aware + debuggers to locate mutex and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( ( xQueueHandle ) xMutex, ( signed portCHAR * ) "Recursive_Mutex" ); + + + if( xMutex != NULL ) + { + xTaskCreate( prvRecursiveMutexControllingTask, ( signed portCHAR * ) "Rec1", configMINIMAL_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle ); + xTaskCreate( prvRecursiveMutexBlockingTask, ( signed portCHAR * ) "Rec2", configMINIMAL_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle ); + xTaskCreate( prvRecursiveMutexPollingTask, ( signed portCHAR * ) "Rec3", configMINIMAL_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexControllingTask( void *pvParameters ) +{ +unsigned portBASE_TYPE ux; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Should not be able to 'give' the mutex, as we have not yet 'taken' + it. The first time through, the mutex will not have been used yet, + subsequent times through, at this point the mutex will be held by the + polling task. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* We should now be able to take the mutex as many times as + we like. + + The first time through the mutex will be immediately available, on + subsequent times through the mutex will be held by the polling task + at this point and this Take will cause the polling task to inherit + the priority of this task. In this case the block time must be + long enough to ensure the polling task will execute again before the + block time expires. If the block time does expire then the error + flag will be set here. */ + if( xSemaphoreTakeRecursive( xMutex, recmuFIVE_TICK_DELAY ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Ensure the other task attempting to access the mutex (and the + other demo tasks) are able to execute to ensure they either block + (where a block time is specified) or return an error (where no + block time is specified) as the mutex is held by this task. */ + vTaskDelay( recmuSHORT_DELAY ); + } + + /* For each time we took the mutex, give it back. */ + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* Ensure the other task attempting to access the mutex (and the + other demo tasks) are able to execute. */ + vTaskDelay( recmuSHORT_DELAY ); + + /* We should now be able to give the mutex as many times as we + took it. When the mutex is available again the Blocking task + should be unblocked but not run because it has a lower priority + than this task. The polling task should also not run at this point + as it too has a lower priority than this task. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Having given it back the same number of times as it was taken, we + should no longer be the mutex owner, so the next give should fail. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Keep count of the number of cycles this task has performed so a + stall can be detected. */ + uxControllingCycles++; + + /* Suspend ourselves so the blocking task can execute. */ + xControllingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xControllingIsSuspended = pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexBlockingTask( void *pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* This task will run while the controlling task is blocked, and the + controlling task will block only once it has the mutex - therefore + this call should block until the controlling task has given up the + mutex, and not actually execute past this call until the controlling + task is suspended. portMAX_DELAY - 1 is used instead of portMAX_DELAY + to ensure the task's state is reported as Blocked and not Suspended in + a later call to configASSERT() (within the polling task). */ + if( xSemaphoreTakeRecursive( xMutex, ( portMAX_DELAY - 1 ) ) == pdPASS ) + { + if( xControllingIsSuspended != pdTRUE ) + { + /* Did not expect to execute until the controlling task was + suspended. */ + xErrorOccurred = pdTRUE; + } + else + { + /* Give the mutex back before suspending ourselves to allow + the polling task to obtain the mutex. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + xBlockingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xBlockingIsSuspended = pdFALSE; + } + } + else + { + /* We should not leave the xSemaphoreTakeRecursive() function + until the mutex was obtained. */ + xErrorOccurred = pdTRUE; + } + + /* The controlling and blocking tasks should be in lock step. */ + if( uxControllingCycles != ( uxBlockingCycles + 1 ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Keep count of the number of cycles this task has performed so a + stall can be detected. */ + uxBlockingCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexPollingTask( void *pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Keep attempting to obtain the mutex. We should only obtain it when + the blocking task has suspended itself, which in turn should only + happen when the controlling task is also suspended. */ + if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS ) + { + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xControllingTaskHandle ) == eSuspended ); + configASSERT( eTaskGetState( xBlockingTaskHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Is the blocking task suspended? */ + if( ( xBlockingIsSuspended != pdTRUE ) || ( xControllingIsSuspended != pdTRUE ) ) + { + xErrorOccurred = pdTRUE; + } + else + { + /* Keep count of the number of cycles this task has performed + so a stall can be detected. */ + uxPollingCycles++; + + /* We can resume the other tasks here even though they have a + higher priority than the polling task. When they execute they + will attempt to obtain the mutex but fail because the polling + task is still the mutex holder. The polling task (this task) + will then inherit the higher priority. The Blocking task will + block indefinitely when it attempts to obtain the mutex, the + Controlling task will only block for a fixed period and an + error will be latched if the polling task has not returned the + mutex by the time this fixed period has expired. */ + vTaskResume( xBlockingTaskHandle ); + vTaskResume( xControllingTaskHandle ); + + /* The other two tasks should now have executed and no longer + be suspended. */ + if( ( xBlockingIsSuspended == pdTRUE ) || ( xControllingIsSuspended == pdTRUE ) ) + { + xErrorOccurred = pdTRUE; + } + + #if( INCLUDE_uxTaskPriorityGet == 1 ) + { + /* Check priority inherited. */ + configASSERT( uxTaskPriorityGet( NULL ) == recmuCONTROLLING_TASK_PRIORITY ); + } + #endif /* INCLUDE_uxTaskPriorityGet */ + + #if( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xControllingTaskHandle ) == eBlocked ); + configASSERT( eTaskGetState( xBlockingTaskHandle ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Release the mutex, disinheriting the higher priority again. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + #if( INCLUDE_uxTaskPriorityGet == 1 ) + { + /* Check priority disinherited. */ + configASSERT( uxTaskPriorityGet( NULL ) == recmuPOLLING_TASK_PRIORITY ); + } + #endif /* INCLUDE_uxTaskPriorityGet */ + } + } + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; +static unsigned portBASE_TYPE uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0; + + /* Is the controlling task still cycling? */ + if( uxLastControllingCycles == uxControllingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastControllingCycles = uxControllingCycles; + } + + /* Is the blocking task still cycling? */ + if( uxLastBlockingCycles == uxBlockingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastBlockingCycles = uxBlockingCycles; + } + + /* Is the polling task still cycling? */ + if( uxLastPollingCycles == uxPollingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastPollingCycles = uxPollingCycles; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + + + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/semtest.c b/third_party/FreeRTOS/Demo/Common/Minimal/semtest.c new file mode 100644 index 0000000..f25547f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/semtest.c @@ -0,0 +1,298 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) + +/* The task function as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + xSemaphoreHandle xSemaphore; + volatile unsigned long *pulSharedVariable; + portTickType xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile short sNextCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ +xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; +const portTickType xBlockTime = ( portTickType ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + pxFirstSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary(); + xSemaphoreGive( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, ( signed char * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, ( signed char * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + if( pxSecondSemaphoreParameters != NULL ) + { + pxSecondSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary(); + xSemaphoreGive( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; + + xTaskCreate( prvSemaphoreTest, ( signed char * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, ( signed char * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + } + } + + /* vQueueAddToRegistry() adds the semaphore to the registry, if one is + in use. The registry is provided as a means for kernel aware + debuggers to locate semaphores and has no purpose if a kernel aware debugger + is not being used. The call to vQueueAddToRegistry() will be removed + by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + defined to be less than 1. */ + vQueueAddToRegistry( ( xQueueHandle ) pxFirstSemaphoreParameters->xSemaphore, ( signed char * ) "Counting_Sem_1" ); + vQueueAddToRegistry( ( xQueueHandle ) pxSecondSemaphoreParameters->xSemaphore, ( signed char * ) "Counting_Sem_2" ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( prvSemaphoreTest, pvParameters ) +{ +xSemaphoreParameters *pxParameters; +volatile unsigned long *pulSharedVariable, ulExpectedValue; +unsigned long ulCounter; +short sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* A structure is passed in as the parameter. This contains the shared + variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + switches occur during the count. */ + if( pxParameters->xBlockTime > ( portTickType ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ;; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + shared variable to have left it in the state we expect to find + it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + before releasing the semaphore. Would expect a context switch or + two during this time. */ + for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + if( *pulSharedVariable != ulCounter ) + { + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + than the idle priority. This task takes a long time to complete + a cycle (deliberately so to test the guarding) so will be starving + out lower priority tasks. Block for some time to allow give lower + priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( portTickType ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + processor. We are not blocking when attempting to obtain the + semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) +{ +static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; +portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} + + diff --git a/third_party/FreeRTOS/Demo/Common/Minimal/sp_flop.c b/third_party/FreeRTOS/Demo/Common/Minimal/sp_flop.c new file mode 100644 index 0000000..7545344 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/Minimal/sp_flop.c @@ -0,0 +1,365 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * Creates eight tasks, each of which loops continuously performing a floating + * point calculation - using single precision variables. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will +stop incrementing its check variable. */ +static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ +volatile float f1, f2, f3, f4; +volatile unsigned short *pusTaskCheckVariable; +volatile float fAnswer; +short sError = pdFALSE; + + f1 = 123.4567F; + f2 = 2345.6789F; + f3 = -918.222F; + + fAnswer = ( f1 + f2 ) * f3; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + f1 = 123.4567F; + f2 = 2345.6789F; + f3 = -918.222F; + + f4 = ( f1 + f2 ) * f3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( f4 - fAnswer ) > 0.001F ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ +volatile float f1, f2, f3, f4; +volatile unsigned short *pusTaskCheckVariable; +volatile float fAnswer; +short sError = pdFALSE; + + f1 = -389.38F; + f2 = 32498.2F; + f3 = -2.0001F; + + fAnswer = ( f1 / f2 ) * f3; + + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + f1 = -389.38F; + f2 = 32498.2F; + f3 = -2.0001F; + + f4 = ( f1 / f2 ) * f3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( f4 - fAnswer ) > 0.001F ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ +volatile float *pfArray, fTotal1, fTotal2, fDifference, fPosition; +volatile unsigned short *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +short sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + fTotal1 = 0.0F; + fTotal2 = 0.0F; + fPosition = 0.0F; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pfArray[ xPosition ] = fPosition + 5.5F; + fTotal1 += fPosition + 5.5F; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + fTotal2 += pfArray[ xPosition ]; + } + + fDifference = fTotal1 - fTotal2; + if( fabs( fDifference ) > 0.001F ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ +volatile float *pfArray, fTotal1, fTotal2, fDifference, fPosition; +volatile unsigned short *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +short sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + fTotal1 = 0.0F; + fTotal2 = 0.0F; + fPosition = 0.0F; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pfArray[ xPosition ] = fPosition * 12.123F; + fTotal1 += fPosition * 12.123F; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + fTotal2 += pfArray[ xPosition ]; + } + + fDifference = fTotal1 - fTotal2; + if( fabs( fDifference ) > 0.001F ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/Makefile.include b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/Makefile.include new file mode 100644 index 0000000..43ba247 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/Makefile.include @@ -0,0 +1,47 @@ + + +ifdef APPS + APPDIRS = $(foreach APP, $(APPS), ../apps/$(APP)) + -include $(foreach APP, $(APPS), ../apps/$(APP)/Makefile.$(APP)) + CFLAGS += $(addprefix -I../apps/,$(APPS)) +endif + +ifndef CCDEP + CCDEP = $(CC) +endif +ifndef CCDEPCFLAGS + CCDEPCFLAGS = $(CFLAGS) +endif +ifndef OBJECTDIR + OBJECTDIR = obj +endif + +ifeq (${wildcard $(OBJECTDIR)},) + DUMMY := ${shell mkdir $(OBJECTDIR)} +endif + + +vpath %.c . ../uip ../lib $(APPDIRS) + +$(OBJECTDIR)/%.o: %.c + $(CC) $(CFLAGS) -c $< -o $@ + +$(OBJECTDIR)/%.d: %.c + @set -e; rm -f $@; \ + $(CCDEP) -MM $(CCDEPCFLAGS) $< > $@.$$$$; \ + sed 's,\($*\)\.o[ :]*,$(OBJECTDIR)/\1.o $@ : ,g' < $@.$$$$ > $@; \ + rm -f $@.$$$$ + +UIP_SOURCES=uip.c uip_arp.c uiplib.c psock.c timer.c uip-neighbor.c + + +ifneq ($(MAKECMDGOALS),clean) +-include $(addprefix $(OBJECTDIR)/,$(UIP_SOURCES:.c=.d) \ + $(APP_SOURCES:.c=.d)) +endif + +uip.a: ${addprefix $(OBJECTDIR)/, $(UIP_SOURCES:.c=.o)} + $(AR) rcf $@ $^ + +apps.a: ${addprefix $(OBJECTDIR)/, $(APP_SOURCES:.c=.o)} + $(AR) rcf $@ $^ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock-arch.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock-arch.h new file mode 100644 index 0000000..cde657b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock.h new file mode 100644 index 0000000..dae6874 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock.h @@ -0,0 +1,88 @@ +/** + * \defgroup clock Clock interface + * + * The clock interface is the interface between the \ref timer "timer library" + * and the platform specific clock functionality. The clock + * interface must be implemented for each platform that uses the \ref + * timer "timer library". + * + * The clock interface does only one this: it measures time. The clock + * interface provides a macro, CLOCK_SECOND, which corresponds to one + * second of system time. + * + * \sa \ref timer "Timer library" + * + * @{ + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: clock.h,v 1.3 2006/06/11 21:46:39 adam Exp $ + */ +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +#include "clock-arch.h" + +/** + * Initialize the clock library. + * + * This function initializes the clock library and should be called + * from the main() function of the system. + * + */ +void clock_init(void); + +/** + * Get the current clock time. + * + * This function returns the current system clock time. + * + * \return The current clock time, measured in system ticks. + */ +clock_time_t clock_time(void); + +/** + * A second, measured in system clock time. + * + * \hideinitializer + */ +#ifdef CLOCK_CONF_SECOND +#define CLOCK_SECOND CLOCK_CONF_SECOND +#else +#define CLOCK_SECOND (clock_time_t)32 +#endif + +#endif /* __CLOCK_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-addrlabels.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-addrlabels.h new file mode 100644 index 0000000..9dff03d --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-addrlabels.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc-addrlabels.h,v 1.3 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on the "Labels as + * values" feature of gcc + * \author + * Adam Dunkels + * + * This implementation of local continuations is based on a special + * feature of the GCC C compiler called "labels as values". This + * feature allows assigning pointers with the address of the code + * corresponding to a particular C label. + * + * For more information, see the GCC documentation: + * http://gcc.gnu.org/onlinedocs/gcc/Labels-as-Values.html + * + * Thanks to dividuum for finding the nice local scope label + * implementation. + */ + +#ifndef __LC_ADDRLABELS_H__ +#define __LC_ADDRLABELS_H__ + +/** \hideinitializer */ +typedef void * lc_t; + +#define LC_INIT(s) s = NULL + + +#define LC_RESUME(s) \ + do { \ + if(s != NULL) { \ + goto *s; \ + } \ + } while(0) + +#define LC_SET(s) \ + do { ({ __label__ resume; resume: (s) = &&resume; }); }while(0) + +#define LC_END(s) + +#endif /* __LC_ADDRLABELS_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-switch.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-switch.h new file mode 100644 index 0000000..17c8811 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-switch.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on switch() statment + * \author Adam Dunkels + * + * This implementation of local continuations uses the C switch() + * statement to resume execution of a function somewhere inside the + * function's body. The implementation is based on the fact that + * switch() statements are able to jump directly into the bodies of + * control structures such as if() or while() statmenets. + * + * This implementation borrows heavily from Simon Tatham's coroutines + * implementation in C: + * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html + */ + +#ifndef __LC_SWITCH_H__ +#define __LC_SWTICH_H__ + +/* WARNING! lc implementation using switch() does not work if an + LC_SET() is done within another switch() statement! */ + +/** \hideinitializer */ +typedef unsigned short lc_t; + +#define LC_INIT(s) s = 0; + +#define LC_RESUME(s) switch(s) { case 0: + +#define LC_SET(s) s = __LINE__; case __LINE__: + +#define LC_END(s) } + +#endif /* __LC_SWITCH_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc.h new file mode 100644 index 0000000..3ad83cd --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \defgroup lc Local continuations + * @{ + * + * Local continuations form the basis for implementing protothreads. A + * local continuation can be set in a specific function to + * capture the state of the function. After a local continuation has + * been set can be resumed in order to restore the state of the + * function at the point where the local continuation was set. + * + * + */ + +/** + * \file lc.h + * Local continuations + * \author + * Adam Dunkels + * + */ + +#ifdef DOXYGEN +/** + * Initialize a local continuation. + * + * This operation initializes the local continuation, thereby + * unsetting any previously set continuation state. + * + * \hideinitializer + */ +#define LC_INIT(lc) + +/** + * Set a local continuation. + * + * The set operation saves the state of the function at the point + * where the operation is executed. As far as the set operation is + * concerned, the state of the function does not include the + * call-stack or local (automatic) variables, but only the program + * counter and such CPU registers that needs to be saved. + * + * \hideinitializer + */ +#define LC_SET(lc) + +/** + * Resume a local continuation. + * + * The resume operation resumes a previously set local continuation, thus + * restoring the state in which the function was when the local + * continuation was set. If the local continuation has not been + * previously set, the resume operation does nothing. + * + * \hideinitializer + */ +#define LC_RESUME(lc) + +/** + * Mark the end of local continuation usage. + * + * The end operation signifies that local continuations should not be + * used any more in the function. This operation is not needed for + * most implementations of local continuation, but is required by a + * few implementations. + * + * \hideinitializer + */ +#define LC_END(lc) + +/** + * \var typedef lc_t; + * + * The local continuation type. + * + * \hideinitializer + */ +#endif /* DOXYGEN */ + +#ifndef __LC_H__ +#define __LC_H__ + +#ifdef LC_CONF_INCLUDE +#include LC_CONF_INCLUDE +#else +#include "lc-switch.h" +#endif /* LC_CONF_INCLUDE */ + +#endif /* __LC_H__ */ + +/** @} */ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.c new file mode 100644 index 0000000..d29ef01 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.c @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: psock.c,v 1.1 2007/01/04 11:06:40 adamdunkels Exp $ + */ +#include +#include + +#include "uipopt.h" +#include "psock.h" +#include "uip.h" + +#define STATE_NONE 0 +#define STATE_ACKED 1 +#define STATE_READ 2 +#define STATE_BLOCKED_NEWDATA 3 +#define STATE_BLOCKED_CLOSE 4 +#define STATE_BLOCKED_SEND 5 +#define STATE_DATA_SENT 6 + +/* + * Return value of the buffering functions that indicates that a + * buffer was not filled by incoming data. + * + */ +#define BUF_NOT_FULL 0 +#define BUF_NOT_FOUND 0 + +/* + * Return value of the buffering functions that indicates that a + * buffer was completely filled by incoming data. + * + */ +#define BUF_FULL 1 + +/* + * Return value of the buffering functions that indicates that an + * end-marker byte was found. + * + */ +#define BUF_FOUND 2 + +/*---------------------------------------------------------------------------*/ +static void buf_setup( struct psock_buf *buf, u8_t *bufptr, u16_t bufsize ) +{ + buf->ptr = bufptr; + buf->left = bufsize; +} + +/*---------------------------------------------------------------------------*/ +static u8_t buf_bufdata( struct psock_buf *buf, u16_t len, u8_t **dataptr, u16_t *datalen ) +{ + ( void ) len; + + if( *datalen < buf->left ) + { + memcpy( buf->ptr, *dataptr, *datalen ); + buf->ptr += *datalen; + buf->left -= *datalen; + *dataptr += *datalen; + *datalen = 0; + return BUF_NOT_FULL; + } + else if( *datalen == buf->left ) + { + memcpy( buf->ptr, *dataptr, *datalen ); + buf->ptr += *datalen; + buf->left = 0; + *dataptr += *datalen; + *datalen = 0; + return BUF_FULL; + } + else + { + memcpy( buf->ptr, *dataptr, buf->left ); + buf->ptr += buf->left; + *datalen -= buf->left; + *dataptr += buf->left; + buf->left = 0; + return BUF_FULL; + } +} + +/*---------------------------------------------------------------------------*/ +static u8_t buf_bufto( register struct psock_buf *buf, u8_t endmarker, register u8_t **dataptr, register u16_t *datalen ) +{ + u8_t c; + while( buf->left > 0 && *datalen > 0 ) + { + c = *buf->ptr = **dataptr; + ++ *dataptr; + ++buf->ptr; + -- *datalen; + --buf->left; + + if( c == endmarker ) + { + return BUF_FOUND; + } + } + + if( *datalen == 0 ) + { + return BUF_NOT_FOUND; + } + + while( *datalen > 0 ) + { + c = **dataptr; + -- *datalen; + ++ *dataptr; + + if( c == endmarker ) + { + return BUF_FOUND | BUF_FULL; + } + } + + return BUF_FULL; +} + +/*---------------------------------------------------------------------------*/ +static char send_data( register struct psock *s ) +{ + if( s->state != STATE_DATA_SENT || uip_rexmit() ) + { + if( s->sendlen > uip_mss() ) + { + uip_send( s->sendptr, uip_mss() ); + } + else + { + uip_send( s->sendptr, s->sendlen ); + } + + s->state = STATE_DATA_SENT; + return 1; + } + + return 0; +} + +/*---------------------------------------------------------------------------*/ +static char data_acked( register struct psock *s ) +{ + if( s->state == STATE_DATA_SENT && uip_acked() ) + { + if( s->sendlen > uip_mss() ) + { + s->sendlen -= uip_mss(); + s->sendptr += uip_mss(); + } + else + { + s->sendptr += s->sendlen; + s->sendlen = 0; + } + + s->state = STATE_ACKED; + return 1; + } + + return 0; +} + +/*---------------------------------------------------------------------------*/ +PT_THREAD( psock_send ( register struct psock *s, const char *buf, unsigned int len ) ) +{ + PT_BEGIN( &s->psockpt ); + + /* If there is no data to send, we exit immediately. */ + if( len == 0 ) + { + PT_EXIT( &s->psockpt ); + } + + /* Save the length of and a pointer to the data that is to be + sent. */ + s->sendptr = ( u8_t * ) buf; + s->sendlen = len; + + s->state = STATE_NONE; + + /* We loop here until all data is sent. The s->sendlen variable is + updated by the data_sent() function. */ + while( s->sendlen > 0 ) + { + /* + * The condition for this PT_WAIT_UNTIL is a little tricky: the + * protothread will wait here until all data has been acknowledged + * (data_acked() returns true) and until all data has been sent + * (send_data() returns true). The two functions data_acked() and + * send_data() must be called in succession to ensure that all + * data is sent. Therefore the & operator is used instead of the + * && operator, which would cause only the data_acked() function + * to be called when it returns false. + */ + PT_WAIT_UNTIL( &s->psockpt, data_acked(s) & send_data(s) ); + } + + s->state = STATE_NONE; + + PT_END( &s->psockpt ); +} + +/*---------------------------------------------------------------------------*/ +PT_THREAD( psock_generator_send ( register struct psock *s, unsigned short ( *generate ) ( void * ), void *arg ) ) +{ + PT_BEGIN( &s->psockpt ); + + /* Ensure that there is a generator function to call. */ + if( generate == NULL ) + { + PT_EXIT( &s->psockpt ); + } + + /* Call the generator function to generate the data in the + uip_appdata buffer. */ + s->sendlen = generate( arg ); + s->sendptr = uip_appdata; + + s->state = STATE_NONE; + do + { + /* Call the generator function again if we are called to perform a + retransmission. */ + if( uip_rexmit() ) + { + generate( arg ); + } + + /* Wait until all data is sent and acknowledged. */ + PT_WAIT_UNTIL( &s->psockpt, data_acked(s) & send_data(s) ); + } while( s->sendlen > 0 ); + + s->state = STATE_NONE; + + PT_END( &s->psockpt ); +} + +/*---------------------------------------------------------------------------*/ +u16_t psock_datalen( struct psock *psock ) +{ + return psock->bufsize - psock->buf.left; +} + +/*---------------------------------------------------------------------------*/ +char psock_newdata( struct psock *s ) +{ + if( s->readlen > 0 ) + { + /* There is data in the uip_appdata buffer that has not yet been + read with the PSOCK_READ functions. */ + return 1; + } + else if( s->state == STATE_READ ) + { + /* All data in uip_appdata buffer already consumed. */ + s->state = STATE_BLOCKED_NEWDATA; + return 0; + } + else if( uip_newdata() ) + { + /* There is new data that has not been consumed. */ + return 1; + } + else + { + /* There is no new data. */ + return 0; + } +} + +/*---------------------------------------------------------------------------*/ +PT_THREAD( psock_readto ( register struct psock *psock, unsigned char c ) ) +{ + PT_BEGIN( &psock->psockpt ); + + buf_setup( &psock->buf, ( u8_t * ) psock->bufptr, psock->bufsize ); + + /* XXX: Should add buf_checkmarker() before do{} loop, if + incoming data has been handled while waiting for a write. */ + do + { + if( psock->readlen == 0 ) + { + PT_WAIT_UNTIL( &psock->psockpt, psock_newdata(psock) ); + psock->state = STATE_READ; + psock->readptr = ( u8_t * ) uip_appdata; + psock->readlen = uip_datalen(); + } + } while( (buf_bufto(&psock->buf, c, &psock->readptr, &psock->readlen) & BUF_FOUND) == 0 ); + + if( psock_datalen(psock) == 0 ) + { + psock->state = STATE_NONE; + PT_RESTART( &psock->psockpt ); + } + + PT_END( &psock->psockpt ); +} + +/*---------------------------------------------------------------------------*/ +PT_THREAD( psock_readbuf ( register struct psock *psock ) ) +{ + PT_BEGIN( &psock->psockpt ); + + buf_setup( &psock->buf, ( u8_t * ) psock->bufptr, psock->bufsize ); + + /* XXX: Should add buf_checkmarker() before do{} loop, if + incoming data has been handled while waiting for a write. */ + do + { + if( psock->readlen == 0 ) + { + PT_WAIT_UNTIL( &psock->psockpt, psock_newdata(psock) ); + printf( "Waited for newdata\n" ); + psock->state = STATE_READ; + psock->readptr = ( u8_t * ) uip_appdata; + psock->readlen = uip_datalen(); + } + } while( buf_bufdata(&psock->buf, psock->bufsize, &psock->readptr, &psock->readlen) != BUF_FULL ); + + if( psock_datalen(psock) == 0 ) + { + psock->state = STATE_NONE; + PT_RESTART( &psock->psockpt ); + } + + PT_END( &psock->psockpt ); +} + +/*---------------------------------------------------------------------------*/ +void psock_init( register struct psock *psock, char *buffer, unsigned int buffersize ) +{ + psock->state = STATE_NONE; + psock->readlen = 0; + psock->bufptr = buffer; + psock->bufsize = buffersize; + buf_setup( &psock->buf, ( u8_t * ) buffer, buffersize ); + PT_INIT( &psock->pt ); + PT_INIT( &psock->psockpt ); +} + +/*---------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.h new file mode 100644 index 0000000..8d41258 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.h @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \defgroup psock Protosockets library + * @{ + * + * The protosocket library provides an interface to the uIP stack that is + * similar to the traditional BSD socket interface. Unlike programs + * written for the ordinary uIP event-driven interface, programs + * written with the protosocket library are executed in a sequential + * fashion and does not have to be implemented as explicit state + * machines. + * + * Protosockets only work with TCP connections. + * + * The protosocket library uses \ref pt protothreads to provide + * sequential control flow. This makes the protosockets lightweight in + * terms of memory, but also means that protosockets inherits the + * functional limitations of protothreads. Each protosocket lives only + * within a single function. Automatic variables (stack variables) are + * not retained across a protosocket library function call. + * + * \note Because the protosocket library uses protothreads, local + * variables will not always be saved across a call to a protosocket + * library function. It is therefore advised that local variables are + * used with extreme care. + * + * The protosocket library provides functions for sending data without + * having to deal with retransmissions and acknowledgements, as well + * as functions for reading data without having to deal with data + * being split across more than one TCP segment. + * + * Because each protosocket runs as a protothread, the protosocket has to be + * started with a call to PSOCK_BEGIN() at the start of the function + * in which the protosocket is used. Similarly, the protosocket protothread can + * be terminated by a call to PSOCK_EXIT(). + * + */ + +/** + * \file + * Protosocket library header file + * \author + * Adam Dunkels + * + */ + +#ifndef __PSOCK_H__ +#define __PSOCK_H__ + +#include "uipopt.h" +#include "pt.h" + + /* + * The structure that holds the state of a buffer. + * + * This structure holds the state of a uIP buffer. The structure has + * no user-visible elements, but is used through the functions + * provided by the library. + * + */ +struct psock_buf { + u8_t *ptr; + unsigned short left; +}; + +/** + * The representation of a protosocket. + * + * The protosocket structrure is an opaque structure with no user-visible + * elements. + */ +struct psock { + struct pt pt, psockpt; /* Protothreads - one that's using the psock + functions, and one that runs inside the + psock functions. */ + const u8_t *sendptr; /* Pointer to the next data to be sent. */ + u8_t *readptr; /* Pointer to the next data to be read. */ + + char *bufptr; /* Pointer to the buffer used for buffering + incoming data. */ + + u16_t sendlen; /* The number of bytes left to be sent. */ + u16_t readlen; /* The number of bytes left to be read. */ + + struct psock_buf buf; /* The structure holding the state of the + input buffer. */ + unsigned int bufsize; /* The size of the input buffer. */ + + unsigned char state; /* The state of the protosocket. */ +}; + +void psock_init(struct psock *psock, char *buffer, unsigned int buffersize); +/** + * Initialize a protosocket. + * + * This macro initializes a protosocket and must be called before the + * protosocket is used. The initialization also specifies the input buffer + * for the protosocket. + * + * \param psock (struct psock *) A pointer to the protosocket to be + * initialized + * + * \param buffer (char *) A pointer to the input buffer for the + * protosocket. + * + * \param buffersize (unsigned int) The size of the input buffer. + * + * \hideinitializer + */ +#define PSOCK_INIT(psock, buffer, buffersize) \ + psock_init(psock, buffer, buffersize) + +/** + * Start the protosocket protothread in a function. + * + * This macro starts the protothread associated with the protosocket and + * must come before other protosocket calls in the function it is used. + * + * \param psock (struct psock *) A pointer to the protosocket to be + * started. + * + * \hideinitializer + */ +#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt)) + +PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len)); +/** + * Send data. + * + * This macro sends data over a protosocket. The protosocket protothread blocks + * until all data has been sent and is known to have been received by + * the remote end of the TCP connection. + * + * \param psock (struct psock *) A pointer to the protosocket over which + * data is to be sent. + * + * \param data (char *) A pointer to the data that is to be sent. + * + * \param datalen (unsigned int) The length of the data that is to be + * sent. + * + * \hideinitializer + */ +#define PSOCK_SEND(psock, data, datalen) \ + PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen)) + +/** + * \brief Send a null-terminated string. + * \param psock Pointer to the protosocket. + * \param str The string to be sent. + * + * This function sends a null-terminated string over the + * protosocket. + * + * \hideinitializer + */ +#define PSOCK_SEND_STR(psock, str) \ + PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str))) + +PT_THREAD(psock_generator_send(struct psock *psock, + unsigned short (*f)(void *), void *arg)); + +/** + * \brief Generate data with a function and send it + * \param psock Pointer to the protosocket. + * \param generator Pointer to the generator function + * \param arg Argument to the generator function + * + * This function generates data and sends it over the + * protosocket. This can be used to dynamically generate + * data for a transmission, instead of generating the data + * in a buffer beforehand. This function reduces the need for + * buffer memory. The generator function is implemented by + * the application, and a pointer to the function is given + * as an argument with the call to PSOCK_GENERATOR_SEND(). + * + * The generator function should place the generated data + * directly in the uip_appdata buffer, and return the + * length of the generated data. The generator function is + * called by the protosocket layer when the data first is + * sent, and once for every retransmission that is needed. + * + * \hideinitializer + */ +#define PSOCK_GENERATOR_SEND(psock, generator, arg) \ + PT_WAIT_THREAD(&((psock)->pt), \ + psock_generator_send(psock, generator, arg)) + + +/** + * Close a protosocket. + * + * This macro closes a protosocket and can only be called from within the + * protothread in which the protosocket lives. + * + * \param psock (struct psock *) A pointer to the protosocket that is to + * be closed. + * + * \hideinitializer + */ +#define PSOCK_CLOSE(psock) uip_close() + +PT_THREAD(psock_readbuf(struct psock *psock)); +/** + * Read data until the buffer is full. + * + * This macro will block waiting for data and read the data into the + * input buffer specified with the call to PSOCK_INIT(). Data is read + * until the buffer is full.. + * + * \param psock (struct psock *) A pointer to the protosocket from which + * data should be read. + * + * \hideinitializer + */ +#define PSOCK_READBUF(psock) \ + PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock)) + +PT_THREAD(psock_readto(struct psock *psock, unsigned char c)); +/** + * Read data up to a specified character. + * + * This macro will block waiting for data and read the data into the + * input buffer specified with the call to PSOCK_INIT(). Data is only + * read until the specifieed character appears in the data stream. + * + * \param psock (struct psock *) A pointer to the protosocket from which + * data should be read. + * + * \param c (char) The character at which to stop reading. + * + * \hideinitializer + */ +#define PSOCK_READTO(psock, c) \ + PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c)) + +/** + * The length of the data that was previously read. + * + * This macro returns the length of the data that was previously read + * using PSOCK_READTO() or PSOCK_READ(). + * + * \param psock (struct psock *) A pointer to the protosocket holding the data. + * + * \hideinitializer + */ +#define PSOCK_DATALEN(psock) psock_datalen(psock) + +u16_t psock_datalen(struct psock *psock); + +/** + * Exit the protosocket's protothread. + * + * This macro terminates the protothread of the protosocket and should + * almost always be used in conjunction with PSOCK_CLOSE(). + * + * \sa PSOCK_CLOSE_EXIT() + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt)) + +/** + * Close a protosocket and exit the protosocket's protothread. + * + * This macro closes a protosocket and exits the protosocket's protothread. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_CLOSE_EXIT(psock) \ + do { \ + PSOCK_CLOSE(psock); \ + PSOCK_EXIT(psock); \ + } while(0) + +/** + * Declare the end of a protosocket's protothread. + * + * This macro is used for declaring that the protosocket's protothread + * ends. It must always be used together with a matching PSOCK_BEGIN() + * macro. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_END(psock) PT_END(&((psock)->pt)) + +char psock_newdata(struct psock *s); + +/** + * Check if new data has arrived on a protosocket. + * + * This macro is used in conjunction with the PSOCK_WAIT_UNTIL() + * macro to check if data has arrived on a protosocket. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_NEWDATA(psock) psock_newdata(psock) + +/** + * Wait until a condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. The macro PSOCK_NEWDATA() can be used to check if new data + * arrives when the protosocket is waiting. + * + * Typically, this macro is used as follows: + * + \code + PT_THREAD(thread(struct psock *s, struct timer *t)) + { + PSOCK_BEGIN(s); + + PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t)); + + if(PSOCK_NEWDATA(s)) { + PSOCK_READTO(s, '\n'); + } else { + handle_timed_out(s); + } + + PSOCK_END(s); + } + \endcode + * + * \param psock (struct psock *) A pointer to the protosocket. + * \param condition The condition to wait for. + * + * \hideinitializer + */ +#define PSOCK_WAIT_UNTIL(psock, condition) \ + PT_WAIT_UNTIL(&((psock)->pt), (condition)); + +#define PSOCK_WAIT_THREAD(psock, condition) \ + PT_WAIT_THREAD(&((psock)->pt), (condition)) + +#endif /* __PSOCK_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/pt.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/pt.h new file mode 100644 index 0000000..00ddd44 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/pt.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \file + * Protothreads implementation. + * \author + * Adam Dunkels + * + */ + +#ifndef __PT_H__ +#define __PT_H__ + +#include "lc.h" + +struct pt { + lc_t lc; +}; + +#define PT_WAITING 0 +#define PT_EXITED 1 +#define PT_ENDED 2 +#define PT_YIELDED 3 + +/** + * \name Initialization + * @{ + */ + +/** + * Initialize a protothread. + * + * Initializes a protothread. Initialization must be done prior to + * starting to execute the protothread. + * + * \param pt A pointer to the protothread control structure. + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_INIT(pt) LC_INIT((pt)->lc) + +/** @} */ + +/** + * \name Declaration and definition + * @{ + */ + +/** + * Declaration of a protothread. + * + * This macro is used to declare a protothread. All protothreads must + * be declared with this macro. + * + * \param name_args The name and arguments of the C function + * implementing the protothread. + * + * \hideinitializer + */ +#define PT_THREAD(name_args) char name_args + +/** + * Declare the start of a protothread inside the C function + * implementing the protothread. + * + * This macro is used to declare the starting point of a + * protothread. It should be placed at the start of the function in + * which the protothread runs. All C statements above the PT_BEGIN() + * invokation will be executed each time the protothread is scheduled. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc) + +/** + * Declare the end of a protothread. + * + * This macro is used for declaring that a protothread ends. It must + * always be used together with a matching PT_BEGIN() macro. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \ + PT_INIT(pt); return PT_ENDED; } + +/** @} */ + +/** + * \name Blocked wait + * @{ + */ + +/** + * Block and wait until condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. + * + * \param pt A pointer to the protothread control structure. + * \param condition The condition. + * + * \hideinitializer + */ +#define PT_WAIT_UNTIL(pt, condition) \ + do { \ + LC_SET((pt)->lc); \ + if(!(condition)) { \ + return PT_WAITING; \ + } \ + } while(0) + +/** + * Block and wait while condition is true. + * + * This function blocks and waits while condition is true. See + * PT_WAIT_UNTIL(). + * + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * \hideinitializer + */ +#define PT_WAIT_WHILE(pt, cond) PT_WAIT_UNTIL((pt), !(cond)) + +/** @} */ + +/** + * \name Hierarchical protothreads + * @{ + */ + +/** + * Block and wait until a child protothread completes. + * + * This macro schedules a child protothread. The current protothread + * will block until the child protothread completes. + * + * \note The child protothread must be manually initialized with the + * PT_INIT() function before this function is used. + * + * \param pt A pointer to the protothread control structure. + * \param thread The child protothread with arguments + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread)) + +/** + * Spawn a child protothread and wait until it exits. + * + * This macro spawns a child protothread and waits until it exits. The + * macro can only be used within a protothread. + * + * \param pt A pointer to the protothread control structure. + * \param child A pointer to the child protothread's control structure. + * \param thread The child protothread with arguments + * + * \hideinitializer + */ +#define PT_SPAWN(pt, child, thread) \ + do { \ + PT_INIT((child)); \ + PT_WAIT_THREAD((pt), (thread)); \ + } while(0) + +/** @} */ + +/** + * \name Exiting and restarting + * @{ + */ + +/** + * Restart the protothread. + * + * This macro will block and cause the running protothread to restart + * its execution at the place of the PT_BEGIN() call. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_RESTART(pt) \ + do { \ + PT_INIT(pt); \ + return PT_WAITING; \ + } while(0) + +/** + * Exit the protothread. + * + * This macro causes the protothread to exit. If the protothread was + * spawned by another protothread, the parent protothread will become + * unblocked and can continue to run. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_EXIT(pt) \ + do { \ + PT_INIT(pt); \ + return PT_EXITED; \ + } while(0) + +/** @} */ + +/** + * \name Calling a protothread + * @{ + */ + +/** + * Schedule a protothread. + * + * This function shedules a protothread. The return value of the + * function is non-zero if the protothread is running or zero if the + * protothread has exited. + * + * \param f The call to the C function implementing the protothread to + * be scheduled + * + * \hideinitializer + */ +#define PT_SCHEDULE(f) ((f) == PT_WAITING) + +/** @} */ + +/** + * \name Yielding from a protothread + * @{ + */ + +/** + * Yield from the current protothread. + * + * This function will yield the protothread, thereby allowing other + * processing to take place in the system. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_YIELD(pt) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if(PT_YIELD_FLAG == 0) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** + * \brief Yield from the protothread until a condition occurs. + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * This function will yield the protothread, until the + * specified condition evaluates to true. + * + * + * \hideinitializer + */ +#define PT_YIELD_UNTIL(pt, cond) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if((PT_YIELD_FLAG == 0) || !(cond)) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** @} */ + +#endif /* __PT_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.c new file mode 100644 index 0000000..9a63653 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.c @@ -0,0 +1,130 @@ +/** + * \addtogroup timer + * @{ + */ + +/** + * \file + * Timer library implementation. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: timer.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +#include "clock.h" +#include "uip_timer.h" + +/*---------------------------------------------------------------------------*/ + +/** + * Set a timer. + * + * This function is used to set a timer for a time sometime in the + * future. The function timer_expired() will evaluate to true after + * the timer has expired. + * + * \param t A pointer to the timer + * \param interval The interval before the timer expires. + * + */ +void timer_set( struct timer *t, clock_time_t interval ) +{ + t->interval = interval; + t->start = clock_time(); +} + +/*---------------------------------------------------------------------------*/ + +/** + * Reset the timer with the same interval. + * + * This function resets the timer with the same interval that was + * given to the timer_set() function. The start point of the interval + * is the exact time that the timer last expired. Therefore, this + * function will cause the timer to be stable over time, unlike the + * timer_rester() function. + * + * \param t A pointer to the timer. + * + * \sa timer_restart() + */ +void timer_reset( struct timer *t ) +{ + t->start += t->interval; +} + +/*---------------------------------------------------------------------------*/ + +/** + * Restart the timer from the current point in time + * + * This function restarts a timer with the same interval that was + * given to the timer_set() function. The timer will start at the + * current time. + * + * \note A periodic timer will drift if this function is used to reset + * it. For preioric timers, use the timer_reset() function instead. + * + * \param t A pointer to the timer. + * + * \sa timer_reset() + */ +void timer_restart( struct timer *t ) +{ + t->start = clock_time(); +} + +/*---------------------------------------------------------------------------*/ + +/** + * Check if a timer has expired. + * + * This function tests if a timer has expired and returns true or + * false depending on its status. + * + * \param t A pointer to the timer + * + * \return Non-zero if the timer has expired, zero otherwise. + * + */ +int timer_expired( struct timer *t ) +{ + return( clock_time_t ) ( clock_time() - t->start ) >= ( clock_time_t ) t->interval; +} + +/*---------------------------------------------------------------------------*/ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.h new file mode 100644 index 0000000..e28e3ca --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.h @@ -0,0 +1,86 @@ +/** + * \defgroup timer Timer library + * + * The timer library provides functions for setting, resetting and + * restarting timers, and for checking if a timer has expired. An + * application must "manually" check if its timers have expired; this + * is not done automatically. + * + * A timer is declared as a \c struct \c timer and all access to the + * timer is made by a pointer to the declared timer. + * + * \note The timer library uses the \ref clock "Clock library" to + * measure time. Intervals should be specified in the format used by + * the clock library. + * + * @{ + */ + + +/** + * \file + * Timer library header file. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $ + */ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "clock.h" + +/** + * A timer. + * + * This structure is used for declaring a timer. The timer must be set + * with timer_set() before it can be used. + * + * \hideinitializer + */ +struct timer { + clock_time_t start; + clock_time_t interval; +}; + +void timer_set(struct timer *t, clock_time_t interval); +void timer_reset(struct timer *t); +void timer_restart(struct timer *t); +int timer_expired(struct timer *t); + +#endif /* __TIMER_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-fw.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-fw.h new file mode 100644 index 0000000..e854ece --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-fw.h @@ -0,0 +1,176 @@ +/** + * \addtogroup uipfw + * @{ + */ + +/** + * \file + * uIP packet forwarding header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-fw.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +#ifndef __UIP_FW_H__ +#define __UIP_FW_H__ + +#include "uip.h" + +/** + * Representation of a uIP network interface. + */ +struct uip_fw_netif { + struct uip_fw_netif *next; /**< Pointer to the next interface when + linked in a list. */ + u16_t ipaddr[2]; /**< The IP address of this interface. */ + u16_t netmask[2]; /**< The netmask of the interface. */ + u8_t (* output)(void); + /**< A pointer to the function that + sends a packet. */ +}; + +/** + * Intantiating macro for a uIP network interface. + * + * Example: + \code + struct uip_fw_netif slipnetif = + {UIP_FW_NETIF(192,168,76,1, 255,255,255,0, slip_output)}; + \endcode + * \param ip1,ip2,ip3,ip4 The IP address of the network interface. + * + * \param nm1,nm2,nm3,nm4 The netmask of the network interface. + * + * \param outputfunc A pointer to the output function of the network interface. + * + * \hideinitializer + */ +#define UIP_FW_NETIF(ip1,ip2,ip3,ip4, nm1,nm2,nm3,nm4, outputfunc) \ + NULL, \ + {HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \ + {HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \ + outputfunc + +/** + * Set the IP address of a network interface. + * + * \param netif A pointer to the uip_fw_netif structure for the network interface. + * + * \param addr A pointer to an IP address. + * + * \hideinitializer + */ +#define uip_fw_setipaddr(netif, addr) \ + do { (netif)->ipaddr[0] = ((u16_t *)(addr))[0]; \ + (netif)->ipaddr[1] = ((u16_t *)(addr))[1]; } while(0) +/** + * Set the netmask of a network interface. + * + * \param netif A pointer to the uip_fw_netif structure for the network interface. + * + * \param addr A pointer to an IP address representing the netmask. + * + * \hideinitializer + */ +#define uip_fw_setnetmask(netif, addr) \ + do { (netif)->netmask[0] = ((u16_t *)(addr))[0]; \ + (netif)->netmask[1] = ((u16_t *)(addr))[1]; } while(0) + +void uip_fw_init(void); +u8_t uip_fw_forward(void); +u8_t uip_fw_output(void); +void uip_fw_register(struct uip_fw_netif *netif); +void uip_fw_default(struct uip_fw_netif *netif); +void uip_fw_periodic(void); + + +/** + * A non-error message that indicates that a packet should be + * processed locally. + * + * \hideinitializer + */ +#define UIP_FW_LOCAL 0 + +/** + * A non-error message that indicates that something went OK. + * + * \hideinitializer + */ +#define UIP_FW_OK 0 + +/** + * A non-error message that indicates that a packet was forwarded. + * + * \hideinitializer + */ +#define UIP_FW_FORWARDED 1 + +/** + * A non-error message that indicates that a zero-length packet + * transmission was attempted, and that no packet was sent. + * + * \hideinitializer + */ +#define UIP_FW_ZEROLEN 2 + +/** + * An error message that indicates that a packet that was too large + * for the outbound network interface was detected. + * + * \hideinitializer + */ +#define UIP_FW_TOOLARGE 3 + +/** + * An error message that indicates that no suitable interface could be + * found for an outbound packet. + * + * \hideinitializer + */ +#define UIP_FW_NOROUTE 4 + +/** + * An error message that indicates that a packet that should be + * forwarded or output was dropped. + * + * \hideinitializer + */ +#define UIP_FW_DROPPED 5 + + +#endif /* __UIP_FW_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-neighbor.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-neighbor.h new file mode 100644 index 0000000..aca096f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-neighbor.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-neighbor.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \file + * Header file for database of link-local neighbors, used by + * IPv6 code and to be used by future ARP code. + * \author + * Adam Dunkels + */ + +#ifndef __UIP_NEIGHBOR_H__ +#define __UIP_NEIGHBOR_H__ + +#include "uip.h" + +struct uip_neighbor_addr { +#if UIP_NEIGHBOR_CONF_ADDRTYPE + UIP_NEIGHBOR_CONF_ADDRTYPE addr; +#else + struct uip_eth_addr addr; +#endif +}; + +void uip_neighbor_init(void); +void uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr); +void uip_neighbor_update(uip_ipaddr_t ipaddr); +struct uip_neighbor_addr *uip_neighbor_lookup(uip_ipaddr_t ipaddr); +void uip_neighbor_periodic(void); + +#endif /* __UIP-NEIGHBOR_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.c new file mode 100644 index 0000000..6828f3c --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-split.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +#include + +#include "uip-split.h" +#include "uip.h" +#include "uip-fw.h" +#include "uip_arch.h" + +#define BUF ( ( struct uip_tcpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) + +/*-----------------------------------------------------------------------------*/ +void uip_split_output( void ) +{ + u16_t tcplen, len1, len2; + + /* We only try to split maximum sized TCP segments. */ + if( BUF->proto == UIP_PROTO_TCP && uip_len == UIP_BUFSIZE - UIP_LLH_LEN ) + { + tcplen = uip_len - UIP_TCPIP_HLEN; + + /* Split the segment in two. If the original packet length was + odd, we make the second packet one byte larger. */ + len1 = len2 = tcplen / 2; + if( len1 + len2 < tcplen ) + { + ++len2; + } + + /* Create the first packet. This is done by altering the length + field of the IP header and updating the checksums. */ + uip_len = len1 + UIP_TCPIP_HLEN; + #if UIP_CONF_IPV6 + + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 ); + BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff ); + #else /* UIP_CONF_IPV6 */ + BUF->len[0] = uip_len >> 8; + BUF->len[1] = uip_len & 0xff; + #endif /* UIP_CONF_IPV6 */ + + /* Recalculate the TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~( uip_tcpchksum() ); + + #if !UIP_CONF_IPV6 + + /* Recalculate the IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + #endif /* UIP_CONF_IPV6 */ + + /* Transmit the first packet. */ + + /* uip_fw_output();*/ + + // tcpip_output(); + + /* Now, create the second packet. To do this, it is not enough to + just alter the length field, but we must also update the TCP + sequence number and point the uip_appdata to a new place in + memory. This place is detemined by the length of the first + packet (len1). */ + uip_len = len2 + UIP_TCPIP_HLEN; + #if UIP_CONF_IPV6 + + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 ); + BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff ); + #else /* UIP_CONF_IPV6 */ + BUF->len[0] = uip_len >> 8; + BUF->len[1] = uip_len & 0xff; + #endif /* UIP_CONF_IPV6 */ + + /* uip_appdata += len1;*/ + memcpy( uip_appdata, ( u8_t * ) uip_appdata + len1, len2 ); + + uip_add32( BUF->seqno, len1 ); + BUF->seqno[0] = uip_acc32[0]; + BUF->seqno[1] = uip_acc32[1]; + BUF->seqno[2] = uip_acc32[2]; + BUF->seqno[3] = uip_acc32[3]; + + /* Recalculate the TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~( uip_tcpchksum() ); + + #if !UIP_CONF_IPV6 + + /* Recalculate the IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + #endif /* UIP_CONF_IPV6 */ + + /* Transmit the second packet. */ + + /* uip_fw_output();*/ + + // tcpip_output(); + } + else + { + /* uip_fw_output();*/ + + // tcpip_output(); + } +} + +/*-----------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.h new file mode 100644 index 0000000..446e192 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-split.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uipsplit uIP TCP throughput booster hack + * @{ + * + * The basic uIP TCP implementation only allows each TCP connection to + * have a single TCP segment in flight at any given time. Because of + * the delayed ACK algorithm employed by most TCP receivers, uIP's + * limit on the amount of in-flight TCP segments seriously reduces the + * maximum achievable throughput for sending data from uIP. + * + * The uip-split module is a hack which tries to remedy this + * situation. By splitting maximum sized outgoing TCP segments into + * two, the delayed ACK algorithm is not invoked at TCP + * receivers. This improves the throughput when sending data from uIP + * by orders of magnitude. + * + * The uip-split module uses the uip-fw module (uIP IP packet + * forwarding) for sending packets. Therefore, the uip-fw module must + * be set up with the appropriate network interfaces for this module + * to work. + */ + + +/** + * \file + * Module for splitting outbound TCP segments in two to avoid the + * delayed ACK throughput degradation. + * \author + * Adam Dunkels + * + */ + +#ifndef __UIP_SPLIT_H__ +#define __UIP_SPLIT_H__ + +/** + * Handle outgoing packets. + * + * This function inspects an outgoing packet in the uip_buf buffer and + * sends it out using the uip_fw_output() function. If the packet is a + * full-sized TCP segment it will be split into two segments and + * transmitted separately. This function should be called instead of + * the actual device driver output function, or the uip_fw_output() + * function. + * + * The headers of the outgoing packet is assumed to be in the uip_buf + * buffer and the payload is assumed to be wherever uip_appdata + * points. The length of the outgoing packet is assumed to be in the + * uip_len variable. + * + */ +void uip_split_output(void); + +#endif /* __UIP_SPLIT_H__ */ + +/** @} */ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.c new file mode 100644 index 0000000..1c07f35 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.c @@ -0,0 +1,2233 @@ +#define DEBUG_PRINTF( ... ) /*printf(__VA_ARGS__)*/ + +/** + * \defgroup uip The uIP TCP/IP stack + * @{ + * + * uIP is an implementation of the TCP/IP protocol stack intended for + * small 8-bit and 16-bit microcontrollers. + * + * uIP provides the necessary protocols for Internet communication, + * with a very small code footprint and RAM requirements - the uIP + * code size is on the order of a few kilobytes and RAM usage is on + * the order of a few hundred bytes. + */ + +/** + * \file + * The uIP TCP/IP stack code. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.c,v 1.65 2006/06/11 21:46:39 adam Exp $ + * + */ + +/* + * uIP is a small implementation of the IP, UDP and TCP protocols (as + * well as some basic ICMP stuff). The implementation couples the IP, + * UDP, TCP and the application layers very tightly. To keep the size + * of the compiled code down, this code frequently uses the goto + * statement. While it would be possible to break the uip_process() + * function into many smaller functions, this would increase the code + * size because of the overhead of parameter passing and the fact that + * the optimier would not be as efficient. + * + * The principle is that we have a small buffer, called the uip_buf, + * in which the device driver puts an incoming packet. The TCP/IP + * stack parses the headers in the packet, and calls the + * application. If the remote host has sent data to the application, + * this data is present in the uip_buf and the application read the + * data from there. It is up to the application to put this data into + * a byte stream if needed. The application will not be fed with data + * that is out of sequence. + * + * If the application whishes to send data to the peer, it should put + * its data into the uip_buf. The uip_appdata pointer points to the + * first available byte. The TCP/IP stack will calculate the + * checksums, and fill in the necessary header fields and finally send + * the packet back to the peer. +*/ +#include "uip.h" +#include "uipopt.h" +#include "uip_arch.h" +#include "uip_arp.h" +#include "FreeRTOS.h" + +#if UIP_CONF_IPV6 + #include "uip-neighbor.h" +#endif /* UIP_CONF_IPV6 */ + +#include + +/*---------------------------------------------------------------------------*/ + +/* Variable definitions. */ + +/* The IP address of this host. If it is defined to be fixed (by + setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set + here. Otherwise, the address */ +#if UIP_FIXEDADDR > 0 +const uip_ipaddr_t uip_hostaddr = { HTONS( (UIP_IPADDR0 << 8) | UIP_IPADDR1 ), HTONS( (UIP_IPADDR2 << 8) | UIP_IPADDR3 ) }; +const uip_ipaddr_t uip_draddr = { HTONS( (UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1 ), HTONS( (UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3 ) }; +const uip_ipaddr_t uip_netmask = { HTONS( (UIP_NETMASK0 << 8) | UIP_NETMASK1 ), HTONS( (UIP_NETMASK2 << 8) | UIP_NETMASK3 ) }; +#else +uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask; +#endif /* UIP_FIXEDADDR */ + +static const uip_ipaddr_t all_ones_addr = +#if UIP_CONF_IPV6 +{ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff }; +#else /* UIP_CONF_IPV6 */ +{ + 0xffff, 0xffff +}; +#endif /* UIP_CONF_IPV6 */ +static const uip_ipaddr_t all_zeroes_addr = +#if UIP_CONF_IPV6 +{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; +#else /* UIP_CONF_IPV6 */ +{ + 0x0000, 0x0000 +}; +#endif /* UIP_CONF_IPV6 */ + +#if UIP_FIXEDETHADDR +const struct uip_eth_addr uip_ethaddr = { { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 } }; +#else +struct uip_eth_addr uip_ethaddr = { { 0, 0, 0, 0, 0, 0 } }; +#endif +#ifndef UIP_CONF_EXTERNAL_BUFFER + #ifdef __ICCARM__ + #pragma data_alignment = 4 +u8_t uip_buf[UIP_BUFSIZE + 2]; /* The packet buffer that contains incoming packets. */ + #else +u8_t uip_buf[UIP_BUFSIZE + 2] ALIGN_STRUCT_END; /* The packet buffer that contains incoming packets. */ + #endif +#endif /* UIP_CONF_EXTERNAL_BUFFER */ + +void *uip_appdata; /* The uip_appdata pointer points to + application data. */ +void *uip_sappdata; /* The uip_appdata pointer points to + the application data which is to + be sent. */ +#if UIP_URGDATA > 0 +void *uip_urgdata; /* The uip_urgdata pointer points to + urgent data (out-of-band data), if + present. */ +u16_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +u16_t uip_len, uip_slen; + +/* The uip_len is either 8 or 16 bits, + depending on the maximum packet + size. */ +u8_t uip_flags; /* The uip_flags variable is used for + communication between the TCP/IP stack + and the application program. */ +struct uip_conn *uip_conn; /* uip_conn always points to the current + connection. */ + +struct uip_conn uip_conns[UIP_CONNS]; + +/* The uip_conns array holds all TCP + connections. */ +u16_t uip_listenports[UIP_LISTENPORTS]; + +/* The uip_listenports list all currently + listning ports. */ +#if UIP_UDP +struct uip_udp_conn *uip_udp_conn; +struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +static u16_t ipid; /* Ths ipid variable is an increasing + number that is used for the IP ID + field. */ + +void uip_setipid( u16_t id ) +{ + ipid = id; +} + +static u8_t iss[4]; /* The iss variable is used for the TCP + initial sequence number. */ + +#if UIP_ACTIVE_OPEN +static u16_t lastport; /* Keeps track of the last port used for + a new connection. */ +#endif /* UIP_ACTIVE_OPEN */ + +/* Temporary variables. */ +u8_t uip_acc32[4]; +static u8_t c, opt; +static u16_t tmp16; + +/* Structures and definitions. */ +#define TCP_FIN 0x01 +#define TCP_SYN 0x02 +#define TCP_RST 0x04 +#define TCP_PSH 0x08 +#define TCP_ACK 0x10 +#define TCP_URG 0x20 +#define TCP_CTL 0x3f + +#define TCP_OPT_END 0 /* End of TCP options list */ +#define TCP_OPT_NOOP 1 /* "No-operation" TCP option */ +#define TCP_OPT_MSS 2 /* Maximum segment size TCP option */ + +#define TCP_OPT_MSS_LEN 4 /* Length of TCP MSS option. */ + +#define ICMP_ECHO_REPLY 0 +#define ICMP_ECHO 8 + +#define ICMP6_ECHO_REPLY 129 +#define ICMP6_ECHO 128 +#define ICMP6_NEIGHBOR_SOLICITATION 135 +#define ICMP6_NEIGHBOR_ADVERTISEMENT 136 + +#define ICMP6_FLAG_S ( 1 << 6 ) +#define ICMP6_OPTION_SOURCE_LINK_ADDRESS 1 +#define ICMP6_OPTION_TARGET_LINK_ADDRESS 2 + +/* Macros. */ +#define BUF ( ( struct uip_tcpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) +#define FBUF ( ( struct uip_tcpip_hdr * ) &uip_reassbuf[0] ) +#define ICMPBUF ( ( struct uip_icmpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) +#define UDPBUF ( ( struct uip_udpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) +#if UIP_STATISTICS == 1 +struct uip_stats uip_stat; + #define UIP_STAT( s ) s +#else + #define UIP_STAT( s ) +#endif /* UIP_STATISTICS == 1 */ + +#if UIP_LOGGING == 1 + #include +void uip_log( char *msg ); + #define UIP_LOG( m ) uip_log( m ) +#else + #define UIP_LOG( m ) +#endif /* UIP_LOGGING == 1 */ + +#if !UIP_ARCH_ADD32 +void uip_add32( u8_t *op32, u16_t op16 ) +{ + uip_acc32[3] = op32[3] + ( op16 & 0xff ); + uip_acc32[2] = op32[2] + ( op16 >> 8 ); + uip_acc32[1] = op32[1]; + uip_acc32[0] = op32[0]; + + if( uip_acc32[2] < (op16 >> 8) ) + { + ++uip_acc32[1]; + if( uip_acc32[1] == 0 ) + { + ++uip_acc32[0]; + } + } + + if( uip_acc32[3] < (op16 & 0xff) ) + { + ++uip_acc32[2]; + if( uip_acc32[2] == 0 ) + { + ++uip_acc32[1]; + if( uip_acc32[1] == 0 ) + { + ++uip_acc32[0]; + } + } + } +} + +#endif /* UIP_ARCH_ADD32 */ + +#if !UIP_ARCH_CHKSUM + +/*---------------------------------------------------------------------------*/ +static u16_t chksum( u16_t sum, const u8_t *data, u16_t len ) +{ + u16_t t; + const u8_t *dataptr; + const u8_t *last_byte; + + dataptr = data; + last_byte = data + len - 1; + + while( dataptr < last_byte ) + { /* At least two more bytes */ + t = ( dataptr[0] << 8 ) + dataptr[1]; + sum += t; + if( sum < t ) + { + sum++; /* carry */ + } + + dataptr += 2; + } + + if( dataptr == last_byte ) + { + t = ( dataptr[0] << 8 ) + 0; + sum += t; + if( sum < t ) + { + sum++; /* carry */ + } + } + + /* Return sum in host byte order. */ + return sum; +} + +/*---------------------------------------------------------------------------*/ +u16_t uip_chksum( u16_t *data, u16_t len ) +{ + return htons( chksum(0, ( u8_t * ) data, len) ); +} + +/*---------------------------------------------------------------------------*/ + #ifndef UIP_ARCH_IPCHKSUM +u16_t uip_ipchksum( void ) +{ + u16_t sum; + + sum = chksum( 0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN ); + DEBUG_PRINTF( "uip_ipchksum: sum 0x%04x\n", sum ); + return( sum == 0 ) ? 0xffff : htons( sum ); +} + + #endif + +/*---------------------------------------------------------------------------*/ +static u16_t upper_layer_chksum( u8_t proto ) +{ + u16_t upper_layer_len; + u16_t sum; + + #if UIP_CONF_IPV6 + upper_layer_len = ( ((u16_t) (BUF->len[0]) << 8) + BUF->len[1] ); + #else /* UIP_CONF_IPV6 */ + upper_layer_len = ( ((u16_t) (BUF->len[0]) << 8) + BUF->len[1] ) - UIP_IPH_LEN; + #endif /* UIP_CONF_IPV6 */ + + /* First sum pseudoheader. */ + + /* IP protocol and length fields. This addition cannot carry. */ + sum = upper_layer_len + proto; + + /* Sum IP source and destination addresses. */ + sum = chksum( sum, ( u8_t * ) &BUF->srcipaddr[0], 2 * sizeof(uip_ipaddr_t) ); + + /* Sum TCP header and data. */ + sum = chksum( sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN], upper_layer_len ); + + return( sum == 0 ) ? 0xffff : htons( sum ); +} + +/*---------------------------------------------------------------------------*/ + #if UIP_CONF_IPV6 +u16_t uip_icmp6chksum( void ) +{ + return upper_layer_chksum( UIP_PROTO_ICMP6 ); +} + + #endif /* UIP_CONF_IPV6 */ + +/*---------------------------------------------------------------------------*/ +u16_t uip_tcpchksum( void ) +{ + return upper_layer_chksum( UIP_PROTO_TCP ); +} + +/*---------------------------------------------------------------------------*/ + #if UIP_UDP_CHECKSUMS +u16_t uip_udpchksum( void ) +{ + return upper_layer_chksum( UIP_PROTO_UDP ); +} + + #endif /* UIP_UDP_CHECKSUMS */ +#endif /* UIP_ARCH_CHKSUM */ + +/*---------------------------------------------------------------------------*/ +void uip_init( void ) +{ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + uip_listenports[c] = 0; + } + + for( c = 0; c < UIP_CONNS; ++c ) + { + uip_conns[c].tcpstateflags = UIP_CLOSED; + } + + #if UIP_ACTIVE_OPEN + lastport = 1024; + #endif /* UIP_ACTIVE_OPEN */ + + #if UIP_UDP + for( c = 0; c < UIP_UDP_CONNS; ++c ) + { + uip_udp_conns[c].lport = 0; + } + + #endif /* UIP_UDP */ + + /* IPv4 initialization. */ + #if UIP_FIXEDADDR == 0 + + /* uip_hostaddr[0] = uip_hostaddr[1] = 0;*/ + #endif /* UIP_FIXEDADDR */ +} + +/*---------------------------------------------------------------------------*/ +#if UIP_ACTIVE_OPEN +struct uip_conn *uip_connect( uip_ipaddr_t *ripaddr, u16_t rport ) +{ + register struct uip_conn *conn, *cconn; + + /* Find an unused local port. */ +again: + ++lastport; + + if( lastport >= 32000 ) + { + lastport = 4096; + } + + /* Check if this port is already in use, and if so try to find + another one. */ + for( c = 0; c < UIP_CONNS; ++c ) + { + conn = &uip_conns[c]; + if( conn->tcpstateflags != UIP_CLOSED && conn->lport == htons(lastport) ) + { + goto again; + } + } + + conn = 0; + for( c = 0; c < UIP_CONNS; ++c ) + { + cconn = &uip_conns[c]; + if( cconn->tcpstateflags == UIP_CLOSED ) + { + conn = cconn; + break; + } + + if( cconn->tcpstateflags == UIP_TIME_WAIT ) + { + if( conn == 0 || cconn->timer > conn->timer ) + { + conn = cconn; + } + } + } + + if( conn == 0 ) + { + return 0; + } + + conn->tcpstateflags = UIP_SYN_SENT; + + conn->snd_nxt[0] = iss[0]; + conn->snd_nxt[1] = iss[1]; + conn->snd_nxt[2] = iss[2]; + conn->snd_nxt[3] = iss[3]; + + conn->initialmss = conn->mss = UIP_TCP_MSS; + + conn->len = 1; /* TCP length of the SYN is one. */ + conn->nrtx = 0; + conn->timer = 1; /* Send the SYN next time around. */ + conn->rto = UIP_RTO; + conn->sa = 0; + conn->sv = 16; /* Initial value of the RTT variance. */ + conn->lport = htons( lastport ); + conn->rport = rport; + uip_ipaddr_copy( &conn->ripaddr, ripaddr ); + + return conn; +} + +#endif /* UIP_ACTIVE_OPEN */ + +/*---------------------------------------------------------------------------*/ +#if UIP_UDP +struct uip_udp_conn *uip_udp_new( uip_ipaddr_t *ripaddr, u16_t rport ) +{ + register struct uip_udp_conn *conn; + + /* Find an unused local port. */ +again: + ++lastport; + + if( lastport >= 32000 ) + { + lastport = 4096; + } + + for( c = 0; c < UIP_UDP_CONNS; ++c ) + { + if( uip_udp_conns[c].lport == htons(lastport) ) + { + goto again; + } + } + + conn = 0; + for( c = 0; c < UIP_UDP_CONNS; ++c ) + { + if( uip_udp_conns[c].lport == 0 ) + { + conn = &uip_udp_conns[c]; + break; + } + } + + if( conn == 0 ) + { + return 0; + } + + conn->lport = HTONS( lastport ); + conn->rport = rport; + if( ripaddr == NULL ) + { + memset( conn->ripaddr, 0, sizeof(uip_ipaddr_t) ); + } + else + { + uip_ipaddr_copy( &conn->ripaddr, ripaddr ); + } + + conn->ttl = UIP_TTL; + + return conn; +} + +#endif /* UIP_UDP */ + +/*---------------------------------------------------------------------------*/ +void uip_unlisten( u16_t port ) +{ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + if( uip_listenports[c] == port ) + { + uip_listenports[c] = 0; + return; + } + } +} + +/*---------------------------------------------------------------------------*/ +void uip_listen( u16_t port ) +{ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + if( uip_listenports[c] == 0 ) + { + uip_listenports[c] = port; + return; + } + } +} + +/*---------------------------------------------------------------------------*/ + +/* XXX: IP fragment reassembly: not well-tested. */ +#if UIP_REASSEMBLY && !UIP_CONF_IPV6 + #define UIP_REASS_BUFSIZE ( UIP_BUFSIZE - UIP_LLH_LEN ) +static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; +static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / ( 8 * 8 )]; +static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01 }; +static u16_t uip_reasslen; +static u8_t uip_reassflags; + #define UIP_REASS_FLAG_LASTFRAG 0x01 +static u8_t uip_reasstmr; + + #define IP_MF 0x20 + +static u8_t uip_reass( void ) +{ + u16_t offset, len; + u16_t i; + + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if( uip_reasstmr == 0 ) + { + memcpy( uip_reassbuf, &BUF->vhl, UIP_IPH_LEN ); + uip_reasstmr = UIP_REASS_MAXAGE; + uip_reassflags = 0; + + /* Clear the bitmap. */ + memset( uip_reassbitmap, 0, sizeof(uip_reassbitmap) ); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if + ( + BUF->srcipaddr[0] == FBUF->srcipaddr[0] && + BUF->srcipaddr[1] == FBUF->srcipaddr[1] && + BUF->destipaddr[0] == FBUF->destipaddr[0] && + BUF->destipaddr[1] == FBUF->destipaddr[1] && + BUF->ipid[0] == FBUF->ipid[0] && + BUF->ipid[1] == FBUF->ipid[1] + ) + { + len = ( BUF->len[0] << 8 ) + BUF->len[1] - ( BUF->vhl & 0x0f ) * 4; + offset = ( ((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1] ) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if( offset > UIP_REASS_BUFSIZE || offset + len > UIP_REASS_BUFSIZE ) + { + uip_reasstmr = 0; + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + memcpy( &uip_reassbuf[UIP_IPH_LEN + offset], ( char * ) BUF + ( int ) ((BUF->vhl & 0x0f) * 4), len ); + + /* Update the bitmap. */ + if( offset / (8 * 8) == (offset + len) / (8 * 8) ) + { + /* If the two endpoints are in the same byte, we only update + that byte. */ + uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7] &~bitmap_bits[( (offset + len) / 8 ) & 7]; + } + else + { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7]; + for( i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i ) + { + uip_reassbitmap[i] = 0xff; + } + + uip_reassbitmap[( offset + len ) / ( 8 * 8 )] |= ~bitmap_bits[( (offset + len) / 8 ) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + if( (BUF->ipoffset[0] & IP_MF) == 0 ) + { + uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; + uip_reasslen = offset + len; + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if( uip_reassflags & UIP_REASS_FLAG_LASTFRAG ) + { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + for( i = 0; i < uip_reasslen / (8 * 8) - 1; ++i ) + { + if( uip_reassbitmap[i] != 0xff ) + { + goto nullreturn; + } + } + + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + if( uip_reassbitmap[uip_reasslen / (8 * 8)] != (u8_t)~bitmap_bits[uip_reasslen / 8 & 7] ) + { + goto nullreturn; + } + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + uip_reasstmr = 0; + memcpy( BUF, FBUF, uip_reasslen ); + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->len[0] = uip_reasslen >> 8; + BUF->len[1] = uip_reasslen & 0xff; + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + + return uip_reasslen; + } + } + +nullreturn: + return 0; +} + +#endif /* UIP_REASSEMBLY */ + +/*---------------------------------------------------------------------------*/ +static void uip_add_rcv_nxt( u16_t n ) +{ + uip_add32( uip_conn->rcv_nxt, n ); + uip_conn->rcv_nxt[0] = uip_acc32[0]; + uip_conn->rcv_nxt[1] = uip_acc32[1]; + uip_conn->rcv_nxt[2] = uip_acc32[2]; + uip_conn->rcv_nxt[3] = uip_acc32[3]; +} + +/*---------------------------------------------------------------------------*/ +void uip_process( u8_t flag ) +{ + register struct uip_conn *uip_connr = uip_conn; + + #if UIP_UDP + if( flag == UIP_UDP_SEND_CONN ) + { + goto udp_send; + } + + #endif /* UIP_UDP */ + + uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN]; + + /* Check if we were invoked because of a poll request for a + particular connection. */ + if( flag == UIP_POLL_REQUEST ) + { + if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED && !uip_outstanding(uip_connr) ) + { + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + + goto drop; + + /* Check if we were invoked because of the perodic timer fireing. */ + } + else if( flag == UIP_TIMER ) + { + #if UIP_REASSEMBLY + if( uip_reasstmr != 0 ) + { + --uip_reasstmr; + } + + #endif /* UIP_REASSEMBLY */ + + /* Increase the initial sequence number. */ + if( ++iss[3] == 0 ) + { + if( ++iss[2] == 0 ) + { + if( ++iss[1] == 0 ) + { + ++iss[0]; + } + } + } + + /* Reset the length variables. */ + uip_len = 0; + uip_slen = 0; + + /* Check if the connection is in a state in which we simply wait + for the connection to time out. If so, we increase the + connection's timer and remove the connection if it times + out. */ + if( uip_connr->tcpstateflags == UIP_TIME_WAIT || uip_connr->tcpstateflags == UIP_FIN_WAIT_2 ) + { + ++( uip_connr->timer ); + if( uip_connr->timer == UIP_TIME_WAIT_TIMEOUT ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + } + } + else if( uip_connr->tcpstateflags != UIP_CLOSED ) + { + /* If the connection has outstanding data, we increase the + connection's timer and see if it has reached the RTO value + in which case we retransmit. */ + if( uip_outstanding(uip_connr) ) + { + uip_connr->timer = uip_connr->timer - 1; + if( uip_connr->timer == 0 ) + { + if + ( + uip_connr->nrtx == UIP_MAXRTX || + ( + (uip_connr->tcpstateflags == UIP_SYN_SENT || uip_connr->tcpstateflags == UIP_SYN_RCVD) && + uip_connr->nrtx == UIP_MAXSYNRTX + ) + ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + + /* We call UIP_APPCALL() with uip_flags set to + UIP_TIMEDOUT to inform the application that the + connection has timed out. */ + uip_flags = UIP_TIMEDOUT; + UIP_APPCALL(); + + /* We also send a reset packet to the remote host. */ + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + /* Exponential backoff. */ + uip_connr->timer = UIP_RTO << ( uip_connr->nrtx > 4 ? 4 : uip_connr->nrtx ); + ++( uip_connr->nrtx ); + + /* Ok, so we need to retransmit. We do this differently + depending on which state we are in. In ESTABLISHED, we + call upon the application so that it may prepare the + data for the retransmit. In SYN_RCVD, we resend the + SYNACK that we sent earlier and in LAST_ACK we have to + retransmit our FINACK. */ + UIP_STAT( ++uip_stat.tcp.rexmit ); + switch( uip_connr->tcpstateflags & UIP_TS_MASK ) + { + case UIP_SYN_RCVD: + /* In the SYN_RCVD state, we should retransmit our + SYNACK. */ + goto tcp_send_synack; + + #if UIP_ACTIVE_OPEN + + case UIP_SYN_SENT: + /* In the SYN_SENT state, we retransmit out SYN. */ + BUF->flags = 0; + goto tcp_send_syn; + #endif /* UIP_ACTIVE_OPEN */ + + case UIP_ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application + to do the actual retransmit after which we jump into + the code for sending out the packet (the apprexmit + label). */ + uip_flags = UIP_REXMIT; + UIP_APPCALL(); + goto apprexmit; + + case UIP_FIN_WAIT_1: + case UIP_CLOSING: + case UIP_LAST_ACK: + /* In all these states we should retransmit a FINACK. */ + goto tcp_send_finack; + } + } + } + else if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED ) + { + /* If there was no need for a retransmission, we poll the + application for new data. */ + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + } + + goto drop; + } + + #if UIP_UDP + if( flag == UIP_UDP_TIMER ) + { + if( uip_udp_conn->lport != 0 ) + { + uip_conn = NULL; + uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + uip_len = uip_slen = 0; + uip_flags = UIP_POLL; + UIP_UDP_APPCALL(); + goto udp_send; + } + else + { + goto drop; + } + } + + #endif + + /* This is where the input processing starts. */ + UIP_STAT( ++uip_stat.ip.recv ); + + /* Start of IP input header processing code. */ + #if UIP_CONF_IPV6 + + /* Check validity of the IP header. */ + if( (BUF->vtc & 0xf0) != 0x60 ) + { /* IP version and header length. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.vhlerr ); + UIP_LOG( "ipv6: invalid version." ); + goto drop; + } + + #else /* UIP_CONF_IPV6 */ + + /* Check validity of the IP header. */ + if( BUF->vhl != 0x45 ) + { /* IP version and header length. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.vhlerr ); + UIP_LOG( "ip: invalid version or header length." ); + goto drop; + } + + #endif /* UIP_CONF_IPV6 */ + + /* Check the size of the packet. If the size reported to us in + uip_len is smaller the size reported in the IP header, we assume + that the packet has been corrupted in transit. If the size of + uip_len is larger than the size reported in the IP packet header, + the packet has been padded and we set uip_len to the correct + value.. */ + if( (BUF->len[0] << 8) + BUF->len[1] <= uip_len ) + { + uip_len = ( BUF->len[0] << 8 ) + BUF->len[1]; + #if UIP_CONF_IPV6 + uip_len += 40; /* The length reported in the IPv6 header is the + length of the payload that follows the + header. However, uIP uses the uip_len variable + for holding the size of the entire packet, + including the IP header. For IPv4 this is not a + problem as the length field in the IPv4 header + contains the length of the entire packet. But + for IPv6 we need to add the size of the IPv6 + header (40 bytes). */ + #endif /* UIP_CONF_IPV6 */ + } + else + { + UIP_LOG( "ip: packet shorter than reported in IP header." ); + goto drop; + } + + #if !UIP_CONF_IPV6 + + /* Check the fragment flag. */ + if( (BUF->ipoffset[0] & 0x3f) != 0 || BUF->ipoffset[1] != 0 ) + { + #if UIP_REASSEMBLY + uip_len = uip_reass(); + if( uip_len == 0 ) + { + goto drop; + } + + #else /* UIP_REASSEMBLY */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.fragerr ); + UIP_LOG( "ip: fragment dropped." ); + goto drop; + #endif /* UIP_REASSEMBLY */ + } + + #endif /* UIP_CONF_IPV6 */ + + if( uip_ipaddr_cmp(uip_hostaddr, all_zeroes_addr) ) + { + /* If we are configured to use ping IP address configuration and + hasn't been assigned an IP address yet, we accept all ICMP + packets. */ + #if UIP_PINGADDRCONF && !UIP_CONF_IPV6 + if( BUF->proto == UIP_PROTO_ICMP ) + { + UIP_LOG( "ip: possible ping config packet received." ); + goto icmp_input; + } + else + { + UIP_LOG( "ip: packet dropped since no address assigned." ); + goto drop; + } + + #endif /* UIP_PINGADDRCONF */ + } + else + { + /* If IP broadcast support is configured, we check for a broadcast + UDP packet, which may be destined to us. */ + #if UIP_BROADCAST + DEBUG_PRINTF( "UDP IP checksum 0x%04x\n", uip_ipchksum() ); + if( BUF->proto == UIP_PROTO_UDP && uip_ipaddr_cmp(BUF->destipaddr, all_ones_addr) /*&& + uip_ipchksum() == 0xffff*/ ) + { + goto udp_input; + } + + #endif /* UIP_BROADCAST */ + + /* Check if the packet is destined for our IP address. */ + #if !UIP_CONF_IPV6 + if( !uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) ) + { + UIP_STAT( ++uip_stat.ip.drop ); + goto drop; + } + + #else /* UIP_CONF_IPV6 */ + + /* For IPv6, packet reception is a little trickier as we need to + make sure that we listen to certain multicast addresses (all + hosts multicast address, and the solicited-node multicast + address) as well. However, we will cheat here and accept all + multicast packets that are sent to the ff02::/16 addresses. */ + if( !uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) && BUF->destipaddr[0] != HTONS(0xff02) ) + { + UIP_STAT( ++uip_stat.ip.drop ); + goto drop; + } + + #endif /* UIP_CONF_IPV6 */ + } + + #if !UIP_CONF_IPV6 + if( uip_ipchksum() != 0xffff ) + { /* Compute and check the IP header + checksum. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.chkerr ); + UIP_LOG( "ip: bad checksum." ); + goto drop; + } + + #endif /* UIP_CONF_IPV6 */ + + if( BUF->proto == UIP_PROTO_TCP ) + { /* Check for TCP packet. If so, + proceed with TCP input + processing. */ + goto tcp_input; + } + + #if UIP_UDP + if( BUF->proto == UIP_PROTO_UDP ) + { + goto udp_input; + } + + #endif /* UIP_UDP */ + + #if !UIP_CONF_IPV6 + + /* ICMPv4 processing code follows. */ + if( BUF->proto != UIP_PROTO_ICMP ) + { /* We only allow ICMP packets from + here. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.protoerr ); + UIP_LOG( "ip: neither tcp nor icmp." ); + goto drop; + } + + #if UIP_PINGADDRCONF + icmp_input : + #endif /* UIP_PINGADDRCONF */ + UIP_STAT( ++uip_stat.icmp.recv ); + + /* ICMP echo (i.e., ping) processing. This is simple, we only change + the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP + checksum before we return the packet. */ + if( ICMPBUF->type != ICMP_ECHO ) + { + UIP_STAT( ++uip_stat.icmp.drop ); + UIP_STAT( ++uip_stat.icmp.typeerr ); + UIP_LOG( "icmp: not icmp echo." ); + goto drop; + } + + /* If we are configured to use ping IP address assignment, we use + the destination IP address of this ping packet and assign it to + ourself. */ + #if UIP_PINGADDRCONF + if( (uip_hostaddr[0] | uip_hostaddr[1]) == 0 ) + { + uip_hostaddr[0] = BUF->destipaddr[0]; + uip_hostaddr[1] = BUF->destipaddr[1]; + } + + #endif /* UIP_PINGADDRCONF */ + + ICMPBUF->type = ICMP_ECHO_REPLY; + + if( ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8)) ) + { + ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 ) + 1; + } + else + { + ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 ); + } + + /* Swap IP addresses. */ + uip_ipaddr_copy( BUF->destipaddr, BUF->srcipaddr ); + uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr ); + + UIP_STAT( ++uip_stat.icmp.sent ); + goto send; + + /* End of IPv4 input header processing code. */ + #else /* !UIP_CONF_IPV6 */ + + /* This is IPv6 ICMPv6 processing code. */ + DEBUG_PRINTF( "icmp6_input: length %d\n", uip_len ); + + if( BUF->proto != UIP_PROTO_ICMP6 ) + { /* We only allow ICMPv6 packets from + here. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.protoerr ); + UIP_LOG( "ip: neither tcp nor icmp6." ); + goto drop; + } + + UIP_STAT( ++uip_stat.icmp.recv ); + + /* If we get a neighbor solicitation for our address we should send + a neighbor advertisement message back. */ + if( ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION ) + { + if( uip_ipaddr_cmp(ICMPBUF->icmp6data, uip_hostaddr) ) + { + if( ICMPBUF->options[0] == ICMP6_OPTION_SOURCE_LINK_ADDRESS ) + { + /* Save the sender's address in our neighbor list. */ + uip_neighbor_add( ICMPBUF->srcipaddr, &(ICMPBUF->options[2]) ); + } + + /* We should now send a neighbor advertisement back to where the + neighbor solicication came from. */ + ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT; + ICMPBUF->flags = ICMP6_FLAG_S; /* Solicited flag. */ + + ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0; + + uip_ipaddr_copy( ICMPBUF->destipaddr, ICMPBUF->srcipaddr ); + uip_ipaddr_copy( ICMPBUF->srcipaddr, uip_hostaddr ); + ICMPBUF->options[0] = ICMP6_OPTION_TARGET_LINK_ADDRESS; + ICMPBUF->options[1] = 1; /* Options length, 1 = 8 bytes. */ + memcpy( &(ICMPBUF->options[2]), &uip_ethaddr, sizeof(uip_ethaddr) ); + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_icmp6chksum(); + goto send; + } + + goto drop; + } + else if( ICMPBUF->type == ICMP6_ECHO ) + { + /* ICMP echo (i.e., ping) processing. This is simple, we only + change the ICMP type from ECHO to ECHO_REPLY and update the + ICMP checksum before we return the packet. */ + ICMPBUF->type = ICMP6_ECHO_REPLY; + + uip_ipaddr_copy( BUF->destipaddr, BUF->srcipaddr ); + uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr ); + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_icmp6chksum(); + + UIP_STAT( ++uip_stat.icmp.sent ); + goto send; + } + else + { + DEBUG_PRINTF( "Unknown icmp6 message type %d\n", ICMPBUF->type ); + UIP_STAT( ++uip_stat.icmp.drop ); + UIP_STAT( ++uip_stat.icmp.typeerr ); + UIP_LOG( "icmp: unknown ICMP message." ); + goto drop; + } + + /* End of IPv6 ICMP processing. */ + #endif /* !UIP_CONF_IPV6 */ + + #if UIP_UDP + + /* UDP input processing. */ + udp_input : + /* UDP processing is really just a hack. We don't do anything to the + UDP/IP headers, but let the UDP application do all the hard + work. If the application sets uip_slen, it has a packet to + send. */ + #if UIP_UDP_CHECKSUMS + uip_len = uip_len - UIP_IPUDPH_LEN; + uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + if( UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff ) + { + UIP_STAT( ++uip_stat.udp.drop ); + UIP_STAT( ++uip_stat.udp.chkerr ); + UIP_LOG( "udp: bad checksum." ); + goto drop; + } + + #else /* UIP_UDP_CHECKSUMS */ + uip_len = uip_len - UIP_IPUDPH_LEN; + #endif /* UIP_UDP_CHECKSUMS */ + + /* Demultiplex this UDP packet between the UDP "connections". */ + for( uip_udp_conn = &uip_udp_conns[0]; uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; ++uip_udp_conn ) + { + /* If the local UDP port is non-zero, the connection is considered + to be used. If so, the local port number is checked against the + destination port number in the received packet. If the two port + numbers match, the remote port number is checked if the + connection is bound to a remote port. Finally, if the + connection is bound to a remote IP address, the source IP + address of the packet is checked. */ + if + ( + uip_udp_conn->lport != 0 && + UDPBUF->destport == uip_udp_conn->lport && + (uip_udp_conn->rport == 0 || UDPBUF->srcport == uip_udp_conn->rport) && + ( + uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_zeroes_addr) || + uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) || + uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr) + ) + ) + { + goto udp_found; + } + } + + UIP_LOG( "udp: no matching connection found" ); + goto drop; + +udp_found: + UIP_STAT( ++uip_stat.udp.recv ); + uip_conn = NULL; + uip_flags = UIP_NEWDATA; + uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + uip_slen = 0; + UIP_UDP_APPCALL(); +udp_send: + if( uip_slen == 0 ) + { + goto drop; + } + + uip_len = uip_slen + UIP_IPUDPH_LEN; + + #if UIP_CONF_IPV6 + + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 ); + BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff ); + #else /* UIP_CONF_IPV6 */ + BUF->len[0] = ( uip_len >> 8 ); + BUF->len[1] = ( uip_len & 0xff ); + #endif /* UIP_CONF_IPV6 */ + + BUF->ttl = uip_udp_conn->ttl; + BUF->proto = UIP_PROTO_UDP; + + UDPBUF->udplen = HTONS( uip_slen + UIP_UDPH_LEN ); + UDPBUF->udpchksum = 0; + + BUF->srcport = uip_udp_conn->lport; + BUF->destport = uip_udp_conn->rport; + + uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr ); + uip_ipaddr_copy( BUF->destipaddr, uip_udp_conn->ripaddr ); + + uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN]; + + #if UIP_UDP_CHECKSUMS + + /* Calculate UDP checksum. */ + UDPBUF->udpchksum = ~( uip_udpchksum() ); + if( UDPBUF->udpchksum == 0 ) + { + UDPBUF->udpchksum = 0xffff; + } + + #endif /* UIP_UDP_CHECKSUMS */ + UIP_STAT( ++uip_stat.udp.sent ); + goto ip_send_nolen; + #endif /* UIP_UDP */ + + /* TCP input processing. */ + tcp_input : UIP_STAT( ++uip_stat.tcp.recv ); + + /* Start of TCP input header processing code. */ + if( uip_tcpchksum() != 0xffff ) + { /* Compute and check the TCP + checksum. */ + UIP_STAT( ++uip_stat.tcp.drop ); + UIP_STAT( ++uip_stat.tcp.chkerr ); + UIP_LOG( "tcp: bad checksum." ); + goto drop; + } + + /* Demultiplex this segment. */ + + /* First check any active connections. */ + for( uip_connr = &uip_conns[0]; uip_connr <= &uip_conns[UIP_CONNS - 1]; ++uip_connr ) + { + if + ( + uip_connr->tcpstateflags != UIP_CLOSED && + BUF->destport == uip_connr->lport && + BUF->srcport == uip_connr->rport && + uip_ipaddr_cmp(BUF->srcipaddr, uip_connr->ripaddr) + ) + { + goto found; + } + } + + /* If we didn't find and active connection that expected the packet, + either this packet is an old duplicate, or this is a SYN packet + destined for a connection in LISTEN. If the SYN flag isn't set, + it is an old packet and we send a RST. */ + if( (BUF->flags & TCP_CTL) != TCP_SYN ) + { + goto reset; + } + + tmp16 = BUF->destport; + + /* Next, check listening connections. */ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + if( tmp16 == uip_listenports[c] ) + { + goto found_listen; + } + } + + /* No matching connection found, so we send a RST packet. */ + UIP_STAT( ++uip_stat.tcp.synrst ); +reset: + /* We do not send resets in response to resets. */ + if( BUF->flags & TCP_RST ) + { + goto drop; + } + + UIP_STAT( ++uip_stat.tcp.rst ); + + BUF->flags = TCP_RST | TCP_ACK; + uip_len = UIP_IPTCPH_LEN; + BUF->tcpoffset = 5 << 4; + + /* Flip the seqno and ackno fields in the TCP header. */ + c = BUF->seqno[3]; + BUF->seqno[3] = BUF->ackno[3]; + BUF->ackno[3] = c; + + c = BUF->seqno[2]; + BUF->seqno[2] = BUF->ackno[2]; + BUF->ackno[2] = c; + + c = BUF->seqno[1]; + BUF->seqno[1] = BUF->ackno[1]; + BUF->ackno[1] = c; + + c = BUF->seqno[0]; + BUF->seqno[0] = BUF->ackno[0]; + BUF->ackno[0] = c; + + /* We also have to increase the sequence number we are + acknowledging. If the least significant byte overflowed, we need + to propagate the carry to the other bytes as well. */ + if( ++BUF->ackno[3] == 0 ) + { + if( ++BUF->ackno[2] == 0 ) + { + if( ++BUF->ackno[1] == 0 ) + { + ++BUF->ackno[0]; + } + } + } + + /* Swap port numbers. */ + tmp16 = BUF->srcport; + BUF->srcport = BUF->destport; + BUF->destport = tmp16; + + /* Swap IP addresses. */ + uip_ipaddr_copy( BUF->destipaddr, BUF->srcipaddr ); + uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr ); + + /* And send out the RST packet! */ + goto tcp_send_noconn; + + /* This label will be jumped to if we matched the incoming packet + with a connection in LISTEN. In that case, we should create a new + connection and send a SYNACK in return. */ +found_listen: + /* First we check if there are any connections avaliable. Unused + connections are kept in the same table as used connections, but + unused ones have the tcpstate set to CLOSED. Also, connections in + TIME_WAIT are kept track of and we'll use the oldest one if no + CLOSED connections are found. Thanks to Eddie C. Dost for a very + nice algorithm for the TIME_WAIT search. */ + uip_connr = 0; + for( c = 0; c < UIP_CONNS; ++c ) + { + if( uip_conns[c].tcpstateflags == UIP_CLOSED ) + { + uip_connr = &uip_conns[c]; + break; + } + + if( uip_conns[c].tcpstateflags == UIP_TIME_WAIT ) + { + if( uip_connr == 0 || uip_conns[c].timer > uip_connr->timer ) + { + uip_connr = &uip_conns[c]; + } + } + } + + if( uip_connr == 0 ) + { + /* All connections are used already, we drop packet and hope that + the remote end will retransmit the packet at a time when we + have more spare connections. */ + UIP_STAT( ++uip_stat.tcp.syndrop ); + UIP_LOG( "tcp: found no unused connections." ); + goto drop; + } + + uip_conn = uip_connr; + + /* Fill in the necessary fields for the new connection. */ + uip_connr->rto = uip_connr->timer = UIP_RTO; + uip_connr->sa = 0; + uip_connr->sv = 4; + uip_connr->nrtx = 0; + uip_connr->lport = BUF->destport; + uip_connr->rport = BUF->srcport; + uip_ipaddr_copy( uip_connr->ripaddr, BUF->srcipaddr ); + uip_connr->tcpstateflags = UIP_SYN_RCVD; + + uip_connr->snd_nxt[0] = iss[0]; + uip_connr->snd_nxt[1] = iss[1]; + uip_connr->snd_nxt[2] = iss[2]; + uip_connr->snd_nxt[3] = iss[3]; + uip_connr->len = 1; + + /* rcv_nxt should be the seqno from the incoming packet + 1. */ + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_add_rcv_nxt( 1 ); + + /* Parse the TCP MSS option, if present. */ + if( (BUF->tcpoffset & 0xf0) > 0x50 ) + { + for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; ) + { + opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; + if( opt == TCP_OPT_END ) + { + /* End of options. */ + break; + } + else if( opt == TCP_OPT_NOOP ) + { + ++c; + + /* NOP option. */ + } + else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN ) + { + /* An MSS option with the right option length. */ + tmp16 = ( (u16_t) uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | ( u16_t ) uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16; + + /* And we are done processing options. */ + break; + } + else + { + /* All other options have a length field, so that we easily + can skip past them. */ + if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 ) + { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + /* Our response will be a SYNACK. */ + #if UIP_ACTIVE_OPEN + tcp_send_synack : BUF->flags = TCP_ACK; + +tcp_send_syn: + BUF->flags |= TCP_SYN; + #else /* UIP_ACTIVE_OPEN */ + tcp_send_synack : BUF->flags = TCP_SYN | TCP_ACK; + #endif /* UIP_ACTIVE_OPEN */ + + /* We send out the TCP Maximum Segment Size option with our + SYNACK. */ + BUF->optdata[0] = TCP_OPT_MSS; + BUF->optdata[1] = TCP_OPT_MSS_LEN; + BUF->optdata[2] = ( UIP_TCP_MSS ) / 256; + BUF->optdata[3] = ( UIP_TCP_MSS ) & 255; + uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN; + BUF->tcpoffset = ( (UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4 ) << 4; + goto tcp_send; + + /* This label will be jumped to if we found an active connection. */ +found: + uip_conn = uip_connr; + uip_flags = 0; + + /* We do a very naive form of TCP reset processing; we just accept + any RST and kill our connection. We should in fact check if the + sequence number of this reset is wihtin our advertised window + before we accept the reset. */ + if( BUF->flags & TCP_RST ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + UIP_LOG( "tcp: got reset, aborting connection." ); + uip_flags = UIP_ABORT; + UIP_APPCALL(); + goto drop; + } + + /* Calculated the length of the data, if the application has sent + any data to us. */ + c = ( BUF->tcpoffset >> 4 ) << 2; + + /* uip_len will contain the length of the actual TCP data. This is + calculated by subtracing the length of the TCP header (in + c) and the length of the IP header (20 bytes). */ + uip_len = uip_len - c - UIP_IPH_LEN; + + /* First, check if the sequence number of the incoming packet is + what we're expecting next. If not, we send out an ACK with the + correct numbers in. */ + if( !(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) && ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK))) ) + { + if + ( + (uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) && + ( + BUF->seqno[0] != uip_connr->rcv_nxt[0] || + BUF->seqno[1] != uip_connr->rcv_nxt[1] || + BUF->seqno[2] != uip_connr->rcv_nxt[2] || + BUF->seqno[3] != uip_connr->rcv_nxt[3] + ) + ) + { + goto tcp_send_ack; + } + } + + /* Next, check if the incoming segment acknowledges any outstanding + data. If so, we update the sequence number, reset the length of + the outstanding data, calculate RTT estimations, and reset the + retransmission timer. */ + if( (BUF->flags & TCP_ACK) && uip_outstanding(uip_connr) ) + { + uip_add32( uip_connr->snd_nxt, uip_connr->len ); + + if + ( + BUF->ackno[0] == uip_acc32[0] && + BUF->ackno[1] == uip_acc32[1] && + BUF->ackno[2] == uip_acc32[2] && + BUF->ackno[3] == uip_acc32[3] + ) + { + /* Update sequence number. */ + uip_connr->snd_nxt[0] = uip_acc32[0]; + uip_connr->snd_nxt[1] = uip_acc32[1]; + uip_connr->snd_nxt[2] = uip_acc32[2]; + uip_connr->snd_nxt[3] = uip_acc32[3]; + + /* Do RTT estimation, unless we have done retransmissions. */ + if( uip_connr->nrtx == 0 ) + { + signed char m; + m = uip_connr->rto - uip_connr->timer; + + /* This is taken directly from VJs original code in his paper */ + m = m - ( uip_connr->sa >> 3 ); + uip_connr->sa += m; + if( m < 0 ) + { + m = -m; + } + + m = m - ( uip_connr->sv >> 2 ); + uip_connr->sv += m; + uip_connr->rto = ( uip_connr->sa >> 3 ) + uip_connr->sv; + } + + /* Set the acknowledged flag. */ + uip_flags = UIP_ACKDATA; + + /* Reset the retransmission timer. */ + uip_connr->timer = uip_connr->rto; + + /* Reset length of outstanding data. */ + uip_connr->len = 0; + } + } + + /* Do different things depending on in what state the connection is. */ + switch( uip_connr->tcpstateflags & UIP_TS_MASK ) + { + /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not + implemented, since we force the application to close when the + peer sends a FIN (hence the application goes directly from + ESTABLISHED to LAST_ACK). */ + case UIP_SYN_RCVD: + /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and + we are waiting for an ACK that acknowledges the data we sent + out the last time. Therefore, we want to have the UIP_ACKDATA + flag set. If so, we enter the ESTABLISHED state. */ + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_ESTABLISHED; + uip_flags = UIP_CONNECTED; + uip_connr->len = 0; + if( uip_len > 0 ) + { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt( uip_len ); + } + + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + + goto drop; + #if UIP_ACTIVE_OPEN + + case UIP_SYN_SENT: + /* In SYN_SENT, we wait for a SYNACK that is sent in response to + our SYN. The rcv_nxt is set to sequence number in the SYNACK + plus one, and we send an ACK. We move into the ESTABLISHED + state. */ + if( (uip_flags & UIP_ACKDATA) && (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK) ) + { + /* Parse the TCP MSS option, if present. */ + if( (BUF->tcpoffset & 0xf0) > 0x50 ) + { + for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; ) + { + opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c]; + if( opt == TCP_OPT_END ) + { + /* End of options. */ + break; + } + else if( opt == TCP_OPT_NOOP ) + { + ++c; + + /* NOP option. */ + } + else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN ) + { + /* An MSS option with the right option length. */ + tmp16 = ( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16; + + /* And we are done processing options. */ + break; + } + else + { + /* All other options have a length field, so that we easily + can skip past them. */ + if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 ) + { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + uip_connr->tcpstateflags = UIP_ESTABLISHED; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_add_rcv_nxt( 1 ); + uip_flags = UIP_CONNECTED | UIP_NEWDATA; + uip_connr->len = 0; + uip_len = 0; + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + + /* Inform the application that the connection failed */ + uip_flags = UIP_ABORT; + UIP_APPCALL(); + + /* The connection is closed after we send the RST */ + uip_conn->tcpstateflags = UIP_CLOSED; + goto reset; + #endif /* UIP_ACTIVE_OPEN */ + + case UIP_ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application to feed + data into the uip_buf. If the UIP_ACKDATA flag is set, the + application should put new data into the buffer, otherwise we are + retransmitting an old segment, and the application should put that + data into the buffer. + + If the incoming packet is a FIN, we should close the connection on + this side as well, and we send out a FIN and enter the LAST_ACK + state. We require that there is no outstanding data; otherwise the + sequence numbers will be screwed up. */ + if( BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED) ) + { + if( uip_outstanding(uip_connr) ) + { + goto drop; + } + + uip_add_rcv_nxt( 1 + uip_len ); + uip_flags |= UIP_CLOSE; + if( uip_len > 0 ) + { + uip_flags |= UIP_NEWDATA; + } + + UIP_APPCALL(); + uip_connr->len = 1; + uip_connr->tcpstateflags = UIP_LAST_ACK; + uip_connr->nrtx = 0; + tcp_send_finack: + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* Check the URG flag. If this is set, the segment carries urgent + data that we must pass to the application. */ + if( (BUF->flags & TCP_URG) != 0 ) + { + #if UIP_URGDATA > 0 + uip_urglen = ( BUF->urgp[0] << 8 ) | BUF->urgp[1]; + if( uip_urglen > uip_len ) + { + /* There is more urgent data in the next segment to come. */ + uip_urglen = uip_len; + } + + uip_add_rcv_nxt( uip_urglen ); + uip_len -= uip_urglen; + uip_urgdata = uip_appdata; + uip_appdata += uip_urglen; + } + else + { + uip_urglen = 0; + #else /* UIP_URGDATA > 0 */ + uip_appdata = ( ( char * ) uip_appdata ) + ( (BUF->urgp[0] << 8) | BUF->urgp[1] ); + uip_len -= ( BUF->urgp[0] << 8 ) | BUF->urgp[1]; + #endif /* UIP_URGDATA > 0 */ + } + + /* If uip_len > 0 we have TCP data in the packet, and we flag this + by setting the UIP_NEWDATA flag and update the sequence number + we acknowledge. If the application has stopped the dataflow + using uip_stop(), we must not accept any data packets from the + remote host. */ + if( uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED) ) + { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt( uip_len ); + } + + /* Check if the available buffer space advertised by the other end + is smaller than the initial MSS for this connection. If so, we + set the current MSS to the window size to ensure that the + application does not send more data than the other end can + handle. + + If the remote host advertises a zero window, we set the MSS to + the initial MSS so that the application will send an entire MSS + of data. This data will not be acknowledged by the receiver, + and the application will retransmit it. This is called the + "persistent timer" and uses the retransmission mechanim. + */ + tmp16 = ( (u16_t) BUF->wnd[0] << 8 ) + ( u16_t ) BUF->wnd[1]; + if( tmp16 > (uip_connr->initialmss * FRAME_MULTIPLE) || tmp16 == 0 ) + { + tmp16 = uip_connr->initialmss * FRAME_MULTIPLE; + } + + uip_connr->mss = tmp16; + + /* If this packet constitutes an ACK for outstanding data (flagged + by the UIP_ACKDATA flag, we should call the application since it + might want to send more data. If the incoming packet had data + from the peer (as flagged by the UIP_NEWDATA flag), the + application must also be notified. + + When the application is called, the global variable uip_len + contains the length of the incoming data. The application can + access the incoming data through the global pointer + uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN + bytes into the uip_buf array. + + If the application wishes to send any data, this data should be + put into the uip_appdata and the length of the data should be + put into uip_len. If the application don't have any data to + send, uip_len must be set to 0. */ + if( uip_flags & (UIP_NEWDATA | UIP_ACKDATA) ) + { + uip_slen = 0; + UIP_APPCALL(); + + appsend: + if( uip_flags & UIP_ABORT ) + { + uip_slen = 0; + uip_connr->tcpstateflags = UIP_CLOSED; + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + if( uip_flags & UIP_CLOSE ) + { + uip_slen = 0; + uip_connr->len = 1; + uip_connr->tcpstateflags = UIP_FIN_WAIT_1; + uip_connr->nrtx = 0; + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* If uip_slen > 0, the application has data to be sent. */ + if( uip_slen > 0 ) + { + /* If the connection has acknowledged data, the contents of + the ->len variable should be discarded. */ + if( (uip_flags & UIP_ACKDATA) != 0 ) + { + uip_connr->len = 0; + } + + /* If the ->len variable is non-zero the connection has + already data in transit and cannot send anymore right + now. */ + if( uip_connr->len == 0 ) + { + /* The application cannot send more than what is allowed by + the mss (the minumum of the MSS and the available + window). */ + if( uip_slen > uip_connr->mss ) + { + uip_slen = uip_connr->mss; + } + + /* Remember how much data we send out now so that we know + when everything has been acknowledged. */ + uip_connr->len = uip_slen; + } + else + { + /* If the application already had unacknowledged data, we + make sure that the application does not send (i.e., + retransmit) out more than it previously sent out. */ + uip_slen = uip_connr->len; + } + } + + uip_connr->nrtx = 0; + apprexmit: + uip_appdata = uip_sappdata; + + /* If the application has data to be sent, or if the incoming + packet had new data in it, we must send out a packet. */ + if( uip_slen > 0 && uip_connr->len > 0 ) + { + /* Add the length of the IP and TCP headers. */ + uip_len = uip_connr->len + UIP_TCPIP_HLEN; + + /* We always set the ACK flag in response packets. */ + BUF->flags = TCP_ACK | TCP_PSH; + + /* Send the packet. */ + goto tcp_send_noopts; + } + + /* If there is no data to send, just send out a pure ACK if + there is newdata. */ + if( uip_flags & UIP_NEWDATA ) + { + uip_len = UIP_TCPIP_HLEN; + BUF->flags = TCP_ACK; + goto tcp_send_noopts; + } + } + + goto drop; + + case UIP_LAST_ACK: + /* We can close this connection if the peer has acknowledged our + FIN. This is indicated by the UIP_ACKDATA flag. */ + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + } + + break; + + case UIP_FIN_WAIT_1: + /* The application has closed the connection, but the remote host + hasn't closed its end yet. Thus we do nothing but wait for a + FIN from the other side. */ + if( uip_len > 0 ) + { + uip_add_rcv_nxt( uip_len ); + } + + if( BUF->flags & TCP_FIN ) + { + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + uip_connr->len = 0; + } + else + { + uip_connr->tcpstateflags = UIP_CLOSING; + } + + uip_add_rcv_nxt( 1 ); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + else if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_FIN_WAIT_2; + uip_connr->len = 0; + goto drop; + } + + if( uip_len > 0 ) + { + goto tcp_send_ack; + } + + goto drop; + + case UIP_FIN_WAIT_2: + if( uip_len > 0 ) + { + uip_add_rcv_nxt( uip_len ); + } + + if( BUF->flags & TCP_FIN ) + { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + uip_add_rcv_nxt( 1 ); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + + if( uip_len > 0 ) + { + goto tcp_send_ack; + } + + goto drop; + + case UIP_TIME_WAIT: + goto tcp_send_ack; + + case UIP_CLOSING: + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + } + } + + goto drop; + + /* We jump here when we are ready to send the packet, and just want + to set the appropriate TCP sequence numbers in the TCP header. */ +tcp_send_ack: + BUF->flags = TCP_ACK; +tcp_send_nodata: + uip_len = UIP_IPTCPH_LEN; +tcp_send_noopts: + BUF->tcpoffset = ( UIP_TCPH_LEN / 4 ) << 4; +tcp_send: + /* We're done with the input processing. We are now ready to send a + reply. Our job is to fill in all the fields of the TCP and IP + headers before calculating the checksum and finally send the + packet. */ + BUF->ackno[0] = uip_connr->rcv_nxt[0]; + BUF->ackno[1] = uip_connr->rcv_nxt[1]; + BUF->ackno[2] = uip_connr->rcv_nxt[2]; + BUF->ackno[3] = uip_connr->rcv_nxt[3]; + + BUF->seqno[0] = uip_connr->snd_nxt[0]; + BUF->seqno[1] = uip_connr->snd_nxt[1]; + BUF->seqno[2] = uip_connr->snd_nxt[2]; + BUF->seqno[3] = uip_connr->snd_nxt[3]; + + BUF->proto = UIP_PROTO_TCP; + + BUF->srcport = uip_connr->lport; + BUF->destport = uip_connr->rport; + + uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr ); + uip_ipaddr_copy( BUF->destipaddr, uip_connr->ripaddr ); + + if( uip_connr->tcpstateflags & UIP_STOPPED ) + { + /* If the connection has issued uip_stop(), we advertise a zero + window so that the remote host will stop sending data. */ + BUF->wnd[0] = BUF->wnd[1] = 0; + } + else + { + BUF->wnd[0] = ( (UIP_RECEIVE_WINDOW) >> 8 ); + BUF->wnd[1] = ( (UIP_RECEIVE_WINDOW) & 0xff ); + } + +tcp_send_noconn: + BUF->ttl = UIP_TTL; + #if UIP_CONF_IPV6 + + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 ); + BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff ); + #else /* UIP_CONF_IPV6 */ + BUF->len[0] = ( uip_len >> 8 ); + BUF->len[1] = ( uip_len & 0xff ); + #endif /* UIP_CONF_IPV6 */ + + BUF->urgp[0] = BUF->urgp[1] = 0; + + /* Calculate TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~( uip_tcpchksum() ); + + #if UIP_UDP + ip_send_nolen : + #endif + #if UIP_CONF_IPV6 + BUF->vtc = 0x60; + BUF->tcflow = 0x00; + BUF->flow = 0x00; + #else /* UIP_CONF_IPV6 */ + BUF->vhl = 0x45; + BUF->tos = 0; + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + ++ipid; + BUF->ipid[0] = ipid >> 8; + BUF->ipid[1] = ipid & 0xff; + + /* Calculate IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + DEBUG_PRINTF( "uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum() ); + #endif /* UIP_CONF_IPV6 */ + + UIP_STAT( ++uip_stat.tcp.sent ); +send: + DEBUG_PRINTF( "Sending packet with length %d (%d)\n", uip_len, (BUF->len[0] << 8) | BUF->len[1] ); + + UIP_STAT( ++uip_stat.ip.sent ); + + /* Return and let the caller do the actual transmission. */ + uip_flags = 0; + return; +drop: + uip_len = 0; + uip_flags = 0; + return; +} + +/*---------------------------------------------------------------------------*/ +u16_t htons( u16_t val ) +{ + return HTONS( val ); +} + +/*---------------------------------------------------------------------------*/ +void uip_send( const void *data, int len ) +{ + if( len > 0 ) + { + uip_slen = len; + if( data != uip_sappdata ) + { + memcpy( uip_sappdata, (data), uip_slen ); + } + } +} + +/*---------------------------------------------------------------------------*/ +int uip_fast_send( int xARP ) +{ + ( void ) xARP; + #if NOT_YET_COMPLETE + + u16_t tcplen, len1 = 0, uiAccumulatedLen = 0, len_previous = 0, split_len; + int iSplitNo = 0; + extern int uip_low_level_output( unsigned char *pcBuf, int ilen ); + + if( xARP == pdTRUE ) + { + if( BUF->proto == UIP_PROTO_TCP && uip_slen > 1 ) + { + tcplen = uip_len - UIP_TCPIP_HLEN; + + if( tcplen > UIP_TCP_MSS ) + { + split_len = UIP_TCP_MSS; + } + else + { + split_len = tcplen / 2; + } + + while( tcplen > 0 ) + { + uiAccumulatedLen += len1; + + if( tcplen > split_len ) + { + len1 = split_len; + tcplen -= split_len; + } + else + { + len1 = tcplen; + tcplen = 0; + } + + uip_len = len1 + UIP_TCPIP_HLEN; + BUF->len[0] = uip_len >> 8; + BUF->len[1] = uip_len & 0xff; + if( iSplitNo == 0 ) + { + iSplitNo++; + + /* Create the first packet. This is done by altering the length + field of the IP header and updating the checksums. */ + } + else + { + /* Now, create the second packet. To do this, it is not enough to + just alter the length field, but we must also update the TCP + sequence number and point the uip_appdata to a new place in + memory. This place is determined by the length of the first + packet (len1). */ + + /* uip_appdata += len1;*/ + memcpy( uip_appdata, ( u8_t * ) uip_appdata + uiAccumulatedLen, len1 ); + uip_add32( BUF->seqno, len_previous ); + BUF->seqno[0] = uip_acc32[0]; + BUF->seqno[1] = uip_acc32[1]; + BUF->seqno[2] = uip_acc32[2]; + BUF->seqno[3] = uip_acc32[3]; + } + + /* Recalculate the TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~( uip_tcpchksum() ); + + /* Recalculate the IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + + /* Transmit the packet. */ + uip_arp_out(); + uip_low_level_output( uip_buf, uip_len ); + + len_previous = len1; + } + } + else + { + uip_arp_out(); + uip_low_level_output( uip_buf, uip_len ); + } + } + else + { + uip_low_level_output( uip_buf, uip_len ); + } + + #endif + return 1; +} + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.h new file mode 100644 index 0000000..e8f173a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.h @@ -0,0 +1,1642 @@ + +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * Header file for the uIP TCP/IP stack. + * \author Adam Dunkels + * + * The uIP TCP/IP stack header file contains definitions for a number + * of C macros that are used by uIP programs as well as internal uIP + * structures, TCP/IP header structures and function declarations. + * + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.h,v 1.40 2006/06/08 07:12:07 adam Exp $ + * + */ + +#ifndef __UIP_H__ +#define __UIP_H__ + +#include "uipopt.h" + +/** + * Repressentation of an IP address. + * + */ +typedef u16_t uip_ip4addr_t[2]; +typedef u16_t uip_ip6addr_t[8]; +#if UIP_CONF_IPV6 +typedef uip_ip6addr_t uip_ipaddr_t; +#else /* UIP_CONF_IPV6 */ +typedef uip_ip4addr_t uip_ipaddr_t; +#endif /* UIP_CONF_IPV6 */ + +/*---------------------------------------------------------------------------*/ +/* First, the functions that should be called from the + * system. Initialization, the periodic timer and incoming packets are + * handled by the following three functions. + */ + +/** + * \defgroup uipconffunc uIP configuration functions + * @{ + * + * The uIP configuration functions are used for setting run-time + * parameters in uIP such as IP addresses. + */ + +/** + * Set the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * Example: + \code + + uip_ipaddr_t addr; + + uip_ipaddr(&addr, 192,168,1,2); + uip_sethostaddr(&addr); + + \endcode + * \param addr A pointer to an IP address of type uip_ipaddr_t; + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_sethostaddr(addr) uip_ipaddr_copy(uip_hostaddr, (addr)) + +/** + * Get the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * Example: + \code + uip_ipaddr_t hostaddr; + + uip_gethostaddr(&hostaddr); + \endcode + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the currently configured IP address. + * + * \hideinitializer + */ +#define uip_gethostaddr(addr) uip_ipaddr_copy((addr), uip_hostaddr) + +/** + * Set the default router's IP address. + * + * \param addr A pointer to a uip_ipaddr_t variable containing the IP + * address of the default router. + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_setdraddr(addr) uip_ipaddr_copy(uip_draddr, (addr)) + +/** + * Set the netmask. + * + * \param addr A pointer to a uip_ipaddr_t variable containing the IP + * address of the netmask. + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_setnetmask(addr) uip_ipaddr_copy(uip_netmask, (addr)) + + +/** + * Get the default router's IP address. + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the IP address of the default router. + * + * \hideinitializer + */ +#define uip_getdraddr(addr) uip_ipaddr_copy((addr), uip_draddr) + +/** + * Get the netmask. + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the value of the netmask. + * + * \hideinitializer + */ +#define uip_getnetmask(addr) uip_ipaddr_copy((addr), uip_netmask) + +/** @} */ + +/** + * \defgroup uipinit uIP initialization functions + * @{ + * + * The uIP initialization functions are used for booting uIP. + */ + +/** + * uIP initialization function. + * + * This function should be called at boot up to initilize the uIP + * TCP/IP stack. + */ +void uip_init(void); + +/** + * uIP initialization function. + * + * This function may be used at boot time to set the initial ip_id. + */ +void uip_setipid(u16_t id); + +/** @} */ + +/** + * \defgroup uipdevfunc uIP device driver functions + * @{ + * + * These functions are used by a network device driver for interacting + * with uIP. + */ + +/** + * Process an incoming packet. + * + * This function should be called when the device driver has received + * a packet from the network. The packet from the device driver must + * be present in the uip_buf buffer, and the length of the packet + * should be placed in the uip_len variable. + * + * When the function returns, there may be an outbound packet placed + * in the uip_buf packet buffer. If so, the uip_len variable is set to + * the length of the packet. If no packet is to be sent out, the + * uip_len variable is set to 0. + * + * The usual way of calling the function is presented by the source + * code below. + \code + uip_len = devicedriver_poll(); + if(uip_len > 0) { + uip_input(); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uIP ARP code before calling + * this function: + \code + #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + uip_len = ethernet_devicedrver_poll(); + if(uip_len > 0) { + if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + ethernet_devicedriver_send(); + } + } + \endcode + * + * \hideinitializer + */ +#define uip_input() uip_process(UIP_DATA) + +/** + * Periodic processing for a connection identified by its number. + * + * This function does the necessary periodic processing (timers, + * polling) for a uIP TCP conneciton, and should be called when the + * periodic uIP timer goes off. It should be called for every + * connection, regardless of whether they are open of closed. + * + * When the function returns, it may have an outbound packet waiting + * for service in the uIP packet buffer, and if so the uip_len + * variable is set to a value larger than zero. The device driver + * should be called to send out the packet. + * + * The ususal way of calling the function is through a for() loop like + * this: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uip_arp_out() function before + * calling the device driver: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the connection which is to be periodically polled. + * + * \hideinitializer + */ +#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ + uip_process(UIP_TIMER); } while (0) + +/** + * + * + */ +#define uip_conn_active(conn) (uip_conns[conn].tcpstateflags != UIP_CLOSED) + +/** + * Perform periodic processing for a connection identified by a pointer + * to its structure. + * + * Same as uip_periodic() but takes a pointer to the actual uip_conn + * struct instead of an integer as its argument. This function can be + * used to force periodic processing of a specific connection. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_periodic_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_TIMER); } while (0) + +/** + * Reuqest that a particular connection should be polled. + * + * Similar to uip_periodic_conn() but does not perform any timer + * processing. The application is polled for new data. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_poll_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_POLL_REQUEST); } while (0) + + +#if UIP_UDP +/** + * Periodic processing for a UDP connection identified by its number. + * + * This function is essentially the same as uip_periodic(), but for + * UDP connections. It is called in a similar fashion as the + * uip_periodic() function: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note As for the uip_periodic() function, special care has to be + * taken when using uIP together with ARP and Ethernet: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the UDP connection to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ + uip_process(UIP_UDP_TIMER); } while (0) + +/** + * Periodic processing for a UDP connection identified by a pointer to + * its structure. + * + * Same as uip_udp_periodic() but takes a pointer to the actual + * uip_conn struct instead of an integer as its argument. This + * function can be used to force periodic processing of a specific + * connection. + * + * \param conn A pointer to the uip_udp_conn struct for the connection + * to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ + uip_process(UIP_UDP_TIMER); } while (0) + + +#endif /* UIP_UDP */ + +/** + * The uIP packet buffer. + * + * The uip_buf array is used to hold incoming and outgoing + * packets. The device driver should place incoming data into this + * buffer. When sending data, the device driver should read the link + * level headers and the TCP/IP headers from this buffer. The size of + * the link level headers is configured by the UIP_LLH_LEN define. + * + * \note The application data need not be placed in this buffer, so + * the device driver must read it from the place pointed to by the + * uip_appdata pointer as illustrated by the following example: + \code + void + devicedriver_send(void) + { + hwsend(&uip_buf[0], UIP_LLH_LEN); + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) { + hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN); + } else { + hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN); + hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN); + } + } + \endcode + */ +#ifndef UIP_CONF_EXTERNAL_BUFFER + extern u8_t uip_buf[UIP_BUFSIZE+2]; +#else + extern unsigned char *uip_buf; +#endif + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Functions that are used by the uIP application program. Opening and + * closing connections, sending and receiving data, etc. is all + * handled by the functions below. +*/ +/** + * \defgroup uipappfunc uIP application functions + * @{ + * + * Functions used by an application running of top of uIP. + */ + +/** + * Start listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_listen(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_listen(u16_t port); + +/** + * Stop listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_unlisten(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_unlisten(u16_t port); + +/** + * Connect to a remote host using TCP. + * + * This function is used to start a new connection to the specified + * port on the specied host. It allocates a new connection identifier, + * sets the connection to the SYN_SENT state and sets the + * retransmission timer to 0. This will cause a TCP SYN segment to be + * sent out the next time this connection is periodically processed, + * which usually is done within 0.5 seconds after the call to + * uip_connect(). + * + * \note This function is avaliable only if support for active open + * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. + * + * \note Since this function requires the port number to be in network + * byte order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_ipaddr_t ipaddr; + + uip_ipaddr(&ipaddr, 192,168,1,2); + uip_connect(&ipaddr, HTONS(80)); + \endcode + * + * \param ripaddr The IP address of the remote hot. + * + * \param port A 16-bit port number in network byte order. + * + * \return A pointer to the uIP connection identifier for the new connection, + * or NULL if no connection could be allocated. + * + */ +struct uip_conn *uip_connect(uip_ipaddr_t *ripaddr, u16_t port); + + + +/** + * \internal + * + * Check if a connection has outstanding (i.e., unacknowledged) data. + * + * \param conn A pointer to the uip_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_outstanding(conn) ((conn)->len) + +/** + * Send data on the current connection. + * + * This function is used to send out a single segment of TCP + * data. Only applications that have been invoked by uIP for event + * processing can send data. + * + * The amount of data that actually is sent out after a call to this + * funcion is determined by the maximum amount of data TCP allows. uIP + * will automatically crop the data so that only the appropriate + * amount of data is sent. The function uip_mss() can be used to query + * uIP for the amount of data that actually will be sent. + * + * \note This function does not guarantee that the sent data will + * arrive at the destination. If the data is lost in the network, the + * application will be invoked with the uip_rexmit() event being + * set. The application will then have to resend the data using this + * function. + * + * \param data A pointer to the data which is to be sent. + * + * \param len The maximum amount of data bytes to be sent. + * + * \hideinitializer + */ +void uip_send(const void *data, int len); + +/** + * The length of any incoming data that is currently avaliable (if avaliable) + * in the uip_appdata buffer. + * + * The test function uip_data() must first be used to check if there + * is any data available at all. + * + * \hideinitializer + */ +/*void uip_datalen(void);*/ +#define uip_datalen() uip_len + +/** + * The length of any out-of-band data (urgent data) that has arrived + * on the connection. + * + * \note The configuration parameter UIP_URGDATA must be set for this + * function to be enabled. + * + * \hideinitializer + */ +#define uip_urgdatalen() uip_urglen + +/** + * Close the current connection. + * + * This function will close the current connection in a nice way. + * + * \hideinitializer + */ +#define uip_close() (uip_flags = UIP_CLOSE) + +/** + * Abort the current connection. + * + * This function will abort (reset) the current connection, and is + * usually used when an error has occured that prevents using the + * uip_close() function. + * + * \hideinitializer + */ +#define uip_abort() (uip_flags = UIP_ABORT) + +/** + * Tell the sending host to stop sending data. + * + * This function will close our receiver's window so that we stop + * receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) + +/** + * Find out if the current connection has been previously stopped with + * uip_stop(). + * + * \hideinitializer + */ +#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) + +/** + * Restart the current connection, if is has previously been stopped + * with uip_stop(). + * + * This function will open the receiver's window again so that we + * start receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ + uip_conn->tcpstateflags &= ~UIP_STOPPED; \ + } while(0) + + +/* uIP tests that can be made to determine in what state the current + connection is, and what the application function should do. */ + +/** + * Is the current connection a UDP connection? + * + * This function checks whether the current connection is a UDP connection. + * + * \hideinitializer + * + */ +#define uip_udpconnection() (uip_conn == NULL) + +/** + * Is new incoming data available? + * + * Will reduce to non-zero if there is new data for the application + * present at the uip_appdata pointer. The size of the data is + * avaliable through the uip_len variable. + * + * \hideinitializer + */ +#define uip_newdata() (uip_flags & UIP_NEWDATA) + +/** + * Has previously sent data been acknowledged? + * + * Will reduce to non-zero if the previously sent data has been + * acknowledged by the remote host. This means that the application + * can send new data. + * + * \hideinitializer + */ +#define uip_acked() (uip_flags & UIP_ACKDATA) + +/** + * Has the connection just been connected? + * + * Reduces to non-zero if the current connection has been connected to + * a remote host. This will happen both if the connection has been + * actively opened (with uip_connect()) or passively opened (with + * uip_listen()). + * + * \hideinitializer + */ +#define uip_connected() (uip_flags & UIP_CONNECTED) + +/** + * Has the connection been closed by the other end? + * + * Is non-zero if the connection has been closed by the remote + * host. The application may then do the necessary clean-ups. + * + * \hideinitializer + */ +#define uip_closed() (uip_flags & UIP_CLOSE) + +/** + * Has the connection been aborted by the other end? + * + * Non-zero if the current connection has been aborted (reset) by the + * remote host. + * + * \hideinitializer + */ +#define uip_aborted() (uip_flags & UIP_ABORT) + +/** + * Has the connection timed out? + * + * Non-zero if the current connection has been aborted due to too many + * retransmissions. + * + * \hideinitializer + */ +#define uip_timedout() (uip_flags & UIP_TIMEDOUT) + +/** + * Do we need to retransmit previously data? + * + * Reduces to non-zero if the previously sent data has been lost in + * the network, and the application should retransmit it. The + * application should send the exact same data as it did the last + * time, using the uip_send() function. + * + * \hideinitializer + */ +#define uip_rexmit() (uip_flags & UIP_REXMIT) + +/** + * Is the connection being polled by uIP? + * + * Is non-zero if the reason the application is invoked is that the + * current connection has been idle for a while and should be + * polled. + * + * The polling event can be used for sending data without having to + * wait for the remote host to send data. + * + * \hideinitializer + */ +#define uip_poll() (uip_flags & UIP_POLL) + +/** + * Get the initial maxium segment size (MSS) of the current + * connection. + * + * \hideinitializer + */ +#define uip_initialmss() (uip_conn->initialmss) + +/** + * Get the current maxium segment size that can be sent on the current + * connection. + * + * The current maxiumum segment size that can be sent on the + * connection is computed from the receiver's window and the MSS of + * the connection (which also is available by calling + * uip_initialmss()). + * + * \hideinitializer + */ +#define uip_mss() (uip_conn->mss) + +/** + * Set up a new UDP connection. + * + * This function sets up a new UDP connection. The function will + * automatically allocate an unused local port for the new + * connection. However, another port can be chosen by using the + * uip_udp_bind() call, after the uip_udp_new() function has been + * called. + * + * Example: + \code + uip_ipaddr_t addr; + struct uip_udp_conn *c; + + uip_ipaddr(&addr, 192,168,2,1); + c = uip_udp_new(&addr, HTONS(12345)); + if(c != NULL) { + uip_udp_bind(c, HTONS(12344)); + } + \endcode + * \param ripaddr The IP address of the remote host. + * + * \param rport The remote port number in network byte order. + * + * \return The uip_udp_conn structure for the new connection or NULL + * if no connection could be allocated. + */ +struct uip_udp_conn *uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport); + +/** + * Removed a UDP connection. + * + * \param conn A pointer to the uip_udp_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_udp_remove(conn) (conn)->lport = 0 + +/** + * Bind a UDP connection to a local port. + * + * \param conn A pointer to the uip_udp_conn structure for the + * connection. + * + * \param port The local port number, in network byte order. + * + * \hideinitializer + */ +#define uip_udp_bind(conn, port) (conn)->lport = port + +/** + * Send a UDP datagram of length len on the current connection. + * + * This function can only be called in response to a UDP event (poll + * or newdata). The data must be present in the uip_buf buffer, at the + * place pointed to by the uip_appdata pointer. + * + * \param len The length of the data in the uip_buf buffer. + * + * \hideinitializer + */ +#define uip_udp_send(len) uip_send((char *)uip_appdata, len) + +/** @} */ + +/* uIP convenience and converting functions. */ + +/** + * \defgroup uipconvfunc uIP conversion functions + * @{ + * + * These functions can be used for converting between different data + * formats used by uIP. + */ + +/** + * Construct an IP address from four bytes. + * + * This function constructs an IP address of the type that uIP handles + * internally from four bytes. The function is handy for specifying IP + * addresses to use with e.g. the uip_connect() function. + * + * Example: + \code + uip_ipaddr_t ipaddr; + struct uip_conn *c; + + uip_ipaddr(&ipaddr, 192,168,1,2); + c = uip_connect(&ipaddr, HTONS(80)); + \endcode + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the IP address. + * + * \param addr0 The first octet of the IP address. + * \param addr1 The second octet of the IP address. + * \param addr2 The third octet of the IP address. + * \param addr3 The forth octet of the IP address. + * + * \hideinitializer + */ +#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ + ((u16_t *)(addr))[0] = HTONS(((addr0) << 8) | (addr1)); \ + ((u16_t *)(addr))[1] = HTONS(((addr2) << 8) | (addr3)); \ + } while(0) + +/** + * Construct an IPv6 address from eight 16-bit words. + * + * This function constructs an IPv6 address. + * + * \hideinitializer + */ +#define uip_ip6addr(addr, addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7) do { \ + ((u16_t *)(addr))[0] = HTONS((addr0)); \ + ((u16_t *)(addr))[1] = HTONS((addr1)); \ + ((u16_t *)(addr))[2] = HTONS((addr2)); \ + ((u16_t *)(addr))[3] = HTONS((addr3)); \ + ((u16_t *)(addr))[4] = HTONS((addr4)); \ + ((u16_t *)(addr))[5] = HTONS((addr5)); \ + ((u16_t *)(addr))[6] = HTONS((addr6)); \ + ((u16_t *)(addr))[7] = HTONS((addr7)); \ + } while(0) + +/** + * Copy an IP address to another IP address. + * + * Copies an IP address from one place to another. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr_copy(&ipaddr2, &ipaddr1); + \endcode + * + * \param dest The destination for the copy. + * \param src The source from where to copy. + * + * \hideinitializer + */ +#if !UIP_CONF_IPV6 +#define uip_ipaddr_copy(dest, src) do { \ + ((u16_t *)dest)[0] = ((u16_t *)src)[0]; \ + ((u16_t *)dest)[1] = ((u16_t *)src)[1]; \ + } while(0) +#else /* !UIP_CONF_IPV6 */ +#define uip_ipaddr_copy(dest, src) memcpy(dest, src, sizeof(uip_ip6addr_t)) +#endif /* !UIP_CONF_IPV6 */ + +/** + * Compare two IP addresses + * + * Compares two IP addresses. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) { + printf("They are the same"); + } + \endcode + * + * \param addr1 The first IP address. + * \param addr2 The second IP address. + * + * \hideinitializer + */ +#if !UIP_CONF_IPV6 +#define uip_ipaddr_cmp(addr1, addr2) (((u16_t *)addr1)[0] == ((u16_t *)addr2)[0] && \ + ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1]) +#else /* !UIP_CONF_IPV6 */ +#define uip_ipaddr_cmp(addr1, addr2) (memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0) +#endif /* !UIP_CONF_IPV6 */ + +/** + * Compare two IP addresses with netmasks + * + * Compares two IP addresses with netmasks. The masks are used to mask + * out the bits that are to be compared. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2, mask; + + uip_ipaddr(&mask, 255,255,255,0); + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr(&ipaddr2, 192,16,1,3); + if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) { + printf("They are the same"); + } + \endcode + * + * \param addr1 The first IP address. + * \param addr2 The second IP address. + * \param mask The netmask. + * + * \hideinitializer + */ +#define uip_ipaddr_maskcmp(addr1, addr2, mask) \ + (((((u16_t *)addr1)[0] & ((u16_t *)mask)[0]) == \ + (((u16_t *)addr2)[0] & ((u16_t *)mask)[0])) && \ + ((((u16_t *)addr1)[1] & ((u16_t *)mask)[1]) == \ + (((u16_t *)addr2)[1] & ((u16_t *)mask)[1]))) + + +/** + * Mask out the network part of an IP address. + * + * Masks out the network part of an IP address, given the address and + * the netmask. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2, netmask; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr(&netmask, 255,255,255,0); + uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask); + \endcode + * + * In the example above, the variable "ipaddr2" will contain the IP + * address 192.168.1.0. + * + * \param dest Where the result is to be placed. + * \param src The IP address. + * \param mask The netmask. + * + * \hideinitializer + */ +#define uip_ipaddr_mask(dest, src, mask) do { \ + ((u16_t *)dest)[0] = ((u16_t *)src)[0] & ((u16_t *)mask)[0]; \ + ((u16_t *)dest)[1] = ((u16_t *)src)[1] & ((u16_t *)mask)[1]; \ + } while(0) + +/** + * Pick the first octet of an IP address. + * + * Picks out the first octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr1(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 1. + * + * \hideinitializer + */ +#define uip_ipaddr1(addr) (htons(((u16_t *)(addr))[0]) >> 8) + +/** + * Pick the second octet of an IP address. + * + * Picks out the second octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr2(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 2. + * + * \hideinitializer + */ +#define uip_ipaddr2(addr) (htons(((u16_t *)(addr))[0]) & 0xff) + +/** + * Pick the third octet of an IP address. + * + * Picks out the third octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr3(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 3. + * + * \hideinitializer + */ +#define uip_ipaddr3(addr) (htons(((u16_t *)(addr))[1]) >> 8) + +/** + * Pick the fourth octet of an IP address. + * + * Picks out the fourth octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr4(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 4. + * + * \hideinitializer + */ +#define uip_ipaddr4(addr) (htons(((u16_t *)(addr))[1]) & 0xff) + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This macro is primarily used for converting constants from host + * byte order to network byte order. For converting variables to + * network byte order, use the htons() function instead. + * + * \hideinitializer + */ +#ifndef HTONS +# if UIP_BYTE_ORDER == UIP_BIG_ENDIAN +# define HTONS(n) (n) +# else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ +# define HTONS(n) (u16_t)((((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8)) +# endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ +#else +#error "HTONS already defined!" +#endif /* HTONS */ + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This function is primarily used for converting variables from host + * byte order to network byte order. For converting constants to + * network byte order, use the HTONS() macro instead. + */ +#ifndef htons +u16_t htons(u16_t val); +#endif /* htons */ +#ifndef ntohs +#define ntohs htons +#endif + +/** @} */ + +/** + * Pointer to the application data in the packet buffer. + * + * This pointer points to the application data when the application is + * called. If the application wishes to send data, the application may + * use this space to write the data into before calling uip_send(). + */ +extern void *uip_appdata; + +#if UIP_URGDATA > 0 +/* u8_t *uip_urgdata: + * + * This pointer points to any urgent data that has been received. Only + * present if compiled with support for urgent data (UIP_URGDATA). + */ +extern void *uip_urgdata; +#endif /* UIP_URGDATA > 0 */ + + +/** + * \defgroup uipdrivervars Variables used in uIP device drivers + * @{ + * + * uIP has a few global variables that are used in device drivers for + * uIP. + */ + +/** + * The length of the packet in the uip_buf buffer. + * + * The global variable uip_len holds the length of the packet in the + * uip_buf buffer. + * + * When the network device driver calls the uIP input function, + * uip_len should be set to the length of the packet in the uip_buf + * buffer. + * + * When sending packets, the device driver should use the contents of + * the uip_len variable to determine the length of the outgoing + * packet. + * + */ +extern u16_t uip_len; + +/** @} */ + +#if UIP_URGDATA > 0 +extern u16_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + + +/** + * Representation of a uIP TCP connection. + * + * The uip_conn structure is used for identifying a connection. All + * but one field in the structure are to be considered read-only by an + * application. The only exception is the appstate field whos purpose + * is to let the application store application-specific state (e.g., + * file pointers) for the connection. The type of this field is + * configured in the "uipopt.h" header file. + */ +struct uip_conn { + uip_ipaddr_t ripaddr; /**< The IP address of the remote host. */ + + u16_t lport; /**< The local TCP port, in network byte order. */ + u16_t rport; /**< The local remote TCP port, in network byte + order. */ + + u8_t rcv_nxt[4]; /**< The sequence number that we expect to + receive next. */ + u8_t snd_nxt[4]; /**< The sequence number that was last sent by + us. */ + u16_t len; /**< Length of the data that was previously sent. */ + u16_t mss; /**< Current maximum segment size for the + connection. */ + u16_t initialmss; /**< Initial maximum segment size for the + connection. */ + u8_t sa; /**< Retransmission time-out calculation state + variable. */ + u8_t sv; /**< Retransmission time-out calculation state + variable. */ + u8_t rto; /**< Retransmission time-out. */ + u8_t tcpstateflags; /**< TCP state and flags. */ + u8_t timer; /**< The retransmission timer. */ + u8_t nrtx; /**< The number of retransmissions for the last + segment sent. */ + + /** The application state. */ + uip_tcp_appstate_t appstate; +}; + + +/** + * Pointer to the current TCP connection. + * + * The uip_conn pointer can be used to access the current TCP + * connection. + */ +extern struct uip_conn *uip_conn; +/* The array containing all uIP connections. */ +extern struct uip_conn uip_conns[UIP_CONNS]; +/** + * \addtogroup uiparch + * @{ + */ + +/** + * 4-byte array used for the 32-bit sequence number calculations. + */ +extern u8_t uip_acc32[4]; + +/** @} */ + + +#if UIP_UDP +/** + * Representation of a uIP UDP connection. + */ +struct uip_udp_conn { + uip_ipaddr_t ripaddr; /**< The IP address of the remote peer. */ + u16_t lport; /**< The local port number in network byte order. */ + u16_t rport; /**< The remote port number in network byte order. */ + u8_t ttl; /**< Default time-to-live. */ + + /** The application state. */ + uip_udp_appstate_t appstate; +}; + +/** + * The current UDP connection. + */ +extern struct uip_udp_conn *uip_udp_conn; +extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +/** + * The structure holding the TCP/IP statistics that are gathered if + * UIP_STATISTICS is set to 1. + * + */ +struct uip_stats { + struct { + uip_stats_t drop; /**< Number of dropped packets at the IP + layer. */ + uip_stats_t recv; /**< Number of received packets at the IP + layer. */ + uip_stats_t sent; /**< Number of sent packets at the IP + layer. */ + uip_stats_t vhlerr; /**< Number of packets dropped due to wrong + IP version or header length. */ + uip_stats_t hblenerr; /**< Number of packets dropped due to wrong + IP length, high byte. */ + uip_stats_t lblenerr; /**< Number of packets dropped due to wrong + IP length, low byte. */ + uip_stats_t fragerr; /**< Number of packets dropped since they + were IP fragments. */ + uip_stats_t chkerr; /**< Number of packets dropped due to IP + checksum errors. */ + uip_stats_t protoerr; /**< Number of packets dropped since they + were neither ICMP, UDP nor TCP. */ + } ip; /**< IP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped ICMP packets. */ + uip_stats_t recv; /**< Number of received ICMP packets. */ + uip_stats_t sent; /**< Number of sent ICMP packets. */ + uip_stats_t typeerr; /**< Number of ICMP packets with a wrong + type. */ + } icmp; /**< ICMP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped TCP segments. */ + uip_stats_t recv; /**< Number of recived TCP segments. */ + uip_stats_t sent; /**< Number of sent TCP segments. */ + uip_stats_t chkerr; /**< Number of TCP segments with a bad + checksum. */ + uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK + number. */ + uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ + uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ + uip_stats_t syndrop; /**< Number of dropped SYNs due to too few + connections was avaliable. */ + uip_stats_t synrst; /**< Number of SYNs for closed ports, + triggering a RST. */ + } tcp; /**< TCP statistics. */ +#if UIP_UDP + struct { + uip_stats_t drop; /**< Number of dropped UDP segments. */ + uip_stats_t recv; /**< Number of recived UDP segments. */ + uip_stats_t sent; /**< Number of sent UDP segments. */ + uip_stats_t chkerr; /**< Number of UDP segments with a bad + checksum. */ + } udp; /**< UDP statistics. */ +#endif /* UIP_UDP */ +}; + +/** + * The uIP TCP/IP statistics. + * + * This is the variable in which the uIP TCP/IP statistics are gathered. + */ +extern struct uip_stats uip_stat; + + +/*---------------------------------------------------------------------------*/ +/* All the stuff below this point is internal to uIP and should not be + * used directly by an application or by a device driver. + */ +/*---------------------------------------------------------------------------*/ +/* u8_t uip_flags: + * + * When the application is called, uip_flags will contain the flags + * that are defined in this file. Please read below for more + * infomation. + */ +extern u8_t uip_flags; + +/* The following flags may be set in the global variable uip_flags + before calling the application callback. The UIP_ACKDATA, + UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time, + whereas the others are mutualy exclusive. Note that these flags + should *NOT* be accessed directly, but only through the uIP + functions/macros. */ + +#define UIP_ACKDATA 1 /* Signifies that the outstanding data was + acked and the application should send + out new data instead of retransmitting + the last data. */ +#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent + us new data. */ +#define UIP_REXMIT 4 /* Tells the application to retransmit the + data that was last sent. */ +#define UIP_POLL 8 /* Used for polling the application, to + check if the application has data that + it wants to send. */ +#define UIP_CLOSE 16 /* The remote host has closed the + connection, thus the connection has + gone away. Or the application signals + that it wants to close the + connection. */ +#define UIP_ABORT 32 /* The remote host has aborted the + connection, thus the connection has + gone away. Or the application signals + that it wants to abort the + connection. */ +#define UIP_CONNECTED 64 /* We have got a connection from a remote + host and have set up a new connection + for it, or an active connection has + been successfully established. */ + +#define UIP_TIMEDOUT 128 /* The connection has been aborted due to + too many retransmissions. */ + +/* uip_process(flag): + * + * The actual uIP function which does all the work. + */ +void uip_process(u8_t flag); + +/* The following flags are passed as an argument to the uip_process() + function. They are used to distinguish between the two cases where + uip_process() is called. It can be called either because we have + incoming data that should be processed, or because the periodic + timer has fired. These values are never used directly, but only in + the macrose defined in this file. */ + +#define UIP_DATA 1 /* Tells uIP that there is incoming + data in the uip_buf buffer. The + length of the data is stored in the + global variable uip_len. */ +#define UIP_TIMER 2 /* Tells uIP that the periodic timer + has fired. */ +#define UIP_POLL_REQUEST 3 /* Tells uIP that a connection should + be polled. */ +#define UIP_UDP_SEND_CONN 4 /* Tells uIP that a UDP datagram + should be constructed in the + uip_buf buffer. */ +#if UIP_UDP +#define UIP_UDP_TIMER 5 +#endif /* UIP_UDP */ + +/* The TCP states used in the uip_conn->tcpstateflags. */ +#define UIP_CLOSED 0 +#define UIP_SYN_RCVD 1 +#define UIP_SYN_SENT 2 +#define UIP_ESTABLISHED 3 +#define UIP_FIN_WAIT_1 4 +#define UIP_FIN_WAIT_2 5 +#define UIP_CLOSING 6 +#define UIP_TIME_WAIT 7 +#define UIP_LAST_ACK 8 +#define UIP_TS_MASK 15 + +#define UIP_STOPPED 16 + +/* The TCP and IP headers. */ + +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_tcpip_hdr { +#if UIP_CONF_IPV6 + /* IPv6 header. */ + u8_t vtc, + tcflow; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPv4 header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +#endif /* UIP_CONF_IPV6 */ + + /* TCP header. */ + u16_t srcport, + destport; + u8_t seqno[4], + ackno[4], + tcpoffset, + flags, + wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +/* The ICMP and IP headers. */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_icmpip_hdr { +#if UIP_CONF_IPV6 + /* IPv6 header. */ + u8_t vtc, + tcf; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPv4 header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +#endif /* UIP_CONF_IPV6 */ + + /* ICMP (echo) header. */ + u8_t type, icode; + u16_t icmpchksum; +#if !UIP_CONF_IPV6 + u16_t id, seqno; +#else /* !UIP_CONF_IPV6 */ + u8_t flags, reserved1, reserved2, reserved3; + u8_t icmp6data[16]; + u8_t options[1]; +#endif /* !UIP_CONF_IPV6 */ +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + + +/* The UDP and IP headers. */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_udpip_hdr { +#if UIP_CONF_IPV6 + /* IPv6 header. */ + u8_t vtc, + tcf; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +#endif /* UIP_CONF_IPV6 */ + + /* UDP header. */ + u16_t srcport, + destport; + u16_t udplen; + u16_t udpchksum; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + + + +/** + * The buffer size available for user data in the \ref uip_buf buffer. + * + * This macro holds the available size for user data in the \ref + * uip_buf buffer. The macro is intended to be used for checking + * bounds of available user data. + * + * Example: + \code + snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i); + \endcode + * + * \hideinitializer + */ +#define UIP_APPDATA_SIZE (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN) + + +#define UIP_PROTO_ICMP 1 +#define UIP_PROTO_TCP 6 +#define UIP_PROTO_UDP 17 +#define UIP_PROTO_ICMP6 58 + +/* Header sizes. */ +#if UIP_CONF_IPV6 +#define UIP_IPH_LEN 40 +#else /* UIP_CONF_IPV6 */ +#define UIP_IPH_LEN 20 /* Size of IP header */ +#endif /* UIP_CONF_IPV6 */ +#define UIP_UDPH_LEN 8 /* Size of UDP header */ +#define UIP_TCPH_LEN 20 /* Size of TCP header */ +#define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN) /* Size of IP + + UDP + header */ +#define UIP_IPTCPH_LEN (UIP_TCPH_LEN + UIP_IPH_LEN) /* Size of IP + + TCP + header */ +#define UIP_TCPIP_HLEN UIP_IPTCPH_LEN + + +#if UIP_FIXEDADDR +extern const uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; +#else /* UIP_FIXEDADDR */ +extern uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; +#endif /* UIP_FIXEDADDR */ + + + +/** + * Representation of a 48-bit Ethernet address. + */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_eth_addr { + u8_t addr[6]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +/** + * Calculate the UDP checksum of the packet in uip_buf and uip_appdata. + * + * The UDP checksum is the Internet checksum of data contents of the + * UDP segment, and a pseudo-header as defined in RFC768. + * + * \return The UDP checksum of the UDP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_udpchksum(void); + +/** + * Work out the fasted way of sending the data to the low level driver. + */ +int uip_fast_send( int xARP ); + +#endif /* __UIP_H__ */ + + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arch.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arch.h new file mode 100644 index 0000000..5ea4578 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arch.h @@ -0,0 +1,138 @@ +/** + * \addtogroup uip + * {@ + */ + +/** + * \defgroup uiparch Architecture specific uIP functions + * @{ + * + * The functions in the architecture specific module implement the IP + * check sum and 32-bit additions. + * + * The IP checksum calculation is the most computationally expensive + * operation in the TCP/IP stack and it therefore pays off to + * implement this in efficient assembler. The purpose of the uip-arch + * module is to let the checksum functions to be implemented in + * architecture specific assembler. + * + */ + +/** + * \file + * Declarations of architecture specific functions. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.h,v 1.2 2006/06/07 09:15:19 adam Exp $ + * + */ + +#ifndef __UIP_ARCH_H__ +#define __UIP_ARCH_H__ + +#include "uip.h" + +/** + * Carry out a 32-bit addition. + * + * Because not all architectures for which uIP is intended has native + * 32-bit arithmetic, uIP uses an external C function for doing the + * required 32-bit additions in the TCP protocol processing. This + * function should add the two arguments and place the result in the + * global variable uip_acc32. + * + * \note The 32-bit integer pointed to by the op32 parameter and the + * result in the uip_acc32 variable are in network byte order (big + * endian). + * + * \param op32 A pointer to a 4-byte array representing a 32-bit + * integer in network byte order (big endian). + * + * \param op16 A 16-bit integer in host byte order. + */ +void uip_add32(u8_t *op32, u16_t op16); + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \note This function is not called in the current version of uIP, + * but future versions might make use of it. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \note The uip_appdata pointer that points to the packet data may + * point anywhere in memory, so it is not possible to simply calculate + * the Internet checksum of the contents of the uip_buf buffer. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +u16_t uip_udpchksum(void); + +/** @} */ +/** @} */ + +#endif /* __UIP_ARCH_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.c new file mode 100644 index 0000000..d105226 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.c @@ -0,0 +1,466 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uiparp uIP Address Resolution Protocol + * @{ + * + * The Address Resolution Protocol ARP is used for mapping between IP + * addresses and link level addresses such as the Ethernet MAC + * addresses. ARP uses broadcast queries to ask for the link level + * address of a known IP address and the host which is configured with + * the IP address for which the query was meant, will respond with its + * link level address. + * + * \note This ARP implementation only supports Ethernet. + */ + +/** + * \file + * Implementation of the ARP Address Resolution Protocol. + * \author Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.c,v 1.8 2006/06/02 23:36:21 adam Exp $ + * + */ +#include "uip_arp.h" + +#include + +#ifdef __ICCARM__ + #pragma pack( 1 ) +#endif +struct arp_hdr +{ + struct uip_eth_hdr ethhdr; + u16_t hwtype; + u16_t protocol; + u8_t hwlen; + u8_t protolen; + u16_t opcode; + struct uip_eth_addr shwaddr; + u16_t sipaddr[2]; + struct uip_eth_addr dhwaddr; + u16_t dipaddr[2]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif +#ifdef __ICCARM__ + #pragma pack( 1 ) +#endif +struct ethip_hdr +{ + struct uip_eth_hdr ethhdr; + + /* IP header. */ + u8_t vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto; + u16_t ipchksum; + u16_t srcipaddr[2], destipaddr[2]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARP_HWTYPE_ETH 1 + +struct arp_entry +{ + u16_t ipaddr[2]; + struct uip_eth_addr ethaddr; + u8_t time; +}; + +static const struct uip_eth_addr broadcast_ethaddr = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; +static const u16_t broadcast_ipaddr[2] = { 0xffff, 0xffff }; + +static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; +static u16_t ipaddr[2]; +static u8_t i, c; + +static u8_t arptime; +static u8_t tmpage; + +#define BUF ( ( struct arp_hdr * ) &uip_buf[0] ) +#define IPBUF ( ( struct ethip_hdr * ) &uip_buf[0] ) + +/*-----------------------------------------------------------------------------------*/ + +/** + * Initialize the ARP module. + * + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_init( void ) +{ + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + memset( arp_table[i].ipaddr, 0, 4 ); + } +} + +/*-----------------------------------------------------------------------------------*/ + +/** + * Periodic ARP processing function. + * + * This function performs periodic timer processing in the ARP module + * and should be called at regular intervals. The recommended interval + * is 10 seconds between the calls. + * + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_timer( void ) +{ + struct arp_entry *tabptr; + + ++arptime; + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( (tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && arptime - tabptr->time >= UIP_ARP_MAXAGE ) + { + memset( tabptr->ipaddr, 0, 4 ); + } + } +} + +/*-----------------------------------------------------------------------------------*/ +static void uip_arp_update( u16_t *ipaddr, struct uip_eth_addr *ethaddr ) +{ + register struct arp_entry *tabptr; + + /* Walk through the ARP mapping table and try to find an entry to + update. If none is found, the IP -> MAC address mapping is + inserted in the ARP table. */ + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + + /* Only check those entries that are actually in use. */ + if( tabptr->ipaddr[0] != 0 && tabptr->ipaddr[1] != 0 ) + { + /* Check if the source IP address of the incoming packet matches + the IP address in this ARP table entry. */ + if( ipaddr[0] == tabptr->ipaddr[0] && ipaddr[1] == tabptr->ipaddr[1] ) + { + /* An old entry found, update this and return. */ + memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 ); + tabptr->time = arptime; + + return; + } + } + } + + /* If we get here, no existing ARP table entry was found, so we + create one. */ + + /* First, we try to find an unused entry in the ARP table. */ + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( tabptr->ipaddr[0] == 0 && tabptr->ipaddr[1] == 0 ) + { + break; + } + } + + /* If no unused entry is found, we try to find the oldest entry and + throw it away. */ + if( i == UIP_ARPTAB_SIZE ) + { + tmpage = 0; + c = 0; + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( arptime - tabptr->time > tmpage ) + { + tmpage = arptime - tabptr->time; + c = i; + } + } + + i = c; + tabptr = &arp_table[i]; + } + + /* Now, i is the ARP table entry which we will fill with the new + information. */ + memcpy( tabptr->ipaddr, ipaddr, 4 ); + memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 ); + tabptr->time = arptime; +} + +/*-----------------------------------------------------------------------------------*/ + +/** + * ARP processing for incoming IP packets + * + * This function should be called by the device driver when an IP + * packet has been received. The function will check if the address is + * in the ARP cache, and if so the ARP cache entry will be + * refreshed. If no ARP cache entry was found, a new one is created. + * + * This function expects an IP packet with a prepended Ethernet header + * in the uip_buf[] buffer, and the length of the packet in the global + * variable uip_len. + */ + +/*-----------------------------------------------------------------------------------*/ +#if 1 +void uip_arp_ipin( void ) +{ + uip_len -= sizeof( struct uip_eth_hdr ); + + /* Only insert/update an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + if( (IPBUF->srcipaddr[0] & uip_netmask[0]) != (uip_hostaddr[0] & uip_netmask[0]) ) + { + return; + } + + if( (IPBUF->srcipaddr[1] & uip_netmask[1]) != (uip_hostaddr[1] & uip_netmask[1]) ) + { + return; + } + + uip_arp_update( IPBUF->srcipaddr, &(IPBUF->ethhdr.src) ); + + return; +} + +#endif /* 0 */ + +/*-----------------------------------------------------------------------------------*/ + +/** + * ARP processing for incoming ARP packets. + * + * This function should be called by the device driver when an ARP + * packet has been received. The function will act differently + * depending on the ARP packet type: if it is a reply for a request + * that we previously sent out, the ARP cache will be filled in with + * the values from the ARP reply. If the incoming ARP packet is an ARP + * request for our IP address, an ARP reply packet is created and put + * into the uip_buf[] buffer. + * + * When the function returns, the value of the global variable uip_len + * indicates whether the device driver should send out a packet or + * not. If uip_len is zero, no packet should be sent. If uip_len is + * non-zero, it contains the length of the outbound packet that is + * present in the uip_buf[] buffer. + * + * This function expects an ARP packet with a prepended Ethernet + * header in the uip_buf[] buffer, and the length of the packet in the + * global variable uip_len. + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_arpin( void ) +{ + if( uip_len < sizeof(struct arp_hdr) ) + { + uip_len = 0; + return; + } + + uip_len = 0; + + switch( BUF->opcode ) + { + case HTONS( ARP_REQUEST ): + /* ARP request. If it asked for our address, we send out a + reply. */ + if( uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr) ) + { + /* First, we register the one who made the request in our ARP + table, since it is likely that we will do more communication + with this host in the future. */ + uip_arp_update( BUF->sipaddr, &BUF->shwaddr ); + + /* The reply opcode is 2. */ + BUF->opcode = HTONS( 2 ); + + memcpy( BUF->dhwaddr.addr, BUF->shwaddr.addr, 6 ); + memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 ); + memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 ); + memcpy( BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6 ); + + BUF->dipaddr[0] = BUF->sipaddr[0]; + BUF->dipaddr[1] = BUF->sipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + + BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP ); + uip_len = sizeof( struct arp_hdr ); + } + + break; + + case HTONS( ARP_REPLY ): + /* ARP reply. We insert or update the ARP table if it was meant + for us. */ + if( uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr) ) + { + uip_arp_update( BUF->sipaddr, &BUF->shwaddr ); + } + + break; + } + + return; +} + +/*-----------------------------------------------------------------------------------*/ + +/** + * Prepend Ethernet header to an outbound IP packet and see if we need + * to send out an ARP request. + * + * This function should be called before sending out an IP packet. The + * function checks the destination IP address of the IP packet to see + * what Ethernet MAC address that should be used as a destination MAC + * address on the Ethernet. + * + * If the destination IP address is in the local network (determined + * by logical ANDing of netmask and our IP address), the function + * checks the ARP cache to see if an entry for the destination IP + * address is found. If so, an Ethernet header is prepended and the + * function returns. If no ARP cache entry is found for the + * destination IP address, the packet in the uip_buf[] is replaced by + * an ARP request packet for the IP address. The IP packet is dropped + * and it is assumed that they higher level protocols (e.g., TCP) + * eventually will retransmit the dropped packet. + * + * If the destination IP address is not on the local network, the IP + * address of the default router is used instead. + * + * When the function returns, a packet is present in the uip_buf[] + * buffer, and the length of the packet is in the global variable + * uip_len. + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_out( void ) +{ + struct arp_entry *tabptr; + + /* Find the destination IP address in the ARP table and construct + the Ethernet header. If the destination IP addres isn't on the + local network, we use the default router's IP address instead. + + If not ARP table entry is found, we overwrite the original IP + packet with an ARP request for the IP address. */ + + /* First check if destination is a local broadcast. */ + if( uip_ipaddr_cmp(IPBUF->destipaddr, broadcast_ipaddr) ) + { + memcpy( IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6 ); + } + else + { + /* Check if the destination address is on the local network. */ + if( !uip_ipaddr_maskcmp(IPBUF->destipaddr, uip_hostaddr, uip_netmask) ) + { + /* Destination address was not on the local network, so we need to + use the default router's IP address instead of the destination + address when determining the MAC address. */ + uip_ipaddr_copy( ipaddr, uip_draddr ); + } + else + { + /* Else, we use the destination IP address. */ + uip_ipaddr_copy( ipaddr, IPBUF->destipaddr ); + } + + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( uip_ipaddr_cmp(ipaddr, tabptr->ipaddr) ) + { + break; + } + } + + if( i == UIP_ARPTAB_SIZE ) + { + /* The destination address was not in our ARP table, so we + overwrite the IP packet with an ARP request. */ + memset( BUF->ethhdr.dest.addr, 0xff, 6 ); + memset( BUF->dhwaddr.addr, 0x00, 6 ); + memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 ); + memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 ); + + uip_ipaddr_copy( BUF->dipaddr, ipaddr ); + uip_ipaddr_copy( BUF->sipaddr, uip_hostaddr ); + BUF->opcode = HTONS( ARP_REQUEST ); /* ARP request. */ + BUF->hwtype = HTONS( ARP_HWTYPE_ETH ); + BUF->protocol = HTONS( UIP_ETHTYPE_IP ); + BUF->hwlen = 6; + BUF->protolen = 4; + BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP ); + + uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN]; + + uip_len = sizeof( struct arp_hdr ); + return; + } + + /* Build an ethernet header. */ + memcpy( IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6 ); + } + + memcpy( IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6 ); + + IPBUF->ethhdr.type = HTONS( UIP_ETHTYPE_IP ); + + uip_len += sizeof( struct uip_eth_hdr ); +} + +/*-----------------------------------------------------------------------------------*/ + +/** @} */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.h new file mode 100644 index 0000000..b6b2b66 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.h @@ -0,0 +1,152 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \addtogroup uiparp + * @{ + */ + +/** + * \file + * Macros and definitions for the ARP module. + * \author Adam Dunkels + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.h,v 1.5 2006/06/11 21:46:39 adam Exp $ + * + */ + +#ifndef __UIP_ARP_H__ +#define __UIP_ARP_H__ + +#include "uip.h" + + +extern struct uip_eth_addr uip_ethaddr; + +/** + * The Ethernet header. + */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_eth_hdr { + struct uip_eth_addr dest; + struct uip_eth_addr src; + u16_t type; +}PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +#define UIP_ETHTYPE_ARP 0x0806 +#define UIP_ETHTYPE_IP 0x0800 +#define UIP_ETHTYPE_IP6 0x86dd + + +/* The uip_arp_init() function must be called before any of the other + ARP functions. */ +void uip_arp_init(void); + +/* The uip_arp_ipin() function should be called whenever an IP packet + arrives from the Ethernet. This function refreshes the ARP table or + inserts a new mapping if none exists. The function assumes that an + IP packet with an Ethernet header is present in the uip_buf buffer + and that the length of the packet is in the uip_len variable. */ +void uip_arp_ipin(void); +//#define uip_arp_ipin() + +/* The uip_arp_arpin() should be called when an ARP packet is received + by the Ethernet driver. This function also assumes that the + Ethernet frame is present in the uip_buf buffer. When the + uip_arp_arpin() function returns, the contents of the uip_buf + buffer should be sent out on the Ethernet if the uip_len variable + is > 0. */ +void uip_arp_arpin(void); + +/* The uip_arp_out() function should be called when an IP packet + should be sent out on the Ethernet. This function creates an + Ethernet header before the IP header in the uip_buf buffer. The + Ethernet header will have the correct Ethernet MAC destination + address filled in if an ARP table entry for the destination IP + address (or the IP address of the default router) is present. If no + such table entry is found, the IP packet is overwritten with an ARP + request and we rely on TCP to retransmit the packet that was + overwritten. In any case, the uip_len variable holds the length of + the Ethernet frame that should be transmitted. */ +void uip_arp_out(void); + +/* The uip_arp_timer() function should be called every ten seconds. It + is responsible for flushing old entries in the ARP table. */ +void uip_arp_timer(void); + +/** @} */ + +/** + * \addtogroup uipconffunc + * @{ + */ + + +/** + * Specifiy the Ethernet MAC address. + * + * The ARP code needs to know the MAC address of the Ethernet card in + * order to be able to respond to ARP queries and to generate working + * Ethernet headers. + * + * \note This macro only specifies the Ethernet MAC address to the ARP + * code. It cannot be used to change the MAC address of the Ethernet + * card. + * + * \param eaddr A pointer to a struct uip_eth_addr containing the + * Ethernet MAC address of the Ethernet card. + * + * \hideinitializer + */ +#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ + uip_ethaddr.addr[1] = eaddr.addr[1];\ + uip_ethaddr.addr[2] = eaddr.addr[2];\ + uip_ethaddr.addr[3] = eaddr.addr[3];\ + uip_ethaddr.addr[4] = eaddr.addr[4];\ + uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) + +/** @} */ +/** @} */ + +#endif /* __UIP_ARP_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_timer.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_timer.h new file mode 100644 index 0000000..e28e3ca --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_timer.h @@ -0,0 +1,86 @@ +/** + * \defgroup timer Timer library + * + * The timer library provides functions for setting, resetting and + * restarting timers, and for checking if a timer has expired. An + * application must "manually" check if its timers have expired; this + * is not done automatically. + * + * A timer is declared as a \c struct \c timer and all access to the + * timer is made by a pointer to the declared timer. + * + * \note The timer library uses the \ref clock "Clock library" to + * measure time. Intervals should be specified in the format used by + * the clock library. + * + * @{ + */ + + +/** + * \file + * Timer library header file. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $ + */ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "clock.h" + +/** + * A timer. + * + * This structure is used for declaring a timer. The timer must be set + * with timer_set() before it can be used. + * + * \hideinitializer + */ +struct timer { + clock_time_t start; + clock_time_t interval; +}; + +void timer_set(struct timer *t, clock_time_t interval); +void timer_reset(struct timer *t); +void timer_restart(struct timer *t); +int timer_expired(struct timer *t); + +#endif /* __TIMER_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.c new file mode 100644 index 0000000..afedc0d --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2004, Adam Dunkels and the Swedish Institute of + * Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uiplib.c,v 1.2 2006/06/12 08:00:31 adam Exp $ + * + */ +#include "uip.h" +#include "uiplib.h" + +/*-----------------------------------------------------------------------------------*/ +unsigned char uiplib_ipaddrconv( char *addrstr, unsigned char *ipaddr ) +{ + unsigned char tmp; + char c; + unsigned char i, j; + + tmp = 0; + + for( i = 0; i < 4; ++i ) + { + j = 0; + do + { + c = *addrstr; + ++j; + if( j > 4 ) + { + return 0; + } + + if( c == '.' || c == 0 ) + { + *ipaddr = tmp; + ++ipaddr; + tmp = 0; + } + else if( c >= '0' && c <= '9' ) + { + tmp = ( tmp * 10 ) + ( c - '0' ); + } + else + { + return 0; + } + + ++addrstr; + } while( c != '.' && c != 0 ); + } + + return 1; +} + +/*-----------------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.h new file mode 100644 index 0000000..6eb0c66 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.h @@ -0,0 +1,71 @@ +/** + * \file + * Various uIP library functions. + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uiplib.h,v 1.1 2006/06/07 09:15:19 adam Exp $ + * + */ +#ifndef __UIPLIB_H__ +#define __UIPLIB_H__ + +/** + * \addtogroup uipconvfunc + * @{ + */ + +/** + * Convert a textual representation of an IP address to a numerical representation. + * + * This function takes a textual representation of an IP address in + * the form a.b.c.d and converts it into a 4-byte array that can be + * used by other uIP functions. + * + * \param addrstr A pointer to a string containing the IP address in + * textual form. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the numerical representation of the address. + * + * \retval 0 If the IP address could not be parsed. + * \retval Non-zero If the IP address was parsed. + */ +unsigned char uiplib_ipaddrconv(char *addrstr, unsigned char *addr); + +/** @} */ + +#endif /* __UIPLIB_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uipopt.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uipopt.h new file mode 100644 index 0000000..cc01001 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uipopt.h @@ -0,0 +1,535 @@ +/** + * \defgroup uipopt Configuration options for uIP + * @{ + * + * uIP is configured using the per-project configuration file + * uipopt.h. This file contains all compile-time options for uIP and + * should be tweaked to match each specific project. The uIP + * distribution contains a documented example "uipopt.h" that can be + * copied and modified for each project. + * + * \note Most of the configuration options in the uipopt.h should not + * be changed, but rather the per-project uip-conf.h file. + */ + +/** + * \file + * Configuration options for uIP. + * \author Adam Dunkels + * + * This file is used for tweaking various configuration options for + * uIP. You should make a copy of this file into one of your project's + * directories instead of editing this example "uipopt.h" file that + * comes with the uIP distribution. + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uipopt.h,v 1.4 2006/06/12 08:00:31 adam Exp $ + * + */ + +#ifndef __UIPOPT_H__ +#define __UIPOPT_H__ + +#ifndef UIP_LITTLE_ENDIAN +#define UIP_LITTLE_ENDIAN 3412 +#endif /* UIP_LITTLE_ENDIAN */ +#ifndef UIP_BIG_ENDIAN +#define UIP_BIG_ENDIAN 1234 +#endif /* UIP_BIG_ENDIAN */ + +#include "uip-conf.h" + +/*------------------------------------------------------------------------------*/ + +/** + * \name Static configuration options + * @{ + * + * These configuration options can be used for setting the IP address + * settings statically, but only if UIP_FIXEDADDR is set to 1. The + * configuration options for a specific node includes IP address, + * netmask and default router as well as the Ethernet address. The + * netmask, default router and Ethernet address are appliciable only + * if uIP should be run over Ethernet. + * + * All of these should be changed to suit your project. +*/ + +/** + * Determines if uIP should use a fixed IP address or not. + * + * If uIP should use a fixed IP address, the settings are set in the + * uipopt.h file. If not, the macros uip_sethostaddr(), + * uip_setdraddr() and uip_setnetmask() should be used instead. + * + * \hideinitializer + */ +#define UIP_FIXEDADDR 0 + +/** + * Ping IP address asignment. + * + * uIP uses a "ping" packets for setting its own IP address if this + * option is set. If so, uIP will start with an empty IP address and + * the destination IP address of the first incoming "ping" (ICMP echo) + * packet will be used for setting the hosts IP address. + * + * \note This works only if UIP_FIXEDADDR is 0. + * + * \hideinitializer + */ +#ifdef UIP_CONF_PINGADDRCONF +#define UIP_PINGADDRCONF UIP_CONF_PINGADDRCONF +#else /* UIP_CONF_PINGADDRCONF */ +#define UIP_PINGADDRCONF 0 +#endif /* UIP_CONF_PINGADDRCONF */ + + +/** + * Specifies if the uIP ARP module should be compiled with a fixed + * Ethernet MAC address or not. + * + * If this configuration option is 0, the macro uip_setethaddr() can + * be used to specify the Ethernet address at run-time. + * + * \hideinitializer + */ +#define UIP_FIXEDETHADDR 0 + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name IP configuration options + * @{ + * + */ +/** + * The IP TTL (time to live) of IP packets sent by uIP. + * + * This should normally not be changed. + */ +#define UIP_TTL 64 + +/** + * Turn on support for IP packet reassembly. + * + * uIP supports reassembly of fragmented IP packets. This features + * requires an additonal amount of RAM to hold the reassembly buffer + * and the reassembly code size is approximately 700 bytes. The + * reassembly buffer is of the same size as the uip_buf buffer + * (configured by UIP_BUFSIZE). + * + * \note IP packet reassembly is not heavily tested. + * + * \hideinitializer + */ +#define UIP_REASSEMBLY 0 + +/** + * The maximum time an IP fragment should wait in the reassembly + * buffer before it is dropped. + * + */ +#define UIP_REASS_MAXAGE 40 + +/** @} */ + +/*------------------------------------------------------------------------------*/ +/** + * \name UDP configuration options + * @{ + */ + +/** + * Toggles wether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP +#define UIP_UDP UIP_CONF_UDP +#else /* UIP_CONF_UDP */ +#define UIP_UDP 0 +#endif /* UIP_CONF_UDP */ + +/** + * Toggles if UDP checksums should be used or not. + * + * \note Support for UDP checksums is currently not included in uIP, + * so this option has no function. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP_CHECKSUMS +#define UIP_UDP_CHECKSUMS UIP_CONF_UDP_CHECKSUMS +#else +#define UIP_UDP_CHECKSUMS 0 +#endif + +/** + * The maximum amount of concurrent UDP connections. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP_CONNS +#define UIP_UDP_CONNS UIP_CONF_UDP_CONNS +#else /* UIP_CONF_UDP_CONNS */ +#define UIP_UDP_CONNS 10 +#endif /* UIP_CONF_UDP_CONNS */ + +/** + * The name of the function that should be called when UDP datagrams arrive. + * + * \hideinitializer + */ + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name TCP configuration options + * @{ + */ + +/** + * Determines if support for opening connections from uIP should be + * compiled in. + * + * If the applications that are running on top of uIP for this project + * do not need to open outgoing TCP connections, this configration + * option can be turned off to reduce the code size of uIP. + * + * \hideinitializer + */ +#define UIP_ACTIVE_OPEN 1 + +/** + * The maximum number of simultaneously open TCP connections. + * + * Since the TCP connections are statically allocated, turning this + * configuration knob down results in less RAM used. Each TCP + * connection requires approximatly 30 bytes of memory. + * + * \hideinitializer + */ +#ifndef UIP_CONF_MAX_CONNECTIONS +#define UIP_CONNS 10 +#else /* UIP_CONF_MAX_CONNECTIONS */ +#define UIP_CONNS UIP_CONF_MAX_CONNECTIONS +#endif /* UIP_CONF_MAX_CONNECTIONS */ + + +/** + * The maximum number of simultaneously listening TCP ports. + * + * Each listening TCP port requires 2 bytes of memory. + * + * \hideinitializer + */ +#ifndef UIP_CONF_MAX_LISTENPORTS +#define UIP_LISTENPORTS 20 +#else /* UIP_CONF_MAX_LISTENPORTS */ +#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS +#endif /* UIP_CONF_MAX_LISTENPORTS */ + +/** + * Determines if support for TCP urgent data notification should be + * compiled in. + * + * Urgent data (out-of-band data) is a rarely used TCP feature that + * very seldom would be required. + * + * \hideinitializer + */ +#define UIP_URGDATA 0 + +/** + * The initial retransmission timeout counted in timer pulses. + * + * This should not be changed. + */ +#define UIP_RTO 3 + +/** + * The maximum number of times a segment should be retransmitted + * before the connection should be aborted. + * + * This should not be changed. + */ +#define UIP_MAXRTX 8 + +/** + * The maximum number of times a SYN segment should be retransmitted + * before a connection request should be deemed to have been + * unsuccessful. + * + * This should not need to be changed. + */ +#define UIP_MAXSYNRTX 5 + +/** + * The TCP maximum segment size. + * + * This is should not be to set to more than + * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN. + */ +#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN) + +/** + * The size of the advertised receiver's window. + * + * Should be set low (i.e., to the size of the uip_buf buffer) is the + * application is slow to process incoming data, or high (32768 bytes) + * if the application processes data quickly. + * + * \hideinitializer + */ +#ifndef UIP_CONF_RECEIVE_WINDOW +#define UIP_RECEIVE_WINDOW UIP_TCP_MSS +#else +#define UIP_RECEIVE_WINDOW UIP_CONF_RECEIVE_WINDOW +#endif + +/** + * How long a connection should stay in the TIME_WAIT state. + * + * This configiration option has no real implication, and it should be + * left untouched. + */ +#define UIP_TIME_WAIT_TIMEOUT 120 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name ARP configuration options + * @{ + */ + +/** + * The size of the ARP table. + * + * This option should be set to a larger value if this uIP node will + * have many connections from the local network. + * + * \hideinitializer + */ +#ifdef UIP_CONF_ARPTAB_SIZE +#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE +#else +#define UIP_ARPTAB_SIZE 8 +#endif + +/** + * The maxium age of ARP table entries measured in 10ths of seconds. + * + * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD + * default). + */ +#define UIP_ARP_MAXAGE 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \name General configuration options + * @{ + */ + +/** + * The size of the uIP packet buffer. + * + * The uIP packet buffer should not be smaller than 60 bytes, and does + * not need to be larger than 1500 bytes. Lower size results in lower + * TCP throughput, larger size results in higher TCP throughput. + * + * \hideinitializer + */ +#ifndef UIP_CONF_BUFFER_SIZE +#define UIP_BUFSIZE 1500 +#else /* UIP_CONF_BUFFER_SIZE */ +#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE +#endif /* UIP_CONF_BUFFER_SIZE */ + + +/** + * Determines if statistics support should be compiled in. + * + * The statistics is useful for debugging and to show the user. + * + * \hideinitializer + */ +#ifndef UIP_CONF_STATISTICS +#define UIP_STATISTICS 0 +#else /* UIP_CONF_STATISTICS */ +#define UIP_STATISTICS UIP_CONF_STATISTICS +#endif /* UIP_CONF_STATISTICS */ + +/** + * Determines if logging of certain events should be compiled in. + * + * This is useful mostly for debugging. The function uip_log() + * must be implemented to suit the architecture of the project, if + * logging is turned on. + * + * \hideinitializer + */ +#ifndef UIP_CONF_LOGGING +#define UIP_LOGGING 0 +#else /* UIP_CONF_LOGGING */ +#define UIP_LOGGING UIP_CONF_LOGGING +#endif /* UIP_CONF_LOGGING */ + +/** + * Broadcast support. + * + * This flag configures IP broadcast support. This is useful only + * together with UDP. + * + * \hideinitializer + * + */ +#ifndef UIP_CONF_BROADCAST +#define UIP_BROADCAST 0 +#else /* UIP_CONF_BROADCAST */ +#define UIP_BROADCAST UIP_CONF_BROADCAST +#endif /* UIP_CONF_BROADCAST */ + +/** + * Print out a uIP log message. + * + * This function must be implemented by the module that uses uIP, and + * is called by uIP whenever a log message is generated. + */ +void uip_log(char *msg); + +/** + * The link level header length. + * + * This is the offset into the uip_buf where the IP header can be + * found. For Ethernet, this should be set to 14. For SLIP, this + * should be set to 0. + * + * \hideinitializer + */ +#ifdef UIP_CONF_LLH_LEN +#define UIP_LLH_LEN UIP_CONF_LLH_LEN +#else /* UIP_CONF_LLH_LEN */ +#define UIP_LLH_LEN 14 +#endif /* UIP_CONF_LLH_LEN */ + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name CPU architecture configuration + * @{ + * + * The CPU architecture configuration is where the endianess of the + * CPU on which uIP is to be run is specified. Most CPUs today are + * little endian, and the most notable exception are the Motorolas + * which are big endian. The BYTE_ORDER macro should be changed to + * reflect the CPU architecture on which uIP is to be run. + */ + +/** + * The byte order of the CPU architecture on which uIP is to be run. + * + * This option can be either BIG_ENDIAN (Motorola byte order) or + * LITTLE_ENDIAN (Intel byte order). + * + * \hideinitializer + */ +#define UIP_BYTE_ORDER UIP_CONF_BYTE_ORDER + +/** @} */ +/*------------------------------------------------------------------------------*/ + +/** + * \name Appication specific configurations + * @{ + * + * An uIP application is implemented using a single application + * function that is called by uIP whenever a TCP/IP event occurs. The + * name of this function must be registered with uIP at compile time + * using the UIP_APPCALL definition. + * + * uIP applications can store the application state within the + * uip_conn structure by specifying the type of the application + * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t. + * + * The file containing the definitions must be included in the + * uipopt.h file. + * + * The following example illustrates how this can look. + \code + +void httpd_appcall(void); +#define UIP_APPCALL httpd_appcall + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; +typedef struct httpd_state uip_tcp_appstate_t + \endcode + */ + +/** + * \var #define UIP_APPCALL + * + * The name of the application function that uIP should call in + * response to TCP/IP events. + * + */ + +/** + * \var typedef uip_tcp_appstate_t + * + * The type of the application state that is to be stored in the + * uip_conn structure. This usually is typedef:ed to a struct holding + * application state information. + */ + +/** + * \var typedef uip_udp_appstate_t + * + * The type of the application state that is to be stored in the + * uip_conn structure. This usually is typedef:ed to a struct holding + * application state information. + */ +/** @} */ +/** @} */ + +#endif /* __UIPOPT_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.c new file mode 100644 index 0000000..a3771dd --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.c @@ -0,0 +1,486 @@ +const char http_http[8] = /* "http://" */ { 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = /* "200 " */ { 0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = /* "301 " */ { 0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = /* "302 " */ { 0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = /* "GET " */ { 0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = /* "HTTP/1.0" */ { 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = /* "HTTP/1.1" */ { 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = + +/* "content-type: " */ +{ 0x63, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, +}; +const char http_texthtml[10] = /* "text/html" */ { 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = /* "location: " */ { 0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = /* "host: " */ { 0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = /* "\r\n" */ { 0xd, 0xa, }; +const char http_index_html[12] = /* "/index.html" */ { 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = /* "/404.html" */ { 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = /* "Referer:" */ { 0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = + +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{ 0x48, + 0x54, + 0x54, + 0x50, + 0x2f, + 0x31, + 0x2e, + 0x30, + 0x20, + 0x32, + 0x30, + 0x30, + 0x20, + 0x4f, + 0x4b, + 0xd, + 0xa, + 0x53, + 0x65, + 0x72, + 0x76, + 0x65, + 0x72, + 0x3a, + 0x20, + 0x75, + 0x49, + 0x50, + 0x2f, + 0x31, + 0x2e, + 0x30, + 0x20, + 0x68, + 0x74, + 0x74, + 0x70, + 0x3a, + 0x2f, + 0x2f, + 0x77, + 0x77, + 0x77, + 0x2e, + 0x73, + 0x69, + 0x63, + 0x73, + 0x2e, + 0x73, + 0x65, + 0x2f, + 0x7e, + 0x61, + 0x64, + 0x61, + 0x6d, + 0x2f, + 0x75, + 0x69, + 0x70, + 0x2f, + 0xd, + 0xa, + 0x43, + 0x6f, + 0x6e, + 0x6e, + 0x65, + 0x63, + 0x74, + 0x69, + 0x6f, + 0x6e, + 0x3a, + 0x20, + 0x63, + 0x6c, + 0x6f, + 0x73, + 0x65, + 0xd, + 0xa, +}; +const char http_header_404[91] = + +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{ 0x48, + 0x54, + 0x54, + 0x50, + 0x2f, + 0x31, + 0x2e, + 0x30, + 0x20, + 0x34, + 0x30, + 0x34, + 0x20, + 0x4e, + 0x6f, + 0x74, + 0x20, + 0x66, + 0x6f, + 0x75, + 0x6e, + 0x64, + 0xd, + 0xa, + 0x53, + 0x65, + 0x72, + 0x76, + 0x65, + 0x72, + 0x3a, + 0x20, + 0x75, + 0x49, + 0x50, + 0x2f, + 0x31, + 0x2e, + 0x30, + 0x20, + 0x68, + 0x74, + 0x74, + 0x70, + 0x3a, + 0x2f, + 0x2f, + 0x77, + 0x77, + 0x77, + 0x2e, + 0x73, + 0x69, + 0x63, + 0x73, + 0x2e, + 0x73, + 0x65, + 0x2f, + 0x7e, + 0x61, + 0x64, + 0x61, + 0x6d, + 0x2f, + 0x75, + 0x69, + 0x70, + 0x2f, + 0xd, + 0xa, + 0x43, + 0x6f, + 0x6e, + 0x6e, + 0x65, + 0x63, + 0x74, + 0x69, + 0x6f, + 0x6e, + 0x3a, + 0x20, + 0x63, + 0x6c, + 0x6f, + 0x73, + 0x65, + 0xd, + 0xa, +}; +const char http_content_type_plain[29] = + +/* "Content-type: text/plain\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x74, + 0x65, + 0x78, + 0x74, + 0x2f, + 0x70, + 0x6c, + 0x61, + 0x69, + 0x6e, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_html[28] = + +/* "Content-type: text/html\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x74, + 0x65, + 0x78, + 0x74, + 0x2f, + 0x68, + 0x74, + 0x6d, + 0x6c, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_css[27] = + +/* "Content-type: text/css\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x74, + 0x65, + 0x78, + 0x74, + 0x2f, + 0x63, + 0x73, + 0x73, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_text[28] = + +/* "Content-type: text/text\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x74, + 0x65, + 0x78, + 0x74, + 0x2f, + 0x74, + 0x65, + 0x78, + 0x74, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_png[28] = + +/* "Content-type: image/png\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x69, + 0x6d, + 0x61, + 0x67, + 0x65, + 0x2f, + 0x70, + 0x6e, + 0x67, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_gif[28] = + +/* "Content-type: image/gif\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x69, + 0x6d, + 0x61, + 0x67, + 0x65, + 0x2f, + 0x67, + 0x69, + 0x66, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_jpg[29] = + +/* "Content-type: image/jpeg\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x69, + 0x6d, + 0x61, + 0x67, + 0x65, + 0x2f, + 0x6a, + 0x70, + 0x65, + 0x67, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_content_type_binary[43] = + +/* "Content-type: application/octet-stream\r\n\r\n" */ +{ 0x43, + 0x6f, + 0x6e, + 0x74, + 0x65, + 0x6e, + 0x74, + 0x2d, + 0x74, + 0x79, + 0x70, + 0x65, + 0x3a, + 0x20, + 0x61, + 0x70, + 0x70, + 0x6c, + 0x69, + 0x63, + 0x61, + 0x74, + 0x69, + 0x6f, + 0x6e, + 0x2f, + 0x6f, + 0x63, + 0x74, + 0x65, + 0x74, + 0x2d, + 0x73, + 0x74, + 0x72, + 0x65, + 0x61, + 0x6d, + 0xd, + 0xa, + 0xd, + 0xa, +}; +const char http_html[6] = /* ".html" */ { 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = /* ".shtml" */ { 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = /* ".htm" */ { 0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = /* ".css" */ { 0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = /* ".png" */ { 0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = /* ".gif" */ { 0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = /* ".jpg" */ { 0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = /* ".txt" */ { 0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = /* ".txt" */ { 0x2e, 0x74, 0x78, 0x74, }; diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.h new file mode 100644 index 0000000..19ad23d --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css[27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png[28]; +extern const char http_content_type_gif[28]; +extern const char http_content_type_jpg[29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.c new file mode 100644 index 0000000..23851d3 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.c @@ -0,0 +1,169 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ +#include "net/uip.h" +#include "net/psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL( file, "file-stats", file_stats ); +HTTPD_CGI_CALL( tcp, "tcp-connections", tcp_stats ); +HTTPD_CGI_CALL( net, "net-stats", net_stats ); + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, NULL }; + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( nullfunction ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +httpd_cgifunction httpd_cgi( char *name ) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for( f = calls; *f != NULL; ++f ) + { + if( strncmp((*f)->name, name, strlen((*f)->name)) == 0 ) + { + return( *f )->function; + } + } + + return nullfunction; +} + +/*---------------------------------------------------------------------------*/ +static unsigned short generate_file_stats( void *arg ) +{ + char *f = ( char * ) arg; + return snprintf( ( char * ) uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f) ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( file_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + + PSOCK_GENERATOR_SEND( &s->sout, generate_file_stats, strchr(ptr, ' ') + 1 ); + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ { 0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0 }; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ { 0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, 0x44, 0 }; +static const char syn_sent[] = /* "SYN-SENT",*/ { 0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, 0x54, 0 }; +static const char established[] = /* "ESTABLISHED",*/ { 0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, 0x45, 0x44, 0 }; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ { 0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 0x54, 0x2d, 0x31, 0 }; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ { 0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 0x54, 0x2d, 0x32, 0 }; +static const char closing[] = /* "CLOSING",*/ { 0x43, 0x4c, 0x4f, 0x53, 0x49, 0x4e, 0x47, 0 }; +static const char time_wait[] = /* "TIME-WAIT,"*/ { 0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, 0x49, 0x54, 0 }; +static const char last_ack[] = /* "LAST-ACK"*/ { 0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, 0x4b, 0 }; + +static const char *states[] = { closed, syn_rcvd, syn_sent, established, fin_wait_1, fin_wait_2, closing, time_wait, last_ack }; + +static unsigned short generate_tcp_stats( void *arg ) +{ + struct uip_conn *conn; + struct httpd_state *s = ( struct httpd_state * ) arg; + + conn = &uip_conns[s->count]; + return snprintf( ( char * ) uip_appdata, UIP_APPDATA_SIZE, + "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, htons(conn->ripaddr[0]) & 0xff, htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, htons(conn->rport), states[conn->tcpstateflags & UIP_TS_MASK], conn->nrtx, conn->timer, + (uip_outstanding(conn)) ? '*' : ' ', (uip_stopped(conn)) ? '!' : ' ' ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( tcp_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + + for( s->count = 0; s->count < UIP_CONNS; ++s->count ) + { + if( (uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED ) + { + PSOCK_GENERATOR_SEND( &s->sout, generate_tcp_stats, s ); + } + } + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static unsigned short generate_net_stats( void *arg ) +{ + struct httpd_state *s = ( struct httpd_state * ) arg; + return snprintf( ( char * ) uip_appdata, UIP_APPDATA_SIZE, "%5u\n", (( uip_stats_t * ) &uip_stat)[s->count] ); +} + +static PT_THREAD( net_stats ( struct httpd_state *s, char *ptr ) ) +{ + PSOCK_BEGIN( &s->sout ); + +#if UIP_STATISTICS + for( s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); ++s->count ) + { + PSOCK_GENERATOR_SEND( &s->sout, generate_net_stats, s ); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.h new file mode 100644 index 0000000..99b61fe --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.h @@ -0,0 +1,85 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "net/psock.h" +#include "httpd.h" + +typedef PT_THREAD( (*httpd_cgifunction) ( struct httpd_state *, char * ) ); + +httpd_cgifunction httpd_cgi( char *name ); + +struct httpd_cgi_call +{ + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL( name, str, function ) \ + static PT_THREAD( function ( struct httpd_state *, char * ) ); \ + static const struct httpd_cgi_call name = \ + { \ + str, function \ + } + +void httpd_cgi_init( void ); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.c new file mode 100644 index 0000000..12084ce --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t httpd_fs_strcmp( const char *str1, const char *str2 ) +{ + u8_t i; + i = 0; +loop: + if( str2[i] == 0 || str1[i] == '\r' || str1[i] == '\n' ) + { + return 0; + } + + if( str1[i] != str2[i] ) + { + return 1; + } + + ++i; + goto loop; +} + +/*-----------------------------------------------------------------------------------*/ +int httpd_fs_open( const char *name, struct httpd_fs_file *file ) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for( f = ( struct httpd_fsdata_file_noconst * ) HTTPD_FS_ROOT; f != NULL; f = ( struct httpd_fsdata_file_noconst * ) f->next ) + { + if( httpd_fs_strcmp(name, f->name) == 0 ) + { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } + +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + } + + return 0; +} + +/*-----------------------------------------------------------------------------------*/ +void httpd_fs_init( void ) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for( i = 0; i < HTTPD_FS_NUMFILES; i++ ) + { + count[i] = 0; + } + +#endif /* HTTPD_FS_STATISTICS */ +} + +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count( char *name ) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for( f = ( struct httpd_fsdata_file_noconst * ) HTTPD_FS_ROOT; f != NULL; f = ( struct httpd_fsdata_file_noconst * ) f->next ) + { + if( httpd_fs_strcmp(name, f->name) == 0 ) + { + return count[i]; + } + + ++i; + } + + return 0; +} + +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.h new file mode 100644 index 0000000..afc6bbc --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file +{ + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open( const char *name, struct httpd_fs_file *file ); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count( char *name ); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init( void ); +#endif /* __HTTPD_FS_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fsdata.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fsdata.h new file mode 100644 index 0000000..a2d2fc9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fsdata.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/17 22:41:14 adamdunkels Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.c new file mode 100644 index 0000000..99564a9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.c @@ -0,0 +1,400 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ +#include "net/uip.h" +#include "apps/httpd/httpd.h" +#include "apps/httpd/httpd-fs.h" +#include "apps/httpd/httpd-cgi.h" +#include "apps/httpd/http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + +/*---------------------------------------------------------------------------*/ +static unsigned short generate_part_of_file( void *state ) +{ + struct httpd_state *s = ( struct httpd_state * ) state; + + if( s->file.len > uip_mss() ) + { + s->len = uip_mss(); + } + else + { + s->len = s->file.len; + } + + memcpy( uip_appdata, s->file.data, s->len ); + + return s->len; +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( send_file ( struct httpd_state *s ) ) +{ + PSOCK_BEGIN( &s->sout ); + + ( void ) PT_YIELD_FLAG; + + do + { + PSOCK_GENERATOR_SEND( &s->sout, generate_part_of_file, s ); + s->file.len -= s->len; + s->file.data += s->len; + } while( s->file.len > 0 ); + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( send_part_of_file ( struct httpd_state *s ) ) +{ + PSOCK_BEGIN( &s->sout ); + ( void ) PT_YIELD_FLAG; + + PSOCK_SEND( &s->sout, s->file.data, s->len ); + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static void next_scriptstate( struct httpd_state *s ) +{ + char *p; + p = strchr( s->scriptptr, ISO_nl ) + 1; + s->scriptlen -= ( unsigned short ) ( p - s->scriptptr ); + s->scriptptr = p; +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( handle_script ( struct httpd_state *s ) ) +{ + char *ptr; + + PT_BEGIN( &s->scriptpt ); + ( void ) PT_YIELD_FLAG; + while( s->file.len > 0 ) + { + /* Check if we should start executing a script. */ + if( *s->file.data == ISO_percent && *(s->file.data + 1) == ISO_bang ) + { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if( *(s->scriptptr - 1) == ISO_colon ) + { + httpd_fs_open( s->scriptptr + 1, &s->file ); + PT_WAIT_THREAD( &s->scriptpt, send_file(s) ); + } + else + { + PT_WAIT_THREAD( &s->scriptpt, httpd_cgi(s->scriptptr) (s, s->scriptptr) ); + } + + next_scriptstate( s ); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } + else + { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + if( s->file.len > uip_mss() ) + { + s->len = uip_mss(); + } + else + { + s->len = s->file.len; + } + + if( *s->file.data == ISO_percent ) + { + ptr = strchr( s->file.data + 1, ISO_percent ); + } + else + { + ptr = strchr( s->file.data, ISO_percent ); + } + + if( ptr != NULL && ptr != s->file.data ) + { + s->len = ( int ) ( ptr - s->file.data ); + if( s->len >= uip_mss() ) + { + s->len = uip_mss(); + } + } + + PT_WAIT_THREAD( &s->scriptpt, send_part_of_file(s) ); + s->file.data += s->len; + s->file.len -= s->len; + } + } + + PT_END( &s->scriptpt ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( send_headers ( struct httpd_state *s, const char *statushdr ) ) +{ + char *ptr; + + PSOCK_BEGIN( &s->sout ); + ( void ) PT_YIELD_FLAG; + PSOCK_SEND_STR( &s->sout, statushdr ); + + ptr = strrchr( s->filename, ISO_period ); + if( ptr == NULL ) + { + PSOCK_SEND_STR( &s->sout, http_content_type_binary ); + } + else if( strncmp(http_html, ptr, 5) == 0 || strncmp(http_shtml, ptr, 6) == 0 ) + { + PSOCK_SEND_STR( &s->sout, http_content_type_html ); + } + else if( strncmp(http_css, ptr, 4) == 0 ) + { + PSOCK_SEND_STR( &s->sout, http_content_type_css ); + } + else if( strncmp(http_png, ptr, 4) == 0 ) + { + PSOCK_SEND_STR( &s->sout, http_content_type_png ); + } + else if( strncmp(http_gif, ptr, 4) == 0 ) + { + PSOCK_SEND_STR( &s->sout, http_content_type_gif ); + } + else if( strncmp(http_jpg, ptr, 4) == 0 ) + { + PSOCK_SEND_STR( &s->sout, http_content_type_jpg ); + } + else + { + PSOCK_SEND_STR( &s->sout, http_content_type_plain ); + } + + PSOCK_END( &s->sout ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( handle_output ( struct httpd_state *s ) ) +{ + char *ptr; + + PT_BEGIN( &s->outputpt ); + ( void ) PT_YIELD_FLAG; + if( !httpd_fs_open(s->filename, &s->file) ) + { + httpd_fs_open( http_404_html, &s->file ); + strcpy( s->filename, http_404_html ); + PT_WAIT_THREAD( &s->outputpt, send_headers(s, http_header_404) ); + PT_WAIT_THREAD( &s->outputpt, send_file(s) ); + } + else + { + PT_WAIT_THREAD( &s->outputpt, send_headers(s, http_header_200) ); + ptr = strchr( s->filename, ISO_period ); + if( ptr != NULL && strncmp(ptr, http_shtml, 6) == 0 ) + { + PT_INIT( &s->scriptpt ); + PT_WAIT_THREAD( &s->outputpt, handle_script(s) ); + } + else + { + PT_WAIT_THREAD( &s->outputpt, send_file(s) ); + } + } + + PSOCK_CLOSE( &s->sout ); + PT_END( &s->outputpt ); +} + +/*---------------------------------------------------------------------------*/ +static PT_THREAD( handle_input ( struct httpd_state *s ) ) +{ + PSOCK_BEGIN( &s->sin ); + ( void ) PT_YIELD_FLAG; + PSOCK_READTO( &s->sin, ISO_space ); + + if( strncmp(s->inputbuf, http_get, 4) != 0 ) + { + PSOCK_CLOSE_EXIT( &s->sin ); + } + + PSOCK_READTO( &s->sin, ISO_space ); + + if( s->inputbuf[0] != ISO_slash ) + { + PSOCK_CLOSE_EXIT( &s->sin ); + } + + if( s->inputbuf[1] == ISO_space ) + { + strncpy( s->filename, http_index_html, sizeof(s->filename) ); + } + else + { + s->inputbuf[PSOCK_DATALEN( &s->sin ) - 1] = 0; + + /* Process any form input being sent to the server. */ + #if UIP_CONF_PROCESS_HTTPD_FORMS == 1 + { + extern void vApplicationProcessFormInput( char *pcInputString ); + vApplicationProcessFormInput( s->inputbuf ); + } + #endif + + strncpy( s->filename, &s->inputbuf[0], sizeof(s->filename) ); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + s->state = STATE_OUTPUT; + + while( 1 ) + { + PSOCK_READTO( &s->sin, ISO_nl ); + + if( strncmp(s->inputbuf, http_referer, 8) == 0 ) + { + s->inputbuf[PSOCK_DATALEN( &s->sin ) - 2] = 0; + + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END( &s->sin ); +} + +/*---------------------------------------------------------------------------*/ +static void handle_connection( struct httpd_state *s ) +{ + handle_input( s ); + if( s->state == STATE_OUTPUT ) + { + handle_output( s ); + } +} + +/*---------------------------------------------------------------------------*/ +void httpd_appcall( void ) +{ + struct httpd_state *s = ( struct httpd_state * ) &( uip_conn->appstate ); + + if( uip_closed() || uip_aborted() || uip_timedout() ) + { + } + else if( uip_connected() ) + { + PSOCK_INIT( &s->sin, s->inputbuf, sizeof(s->inputbuf) - 1 ); + PSOCK_INIT( &s->sout, s->inputbuf, sizeof(s->inputbuf) - 1 ); + PT_INIT( &s->outputpt ); + s->state = STATE_WAITING; + + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection( s ); + } + else if( s != NULL ) + { + if( uip_poll() ) + { + ++s->timer; + if( s->timer >= 20 ) + { + uip_abort(); + } + } + else + { + s->timer = 0; + } + + handle_connection( s ); + } + else + { + uip_abort(); + } +} + +/*---------------------------------------------------------------------------*/ + +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void httpd_init( void ) +{ + uip_listen( HTONS(80) ); +} + +/*---------------------------------------------------------------------------*/ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.h new file mode 100644 index 0000000..cd2b891 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "net/psock.h" +#include "httpd-fs.h" + +struct httpd_state +{ + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init( void ); +void httpd_appcall( void ); + +void httpd_log( char *msg ); +void httpd_log_file( u16_t *requester, char *file ); +#endif /* __HTTPD_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/makefsdata b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/makefsdata new file mode 100644 index 0000000..8d2715a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/clock-arch.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/clock-arch.h new file mode 100644 index 0000000..73d32e2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef portTickType clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc-switch.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc-switch.h new file mode 100644 index 0000000..17c8811 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc-switch.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on switch() statment + * \author Adam Dunkels + * + * This implementation of local continuations uses the C switch() + * statement to resume execution of a function somewhere inside the + * function's body. The implementation is based on the fact that + * switch() statements are able to jump directly into the bodies of + * control structures such as if() or while() statmenets. + * + * This implementation borrows heavily from Simon Tatham's coroutines + * implementation in C: + * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html + */ + +#ifndef __LC_SWITCH_H__ +#define __LC_SWTICH_H__ + +/* WARNING! lc implementation using switch() does not work if an + LC_SET() is done within another switch() statement! */ + +/** \hideinitializer */ +typedef unsigned short lc_t; + +#define LC_INIT(s) s = 0; + +#define LC_RESUME(s) switch(s) { case 0: + +#define LC_SET(s) s = __LINE__; case __LINE__: + +#define LC_END(s) } + +#endif /* __LC_SWITCH_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc.h new file mode 100644 index 0000000..3ad83cd --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \defgroup lc Local continuations + * @{ + * + * Local continuations form the basis for implementing protothreads. A + * local continuation can be set in a specific function to + * capture the state of the function. After a local continuation has + * been set can be resumed in order to restore the state of the + * function at the point where the local continuation was set. + * + * + */ + +/** + * \file lc.h + * Local continuations + * \author + * Adam Dunkels + * + */ + +#ifdef DOXYGEN +/** + * Initialize a local continuation. + * + * This operation initializes the local continuation, thereby + * unsetting any previously set continuation state. + * + * \hideinitializer + */ +#define LC_INIT(lc) + +/** + * Set a local continuation. + * + * The set operation saves the state of the function at the point + * where the operation is executed. As far as the set operation is + * concerned, the state of the function does not include the + * call-stack or local (automatic) variables, but only the program + * counter and such CPU registers that needs to be saved. + * + * \hideinitializer + */ +#define LC_SET(lc) + +/** + * Resume a local continuation. + * + * The resume operation resumes a previously set local continuation, thus + * restoring the state in which the function was when the local + * continuation was set. If the local continuation has not been + * previously set, the resume operation does nothing. + * + * \hideinitializer + */ +#define LC_RESUME(lc) + +/** + * Mark the end of local continuation usage. + * + * The end operation signifies that local continuations should not be + * used any more in the function. This operation is not needed for + * most implementations of local continuation, but is required by a + * few implementations. + * + * \hideinitializer + */ +#define LC_END(lc) + +/** + * \var typedef lc_t; + * + * The local continuation type. + * + * \hideinitializer + */ +#endif /* DOXYGEN */ + +#ifndef __LC_H__ +#define __LC_H__ + +#ifdef LC_CONF_INCLUDE +#include LC_CONF_INCLUDE +#else +#include "lc-switch.h" +#endif /* LC_CONF_INCLUDE */ + +#endif /* __LC_H__ */ + +/** @} */ +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_end.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_end.h new file mode 100644 index 0000000..a23febe --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_end.h @@ -0,0 +1,33 @@ +#ifdef __GNUC__ + __attribute__( (packed) ); +#endif + +#ifdef _SH + #ifdef __RENESAS__ + ; + #pragma unpack + #endif +#endif + +#ifdef __RX + #ifdef __RENESAS__ + ; + /* Nothing to do. */ + #endif +#endif + + +#ifdef __ICCRX__ + ; + #pragma pack() +#endif + +#ifdef __ICCARM__ + ; + #pragma pack() +#endif + + +#ifdef __CC_ARM + ; +#endif diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_start.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_start.h new file mode 100644 index 0000000..49a4dc9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_start.h @@ -0,0 +1,34 @@ +#ifdef __GNUC__ + +/* Nothing to do here. */ +; +#endif + +/* Used by SH2A port. */ +#ifdef _SH + #ifdef __RENESAS__ + #pragma pack 1 + #endif +#endif + + +#ifdef __RX + #ifdef __RENESAS__ + /* Nothing to do. */ + #endif +#endif + + +#ifdef __ICCRX__ + #pragma pack(1) +#endif + + +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +#ifdef __CC_ARM + __packed +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/psock.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/psock.h new file mode 100644 index 0000000..8d41258 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/psock.h @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \defgroup psock Protosockets library + * @{ + * + * The protosocket library provides an interface to the uIP stack that is + * similar to the traditional BSD socket interface. Unlike programs + * written for the ordinary uIP event-driven interface, programs + * written with the protosocket library are executed in a sequential + * fashion and does not have to be implemented as explicit state + * machines. + * + * Protosockets only work with TCP connections. + * + * The protosocket library uses \ref pt protothreads to provide + * sequential control flow. This makes the protosockets lightweight in + * terms of memory, but also means that protosockets inherits the + * functional limitations of protothreads. Each protosocket lives only + * within a single function. Automatic variables (stack variables) are + * not retained across a protosocket library function call. + * + * \note Because the protosocket library uses protothreads, local + * variables will not always be saved across a call to a protosocket + * library function. It is therefore advised that local variables are + * used with extreme care. + * + * The protosocket library provides functions for sending data without + * having to deal with retransmissions and acknowledgements, as well + * as functions for reading data without having to deal with data + * being split across more than one TCP segment. + * + * Because each protosocket runs as a protothread, the protosocket has to be + * started with a call to PSOCK_BEGIN() at the start of the function + * in which the protosocket is used. Similarly, the protosocket protothread can + * be terminated by a call to PSOCK_EXIT(). + * + */ + +/** + * \file + * Protosocket library header file + * \author + * Adam Dunkels + * + */ + +#ifndef __PSOCK_H__ +#define __PSOCK_H__ + +#include "uipopt.h" +#include "pt.h" + + /* + * The structure that holds the state of a buffer. + * + * This structure holds the state of a uIP buffer. The structure has + * no user-visible elements, but is used through the functions + * provided by the library. + * + */ +struct psock_buf { + u8_t *ptr; + unsigned short left; +}; + +/** + * The representation of a protosocket. + * + * The protosocket structrure is an opaque structure with no user-visible + * elements. + */ +struct psock { + struct pt pt, psockpt; /* Protothreads - one that's using the psock + functions, and one that runs inside the + psock functions. */ + const u8_t *sendptr; /* Pointer to the next data to be sent. */ + u8_t *readptr; /* Pointer to the next data to be read. */ + + char *bufptr; /* Pointer to the buffer used for buffering + incoming data. */ + + u16_t sendlen; /* The number of bytes left to be sent. */ + u16_t readlen; /* The number of bytes left to be read. */ + + struct psock_buf buf; /* The structure holding the state of the + input buffer. */ + unsigned int bufsize; /* The size of the input buffer. */ + + unsigned char state; /* The state of the protosocket. */ +}; + +void psock_init(struct psock *psock, char *buffer, unsigned int buffersize); +/** + * Initialize a protosocket. + * + * This macro initializes a protosocket and must be called before the + * protosocket is used. The initialization also specifies the input buffer + * for the protosocket. + * + * \param psock (struct psock *) A pointer to the protosocket to be + * initialized + * + * \param buffer (char *) A pointer to the input buffer for the + * protosocket. + * + * \param buffersize (unsigned int) The size of the input buffer. + * + * \hideinitializer + */ +#define PSOCK_INIT(psock, buffer, buffersize) \ + psock_init(psock, buffer, buffersize) + +/** + * Start the protosocket protothread in a function. + * + * This macro starts the protothread associated with the protosocket and + * must come before other protosocket calls in the function it is used. + * + * \param psock (struct psock *) A pointer to the protosocket to be + * started. + * + * \hideinitializer + */ +#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt)) + +PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len)); +/** + * Send data. + * + * This macro sends data over a protosocket. The protosocket protothread blocks + * until all data has been sent and is known to have been received by + * the remote end of the TCP connection. + * + * \param psock (struct psock *) A pointer to the protosocket over which + * data is to be sent. + * + * \param data (char *) A pointer to the data that is to be sent. + * + * \param datalen (unsigned int) The length of the data that is to be + * sent. + * + * \hideinitializer + */ +#define PSOCK_SEND(psock, data, datalen) \ + PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen)) + +/** + * \brief Send a null-terminated string. + * \param psock Pointer to the protosocket. + * \param str The string to be sent. + * + * This function sends a null-terminated string over the + * protosocket. + * + * \hideinitializer + */ +#define PSOCK_SEND_STR(psock, str) \ + PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str))) + +PT_THREAD(psock_generator_send(struct psock *psock, + unsigned short (*f)(void *), void *arg)); + +/** + * \brief Generate data with a function and send it + * \param psock Pointer to the protosocket. + * \param generator Pointer to the generator function + * \param arg Argument to the generator function + * + * This function generates data and sends it over the + * protosocket. This can be used to dynamically generate + * data for a transmission, instead of generating the data + * in a buffer beforehand. This function reduces the need for + * buffer memory. The generator function is implemented by + * the application, and a pointer to the function is given + * as an argument with the call to PSOCK_GENERATOR_SEND(). + * + * The generator function should place the generated data + * directly in the uip_appdata buffer, and return the + * length of the generated data. The generator function is + * called by the protosocket layer when the data first is + * sent, and once for every retransmission that is needed. + * + * \hideinitializer + */ +#define PSOCK_GENERATOR_SEND(psock, generator, arg) \ + PT_WAIT_THREAD(&((psock)->pt), \ + psock_generator_send(psock, generator, arg)) + + +/** + * Close a protosocket. + * + * This macro closes a protosocket and can only be called from within the + * protothread in which the protosocket lives. + * + * \param psock (struct psock *) A pointer to the protosocket that is to + * be closed. + * + * \hideinitializer + */ +#define PSOCK_CLOSE(psock) uip_close() + +PT_THREAD(psock_readbuf(struct psock *psock)); +/** + * Read data until the buffer is full. + * + * This macro will block waiting for data and read the data into the + * input buffer specified with the call to PSOCK_INIT(). Data is read + * until the buffer is full.. + * + * \param psock (struct psock *) A pointer to the protosocket from which + * data should be read. + * + * \hideinitializer + */ +#define PSOCK_READBUF(psock) \ + PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock)) + +PT_THREAD(psock_readto(struct psock *psock, unsigned char c)); +/** + * Read data up to a specified character. + * + * This macro will block waiting for data and read the data into the + * input buffer specified with the call to PSOCK_INIT(). Data is only + * read until the specifieed character appears in the data stream. + * + * \param psock (struct psock *) A pointer to the protosocket from which + * data should be read. + * + * \param c (char) The character at which to stop reading. + * + * \hideinitializer + */ +#define PSOCK_READTO(psock, c) \ + PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c)) + +/** + * The length of the data that was previously read. + * + * This macro returns the length of the data that was previously read + * using PSOCK_READTO() or PSOCK_READ(). + * + * \param psock (struct psock *) A pointer to the protosocket holding the data. + * + * \hideinitializer + */ +#define PSOCK_DATALEN(psock) psock_datalen(psock) + +u16_t psock_datalen(struct psock *psock); + +/** + * Exit the protosocket's protothread. + * + * This macro terminates the protothread of the protosocket and should + * almost always be used in conjunction with PSOCK_CLOSE(). + * + * \sa PSOCK_CLOSE_EXIT() + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt)) + +/** + * Close a protosocket and exit the protosocket's protothread. + * + * This macro closes a protosocket and exits the protosocket's protothread. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_CLOSE_EXIT(psock) \ + do { \ + PSOCK_CLOSE(psock); \ + PSOCK_EXIT(psock); \ + } while(0) + +/** + * Declare the end of a protosocket's protothread. + * + * This macro is used for declaring that the protosocket's protothread + * ends. It must always be used together with a matching PSOCK_BEGIN() + * macro. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_END(psock) PT_END(&((psock)->pt)) + +char psock_newdata(struct psock *s); + +/** + * Check if new data has arrived on a protosocket. + * + * This macro is used in conjunction with the PSOCK_WAIT_UNTIL() + * macro to check if data has arrived on a protosocket. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_NEWDATA(psock) psock_newdata(psock) + +/** + * Wait until a condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. The macro PSOCK_NEWDATA() can be used to check if new data + * arrives when the protosocket is waiting. + * + * Typically, this macro is used as follows: + * + \code + PT_THREAD(thread(struct psock *s, struct timer *t)) + { + PSOCK_BEGIN(s); + + PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t)); + + if(PSOCK_NEWDATA(s)) { + PSOCK_READTO(s, '\n'); + } else { + handle_timed_out(s); + } + + PSOCK_END(s); + } + \endcode + * + * \param psock (struct psock *) A pointer to the protosocket. + * \param condition The condition to wait for. + * + * \hideinitializer + */ +#define PSOCK_WAIT_UNTIL(psock, condition) \ + PT_WAIT_UNTIL(&((psock)->pt), (condition)); + +#define PSOCK_WAIT_THREAD(psock, condition) \ + PT_WAIT_THREAD(&((psock)->pt), (condition)) + +#endif /* __PSOCK_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pt.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pt.h new file mode 100644 index 0000000..00ddd44 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pt.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \file + * Protothreads implementation. + * \author + * Adam Dunkels + * + */ + +#ifndef __PT_H__ +#define __PT_H__ + +#include "lc.h" + +struct pt { + lc_t lc; +}; + +#define PT_WAITING 0 +#define PT_EXITED 1 +#define PT_ENDED 2 +#define PT_YIELDED 3 + +/** + * \name Initialization + * @{ + */ + +/** + * Initialize a protothread. + * + * Initializes a protothread. Initialization must be done prior to + * starting to execute the protothread. + * + * \param pt A pointer to the protothread control structure. + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_INIT(pt) LC_INIT((pt)->lc) + +/** @} */ + +/** + * \name Declaration and definition + * @{ + */ + +/** + * Declaration of a protothread. + * + * This macro is used to declare a protothread. All protothreads must + * be declared with this macro. + * + * \param name_args The name and arguments of the C function + * implementing the protothread. + * + * \hideinitializer + */ +#define PT_THREAD(name_args) char name_args + +/** + * Declare the start of a protothread inside the C function + * implementing the protothread. + * + * This macro is used to declare the starting point of a + * protothread. It should be placed at the start of the function in + * which the protothread runs. All C statements above the PT_BEGIN() + * invokation will be executed each time the protothread is scheduled. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc) + +/** + * Declare the end of a protothread. + * + * This macro is used for declaring that a protothread ends. It must + * always be used together with a matching PT_BEGIN() macro. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \ + PT_INIT(pt); return PT_ENDED; } + +/** @} */ + +/** + * \name Blocked wait + * @{ + */ + +/** + * Block and wait until condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. + * + * \param pt A pointer to the protothread control structure. + * \param condition The condition. + * + * \hideinitializer + */ +#define PT_WAIT_UNTIL(pt, condition) \ + do { \ + LC_SET((pt)->lc); \ + if(!(condition)) { \ + return PT_WAITING; \ + } \ + } while(0) + +/** + * Block and wait while condition is true. + * + * This function blocks and waits while condition is true. See + * PT_WAIT_UNTIL(). + * + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * \hideinitializer + */ +#define PT_WAIT_WHILE(pt, cond) PT_WAIT_UNTIL((pt), !(cond)) + +/** @} */ + +/** + * \name Hierarchical protothreads + * @{ + */ + +/** + * Block and wait until a child protothread completes. + * + * This macro schedules a child protothread. The current protothread + * will block until the child protothread completes. + * + * \note The child protothread must be manually initialized with the + * PT_INIT() function before this function is used. + * + * \param pt A pointer to the protothread control structure. + * \param thread The child protothread with arguments + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread)) + +/** + * Spawn a child protothread and wait until it exits. + * + * This macro spawns a child protothread and waits until it exits. The + * macro can only be used within a protothread. + * + * \param pt A pointer to the protothread control structure. + * \param child A pointer to the child protothread's control structure. + * \param thread The child protothread with arguments + * + * \hideinitializer + */ +#define PT_SPAWN(pt, child, thread) \ + do { \ + PT_INIT((child)); \ + PT_WAIT_THREAD((pt), (thread)); \ + } while(0) + +/** @} */ + +/** + * \name Exiting and restarting + * @{ + */ + +/** + * Restart the protothread. + * + * This macro will block and cause the running protothread to restart + * its execution at the place of the PT_BEGIN() call. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_RESTART(pt) \ + do { \ + PT_INIT(pt); \ + return PT_WAITING; \ + } while(0) + +/** + * Exit the protothread. + * + * This macro causes the protothread to exit. If the protothread was + * spawned by another protothread, the parent protothread will become + * unblocked and can continue to run. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_EXIT(pt) \ + do { \ + PT_INIT(pt); \ + return PT_EXITED; \ + } while(0) + +/** @} */ + +/** + * \name Calling a protothread + * @{ + */ + +/** + * Schedule a protothread. + * + * This function shedules a protothread. The return value of the + * function is non-zero if the protothread is running or zero if the + * protothread has exited. + * + * \param f The call to the C function implementing the protothread to + * be scheduled + * + * \hideinitializer + */ +#define PT_SCHEDULE(f) ((f) == PT_WAITING) + +/** @} */ + +/** + * \name Yielding from a protothread + * @{ + */ + +/** + * Yield from the current protothread. + * + * This function will yield the protothread, thereby allowing other + * processing to take place in the system. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_YIELD(pt) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if(PT_YIELD_FLAG == 0) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** + * \brief Yield from the protothread until a condition occurs. + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * This function will yield the protothread, until the + * specified condition evaluates to true. + * + * + * \hideinitializer + */ +#define PT_YIELD_UNTIL(pt, cond) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if((PT_YIELD_FLAG == 0) || !(cond)) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** @} */ + +#endif /* __PT_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip.h new file mode 100644 index 0000000..3a0ed19 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip.h @@ -0,0 +1,2184 @@ + + /** + * \addtogroup uip + * @{ + */ + +/** + * \file + * Header file for the uIP TCP/IP stack. + * \author Adam Dunkels + * \author Julien Abeille (IPv6 related code) + * \author Mathilde Durvy (IPv6 related code) + * + * The uIP TCP/IP stack header file contains definitions for a number + * of C macros that are used by uIP programs as well as internal uIP + * structures, TCP/IP header structures and function declarations. + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.h,v 1.24 2009/04/06 13:18:50 nvt-se Exp $ + * + */ +#ifndef __UIP_H__ +#define __UIP_H__ + +#include "net/uipopt.h" +#include "uip-conf.h" + +/** + * Representation of an IP address. + * + */ +#if UIP_CONF_IPV6 != 0 + typedef union uip_ip6addr_t + { + u8_t u8[16]; /* Initializer, must come first!!! */ + u16_t u16[8]; + } uip_ip6addr_t; + + typedef uip_ip6addr_t uip_ipaddr_t; +#else /* UIP_CONF_IPV6 */ + #ifdef __CC_ARM + __packed /* The ARM compiler insists on this being packed, but with other compilers packing it generates a warning as it will be packed anyway. */ + #endif + + typedef union uip_ip4addr_t + { + u8_t u8[4]; /* Initializer, must come first!!! */ + u16_t u16[2]; + } uip_ip4addr_t; + typedef uip_ip4addr_t uip_ipaddr_t; +#endif /* UIP_CONF_IPV6 */ + +/*---------------------------------------------------------------------------*/ + +/** \brief 16 bit 802.15.4 address */ +struct uip_802154_shortaddr +{ + u8_t addr[2]; +}; + +/** \brief 64 bit 802.15.4 address */ +struct uip_802154_longaddr +{ + u8_t addr[8]; +}; + +/** \brief 802.11 address */ +struct uip_80211_addr +{ + u8_t addr[6]; +}; + +/** \brief 802.3 address */ +#include "net/pack_struct_start.h" +struct uip_eth_addr +{ + u8_t addr[6]; +} +#include "net/pack_struct_end.h" + +#ifdef UIP_CONF_LL_802154 + + /** \brief 802.15.4 address */ + typedef struct uip_802154_longaddr uip_lladdr_t; + #define UIP_802154_SHORTADDR_LEN 2 + #define UIP_802154_LONGADDR_LEN 8 + #define UIP_LLADDR_LEN UIP_802154_LONGADDR_LEN +#else /*UIP_CONF_LL_802154*/ + #ifdef UIP_CONF_LL_80211 + /** \brief 802.11 address */ + typedef struct uip_80211_addr uip_lladdr_t; + #define UIP_LLADDR_LEN 6 + #else /*UIP_CONF_LL_80211*/ + + /** \brief Ethernet address */ + typedef struct uip_eth_addr uip_lladdr_t; + + #define UIP_LLADDR_LEN 6 + #endif /*UIP_CONF_LL_80211*/ +#endif /*UIP_CONF_LL_802154*/ + +//_RB_#include "net/tcpip.h" + +/*---------------------------------------------------------------------------*/ + +/* First, the functions that should be called from the + * system. Initialization, the periodic timer, and incoming packets are + * handled by the following three functions. + */ + +/** + * \defgroup uipconffunc uIP configuration functions + * @{ + * + * The uIP configuration functions are used for setting run-time + * parameters in uIP such as IP addresses. + */ + +/** + * Set the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * Example: + \code + + uip_ipaddr_t addr; + + uip_ipaddr(&addr, 192,168,1,2); + uip_sethostaddr(&addr); + + \endcode + * \param addr A pointer to an IP address of type uip_ipaddr_t; + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_sethostaddr( addr ) uip_ipaddr_copy( &uip_hostaddr, (addr) ) + +/** + * Get the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * Example: + \code + uip_ipaddr_t hostaddr; + + uip_gethostaddr(&hostaddr); + \endcode + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the currently configured IP address. + * + * \hideinitializer + */ +#define uip_gethostaddr( addr ) uip_ipaddr_copy( (addr), &uip_hostaddr ) + +/** + * Set the default router's IP address. + * + * \param addr A pointer to a uip_ipaddr_t variable containing the IP + * address of the default router. + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_setdraddr( addr ) uip_ipaddr_copy( &uip_draddr, (addr) ) + +/** + * Set the netmask. + * + * \param addr A pointer to a uip_ipaddr_t variable containing the IP + * address of the netmask. + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_setnetmask( addr ) uip_ipaddr_copy( &uip_netmask, (addr) ) + +/** + * Get the default router's IP address. + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the IP address of the default router. + * + * \hideinitializer + */ +#define uip_getdraddr( addr ) uip_ipaddr_copy( (addr), &uip_draddr ) + +/** + * Get the netmask. + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the value of the netmask. + * + * \hideinitializer + */ +#define uip_getnetmask( addr ) uip_ipaddr_copy( (addr), &uip_netmask ) + +/** @} */ + +/** + * \defgroup uipinit uIP initialization functions + * @{ + * + * The uIP initialization functions are used for booting uIP. + */ + +/** + * uIP initialization function. + * + * This function should be called at boot up to initilize the uIP + * TCP/IP stack. + */ +void uip_init( void ); + +/** + * uIP initialization function. + * + * This function may be used at boot time to set the initial ip_id. + */ +void uip_setipid( u16_t id ); + +/** @} */ + +/** + * \defgroup uipdevfunc uIP device driver functions + * @{ + * + * These functions are used by a network device driver for interacting + * with uIP. + */ + +/** + * Process an incoming packet. + * + * This function should be called when the device driver has received + * a packet from the network. The packet from the device driver must + * be present in the uip_buf buffer, and the length of the packet + * should be placed in the uip_len variable. + * + * When the function returns, there may be an outbound packet placed + * in the uip_buf packet buffer. If so, the uip_len variable is set to + * the length of the packet. If no packet is to be sent out, the + * uip_len variable is set to 0. + * + * The usual way of calling the function is presented by the source + * code below. + \code + uip_len = devicedriver_poll(); + if(uip_len > 0) { + uip_input(); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uIP ARP code before calling + * this function: + \code + #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + uip_len = ethernet_devicedrver_poll(); + if(uip_len > 0) { + if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + ethernet_devicedriver_send(); + } + } + \endcode + * + * \hideinitializer + */ +#define uip_input() uip_process( UIP_DATA ) + +/** + * Periodic processing for a connection identified by its number. + * + * This function does the necessary periodic processing (timers, + * polling) for a uIP TCP conneciton, and should be called when the + * periodic uIP timer goes off. It should be called for every + * connection, regardless of whether they are open of closed. + * + * When the function returns, it may have an outbound packet waiting + * for service in the uIP packet buffer, and if so the uip_len + * variable is set to a value larger than zero. The device driver + * should be called to send out the packet. + * + * The usual way of calling the function is through a for() loop like + * this: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uip_arp_out() function before + * calling the device driver: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the connection which is to be periodically polled. + * + * \hideinitializer + */ +#ifdef UIP_TCP +#define uip_periodic( conn ) \ + do \ + { \ + uip_conn = &uip_conns[conn]; \ + uip_process( UIP_TIMER ); \ + } while( 0 ) + +/** + * + * + */ +#define uip_conn_active( conn ) ( uip_conns[conn].tcpstateflags != UIP_CLOSED ) + +/** + * Perform periodic processing for a connection identified by a pointer + * to its structure. + * + * Same as uip_periodic() but takes a pointer to the actual uip_conn + * struct instead of an integer as its argument. This function can be + * used to force periodic processing of a specific connection. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_periodic_conn( conn ) \ + do \ + { \ + uip_conn = conn; \ + uip_process( UIP_TIMER ); \ + } while( 0 ) + +/** + * Request that a particular connection should be polled. + * + * Similar to uip_periodic_conn() but does not perform any timer + * processing. The application is polled for new data. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_poll_conn( conn ) \ + do \ + { \ + uip_conn = conn; \ + uip_process( UIP_POLL_REQUEST ); \ + } while( 0 ) +#endif /* UIP_TCP */ + +#ifdef UIP_UDP + +/** + * Periodic processing for a UDP connection identified by its number. + * + * This function is essentially the same as uip_periodic(), but for + * UDP connections. It is called in a similar fashion as the + * uip_periodic() function: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note As for the uip_periodic() function, special care has to be + * taken when using uIP together with ARP and Ethernet: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the UDP connection to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic( conn ) \ + do \ + { \ + uip_udp_conn = &uip_udp_conns[conn]; \ + uip_process( UIP_UDP_TIMER ); \ + } while( 0 ) + +/** + * Periodic processing for a UDP connection identified by a pointer to + * its structure. + * + * Same as uip_udp_periodic() but takes a pointer to the actual + * uip_conn struct instead of an integer as its argument. This + * function can be used to force periodic processing of a specific + * connection. + * + * \param conn A pointer to the uip_udp_conn struct for the connection + * to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic_conn( conn ) \ + do \ + { \ + uip_udp_conn = conn; \ + uip_process( UIP_UDP_TIMER ); \ + } while( 0 ) +#endif /* UIP_UDP */ + + /** \brief Abandon the reassembly of the current packet */ + void uip_reass_over( void ); + +/** + * The uIP packet buffer. + * + * The uip_buf array is used to hold incoming and outgoing + * packets. The device driver should place incoming data into this + * buffer. When sending data, the device driver should read the link + * level headers and the TCP/IP headers from this buffer. The size of + * the link level headers is configured by the UIP_LLH_LEN define. + * + * \note The application data need not be placed in this buffer, so + * the device driver must read it from the place pointed to by the + * uip_appdata pointer as illustrated by the following example: + \code + void + devicedriver_send(void) + { + hwsend(&uip_buf[0], UIP_LLH_LEN); + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) { + hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN); + } else { + hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN); + hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN); + } + } + \endcode +*/ +#ifndef UIP_CONF_EXTERNAL_BUFFER +CCIF extern u8_t uip_buf[UIP_BUFSIZE + 2]; +#else +CCIF extern unsigned char *uip_buf; +#endif + +/** @} */ + +/*---------------------------------------------------------------------------*/ + +/* Functions that are used by the uIP application program. Opening and + * closing connections, sending and receiving data, etc. is all + * handled by the functions below. + */ + +/** + * \defgroup uipappfunc uIP application functions + * @{ + * + * Functions used by an application running of top of uIP. + */ + +/** + * Start listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_listen(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_listen( u16_t port ); + +/** + * Stop listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_unlisten(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_unlisten( u16_t port ); + +/** + * Connect to a remote host using TCP. + * + * This function is used to start a new connection to the specified + * port on the specified host. It allocates a new connection identifier, + * sets the connection to the SYN_SENT state and sets the + * retransmission timer to 0. This will cause a TCP SYN segment to be + * sent out the next time this connection is periodically processed, + * which usually is done within 0.5 seconds after the call to + * uip_connect(). + * + * \note This function is available only if support for active open + * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. + * + * \note Since this function requires the port number to be in network + * byte order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_ipaddr_t ipaddr; + + uip_ipaddr(&ipaddr, 192,168,1,2); + uip_connect(&ipaddr, HTONS(80)); + \endcode + * + * \param ripaddr The IP address of the remote host. + * + * \param port A 16-bit port number in network byte order. + * + * \return A pointer to the uIP connection identifier for the new connection, + * or NULL if no connection could be allocated. + * + */ +struct uip_conn *uip_connect( uip_ipaddr_t *ripaddr, u16_t port ); + +/** + * \internal + * + * Check if a connection has outstanding (i.e., unacknowledged) data. + * + * \param conn A pointer to the uip_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_outstanding( conn ) ( (conn)->len ) + +/** + * Send data on the current connection. + * + * This function is used to send out a single segment of TCP + * data. Only applications that have been invoked by uIP for event + * processing can send data. + * + * The amount of data that actually is sent out after a call to this + * function is determined by the maximum amount of data TCP allows. uIP + * will automatically crop the data so that only the appropriate + * amount of data is sent. The function uip_mss() can be used to query + * uIP for the amount of data that actually will be sent. + * + * \note This function does not guarantee that the sent data will + * arrive at the destination. If the data is lost in the network, the + * application will be invoked with the uip_rexmit() event being + * set. The application will then have to resend the data using this + * function. + * + * \param data A pointer to the data which is to be sent. + * + * \param len The maximum amount of data bytes to be sent. + * + * \hideinitializer + */ +CCIF void uip_send( const void *data, int len ); + +/** + * The length of any incoming data that is currently available (if available) + * in the uip_appdata buffer. + * + * The test function uip_data() must first be used to check if there + * is any data available at all. + * + * \hideinitializer + */ + +/*void uip_datalen(void);*/ +#define uip_datalen() uip_len + +/** + * The length of any out-of-band data (urgent data) that has arrived + * on the connection. + * + * \note The configuration parameter UIP_URGDATA must be set for this + * function to be enabled. + * + * \hideinitializer + */ +#define uip_urgdatalen() uip_urglen + +/** + * Close the current connection. + * + * This function will close the current connection in a nice way. + * + * \hideinitializer + */ +#define uip_close() ( uip_flags = UIP_CLOSE ) + +/** + * Abort the current connection. + * + * This function will abort (reset) the current connection, and is + * usually used when an error has occurred that prevents using the + * uip_close() function. + * + * \hideinitializer + */ +#define uip_abort() ( uip_flags = UIP_ABORT ) + +/** + * Tell the sending host to stop sending data. + * + * This function will close our receiver's window so that we stop + * receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_stop() ( uip_conn->tcpstateflags |= UIP_STOPPED ) + +/** + * Find out if the current connection has been previously stopped with + * uip_stop(). + * + * \hideinitializer + */ +#define uip_stopped( conn ) ( (conn)->tcpstateflags & UIP_STOPPED ) + +/** + * Restart the current connection, if is has previously been stopped + * with uip_stop(). + * + * This function will open the receiver's window again so that we + * start receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_restart() \ + do \ + { \ + uip_flags |= UIP_NEWDATA; \ + uip_conn->tcpstateflags &= ~UIP_STOPPED; \ + } while( 0 ) + + /* uIP tests that can be made to determine in what state the current + connection is, and what the application function should do. */ + +/** + * Is the current connection a UDP connection? + * + * This function checks whether the current connection is a UDP connection. + * + * \hideinitializer + * + */ +#define uip_udpconnection() ( uip_conn == NULL ) + +/** + * Is new incoming data available? + * + * Will reduce to non-zero if there is new data for the application + * present at the uip_appdata pointer. The size of the data is + * available through the uip_len variable. + * + * \hideinitializer + */ +#define uip_newdata() ( uip_flags & UIP_NEWDATA ) + +/** + * Has previously sent data been acknowledged? + * + * Will reduce to non-zero if the previously sent data has been + * acknowledged by the remote host. This means that the application + * can send new data. + * + * \hideinitializer + */ +#define uip_acked() ( uip_flags & UIP_ACKDATA ) + +/** + * Has the connection just been connected? + * + * Reduces to non-zero if the current connection has been connected to + * a remote host. This will happen both if the connection has been + * actively opened (with uip_connect()) or passively opened (with + * uip_listen()). + * + * \hideinitializer + */ +#define uip_connected() ( uip_flags & UIP_CONNECTED ) + +/** + * Has the connection been closed by the other end? + * + * Is non-zero if the connection has been closed by the remote + * host. The application may then do the necessary clean-ups. + * + * \hideinitializer + */ +#define uip_closed() ( uip_flags & UIP_CLOSE ) + +/** + * Has the connection been aborted by the other end? + * + * Non-zero if the current connection has been aborted (reset) by the + * remote host. + * + * \hideinitializer + */ +#define uip_aborted() ( uip_flags & UIP_ABORT ) + +/** + * Has the connection timed out? + * + * Non-zero if the current connection has been aborted due to too many + * retransmissions. + * + * \hideinitializer + */ +#define uip_timedout() ( uip_flags & UIP_TIMEDOUT ) + +/** + * Do we need to retransmit previously data? + * + * Reduces to non-zero if the previously sent data has been lost in + * the network, and the application should retransmit it. The + * application should send the exact same data as it did the last + * time, using the uip_send() function. + * + * \hideinitializer + */ +#define uip_rexmit() ( uip_flags & UIP_REXMIT ) + +/** + * Is the connection being polled by uIP? + * + * Is non-zero if the reason the application is invoked is that the + * current connection has been idle for a while and should be + * polled. + * + * The polling event can be used for sending data without having to + * wait for the remote host to send data. + * + * \hideinitializer + */ +#define uip_poll() ( uip_flags & UIP_POLL ) + +/** + * Get the initial maximum segment size (MSS) of the current + * connection. + * + * \hideinitializer + */ +#define uip_initialmss() ( uip_conn->initialmss ) + +/** + * Get the current maximum segment size that can be sent on the current + * connection. + * + * The current maximum segment size that can be sent on the + * connection is computed from the receiver's window and the MSS of + * the connection (which also is available by calling + * uip_initialmss()). + * + * \hideinitializer + */ +#define uip_mss() ( uip_conn->mss ) + /** + * Set up a new UDP connection. + * + * This function sets up a new UDP connection. The function will + * automatically allocate an unused local port for the new + * connection. However, another port can be chosen by using the + * uip_udp_bind() call, after the uip_udp_new() function has been + * called. + * + * Example: + \code + uip_ipaddr_t addr; + struct uip_udp_conn *c; + + uip_ipaddr(&addr, 192,168,2,1); + c = uip_udp_new(&addr, HTONS(12345)); + if(c != NULL) { + uip_udp_bind(c, HTONS(12344)); + } + \endcode + * \param ripaddr The IP address of the remote host. + * + * \param rport The remote port number in network byte order. + * + * \return The uip_udp_conn structure for the new connection or NULL + * if no connection could be allocated. + */ + struct uip_udp_conn *uip_udp_new( const uip_ipaddr_t *ripaddr, u16_t rport ); + +/** + * Removed a UDP connection. + * + * \param conn A pointer to the uip_udp_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_udp_remove( conn ) ( conn )->lport = 0 + +/** + * Bind a UDP connection to a local port. + * + * \param conn A pointer to the uip_udp_conn structure for the + * connection. + * + * \param port The local port number, in network byte order. + * + * \hideinitializer + */ +#define uip_udp_bind( conn, port ) ( conn )->lport = port + +/** + * Send a UDP datagram of length len on the current connection. + * + * This function can only be called in response to a UDP event (poll + * or newdata). The data must be present in the uip_buf buffer, at the + * place pointed to by the uip_appdata pointer. + * + * \param len The length of the data in the uip_buf buffer. + * + * \hideinitializer + */ +#define uip_udp_send( len ) uip_send( ( char * ) uip_appdata, len ) + +/** @} */ + +/* uIP convenience and converting functions. */ + +/** + * \defgroup uipconvfunc uIP conversion functions + * @{ + * + * These functions can be used for converting between different data + * formats used by uIP. + */ + +/** + * Convert an IP address to four bytes separated by commas. + * + * Example: + \code + uip_ipaddr_t ipaddr; + printf("ipaddr=%d.%d.%d.%d\n", uip_ipaddr_to_quad(&ipaddr)); + \endcode + * + * \param a A pointer to a uip_ipaddr_t. + * \hideinitializer + */ +#define uip_ipaddr_to_quad( a ) ( a )->u8[0], ( a )->u8[1], ( a )->u8[2], ( a )->u8[3] + +/** + * Construct an IP address from four bytes. + * + * This function constructs an IP address of the type that uIP handles + * internally from four bytes. The function is handy for specifying IP + * addresses to use with e.g. the uip_connect() function. + * + * Example: + \code + uip_ipaddr_t ipaddr; + struct uip_conn *c; + + uip_ipaddr(&ipaddr, 192,168,1,2); + c = uip_connect(&ipaddr, HTONS(80)); + \endcode + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the IP address. + * + * \param addr0 The first octet of the IP address. + * \param addr1 The second octet of the IP address. + * \param addr2 The third octet of the IP address. + * \param addr3 The forth octet of the IP address. + * + * \hideinitializer + */ +#define uip_ipaddr( addr, addr0, addr1, addr2, addr3 ) \ + do \ + { \ + ( addr )->u8[0] = addr0; \ + ( addr )->u8[1] = addr1; \ + ( addr )->u8[2] = addr2; \ + ( addr )->u8[3] = addr3; \ + } while( 0 ) + +/** + * Construct an IPv6 address from eight 16-bit words. + * + * This function constructs an IPv6 address. + * + * \hideinitializer + */ +#define uip_ip6addr( addr, addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7 ) \ + do \ + { \ + ( addr )->u16[0] = HTONS( addr0 ); \ + ( addr )->u16[1] = HTONS( addr1 ); \ + ( addr )->u16[2] = HTONS( addr2 ); \ + ( addr )->u16[3] = HTONS( addr3 ); \ + ( addr )->u16[4] = HTONS( addr4 ); \ + ( addr )->u16[5] = HTONS( addr5 ); \ + ( addr )->u16[6] = HTONS( addr6 ); \ + ( addr )->u16[7] = HTONS( addr7 ); \ + } while( 0 ) /** + * Construct an IPv6 address from eight 8-bit words. + * + * This function constructs an IPv6 address. + * + * \hideinitializer + */ +#define uip_ip6addr_u8 ( addr, addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7, addr8, addr9, addr10, addr11, addr12, addr13, addr14, \ + addr15 ) do \ + {\ + ( addr )->u8[0] = addr0; \ + ( addr )->u8[1] = addr1; \ + ( addr )->u8[2] = addr2; \ + ( addr )->u8[3] = addr3; \ + ( addr )->u8[4] = addr4; \ + ( addr )->u8[5] = addr5; \ + ( addr )->u8[6] = addr6; \ + ( addr )->u8[7] = addr7; \ + ( addr )->u8[8] = addr8; \ + ( addr )->u8[9] = addr9; \ + ( addr )->u8[10] = addr10; \ + ( addr )->u8[11] = addr11; \ + ( addr )->u8[12] = addr12; \ + ( addr )->u8[13] = addr13; \ + ( addr )->u8[14] = addr14; \ + ( addr )->u8[15] = addr15; \ + } while( 0 ) + /** + * Copy an IP address to another IP address. + * + * Copies an IP address from one place to another. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr_copy(&ipaddr2, &ipaddr1); + \endcode + * + * \param dest The destination for the copy. + * \param src The source from where to copy. + * + * \hideinitializer + */ +#ifndef uip_ipaddr_copy + #define uip_ipaddr_copy( dest, src ) \ + do \ + { \ + (dest)->u8[0] = (src)->u8[0]; \ + (dest)->u8[1] = (src)->u8[1]; \ + (dest)->u8[2] = (src)->u8[2]; \ + (dest)->u8[3] = (src)->u8[3]; \ + } while( 0 ) +#endif + + /** + * Compare two IP addresses + * + * Compares two IP addresses. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) { + printf("They are the same"); + } + \endcode + * + * \param addr1 The first IP address. + * \param addr2 The second IP address. + * + * \hideinitializer + */ +#if !UIP_CONF_IPV6 +#define uip_ipaddr_cmp( addr1, addr2 ) ( (addr1)->u16[0] == (addr2)->u16[0] && (addr1)->u16[1] == (addr2)->u16[1] ) +#else /* !UIP_CONF_IPV6 */ +#define uip_ipaddr_cmp( addr1, addr2 ) ( memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0 ) +#endif /* !UIP_CONF_IPV6 */ + + /** + * Compare two IP addresses with netmasks + * + * Compares two IP addresses with netmasks. The masks are used to mask + * out the bits that are to be compared. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2, mask; + + uip_ipaddr(&mask, 255,255,255,0); + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr(&ipaddr2, 192,16,1,3); + if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) { + printf("They are the same"); + } + \endcode + * + * \param addr1 The first IP address. + * \param addr2 The second IP address. + * \param mask The netmask. + * + * \hideinitializer + */ +#if !UIP_CONF_IPV6 +#define uip_ipaddr_maskcmp( addr1, addr2, mask ) \ + ( \ + (((( u16_t * ) addr1)[0] & (( u16_t * ) mask)[0]) == ((( u16_t * ) addr2)[0] & (( u16_t * ) mask)[0])) && \ + (((( u16_t * ) addr1)[1] & (( u16_t * ) mask)[1]) == ((( u16_t * ) addr2)[1] & (( u16_t * ) mask)[1])) \ + ) +#else +#define uip_ipaddr_prefixcmp( addr1, addr2, length ) ( memcmp(addr1, addr2, length >> 3) == 0 ) +#endif + + /** + * Check if an address is a broadcast address for a network. + * + * Checks if an address is the broadcast address for a network. The + * network is defined by an IP address that is on the network and the + * network's netmask. + * + * \param addr The IP address. + * \param netaddr The network's IP address. + * \param netmask The network's netmask. + * + * \hideinitializer + */ + + /*#define uip_ipaddr_isbroadcast(addr, netaddr, netmask) + ((uip_ipaddr_t *)(addr)).u16 & ((uip_ipaddr_t *)(addr)).u16*/ + +/** + * Mask out the network part of an IP address. + * + * Masks out the network part of an IP address, given the address and + * the netmask. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2, netmask; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr(&netmask, 255,255,255,0); + uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask); + \endcode + * + * In the example above, the variable "ipaddr2" will contain the IP + * address 192.168.1.0. + * + * \param dest Where the result is to be placed. + * \param src The IP address. + * \param mask The netmask. + * + * \hideinitializer + */ +#define uip_ipaddr_mask( dest, src, mask ) \ + do \ + { \ + ( ( u16_t * ) dest )[0] = ( ( u16_t * ) src )[0] & ( ( u16_t * ) mask )[0]; \ + ( ( u16_t * ) dest )[1] = ( ( u16_t * ) src )[1] & ( ( u16_t * ) mask )[1]; \ + } while( 0 ) + +/** + * Pick the first octet of an IP address. + * + * Picks out the first octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr1(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 1. + * + * \hideinitializer + */ +#define uip_ipaddr1( addr ) ( (addr)->u8[0] ) + +/** + * Pick the second octet of an IP address. + * + * Picks out the second octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr2(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 2. + * + * \hideinitializer + */ +#define uip_ipaddr2( addr ) ( (addr)->u8[1] ) + +/** + * Pick the third octet of an IP address. + * + * Picks out the third octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr3(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 3. + * + * \hideinitializer + */ +#define uip_ipaddr3( addr ) ( (addr)->u8[2] ) + +/** + * Pick the fourth octet of an IP address. + * + * Picks out the fourth octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr4(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 4. + * + * \hideinitializer + */ +#define uip_ipaddr4( addr ) ( (addr)->u8[3] ) + /** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This macro is primarily used for converting constants from host + * byte order to network byte order. For converting variables to + * network byte order, use the htons() function instead. + * + * \hideinitializer + */ +#ifndef HTONS +#if UIP_BYTE_ORDER == UIP_BIG_ENDIAN +#define HTONS( n ) ( n ) +#define HTONL( n ) ( n ) +#else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ +#define HTONS( n ) ( u16_t ) ( (((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8) ) +#define HTONL( n ) ( ((u32_t) HTONS(n) << 16) | HTONS((u32_t) (n) >> 16) ) +#endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ +#else +#error "HTONS already defined!" +#endif /* HTONS */ + + /** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This function is primarily used for converting variables from host + * byte order to network byte order. For converting constants to + * network byte order, use the HTONS() macro instead. + */ +#ifndef htons + CCIF u16_t htons( u16_t val ); +#endif /* htons */ + +#ifndef ntohs + #define ntohs htons +#endif + +#ifndef htonl + CCIF u32_t htonl( u32_t val ); +#endif /* htonl */ + +#ifndef ntohl + #define ntohl htonl +#endif + +/** @} */ + +/** + * Pointer to the application data in the packet buffer. + * + * This pointer points to the application data when the application is + * called. If the application wishes to send data, the application may + * use this space to write the data into before calling uip_send(). + */ +CCIF extern void *uip_appdata; + +#if UIP_URGDATA > 0 + +/* u8_t *uip_urgdata: + * + * This pointer points to any urgent data that has been received. Only + * present if compiled with support for urgent data (UIP_URGDATA). + */ +extern void *uip_urgdata; +#endif /* UIP_URGDATA > 0 */ + +/** + * \defgroup uipdrivervars Variables used in uIP device drivers + * @{ + * + * uIP has a few global variables that are used in device drivers for + * uIP. + */ + +/** + * The length of the packet in the uip_buf buffer. + * + * The global variable uip_len holds the length of the packet in the + * uip_buf buffer. + * + * When the network device driver calls the uIP input function, + * uip_len should be set to the length of the packet in the uip_buf + * buffer. + * + * When sending packets, the device driver should use the contents of + * the uip_len variable to determine the length of the outgoing + * packet. + * + */ +CCIF extern u16_t uip_len; + +/** + * The length of the extension headers + */ +extern u8_t uip_ext_len; + +/** @} */ +#if UIP_URGDATA > 0 +extern u16_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +/** + * Representation of a uIP TCP connection. + * + * The uip_conn structure is used for identifying a connection. All + * but one field in the structure are to be considered read-only by an + * application. The only exception is the appstate field whose purpose + * is to let the application store application-specific state (e.g., + * file pointers) for the connection. The type of this field is + * configured in the "uipopt.h" header file. + */ +struct uip_conn +{ + uip_ipaddr_t ripaddr; /**< The IP address of the remote host. */ + + u16_t lport; /**< The local TCP port, in network byte order. */ + u16_t rport; /**< The local remote TCP port, in network byte + order. */ + + u8_t rcv_nxt[4]; /**< The sequence number that we expect to + receive next. */ + u8_t snd_nxt[4]; /**< The sequence number that was last sent by + us. */ + u16_t len; /**< Length of the data that was previously sent. */ + u16_t mss; /**< Current maximum segment size for the + connection. */ + u16_t initialmss; /**< Initial maximum segment size for the + connection. */ + u8_t sa; /**< Retransmission time-out calculation state + variable. */ + u8_t sv; /**< Retransmission time-out calculation state + variable. */ + u8_t rto; /**< Retransmission time-out. */ + u8_t tcpstateflags; /**< TCP state and flags. */ + u8_t timer; /**< The retransmission timer. */ + u8_t nrtx; /**< The number of retransmissions for the last + segment sent. */ + + /** The application state. */ + uip_tcp_appstate_t appstate; +}; + +/** + * Pointer to the current TCP connection. + * + * The uip_conn pointer can be used to access the current TCP + * connection. + */ +CCIF extern struct uip_conn *uip_conn; +#ifdef UIP_TCP + +/* The array containing all uIP connections. */ +CCIF extern struct uip_conn uip_conns[UIP_CONNS]; +#endif + +/** + * \addtogroup uiparch + * @{ + */ + +/** + * 4-byte array used for the 32-bit sequence number calculations. + */ +extern u8_t uip_acc32[4]; + +/** @} */ +#if UIP_UDP == 1 +/** + * Representation of a uIP UDP connection. + */ +struct uip_udp_conn +{ + uip_ipaddr_t ripaddr; /**< The IP address of the remote peer. */ + u16_t lport; /**< The local port number in network byte order. */ + u16_t rport; /**< The remote port number in network byte order. */ + u8_t ttl; /**< Default time-to-live. */ + + /** The application state. */ + uip_udp_appstate_t appstate; +}; + +/** + * The current UDP connection. + */ +extern struct uip_udp_conn *uip_udp_conn; +extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +struct uip_router +{ + int ( *activate ) ( void ); + int ( *deactivate ) ( void ); + uip_ipaddr_t * ( *lookup ) ( uip_ipaddr_t *destipaddr, uip_ipaddr_t *nexthop ); +}; + +#ifdef UIP_CONF_ROUTER +extern const struct uip_router *uip_router; + +/** + * uIP routing driver registration function. + */ +void uip_router_register( const struct uip_router *router ); +#endif /*UIP_CONF_ROUTER*/ + +#ifdef UIP_CONF_ICMP6 +struct uip_icmp6_conn +{ + uip_icmp6_appstate_t appstate; +}; +extern struct uip_icmp6_conn uip_icmp6_conns; +#endif /*UIP_CONF_ICMP6*/ + +/** + * The uIP TCP/IP statistics. + * + * This is the variable in which the uIP TCP/IP statistics are gathered. + */ +#if UIP_STATISTICS == 1 +extern struct uip_stats uip_stat; +#define UIP_STAT( s ) s +#else +#define UIP_STAT( s ) +#endif /* UIP_STATISTICS == 1 */ + +/** + * The structure holding the TCP/IP statistics that are gathered if + * UIP_STATISTICS is set to 1. + * + */ +struct uip_stats +{ + struct + { + uip_stats_t recv; /**< Number of received packets at the IP + layer. */ + uip_stats_t sent; /**< Number of sent packets at the IP + layer. */ + uip_stats_t forwarded; /**< Number of forwarded packets at the IP + layer. */ + uip_stats_t drop; /**< Number of dropped packets at the IP + layer. */ + uip_stats_t vhlerr; /**< Number of packets dropped due to wrong + IP version or header length. */ + uip_stats_t hblenerr; /**< Number of packets dropped due to wrong + IP length, high byte. */ + uip_stats_t lblenerr; /**< Number of packets dropped due to wrong + IP length, low byte. */ + uip_stats_t fragerr; /**< Number of packets dropped since they + were IP fragments. */ + uip_stats_t chkerr; /**< Number of packets dropped due to IP + checksum errors. */ + uip_stats_t protoerr; /**< Number of packets dropped since they + were neither ICMP, UDP nor TCP. */ + } ip; /**< IP statistics. */ + struct + { + uip_stats_t recv; /**< Number of received ICMP packets. */ + uip_stats_t sent; /**< Number of sent ICMP packets. */ + uip_stats_t drop; /**< Number of dropped ICMP packets. */ + uip_stats_t typeerr; /**< Number of ICMP packets with a wrong + type. */ + uip_stats_t chkerr; /**< Number of ICMP packets with a bad + checksum. */ + } icmp; /**< ICMP statistics. */ +#ifdef UIP_TCP + struct + { + uip_stats_t recv; /**< Number of recived TCP segments. */ + uip_stats_t sent; /**< Number of sent TCP segments. */ + uip_stats_t drop; /**< Number of dropped TCP segments. */ + uip_stats_t chkerr; /**< Number of TCP segments with a bad + checksum. */ + uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK + number. */ + uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ + uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ + uip_stats_t syndrop; /**< Number of dropped SYNs due to too few + connections was avaliable. */ + uip_stats_t synrst; /**< Number of SYNs for closed ports, + triggering a RST. */ + } tcp; /**< TCP statistics. */ +#endif +#ifdef UIP_UDP + struct + { + uip_stats_t drop; /**< Number of dropped UDP segments. */ + uip_stats_t recv; /**< Number of recived UDP segments. */ + uip_stats_t sent; /**< Number of sent UDP segments. */ + uip_stats_t chkerr; /**< Number of UDP segments with a bad + checksum. */ + } udp; /**< UDP statistics. */ +#endif /* UIP_UDP */ +#if UIP_CONF_IPV6 != 0 + struct + { + uip_stats_t drop; /**< Number of dropped ND6 packets. */ + uip_stats_t recv; /**< Number of recived ND6 packets */ + uip_stats_t sent; /**< Number of sent ND6 packets */ + } nd6; +#endif /*UIP_CONF_IPV6*/ +}; + +/*---------------------------------------------------------------------------*/ + +/* All the stuff below this point is internal to uIP and should not be + * used directly by an application or by a device driver. + */ + +/*---------------------------------------------------------------------------*/ + +/* u8_t uip_flags: + * + * When the application is called, uip_flags will contain the flags + * that are defined in this file. Please read below for more + * information. + */ +CCIF extern u8_t uip_flags; + +/* The following flags may be set in the global variable uip_flags + before calling the application callback. The UIP_ACKDATA, + UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time, + whereas the others are mutually exclusive. Note that these flags + should *NOT* be accessed directly, but only through the uIP + functions/macros. */ +#define UIP_ACKDATA 1 /* Signifies that the outstanding data was + acked and the application should send + out new data instead of retransmitting + the last data. */ +#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent + us new data. */ +#define UIP_REXMIT 4 /* Tells the application to retransmit the + data that was last sent. */ +#define UIP_POLL 8 /* Used for polling the application, to + check if the application has data that + it wants to send. */ +#define UIP_CLOSE 16 /* The remote host has closed the + connection, thus the connection has + gone away. Or the application signals + that it wants to close the + connection. */ +#define UIP_ABORT 32 /* The remote host has aborted the + connection, thus the connection has + gone away. Or the application signals + that it wants to abort the + connection. */ +#define UIP_CONNECTED 64 /* We have got a connection from a remote + host and have set up a new connection + for it, or an active connection has + been successfully established. */ + +#define UIP_TIMEDOUT 128 /* The connection has been aborted due to + too many retransmissions. */ + +/** + * \brief process the options within a hop by hop or destination option header + * \retval 0: nothing to send, + * \retval 1: drop pkt + * \retval 2: ICMP error message to send +*/ + +/*static u8_t +uip_ext_hdr_options_process(); */ + +/* uip_process(flag): + * + * The actual uIP function which does all the work. + */ +void uip_process( u8_t flag ); + +/* The following flags are passed as an argument to the uip_process() + function. They are used to distinguish between the two cases where + uip_process() is called. It can be called either because we have + incoming data that should be processed, or because the periodic + timer has fired. These values are never used directly, but only in + the macros defined in this file. */ +#define UIP_DATA 1 /* Tells uIP that there is incoming + data in the uip_buf buffer. The + length of the data is stored in the + global variable uip_len. */ +#define UIP_TIMER 2 /* Tells uIP that the periodic timer + has fired. */ +#define UIP_POLL_REQUEST 3 /* Tells uIP that a connection should + be polled. */ +#define UIP_UDP_SEND_CONN 4 /* Tells uIP that a UDP datagram + should be constructed in the + uip_buf buffer. */ +#ifdef UIP_UDP +#define UIP_UDP_TIMER 5 +#endif /* UIP_UDP */ + +/* The TCP states used in the uip_conn->tcpstateflags. */ +#define UIP_CLOSED 0 +#define UIP_SYN_RCVD 1 +#define UIP_SYN_SENT 2 +#define UIP_ESTABLISHED 3 +#define UIP_FIN_WAIT_1 4 +#define UIP_FIN_WAIT_2 5 +#define UIP_CLOSING 6 +#define UIP_TIME_WAIT 7 +#define UIP_LAST_ACK 8 +#define UIP_TS_MASK 15 + +#define UIP_STOPPED 16 + +/* The TCP and IP headers. */ +#include "net/pack_struct_start.h" +struct uip_tcpip_hdr +{ +#if UIP_CONF_IPV6 != 0 + /* IPv6 header. */ + u8_t vtc, tcflow; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPv4 header. */ + u8_t vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto; + u16_t ipchksum; + uip_ipaddr_t srcipaddr, destipaddr; +#endif /* UIP_CONF_IPV6 */ + + /* TCP header. */ + u16_t srcport, destport; + u8_t seqno[4], ackno[4], tcpoffset, flags, wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} +#include "net/pack_struct_end.h" + +/* The ICMP and IP headers. */ +#include "net/pack_struct_start.h" +struct uip_icmpip_hdr +{ +#if UIP_CONF_IPV6 != 0 + /* IPv6 header. */ + u8_t vtc, tcf; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPv4 header. */ + u8_t vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto; + u16_t ipchksum; + uip_ipaddr_t srcipaddr, destipaddr; +#endif /* UIP_CONF_IPV6 */ + + /* ICMP header. */ + u8_t type, icode; + u16_t icmpchksum; +#if !UIP_CONF_IPV6 + u16_t id, seqno; + u8_t payload[1]; +#endif /* !UIP_CONF_IPV6 */ +} + +#include "net/pack_struct_end.h" + +/* The UDP and IP headers. */ +#include "net/pack_struct_start.h" +struct uip_udpip_hdr +{ +#if UIP_CONF_IPV6 != 0 + /* IPv6 header. */ + u8_t vtc, tcf; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IP header. */ + u8_t vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto; + u16_t ipchksum; + uip_ipaddr_t srcipaddr, destipaddr; +#endif /* UIP_CONF_IPV6 */ + + /* UDP header. */ + u16_t srcport, destport; + u16_t udplen; + u16_t udpchksum; +} + +#include "net/pack_struct_end.h" + +/* + * In IPv6 the length of the L3 headers before the transport header is + * not fixed, due to the possibility to include extension option headers + * after the IP header. hence we split here L3 and L4 headers + */ + +/* The IP header */ +struct uip_ip_hdr +{ +#if UIP_CONF_IPV6 != 0 + /* IPV6 header */ + u8_t vtc; + u8_t tcflow; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPV4 header */ + u8_t vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto; + u16_t ipchksum; + uip_ipaddr_t srcipaddr, destipaddr; +#endif /* UIP_CONF_IPV6 */ +}; + +/* + * IPv6 extension option headers: we are able to process + * the 4 extension headers defined in RFC2460 (IPv6): + * - Hop by hop option header, destination option header: + * These two are not used by any core IPv6 protocol, hence + * we just read them and go to the next. They convey options, + * the options defined in RFC2460 are Pad1 and PadN, which do + * some padding, and that we do not need to read (the length + * field in the header is enough) + * - Routing header: this one is most notably used by MIPv6, + * which we do not implement, hence we just read it and go + * to the next + * - Fragmentation header: we read this header and are able to + * reassemble packets + * + * We do not offer any means to send packets with extension headers + * + * We do not implement Authentication and ESP headers, which are + * used in IPSec and defined in RFC4302,4303,4305,4385 + */ + +/* common header part */ +struct uip_ext_hdr +{ + u8_t next; + u8_t len; +}; + +/* Hop by Hop option header */ +struct uip_hbho_hdr +{ + u8_t next; + u8_t len; +}; + +/* destination option header */ +struct uip_desto_hdr +{ + u8_t next; + u8_t len; +}; + +/* We do not define structures for PAD1 and PADN options */ + +/* + * routing header + * the routing header as 4 common bytes, then routing header type + * specific data there are several types of routing header. Type 0 was + * deprecated as per RFC5095 most notable other type is 2, used in + * RFC3775 (MIPv6) here we do not implement MIPv6, so we just need to + * parse the 4 first bytes + */ +struct uip_routing_hdr +{ + u8_t next; + u8_t len; + u8_t routing_type; + u8_t seg_left; +}; + +/* fragmentation header */ +struct uip_frag_hdr +{ + u8_t next; + u8_t res; + u16_t offsetresmore; + u32_t id; +}; + +/* + * an option within the destination or hop by hop option headers + * it contains type an length, which is true for all options but PAD1 + */ +struct uip_ext_hdr_opt +{ + u8_t type; + u8_t len; +}; + +/* PADN option */ +struct uip_ext_hdr_opt_padn +{ + u8_t opt_type; + u8_t opt_len; +}; + +/* TCP header */ +struct uip_tcp_hdr +{ + u16_t srcport; + u16_t destport; + u8_t seqno[4]; + u8_t ackno[4]; + u8_t tcpoffset; + u8_t flags; + u8_t wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +}; + +/* The ICMP headers. */ +struct uip_icmp_hdr +{ + u8_t type, icode; + u16_t icmpchksum; +#if !UIP_CONF_IPV6 + u16_t id, seqno; +#endif /* !UIP_CONF_IPV6 */ +}; + +/* The UDP headers. */ +struct uip_udp_hdr +{ + u16_t srcport; + u16_t destport; + u16_t udplen; + u16_t udpchksum; +}; + +/** + * The buffer size available for user data in the \ref uip_buf buffer. + * + * This macro holds the available size for user data in the \ref + * uip_buf buffer. The macro is intended to be used for checking + * bounds of available user data. + * + * Example: + \code + snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i); + \endcode + * + * \hideinitializer + */ +#define UIP_APPDATA_SIZE ( UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN ) +#define UIP_APPDATA_PTR ( void * ) &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN] + +#define UIP_PROTO_ICMP 1 +#define UIP_PROTO_TCP 6 +#define UIP_PROTO_UDP 17 +#define UIP_PROTO_ICMP6 58 + +#if UIP_CONF_IPV6 != 0 + +/** @{ */ + +/** \brief extension headers types */ +#define UIP_PROTO_HBHO 0 +#define UIP_PROTO_DESTO 60 +#define UIP_PROTO_ROUTING 43 +#define UIP_PROTO_FRAG 44 +#define UIP_PROTO_NONE 59 + +/** @} */ + +/** @{ */ + +/** \brief Destination and Hop By Hop extension headers option types */ +#define UIP_EXT_HDR_OPT_PAD1 0 +#define UIP_EXT_HDR_OPT_PADN 1 + +/** @} */ + +/** @{ */ + +/** + * \brief Bitmaps for extension header processing + * + * When processing extension headers, we should record somehow which one we + * see, because you cannot have twice the same header, except for destination + * We store all this in one u8_t bitmap one bit for each header expected. The + * order in the bitmap is the order recommended in RFC2460 + */ +#define UIP_EXT_HDR_BITMAP_HBHO 0x01 +#define UIP_EXT_HDR_BITMAP_DESTO1 0x02 +#define UIP_EXT_HDR_BITMAP_ROUTING 0x04 +#define UIP_EXT_HDR_BITMAP_FRAG 0x08 +#define UIP_EXT_HDR_BITMAP_AH 0x10 +#define UIP_EXT_HDR_BITMAP_ESP 0x20 +#define UIP_EXT_HDR_BITMAP_DESTO2 0x40 + +/** @} */ +#endif /* UIP_CONF_IPV6 */ + +/* Header sizes. */ +#if UIP_CONF_IPV6 != 0 +#define UIP_IPH_LEN 40 +#define UIP_FRAGH_LEN 8 +#else /* UIP_CONF_IPV6 */ +#define UIP_IPH_LEN 20 /* Size of IP header */ +#endif /* UIP_CONF_IPV6 */ + +#define UIP_UDPH_LEN 8 /* Size of UDP header */ +#define UIP_TCPH_LEN 20 /* Size of TCP header */ +#ifdef UIP_IPH_LEN +#define UIP_ICMPH_LEN 4 /* Size of ICMP header */ +#endif +#define UIP_IPUDPH_LEN ( UIP_UDPH_LEN + UIP_IPH_LEN ) /* Size of IP + + * UDP + * header */ +#define UIP_IPTCPH_LEN ( UIP_TCPH_LEN + UIP_IPH_LEN ) /* Size of IP + + * TCP + * header */ +#define UIP_TCPIP_HLEN UIP_IPTCPH_LEN +#define UIP_IPICMPH_LEN ( UIP_IPH_LEN + UIP_ICMPH_LEN ) /* size of ICMP + + IP header */ +#define UIP_LLIPH_LEN ( UIP_LLH_LEN + UIP_IPH_LEN ) /* size of L2 + + IP header */ +#if UIP_CONF_IPV6 != 0 + +/** + * The sums below are quite used in ND. When used for uip_buf, we + * include link layer length when used for uip_len, we do not, hence + * we need values with and without LLH_LEN we do not use capital + * letters as these values are variable + */ +#define uip_l2_l3_hdr_len ( UIP_LLH_LEN + UIP_IPH_LEN + uip_ext_len ) +#define uip_l2_l3_icmp_hdr_len ( UIP_LLH_LEN + UIP_IPH_LEN + uip_ext_len + UIP_ICMPH_LEN ) +#define uip_l3_hdr_len ( UIP_IPH_LEN + uip_ext_len ) +#define uip_l3_icmp_hdr_len ( UIP_IPH_LEN + uip_ext_len + UIP_ICMPH_LEN ) +#endif /*UIP_CONF_IPV6*/ + +#ifdef UIP_FIXEDADDR +CCIF extern const uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; +#else /* UIP_FIXEDADDR */ +CCIF extern uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; +#endif /* UIP_FIXEDADDR */ +CCIF extern const uip_ipaddr_t uip_broadcast_addr; +CCIF extern const uip_ipaddr_t uip_all_zeroes_addr; + +#ifdef UIP_FIXEDETHADDR +CCIF extern const uip_lladdr_t uip_lladdr; +#else +CCIF extern uip_lladdr_t uip_lladdr; +#endif +#if UIP_CONF_IPV6 != 0 + +/** + * \brief Is IPv6 address a the unspecified address + * a is of type uip_ipaddr_t + */ +#define uip_is_addr_unspecified( a ) \ + ( \ + (((a)->u16[0]) == 0) && \ + (((a)->u16[1]) == 0) && \ + (((a)->u16[2]) == 0) && \ + (((a)->u16[3]) == 0) && \ + (((a)->u16[4]) == 0) && \ + (((a)->u16[5]) == 0) && \ + (((a)->u16[6]) == 0) && \ + (((a)->u16[7]) == 0) \ + ) + +/** \brief Is IPv6 address a the link local all-nodes multicast address */ +#define uip_is_addr_linklocal_allnodes_mcast( a ) \ + ( \ + (((a)->u8[0]) == 0xff) && \ + (((a)->u8[1]) == 0x02) && \ + (((a)->u16[1]) == 0) && \ + (((a)->u16[2]) == 0) && \ + (((a)->u16[3]) == 0) && \ + (((a)->u16[4]) == 0) && \ + (((a)->u16[5]) == 0) && \ + (((a)->u16[6]) == 0) && \ + (((a)->u8[14]) == 0) && \ + (((a)->u8[15]) == 0x01) \ + ) + +/** \brief set IP address a to unspecified */ +#define uip_create_unspecified( a ) uip_ip6addr( a, 0, 0, 0, 0, 0, 0, 0, 0 ) + +/** \brief set IP address a to the link local all-nodes multicast address */ +#define uip_create_linklocal_allnodes_mcast( a ) uip_ip6addr( a, 0xff02, 0, 0, 0, 0, 0, 0, 0x0001 ) + +/** \brief set IP address a to the link local all-routers multicast address */ +#define uip_create_linklocal_allrouters_mcast( a ) uip_ip6addr( a, 0xff02, 0, 0, 0, 0, 0, 0, 0x0002 ) + +/** + * \brief is addr (a) a solicited node multicast address, see RFC3513 + * a is of type uip_ipaddr_t* + */ +#define uip_is_addr_solicited_node( a ) \ + ( \ + (((a)->u8[0]) == 0xFF) && \ + (((a)->u8[1]) == 0x02) && \ + (((a)->u16[1]) == 0) && \ + (((a)->u16[2]) == 0) && \ + (((a)->u16[3]) == 0) && \ + (((a)->u16[4]) == 0) && \ + (((a)->u16[5]) == 1) && \ + (((a)->u8[12]) == 0xFF) \ + ) + +/** + * \briefput in b the solicited node address corresponding to address a + * both a and b are of type uip_ipaddr_t* + * */ +#define uip_create_solicited_node( a, b ) \ + ( ((b)->u8[0]) = 0xFF ); \ + ( ((b)->u8[1]) = 0x02 ); \ + ( ((b)->u16[1]) = 0 ); \ + ( ((b)->u16[2]) = 0 ); \ + ( ((b)->u16[3]) = 0 ); \ + ( ((b)->u16[4]) = 0 ); \ + ( ((b)->u8[10]) = 0 ); \ + ( ((b)->u8[11]) = 0x01 ); \ + ( ((b)->u8[12]) = 0xFF ); \ + ( ((b)->u8[13]) = ((a)->u8[13]) ); \ + ( ((b)->u16[7]) = ((a)->u16[7]) ) + +/** + * \brief is addr (a) a link local unicast address, see RFC3513 + * i.e. is (a) on prefix FE80::/10 + * a is of type uip_ipaddr_t* + */ +#define uip_is_addr_link_local( a ) ( (((a)->u8[0]) == 0xFE) && (((a)->u8[1]) == 0x80) ) + +/** + * \brief was addr (a) forged based on the mac address m + * a type is uip_ipaddr_t + * m type is uiplladdr_t + */ +#ifdef UIP_CONF_LL_802154 +#define uip_is_addr_mac_addr_based( a, m ) \ + ( \ + (((a)->u8[8]) == (((m)->addr[0]) ^ 0x02)) && \ + (((a)->u8[9]) == (m)->addr[1]) && \ + (((a)->u8[10]) == (m)->addr[2]) && \ + (((a)->u8[11]) == (m)->addr[3]) && \ + (((a)->u8[12]) == (m)->addr[4]) && \ + (((a)->u8[13]) == (m)->addr[5]) && \ + (((a)->u8[14]) == (m)->addr[6]) && \ + (((a)->u8[15]) == (m)->addr[7]) \ + ) +#else +#define uip_is_addr_mac_addr_based( a, m ) \ + ( \ + (((a)->u8[8]) == (((m)->addr[0]) | 0x02)) && \ + (((a)->u8[9]) == (m)->addr[1]) && \ + (((a)->u8[10]) == (m)->addr[2]) && \ + (((a)->u8[11]) == 0xff) && \ + (((a)->u8[12]) == 0xfe) && \ + (((a)->u8[13]) == (m)->addr[3]) && \ + (((a)->u8[14]) == (m)->addr[4]) && \ + (((a)->u8[15]) == (m)->addr[5]) \ + ) +#endif /*UIP_CONF_LL_802154*/ + +/** + * \brief is address a multicast address, see RFC 3513 + * a is of type uip_ipaddr_t* + * */ +#define uip_is_addr_mcast( a ) ( ((a)->u8[0]) == 0xFF ) + +/** + * \brief is group-id of multicast address a + * the all nodes group-id + */ +#define uip_is_mcast_group_id_all_nodes( a ) \ + ( \ + (((a)->u16[1]) == 0) && \ + (((a)->u16[2]) == 0) && \ + (((a)->u16[3]) == 0) && \ + (((a)->u16[4]) == 0) && \ + (((a)->u16[5]) == 0) && \ + (((a)->u16[6]) == 0) && \ + (((a)->u8[14]) == 0) && \ + (((a)->u8[15]) == 1) \ + ) + +/** + * \brief is group-id of multicast address a + * the all routers group-id + */ +#define uip_is_mcast_group_id_all_routers( a ) \ + ( \ + (((a)->u16[1]) == 0) && \ + (((a)->u16[2]) == 0) && \ + (((a)->u16[3]) == 0) && \ + (((a)->u16[4]) == 0) && \ + (((a)->u16[5]) == 0) && \ + (((a)->u16[6]) == 0) && \ + (((a)->u8[14]) == 0) && \ + (((a)->u8[15]) == 2) \ + ) +#endif /*UIP_CONF_IPV6*/ + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum( u16_t *buf, u16_t len ); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum( void ); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum( void ); + +/** + * Calculate the UDP checksum of the packet in uip_buf and uip_appdata. + * + * The UDP checksum is the Internet checksum of data contents of the + * UDP segment, and a pseudo-header as defined in RFC768. + * + * \return The UDP checksum of the UDP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_udpchksum( void ); + +/** + * Calculate the ICMP checksum of the packet in uip_buf. + * + * \return The ICMP checksum of the ICMP packet in uip_buf + */ +u16_t uip_icmp6chksum( void ); + +/* Events that can get posted to the uIP event queue. These are events +originating from the Ethernet interface or from a timer. */ +#define uipETHERNET_RX_EVENT 0x01UL +#define uipETHERNET_TX_EVENT 0x02UL +#define uipARP_TIMER_EVENT 0x04UL +#define uipPERIODIC_TIMER_EVENT 0x08UL +#define uipAPPLICATION_SEND_EVENT 0x10UL + + +#endif /* __UIP_H__ */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arch.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arch.h new file mode 100644 index 0000000..b529a73 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arch.h @@ -0,0 +1,138 @@ +/** + * \addtogroup uip + * {@ + */ + +/** + * \defgroup uiparch Architecture specific uIP functions + * @{ + * + * The functions in the architecture specific module implement the IP + * check sum and 32-bit additions. + * + * The IP checksum calculation is the most computationally expensive + * operation in the TCP/IP stack and it therefore pays off to + * implement this in efficient assembler. The purpose of the uip-arch + * module is to let the checksum functions to be implemented in + * architecture specific assembler. + * + */ + +/** + * \file + * Declarations of architecture specific functions. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.h,v 1.1 2006/06/17 22:41:19 adamdunkels Exp $ + * + */ + +#ifndef __UIP_ARCH_H__ +#define __UIP_ARCH_H__ + +#include "net/uip.h" + +/** + * Carry out a 32-bit addition. + * + * Because not all architectures for which uIP is intended has native + * 32-bit arithmetic, uIP uses an external C function for doing the + * required 32-bit additions in the TCP protocol processing. This + * function should add the two arguments and place the result in the + * global variable uip_acc32. + * + * \note The 32-bit integer pointed to by the op32 parameter and the + * result in the uip_acc32 variable are in network byte order (big + * endian). + * + * \param op32 A pointer to a 4-byte array representing a 32-bit + * integer in network byte order (big endian). + * + * \param op16 A 16-bit integer in host byte order. + */ +void uip_add32(u8_t *op32, u16_t op16); + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \note This function is not called in the current version of uIP, + * but future versions might make use of it. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \note The uip_appdata pointer that points to the packet data may + * point anywhere in memory, so it is not possible to simply calculate + * the Internet checksum of the contents of the uip_buf buffer. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +u16_t uip_udpchksum(void); + +/** @} */ +/** @} */ + +#endif /* __UIP_ARCH_H__ */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arp.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arp.h new file mode 100644 index 0000000..e04d353 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arp.h @@ -0,0 +1,149 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \addtogroup uiparp + * @{ + */ + +/** + * \file + * Macros and definitions for the ARP module. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.h,v 1.2 2006/08/26 23:58:45 oliverschmidt Exp $ + * + */ +#ifndef __UIP_ARP_H__ +#define __UIP_ARP_H__ + +#include "net/uip.h" + +CCIF extern struct uip_eth_addr uip_ethaddr; + +/** + * The Ethernet header. + */ +#include "net/pack_struct_start.h" +struct uip_eth_hdr +{ + struct uip_eth_addr dest; + struct uip_eth_addr src; + u16_t type; +} + +#include "net/pack_struct_end.h" + +#define UIP_ETHTYPE_ARP 0x0806 +#define UIP_ETHTYPE_IP 0x0800 +#define UIP_ETHTYPE_IPV6 0x86dd + +/* The uip_arp_init() function must be called before any of the other + ARP functions. */ +void uip_arp_init( void ); + +/* The uip_arp_ipin() function should be called whenever an IP packet + arrives from the Ethernet. This function refreshes the ARP table or + inserts a new mapping if none exists. The function assumes that an + IP packet with an Ethernet header is present in the uip_buf buffer + and that the length of the packet is in the uip_len variable. */ + +/*void uip_arp_ipin(void);*/ +#define uip_arp_ipin() + +/* The uip_arp_arpin() should be called when an ARP packet is received + by the Ethernet driver. This function also assumes that the + Ethernet frame is present in the uip_buf buffer. When the + uip_arp_arpin() function returns, the contents of the uip_buf + buffer should be sent out on the Ethernet if the uip_len variable + is > 0. */ +void uip_arp_arpin( void ); + +/* The uip_arp_out() function should be called when an IP packet + should be sent out on the Ethernet. This function creates an + Ethernet header before the IP header in the uip_buf buffer. The + Ethernet header will have the correct Ethernet MAC destination + address filled in if an ARP table entry for the destination IP + address (or the IP address of the default router) is present. If no + such table entry is found, the IP packet is overwritten with an ARP + request and we rely on TCP to retransmit the packet that was + overwritten. In any case, the uip_len variable holds the length of + the Ethernet frame that should be transmitted. */ +void uip_arp_out( void ); + +/* The uip_arp_timer() function should be called every ten seconds. It + is responsible for flushing old entries in the ARP table. */ +void uip_arp_timer( void ); + +/** @} */ + +/** + * \addtogroup uipconffunc + * @{ + */ + +/** + * Specifiy the Ethernet MAC address. + * + * The ARP code needs to know the MAC address of the Ethernet card in + * order to be able to respond to ARP queries and to generate working + * Ethernet headers. + * + * \note This macro only specifies the Ethernet MAC address to the ARP + * code. It cannot be used to change the MAC address of the Ethernet + * card. + * + * \param eaddr A pointer to a struct uip_eth_addr containing the + * Ethernet MAC address of the Ethernet card. + * + * \hideinitializer + */ +#define uip_setethaddr( eaddr ) \ + do \ + { \ + uip_ethaddr.addr[0] = eaddr.addr[0]; \ + uip_ethaddr.addr[1] = eaddr.addr[1]; \ + uip_ethaddr.addr[2] = eaddr.addr[2]; \ + uip_ethaddr.addr[3] = eaddr.addr[3]; \ + uip_ethaddr.addr[4] = eaddr.addr[4]; \ + uip_ethaddr.addr[5] = eaddr.addr[5]; \ + } while( 0 ) + + /** @} */ +#endif /* __UIP_ARP_H__ */ + + /** @} */ + diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uipopt.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uipopt.h new file mode 100644 index 0000000..ddf6a24 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uipopt.h @@ -0,0 +1,695 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uipopt Configuration options for uIP + * @{ + * + * uIP is configured using the per-project configuration file + * "uipopt.h". This file contains all compile-time options for uIP and + * should be tweaked to match each specific project. The uIP + * distribution contains a documented example "uipopt.h" that can be + * copied and modified for each project. + * + * \note Contiki does not use the uipopt.h file to configure uIP, but + * uses a per-port uip-conf.h file that should be edited instead. + */ + +/** + * \file + * Configuration options for uIP. + * \author Adam Dunkels + * + * This file is used for tweaking various configuration options for + * uIP. You should make a copy of this file into one of your project's + * directories instead of editing this example "uipopt.h" file that + * comes with the uIP distribution. + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uipopt.h,v 1.11 2009/04/10 00:37:48 adamdunkels Exp $ + * + */ +#ifndef __UIPOPT_H__ +#define __UIPOPT_H__ + +#ifndef UIP_LITTLE_ENDIAN +#define UIP_LITTLE_ENDIAN 3412 +#endif /* UIP_LITTLE_ENDIAN */ +#ifndef UIP_BIG_ENDIAN +#define UIP_BIG_ENDIAN 1234 +#endif /* UIP_BIG_ENDIAN */ + +#include "uip-conf.h" +//_RB_#include "contiki-conf.h" + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptstaticconf Static configuration options + * @{ + * + * These configuration options can be used for setting the IP address + * settings statically, but only if UIP_FIXEDADDR is set to 1. The + * configuration options for a specific node includes IP address, + * netmask and default router as well as the Ethernet address. The + * netmask, default router and Ethernet address are applicable only + * if uIP should be run over Ethernet. + * + * This options are meaningful only for the IPv4 code. + * + * All of these should be changed to suit your project. + */ + +/** + * Determines if uIP should use a fixed IP address or not. + * + * If uIP should use a fixed IP address, the settings are set in the + * uipopt.h file. If not, the macros uip_sethostaddr(), + * uip_setdraddr() and uip_setnetmask() should be used instead. + * + * \hideinitializer + */ +#ifdef UIP_CONF_FIXEDADDR +#define UIP_FIXED_ADDR UIP_CONF_FIXEDADDR +#define UIP_FIXEDADDR 1 +#endif + +/** + * Ping IP address assignment. + * + * uIP uses a "ping" packets for setting its own IP address if this + * option is set. If so, uIP will start with an empty IP address and + * the destination IP address of the first incoming "ping" (ICMP echo) + * packet will be used for setting the hosts IP address. + * + * \note This works only if UIP_FIXEDADDR is 0. + * + * \hideinitializer + */ +#ifdef UIP_CONF_PINGADDRCONF +#define UIP_PINGADDRCONF UIP_CONF_PINGADDRCONF +#else /* UIP_CONF_PINGADDRCONF */ +#define UIP_PINGADDRCONF 0 +#endif /* UIP_CONF_PINGADDRCONF */ + +/** + * Specifies if the uIP ARP module should be compiled with a fixed + * Ethernet MAC address or not. + * + * If this configuration option is 0, the macro uip_setethaddr() can + * be used to specify the Ethernet address at run-time. + * + * \hideinitializer + */ +#define UIP_FIXEDETHADDR 0 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptip IP configuration options + * @{ + * + */ + +/** + * The IP TTL (time to live) of IP packets sent by uIP. + * + * This should normally not be changed. + */ +#define UIP_TTL 64 + +/** + * The maximum time an IP fragment should wait in the reassembly + * buffer before it is dropped. + * + */ +#define UIP_REASS_MAXAGE 60 /*60s*/ + +/** + * Turn on support for IP packet reassembly. + * + * uIP supports reassembly of fragmented IP packets. This features + * requires an additional amount of RAM to hold the reassembly buffer + * and the reassembly code size is approximately 700 bytes. The + * reassembly buffer is of the same size as the uip_buf buffer + * (configured by UIP_BUFSIZE). + * + * \note IP packet reassembly is not heavily tested. + * + * \hideinitializer + */ +#ifdef UIP_CONF_REASSEMBLY +#define UIP_REASSEMBLY UIP_CONF_REASSEMBLY +#else /* UIP_CONF_REASSEMBLY */ +#define UIP_REASSEMBLY 0 +#endif /* UIP_CONF_REASSEMBLY */ + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptipv6 IPv6 configuration options + * @{ + * + */ + +/** The maximum transmission unit at the IP Layer*/ +#define UIP_LINK_MTU 1280 + +#ifndef UIP_CONF_IPV6 + +/** Do we use IPv6 or not (default: no) */ +#define UIP_CONF_IPV6 0 +#endif +#ifndef UIP_CONF_IPV6_QUEUE_PKT + +/** Do we do per %neighbor queuing during address resolution (default: no) */ +#define UIP_CONF_IPV6_QUEUE_PKT 0 +#endif +#ifndef UIP_CONF_IPV6_CHECKS + +/** Do we do IPv6 consistency checks (highly recommended, default: yes) */ +#define UIP_CONF_IPV6_CHECKS 1 +#endif +#ifndef UIP_CONF_IPV6_REASSEMBLY + +/** Do we do IPv6 fragmentation (default: no) */ +#define UIP_CONF_IPV6_REASSEMBLY 0 +#endif +#ifndef UIP_CONF_NETIF_MAX_ADDRESSES + +/** Default number of IPv6 addresses associated to the node's interface */ +#define UIP_CONF_NETIF_MAX_ADDRESSES 3 +#endif +#ifndef UIP_CONF_ND6_MAX_PREFIXES + +/** Default number of IPv6 prefixes associated to the node's interface */ +#define UIP_CONF_ND6_MAX_PREFIXES 3 +#endif +#ifndef UIP_CONF_ND6_MAX_NEIGHBORS + +/** Default number of neighbors that can be stored in the %neighbor cache */ +#define UIP_CONF_ND6_MAX_NEIGHBORS 4 +#endif +#ifndef UIP_CONF_ND6_MAX_DEFROUTERS + +/** Minimum number of default routers */ +#define UIP_CONF_ND6_MAX_DEFROUTERS 2 +#endif + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptudp UDP configuration options + * @{ + * + * \note The UDP support in uIP is still not entirely complete; there + * is no support for sending or receiving broadcast or multicast + * packets, but it works well enough to support a number of vital + * applications such as DNS queries, though + */ + +/** + * Toggles whether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP +#define UIP_UDP UIP_CONF_UDP +#else /* UIP_CONF_UDP */ +#define UIP_UDP 0 +#endif /* UIP_CONF_UDP */ + +/** + * Toggles if UDP checksums should be used or not. + * + * \note Support for UDP checksums is currently not included in uIP, + * so this option has no function. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP_CHECKSUMS +#define UIP_UDP_CHECKSUMS UIP_CONF_UDP_CHECKSUMS +#else +#define UIP_UDP_CHECKSUMS 0 +#endif + +/** + * The maximum amount of concurrent UDP connections. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP_CONNS +#define UIP_UDP_CONNS UIP_CONF_UDP_CONNS +#else /* UIP_CONF_UDP_CONNS */ +#define UIP_UDP_CONNS 10 +#endif /* UIP_CONF_UDP_CONNS */ + +/** + * The name of the function that should be called when UDP datagrams arrive. + * + * \hideinitializer + */ + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipopttcp TCP configuration options + * @{ + */ + +/** + * Toggles whether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#ifdef UIP_CONF_TCP +#define UIP_TCP UIP_CONF_TCP +#else /* UIP_CONF_UDP */ +#define UIP_TCP 1 +#endif /* UIP_CONF_UDP */ + +/** + * Determines if support for opening connections from uIP should be + * compiled in. + * + * If the applications that are running on top of uIP for this project + * do not need to open outgoing TCP connections, this configuration + * option can be turned off to reduce the code size of uIP. + * + * \hideinitializer + */ +#ifndef UIP_CONF_ACTIVE_OPEN +#define UIP_ACTIVE_OPEN 1 +#else /* UIP_CONF_ACTIVE_OPEN */ +#define UIP_ACTIVE_OPEN UIP_CONF_ACTIVE_OPEN +#endif /* UIP_CONF_ACTIVE_OPEN */ + +/** + * The maximum number of simultaneously open TCP connections. + * + * Since the TCP connections are statically allocated, turning this + * configuration knob down results in less RAM used. Each TCP + * connection requires approximately 30 bytes of memory. + * + * \hideinitializer + */ +#ifndef UIP_CONF_MAX_CONNECTIONS +#define UIP_CONNS 10 +#else /* UIP_CONF_MAX_CONNECTIONS */ +#define UIP_CONNS UIP_CONF_MAX_CONNECTIONS +#endif /* UIP_CONF_MAX_CONNECTIONS */ + +/** + * The maximum number of simultaneously listening TCP ports. + * + * Each listening TCP port requires 2 bytes of memory. + * + * \hideinitializer + */ +#ifndef UIP_CONF_MAX_LISTENPORTS +#define UIP_LISTENPORTS 20 +#else /* UIP_CONF_MAX_LISTENPORTS */ +#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS +#endif /* UIP_CONF_MAX_LISTENPORTS */ + +/** + * Determines if support for TCP urgent data notification should be + * compiled in. + * + * Urgent data (out-of-band data) is a rarely used TCP feature that + * very seldom would be required. + * + * \hideinitializer + */ +#define UIP_URGDATA 0 + +/** + * The initial retransmission timeout counted in timer pulses. + * + * This should not be changed. + */ +#define UIP_RTO 3 + +/** + * The maximum number of times a segment should be retransmitted + * before the connection should be aborted. + * + * This should not be changed. + */ +#define UIP_MAXRTX 8 + +/** + * The maximum number of times a SYN segment should be retransmitted + * before a connection request should be deemed to have been + * unsuccessful. + * + * This should not need to be changed. + */ +#define UIP_MAXSYNRTX 5 + +/** + * The TCP maximum segment size. + * + * This is should not be to set to more than + * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN. + */ +#ifdef UIP_CONF_TCP_MSS +#define UIP_TCP_MSS UIP_CONF_TCP_MSS +#else +#define UIP_TCP_MSS ( UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN ) +#endif + +/** + * The size of the advertised receiver's window. + * + * Should be set low (i.e., to the size of the uip_buf buffer) if the + * application is slow to process incoming data, or high (32768 bytes) + * if the application processes data quickly. + * + * \hideinitializer + */ +#ifndef UIP_CONF_RECEIVE_WINDOW +#define UIP_RECEIVE_WINDOW UIP_TCP_MSS +#else +#define UIP_RECEIVE_WINDOW UIP_CONF_RECEIVE_WINDOW +#endif + +/** + * How long a connection should stay in the TIME_WAIT state. + * + * This configuration option has no real implication, and it should be + * left untouched. + */ +#define UIP_TIME_WAIT_TIMEOUT 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptarp ARP configuration options + * @{ + */ + +/** + * The size of the ARP table. + * + * This option should be set to a larger value if this uIP node will + * have many connections from the local network. + * + * \hideinitializer + */ +#ifdef UIP_CONF_ARPTAB_SIZE +#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE +#else +#define UIP_ARPTAB_SIZE 8 +#endif + +/** + * The maximum age of ARP table entries measured in 10ths of seconds. + * + * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD + * default). + */ +#define UIP_ARP_MAXAGE 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptmac layer 2 options (for ipv6) + * @{ + */ +#define UIP_DEFAULT_PREFIX_LEN 64 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptsics 6lowpan options (for ipv6) + * @{ + */ + +/** + * Timeout for packet reassembly at the 6lowpan layer + * (should be < 60s) + */ +#ifdef SICSLOWPAN_CONF_MAXAGE +#define SICSLOWPAN_REASS_MAXAGE SICSLOWPAN_CONF_MAXAGE +#else +#define SICSLOWPAN_REASS_MAXAGE 20 +#endif + +/** + * Do we compress the IP header or not (default: no) + */ +#ifndef SICSLOWPAN_CONF_COMPRESSION +#define SICSLOWPAN_CONF_COMPRESSION 0 +#endif + +/** + * If we use IPHC compression, how many address contexts do we support + */ +#ifndef SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS +#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS 1 +#endif + +/** + * Do we support 6lowpan fragmentation + */ +#ifndef SICSLOWPAN_CONF_FRAG +#define SICSLOWPAN_CONF_FRAG 0 +#endif + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptgeneral General configuration options + * @{ + */ + +/** + * The size of the uIP packet buffer. + * + * The uIP packet buffer should not be smaller than 60 bytes, and does + * not need to be larger than 1514 bytes. Lower size results in lower + * TCP throughput, larger size results in higher TCP throughput. + * + * \hideinitializer + */ +#ifndef UIP_CONF_BUFFER_SIZE +#define UIP_BUFSIZE UIP_LINK_MTU + UIP_LLH_LEN +#else /* UIP_CONF_BUFFER_SIZE */ +#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE +#endif /* UIP_CONF_BUFFER_SIZE */ + +/** + * Determines if statistics support should be compiled in. + * + * The statistics is useful for debugging and to show the user. + * + * \hideinitializer + */ +#ifndef UIP_CONF_STATISTICS +#define UIP_STATISTICS 0 +#else /* UIP_CONF_STATISTICS */ +#define UIP_STATISTICS UIP_CONF_STATISTICS +#endif /* UIP_CONF_STATISTICS */ + +/** + * Determines if logging of certain events should be compiled in. + * + * This is useful mostly for debugging. The function uip_log() + * must be implemented to suit the architecture of the project, if + * logging is turned on. + * + * \hideinitializer + */ +#ifndef UIP_CONF_LOGGING +#define UIP_LOGGING 0 +#else /* UIP_CONF_LOGGING */ +#define UIP_LOGGING UIP_CONF_LOGGING +#endif /* UIP_CONF_LOGGING */ + +/** + * Broadcast support. + * + * This flag configures IP broadcast support. This is useful only + * together with UDP. + * + * \hideinitializer + * + */ +#ifndef UIP_CONF_BROADCAST +#define UIP_BROADCAST 0 +#else /* UIP_CONF_BROADCAST */ +#define UIP_BROADCAST UIP_CONF_BROADCAST +#endif /* UIP_CONF_BROADCAST */ + +/** + * Print out a uIP log message. + * + * This function must be implemented by the module that uses uIP, and + * is called by uIP whenever a log message is generated. + */ +void uip_log( char *msg ); + +/** + * The link level header length. + * + * This is the offset into the uip_buf where the IP header can be + * found. For Ethernet, this should be set to 14. For SLIP, this + * should be set to 0. + * + * \note we probably won't use this constant for other link layers than + * ethernet as they have variable header length (this is due to variable + * number and type of address fields and to optional security features) + * E.g.: 802.15.4 -> 2 + (1/2*4/8) + 0/5/6/10/14 + * 802.11 -> 4 + (6*3/4) + 2 + * \hideinitializer + */ +#ifdef UIP_CONF_LLH_LEN +#define UIP_LLH_LEN UIP_CONF_LLH_LEN +#else /* UIP_LLH_LEN */ +#define UIP_LLH_LEN 14 +#endif /* UIP_CONF_LLH_LEN */ + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptcpu CPU architecture configuration + * @{ + * + * The CPU architecture configuration is where the endianess of the + * CPU on which uIP is to be run is specified. Most CPUs today are + * little endian, and the most notable exception are the Motorolas + * which are big endian. The BYTE_ORDER macro should be changed to + * reflect the CPU architecture on which uIP is to be run. + */ + +/** + * The byte order of the CPU architecture on which uIP is to be run. + * + * This option can be either UIP_BIG_ENDIAN (Motorola byte order) or + * UIP_LITTLE_ENDIAN (Intel byte order). + * + * \hideinitializer + */ +#ifdef UIP_CONF_BYTE_ORDER +#define UIP_BYTE_ORDER UIP_CONF_BYTE_ORDER +#else /* UIP_CONF_BYTE_ORDER */ +#define UIP_BYTE_ORDER UIP_LITTLE_ENDIAN +#endif /* UIP_CONF_BYTE_ORDER */ + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptapp Application specific configurations + * @{ + * + * An uIP application is implemented using a single application + * function that is called by uIP whenever a TCP/IP event occurs. The + * name of this function must be registered with uIP at compile time + * using the UIP_APPCALL definition. + * + * uIP applications can store the application state within the + * uip_conn structure by specifying the type of the application + * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t. + * + * The file containing the definitions must be included in the + * uipopt.h file. + * + * The following example illustrates how this can look. + \code + + void httpd_appcall(void); + #define UIP_APPCALL httpd_appcall + + struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; + }; + typedef struct httpd_state uip_tcp_appstate_t + \endcode +*/ + +/** + * \var #define UIP_APPCALL + * + * The name of the application function that uIP should call in + * response to TCP/IP events. + * + */ + +/** + * \var typedef uip_tcp_appstate_t + * + * The type of the application state that is to be stored in the + * uip_conn structure. This usually is typedef:ed to a struct holding + * application state information. + */ + +/** + * \var typedef uip_udp_appstate_t + * + * The type of the application state that is to be stored in the + * uip_conn structure. This usually is typedef:ed to a struct holding + * application state information. + */ + +/** @} */ +#endif /* __UIPOPT_H__ */ + +/** @} */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/psock.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/psock.c new file mode 100644 index 0000000..1f224b6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/psock.c @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: psock.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +#include +#include + +#include "net/uipopt.h" +#include "net/psock.h" +#include "net/uip.h" + +#define STATE_NONE 0 +#define STATE_ACKED 1 +#define STATE_READ 2 +#define STATE_BLOCKED_NEWDATA 3 +#define STATE_BLOCKED_CLOSE 4 +#define STATE_BLOCKED_SEND 5 +#define STATE_DATA_SENT 6 + +/* + * Return value of the buffering functions that indicates that a + * buffer was not filled by incoming data. + * + */ +#define BUF_NOT_FULL 0 +#define BUF_NOT_FOUND 0 + +/* + * Return value of the buffering functions that indicates that a + * buffer was completely filled by incoming data. + * + */ +#define BUF_FULL 1 + +/* + * Return value of the buffering functions that indicates that an + * end-marker byte was found. + * + */ +#define BUF_FOUND 2 + +/*---------------------------------------------------------------------------*/ +static void +buf_setup(struct psock_buf *buf, + u8_t *bufptr, u16_t bufsize) +{ + buf->ptr = bufptr; + buf->left = bufsize; +} +/*---------------------------------------------------------------------------*/ +static u8_t +buf_bufdata(struct psock_buf *buf, u16_t len, + u8_t **dataptr, u16_t *datalen) +{ + ( void ) len; + if(*datalen < buf->left) { + memcpy(buf->ptr, *dataptr, *datalen); + buf->ptr += *datalen; + buf->left -= *datalen; + *dataptr += *datalen; + *datalen = 0; + return BUF_NOT_FULL; + } else if(*datalen == buf->left) { + memcpy(buf->ptr, *dataptr, *datalen); + buf->ptr += *datalen; + buf->left = 0; + *dataptr += *datalen; + *datalen = 0; + return BUF_FULL; + } else { + memcpy(buf->ptr, *dataptr, buf->left); + buf->ptr += buf->left; + *datalen -= buf->left; + *dataptr += buf->left; + buf->left = 0; + return BUF_FULL; + } +} +/*---------------------------------------------------------------------------*/ +static u8_t +buf_bufto(register struct psock_buf *buf, u8_t endmarker, + register u8_t **dataptr, register u16_t *datalen) +{ + u8_t c; + while(buf->left > 0 && *datalen > 0) { + c = *buf->ptr = **dataptr; + ++*dataptr; + ++buf->ptr; + --*datalen; + --buf->left; + + if(c == endmarker) { + return BUF_FOUND; + } + } + + if(*datalen == 0) { + return BUF_NOT_FOUND; + } + + while(*datalen > 0) { + c = **dataptr; + --*datalen; + ++*dataptr; + + if(c == endmarker) { + return BUF_FOUND | BUF_FULL; + } + } + + return BUF_FULL; +} +/*---------------------------------------------------------------------------*/ +static char +send_data(register struct psock *s) +{ + if(s->state != STATE_DATA_SENT || uip_rexmit()) { + if(s->sendlen > uip_mss()) { + uip_send(s->sendptr, uip_mss()); + } else { + uip_send(s->sendptr, s->sendlen); + } + s->state = STATE_DATA_SENT; + return 1; + } + return 0; +} +/*---------------------------------------------------------------------------*/ +static char +data_acked(register struct psock *s) +{ + if(s->state == STATE_DATA_SENT && uip_acked()) { + if(s->sendlen > uip_mss()) { + s->sendlen -= uip_mss(); + s->sendptr += uip_mss(); + } else { + s->sendptr += s->sendlen; + s->sendlen = 0; + } + s->state = STATE_ACKED; + return 1; + } + return 0; +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_send(register struct psock *s, const char *buf, + unsigned int len)) +{ + PT_BEGIN(&s->psockpt); + ( void ) PT_YIELD_FLAG; + /* If there is no data to send, we exit immediately. */ + if(len == 0) { + PT_EXIT(&s->psockpt); + } + + /* Save the length of and a pointer to the data that is to be + sent. */ + s->sendptr = (unsigned char*)buf; + s->sendlen = (unsigned short)len; + + s->state = STATE_NONE; + + /* We loop here until all data is sent. The s->sendlen variable is + updated by the data_sent() function. */ + while(s->sendlen > 0) { + + /* + * The condition for this PT_WAIT_UNTIL is a little tricky: the + * protothread will wait here until all data has been acknowledged + * (data_acked() returns true) and until all data has been sent + * (send_data() returns true). The two functions data_acked() and + * send_data() must be called in succession to ensure that all + * data is sent. Therefore the & operator is used instead of the + * && operator, which would cause only the data_acked() function + * to be called when it returns false. + */ + PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s)); + } + + s->state = STATE_NONE; + + PT_END(&s->psockpt); +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_generator_send(register struct psock *s, + unsigned short (*generate)(void *), void *arg)) +{ + PT_BEGIN(&s->psockpt); + ( void ) PT_YIELD_FLAG; + /* Ensure that there is a generator function to call. */ + if(generate == NULL) { + PT_EXIT(&s->psockpt); + } + + /* Call the generator function to generate the data in the + uip_appdata buffer. */ + s->sendlen = generate(arg); + s->sendptr = uip_appdata; + + s->state = STATE_NONE; + do { + /* Call the generator function again if we are called to perform a + retransmission. */ + if(uip_rexmit()) { + generate(arg); + } + /* Wait until all data is sent and acknowledged. */ + PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s)); + } while(s->sendlen > 0); + + s->state = STATE_NONE; + + PT_END(&s->psockpt); +} +/*---------------------------------------------------------------------------*/ +u16_t +psock_datalen(struct psock *psock) +{ + return psock->bufsize - psock->buf.left; +} +/*---------------------------------------------------------------------------*/ +char +psock_newdata(struct psock *s) +{ + if(s->readlen > 0) { + /* There is data in the uip_appdata buffer that has not yet been + read with the PSOCK_READ functions. */ + return 1; + } else if(s->state == STATE_READ) { + /* All data in uip_appdata buffer already consumed. */ + s->state = STATE_BLOCKED_NEWDATA; + return 0; + } else if(uip_newdata()) { + /* There is new data that has not been consumed. */ + return 1; + } else { + /* There is no new data. */ + return 0; + } +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_readto(register struct psock *psock, unsigned char c)) +{ + PT_BEGIN(&psock->psockpt); + ( void ) PT_YIELD_FLAG; + buf_setup(&psock->buf, (unsigned char*)psock->bufptr, psock->bufsize); + + /* XXX: Should add buf_checkmarker() before do{} loop, if + incoming data has been handled while waiting for a write. */ + + do { + if(psock->readlen == 0) { + PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock)); + psock->state = STATE_READ; + psock->readptr = (u8_t *)uip_appdata; + psock->readlen = uip_datalen(); + } + } while((buf_bufto(&psock->buf, c, + &psock->readptr, + &psock->readlen) & BUF_FOUND) == 0); + + if(psock_datalen(psock) == 0) { + psock->state = STATE_NONE; + PT_RESTART(&psock->psockpt); + } + PT_END(&psock->psockpt); +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_readbuf(register struct psock *psock)) +{ + PT_BEGIN(&psock->psockpt); + ( void ) PT_YIELD_FLAG; + buf_setup(&psock->buf, (unsigned char * ) psock->bufptr, psock->bufsize); + + /* XXX: Should add buf_checkmarker() before do{} loop, if + incoming data has been handled while waiting for a write. */ + + do { + if(psock->readlen == 0) { + PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock)); + psock->state = STATE_READ; + psock->readptr = (u8_t *)uip_appdata; + psock->readlen = uip_datalen(); + } + } while(buf_bufdata(&psock->buf, psock->bufsize, + &psock->readptr, + &psock->readlen) != BUF_FULL); + + if(psock_datalen(psock) == 0) { + psock->state = STATE_NONE; + PT_RESTART(&psock->psockpt); + } + PT_END(&psock->psockpt); +} +/*---------------------------------------------------------------------------*/ +void +psock_init(register struct psock *psock, char *buffer, unsigned int buffersize) +{ + psock->state = STATE_NONE; + psock->readlen = 0; + psock->bufptr = buffer; + psock->bufsize = buffersize; + buf_setup(&psock->buf, (unsigned char*) buffer, buffersize); + PT_INIT(&psock->pt); + PT_INIT(&psock->psockpt); +} +/*---------------------------------------------------------------------------*/ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/clock.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/clock.h new file mode 100644 index 0000000..9f93583 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/clock.h @@ -0,0 +1,115 @@ +/** \addtogroup sys + * @{ + */ + +/** + * \defgroup clock Clock library + * + * The clock library is the interface between Contiki and the platform + * specific clock functionality. The clock library performs a single + * function: measuring time. Additionally, the clock library provides + * a macro, CLOCK_SECOND, which corresponds to one second of system + * time. + * + * \note The clock library need in many cases not be used + * directly. Rather, the \ref timer "timer library" or the \ref etimer + * "event timers" should be used. + * + * \sa \ref timer "Timer library" + * \sa \ref etimer "Event timers" + * + * @{ + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: clock.h,v 1.11 2009/01/24 15:20:11 adamdunkels Exp $ + */ +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +#include "net/clock-arch.h" + +//_RB_#include "contiki-conf.h" +#if 0 /* XXX problems with signedness and use in timer_expired(). #if:ed it out for now. */ + +/** + * Check if a clock time value is less than another clock time value. + * + * This macro checks if a clock time value is less than another clock + * time value. This macro is needed to correctly handle wrap-around of + * clock time values. + * + */ +#define CLOCK_LT( a, b ) ( (clock_time_t) ((a) - (b)) < ((clock_time_t) (~((clock_time_t) 0)) >> 1) ) +#endif /* 0 */ + +/** + * Initialize the clock library. + * + * This function initializes the clock library and should be called + * from the main() function of the system. + * + */ +void clock_init( void ); + +/** + * Get the current clock time. + * + * This function returns the current system clock time. + * + * \return The current clock time, measured in system ticks. + */ +CCIF clock_time_t clock_time( void ); + +void clock_delay( unsigned int ); + +/** + * A second, measured in system clock time. + * + * \hideinitializer + */ +#ifdef CLOCK_CONF_SECOND +#define CLOCK_SECOND CLOCK_CONF_SECOND +#else +#define CLOCK_SECOND ( clock_time_t ) 32 +#endif +int clock_fine_max( void ); +unsigned short clock_fine( void ); + +CCIF unsigned long clock_seconds( void ); +#endif /* __CLOCK_H__ */ + +/** @} */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/pt.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/pt.h new file mode 100644 index 0000000..b0b9408 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/pt.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: pt.h,v 1.3 2008/10/14 12:46:39 nvt-se Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \file + * Protothreads implementation. + * \author + * Adam Dunkels + * + */ +#ifndef __PT_H__ +#define __PT_H__ + +#include "sys/lc.h" + +struct pt +{ + lc_t lc; +}; + +#define PT_WAITING 0 +#define PT_YIELDED 1 +#define PT_EXITED 2 +#define PT_ENDED 3 + +/** + * \name Initialization + * @{ + */ + +/** + * Initialize a protothread. + * + * Initializes a protothread. Initialization must be done prior to + * starting to execute the protothread. + * + * \param pt A pointer to the protothread control structure. + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_INIT( pt ) LC_INIT( (pt)->lc ) + +/** @} */ + +/** + * \name Declaration and definition + * @{ + */ + +/** + * Declaration of a protothread. + * + * This macro is used to declare a protothread. All protothreads must + * be declared with this macro. + * + * \param name_args The name and arguments of the C function + * implementing the protothread. + * + * \hideinitializer + */ +#define PT_THREAD( name_args ) char name_args + +/** + * Declare the start of a protothread inside the C function + * implementing the protothread. + * + * This macro is used to declare the starting point of a + * protothread. It should be placed at the start of the function in + * which the protothread runs. All C statements above the PT_BEGIN() + * invokation will be executed each time the protothread is scheduled. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_BEGIN( pt ) \ + { \ + char PT_YIELD_FLAG = 1; \ + LC_RESUME( (pt)->lc ) + +/** + * Declare the end of a protothread. + * + * This macro is used for declaring that a protothread ends. It must + * always be used together with a matching PT_BEGIN() macro. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_END( pt ) \ + LC_END( (pt)->lc ); \ + PT_YIELD_FLAG = 0; \ + PT_INIT( pt ); \ + return PT_ENDED; \ +} + +/** @} */ + +/** + * \name Blocked wait + * @{ + */ + +/** + * Block and wait until condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. + * + * \param pt A pointer to the protothread control structure. + * \param condition The condition. + * + * \hideinitializer + */ +#define PT_WAIT_UNTIL( pt, condition ) \ + do \ + { \ + LC_SET( (pt)->lc ); \ + if( !(condition) ) \ + { \ + return PT_WAITING; \ + } \ + } while( 0 ) + +/** + * Block and wait while condition is true. + * + * This function blocks and waits while condition is true. See + * PT_WAIT_UNTIL(). + * + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * \hideinitializer + */ +#define PT_WAIT_WHILE( pt, cond ) PT_WAIT_UNTIL( (pt), !(cond) ) + /** @} */ + + /** + * \name Hierarchical protothreads + * @{ + */ + +/** + * Block and wait until a child protothread completes. + * + * This macro schedules a child protothread. The current protothread + * will block until the child protothread completes. + * + * \note The child protothread must be manually initialized with the + * PT_INIT() function before this function is used. + * + * \param pt A pointer to the protothread control structure. + * \param thread The child protothread with arguments + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_WAIT_THREAD( pt, thread ) PT_WAIT_WHILE( (pt), PT_SCHEDULE(thread) ) + +/** + * Spawn a child protothread and wait until it exits. + * + * This macro spawns a child protothread and waits until it exits. The + * macro can only be used within a protothread. + * + * \param pt A pointer to the protothread control structure. + * \param child A pointer to the child protothread's control structure. + * \param thread The child protothread with arguments + * + * \hideinitializer + */ +#define PT_SPAWN( pt, child, thread ) \ + do \ + { \ + PT_INIT( (child) ); \ + PT_WAIT_THREAD( (pt), (thread) ); \ + } while( 0 ) + + /** @} */ + + /** + * \name Exiting and restarting + * @{ + */ + +/** + * Restart the protothread. + * + * This macro will block and cause the running protothread to restart + * its execution at the place of the PT_BEGIN() call. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_RESTART( pt ) \ + do \ + { \ + PT_INIT( pt ); \ + return PT_WAITING; \ + } while( 0 ) + +/** + * Exit the protothread. + * + * This macro causes the protothread to exit. If the protothread was + * spawned by another protothread, the parent protothread will become + * unblocked and can continue to run. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_EXIT( pt ) \ + do \ + { \ + PT_INIT( pt ); \ + return PT_EXITED; \ + } while( 0 ) + /** @} */ + + /** + * \name Calling a protothread + * @{ + */ + +/** + * Schedule a protothread. + * + * This function schedules a protothread. The return value of the + * function is non-zero if the protothread is running or zero if the + * protothread has exited. + * + * \param f The call to the C function implementing the protothread to + * be scheduled + * + * \hideinitializer + */ +#define PT_SCHEDULE( f ) ( (f) < PT_EXITED ) + /** @} */ + + /** + * \name Yielding from a protothread + * @{ + */ + +/** + * Yield from the current protothread. + * + * This function will yield the protothread, thereby allowing other + * processing to take place in the system. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_YIELD( pt ) \ + do \ + { \ + PT_YIELD_FLAG = 0; \ + LC_SET( (pt)->lc ); \ + if( PT_YIELD_FLAG == 0 ) \ + { \ + return PT_YIELDED; \ + } \ + } while( 0 ) + +/** + * \brief Yield from the protothread until a condition occurs. + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * This function will yield the protothread, until the + * specified condition evaluates to true. + * + * + * \hideinitializer + */ +#define PT_YIELD_UNTIL( pt, cond ) \ + do \ + { \ + PT_YIELD_FLAG = 0; \ + LC_SET( (pt)->lc ); \ + if( (PT_YIELD_FLAG == 0) || !(cond) ) \ + { \ + return PT_YIELDED; \ + } \ + } while( 0 ) + /** @} */ +#endif /* __PT_H__ */ + + /** @} */ + \ No newline at end of file diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/timer.h b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/timer.h new file mode 100644 index 0000000..1d87e7e --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/timer.h @@ -0,0 +1,101 @@ +/** \addtogroup sys + * @{ */ + +/** + * \defgroup timer Timer library + * + * The Contiki kernel does not provide support for timed + * events. Rather, an application that wants to use timers needs to + * explicitly use the timer library. + * + * The timer library provides functions for setting, resetting and + * restarting timers, and for checking if a timer has expired. An + * application must "manually" check if its timers have expired; this + * is not done automatically. + * + * A timer is declared as a \c struct \c timer and all access to the + * timer is made by a pointer to the declared timer. + * + * \note The timer library is not able to post events when a timer + * expires. The \ref etimer "Event timers" should be used for this + * purpose. + * + * \note The timer library uses the \ref clock "Clock library" to + * measure time. Intervals should be specified in the format used by + * the clock library. + * + * \sa \ref etimer "Event timers" + * + * @{ + */ + +/** + * \file + * Timer library header file. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: timer.h,v 1.2 2008/09/21 08:58:05 adamdunkels Exp $ + */ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "sys/clock.h" + +/** + * A timer. + * + * This structure is used for declaring a timer. The timer must be set + * with timer_set() before it can be used. + * + * \hideinitializer + */ +struct timer +{ + clock_time_t start; + clock_time_t interval; +}; + +void timer_set( struct timer *t, clock_time_t interval ); +void timer_reset( struct timer *t ); +void timer_restart( struct timer *t ); +int timer_expired( struct timer *t ); +clock_time_t timer_remaining( struct timer *t ); +#endif /* __TIMER_H__ */ + +/** @} */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/timer.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/timer.c new file mode 100644 index 0000000..e520391 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/timer.c @@ -0,0 +1,151 @@ +/** + * \addtogroup timer + * @{ + */ + +/** + * \file + * Timer library implementation. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: timer.c,v 1.5 2009/01/24 15:20:11 adamdunkels Exp $ + */ + +//_RB_#include "contiki-conf.h" +#include "uip-conf.h" +#include "net/clock-arch.h" +#include "sys/clock.h" +#include "sys/timer.h" + +/*---------------------------------------------------------------------------*/ + +/** + * Set a timer. + * + * This function is used to set a timer for a time sometime in the + * future. The function timer_expired() will evaluate to true after + * the timer has expired. + * + * \param t A pointer to the timer + * \param interval The interval before the timer expires. + * + */ +void timer_set( struct timer *t, clock_time_t interval ) +{ + t->interval = interval; + t->start = clock_time(); +} + +/*---------------------------------------------------------------------------*/ + +/** + * Reset the timer with the same interval. + * + * This function resets the timer with the same interval that was + * given to the timer_set() function. The start point of the interval + * is the exact time that the timer last expired. Therefore, this + * function will cause the timer to be stable over time, unlike the + * timer_restart() function. + * + * \param t A pointer to the timer. + * + * \sa timer_restart() + */ +void timer_reset( struct timer *t ) +{ + t->start += t->interval; +} + +/*---------------------------------------------------------------------------*/ + +/** + * Restart the timer from the current point in time + * + * This function restarts a timer with the same interval that was + * given to the timer_set() function. The timer will start at the + * current time. + * + * \note A periodic timer will drift if this function is used to reset + * it. For preioric timers, use the timer_reset() function instead. + * + * \param t A pointer to the timer. + * + * \sa timer_reset() + */ +void timer_restart( struct timer *t ) +{ + t->start = clock_time(); +} + +/*---------------------------------------------------------------------------*/ + +/** + * Check if a timer has expired. + * + * This function tests if a timer has expired and returns true or + * false depending on its status. + * + * \param t A pointer to the timer + * + * \return Non-zero if the timer has expired, zero otherwise. + * + */ +int timer_expired( struct timer *t ) +{ + return( clock_time_t ) ( clock_time() - t->start ) >= ( clock_time_t ) t->interval; +} + +/*---------------------------------------------------------------------------*/ + +/** + * The time until the timer expires + * + * This function returns the time until the timer expires. + * + * \param t A pointer to the timer + * + * \return The time until the timer expires + * + */ +clock_time_t timer_remaining( struct timer *t ) +{ + return t->start + t->interval - clock_time(); +} + +/*---------------------------------------------------------------------------*/ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip.c new file mode 100644 index 0000000..78c6713 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip.c @@ -0,0 +1,2143 @@ +//#define DEBUG_PRINTF( ... ) /*printf(__VA_ARGS__)*/ + +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * The uIP TCP/IP stack code. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.c,v 1.15 2008/10/15 08:08:32 adamdunkels Exp $ + * + */ + +/* + * uIP is a small implementation of the IP, UDP and TCP protocols (as + * well as some basic ICMP stuff). The implementation couples the IP, + * UDP, TCP and the application layers very tightly. To keep the size + * of the compiled code down, this code frequently uses the goto + * statement. While it would be possible to break the uip_process() + * function into many smaller functions, this would increase the code + * size because of the overhead of parameter passing and the fact that + * the optimier would not be as efficient. + * + * The principle is that we have a small buffer, called the uip_buf, + * in which the device driver puts an incoming packet. The TCP/IP + * stack parses the headers in the packet, and calls the + * application. If the remote host has sent data to the application, + * this data is present in the uip_buf and the application read the + * data from there. It is up to the application to put this data into + * a byte stream if needed. The application will not be fed with data + * that is out of sequence. + * + * If the application whishes to send data to the peer, it should put + * its data into the uip_buf. The uip_appdata pointer points to the + * first available byte. The TCP/IP stack will calculate the + * checksums, and fill in the necessary header fields and finally send + * the packet back to the peer. +*/ +#include "net/uip.h" +#include "net/uipopt.h" +#include "net/uip_arp.h" +#include "net/uip_arch.h" + +/* If UIP_CONF_IPV6 is defined, we compile the uip6.c file instead of this one. +Therefore this #ifndef removes the entire compilation output of the uip.c file */ +#if !UIP_CONF_IPV6 + +#if UIP_CONF_IPV6 + #include "net/uip-neighbor.h" +#endif /* UIP_CONF_IPV6 */ + +#include + +/*---------------------------------------------------------------------------*/ + +/* Variable definitions. */ + +/* The IP address of this host. If it is defined to be fixed (by setting +UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ +#if UIP_FIXEDADDR > 0 + const uip_ipaddr_t uip_hostaddr = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 }; + const uip_ipaddr_t uip_draddr = { UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3 }; + const uip_ipaddr_t uip_netmask = { UIP_NETMASK0, UIP_NETMASK1, UIP_NETMASK2, UIP_NETMASK3 }; +#else + uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask; +#endif /* UIP_FIXEDADDR */ + +const uip_ipaddr_t uip_broadcast_addr = +#if UIP_CONF_IPV6 + { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; +#else /* UIP_CONF_IPV6 */ + { { 0xff, 0xff, 0xff, 0xff } }; +#endif /* UIP_CONF_IPV6 */ + +const uip_ipaddr_t uip_all_zeroes_addr = { { 0x0, /* rest is 0 */ } }; + +#if UIP_FIXEDETHADDR + const struct uip_eth_addr uip_ethaddr = { { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 } }; +#else + struct uip_eth_addr uip_ethaddr = { { 0, 0, 0, 0, 0, 0 } }; +#endif + +#ifndef UIP_CONF_EXTERNAL_BUFFER + /* The packet buffer that contains incoming packets. */ + u8_t uip_buf[ UIP_BUFSIZE + 2 ]; +#endif /* UIP_CONF_EXTERNAL_BUFFER */ + +/* The uip_appdata pointer points to application data. */ +void *uip_appdata; + +/* The uip_appdata pointer points to the application data which is to be sent. */ +void *uip_sappdata; + +#if UIP_URGDATA > 0 + /* The uip_urgdata pointer points to urgent data (out-of-band data), if + present. */ + void *uip_urgdata; + u16_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +/* The uip_len is either 8 or 16 bits, depending on the maximum packet size. */ +u16_t uip_len, uip_slen; + +/* The uip_flags variable is used for communication between the TCP/IP stack +and the application program. */ +u8_t uip_flags; + +/* uip_conn always points to the current connection. */ +struct uip_conn *uip_conn; +struct uip_conn uip_conns[ UIP_CONNS ]; + +/* The uip_conns array holds all TCP connections. */ +u16_t uip_listenports[UIP_LISTENPORTS]; + +/* The uip_listenports list all currently listning ports. */ +#if UIP_UDP + struct uip_udp_conn *uip_udp_conn; + struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +/* Ths ipid variable is an increasing number that is used for the IP ID field. */ +static u16_t ipid; + +void uip_setipid( u16_t id ) +{ + ipid = id; +} + +/* The iss variable is used for the TCP initial sequence number. */ +static u8_t iss[ 4 ]; + +#if UIP_ACTIVE_OPEN + /* Keeps track of the last port used for a new connection. */ + static u16_t lastport; +#endif /* UIP_ACTIVE_OPEN */ + +/* Temporary variables. */ +u8_t uip_acc32[ 4 ]; +static u8_t c, opt; +static u16_t tmp16; + +/* Structures and definitions. */ +#define TCP_FIN 0x01 +#define TCP_SYN 0x02 +#define TCP_RST 0x04 +#define TCP_PSH 0x08 +#define TCP_ACK 0x10 +#define TCP_URG 0x20 +#define TCP_CTL 0x3f + +#define TCP_OPT_END 0 /* End of TCP options list */ +#define TCP_OPT_NOOP 1 /* "No-operation" TCP option */ +#define TCP_OPT_MSS 2 /* Maximum segment size TCP option */ + +#define TCP_OPT_MSS_LEN 4 /* Length of TCP MSS option. */ + +#define ICMP_ECHO_REPLY 0 +#define ICMP_ECHO 8 + +#define ICMP_DEST_UNREACHABLE 3 +#define ICMP_PORT_UNREACHABLE 3 + +#define ICMP6_ECHO_REPLY 129 +#define ICMP6_ECHO 128 +#define ICMP6_NEIGHBOR_SOLICITATION 135 +#define ICMP6_NEIGHBOR_ADVERTISEMENT 136 + +#define ICMP6_FLAG_S ( 1 << 6 ) +#define ICMP6_OPTION_SOURCE_LINK_ADDRESS 1 +#define ICMP6_OPTION_TARGET_LINK_ADDRESS 2 + +/* Macros. */ +#define BUF ( ( struct uip_tcpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) +#define FBUF ( ( struct uip_tcpip_hdr * ) &uip_reassbuf[0] ) +#define ICMPBUF ( ( struct uip_icmpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) +#define UDPBUF ( ( struct uip_udpip_hdr * ) &uip_buf[UIP_LLH_LEN] ) + +#if UIP_STATISTICS == 1 + struct uip_stats uip_stat; + #define UIP_STAT( s ) s +#else + #define UIP_STAT( s ) +#endif /* UIP_STATISTICS == 1 */ + +#if UIP_LOGGING == 1 + #include + void uip_log( char *msg ); + #define UIP_LOG( m ) uip_log( m ) +#else + #define UIP_LOG( m ) +#endif /* UIP_LOGGING == 1 */ + +#if !UIP_ARCH_ADD32 + void uip_add32( u8_t *op32, u16_t op16 ) + { + uip_acc32[3] = op32[3] + ( op16 & 0xff ); + uip_acc32[2] = op32[2] + ( op16 >> 8 ); + uip_acc32[1] = op32[1]; + uip_acc32[0] = op32[0]; + + if( uip_acc32[2] < (op16 >> 8) ) + { + ++uip_acc32[1]; + if( uip_acc32[1] == 0 ) + { + ++uip_acc32[0]; + } + } + + if( uip_acc32[3] < (op16 & 0xff) ) + { + ++uip_acc32[2]; + if( uip_acc32[2] == 0 ) + { + ++uip_acc32[1]; + if( uip_acc32[1] == 0 ) + { + ++uip_acc32[0]; + } + } + } + } +/*---------------------------------------------------------------------------*/ +#endif /* UIP_ARCH_ADD32 */ + +#if !UIP_ARCH_CHKSUM + + static u16_t chksum( u16_t sum, const u8_t *data, u16_t len ) + { + u16_t t; + const u8_t *dataptr; + const u8_t *last_byte; + + dataptr = data; + last_byte = data + len - 1; + + while( dataptr < last_byte ) + { + /* At least two more bytes */ + t = ( dataptr[ 0 ] << 8 ) + dataptr[ 1 ]; + sum += t; + if( sum < t ) + { + sum++; /* carry */ + } + + dataptr += 2; + } + + if( dataptr == last_byte ) + { + t = ( dataptr[ 0 ] << 8 ) + 0; + sum += t; + if( sum < t ) + { + sum++; /* carry */ + } + } + + /* Return sum in host byte order. */ + return sum; + } + /*---------------------------------------------------------------------------*/ + + u16_t uip_chksum( u16_t *data, u16_t len ) + { + return htons( chksum( 0, ( u8_t * ) data, len ) ); + } + /*---------------------------------------------------------------------------*/ + + #ifndef UIP_ARCH_IPCHKSUM + u16_t uip_ipchksum( void ) + { + u16_t sum; + + sum = chksum( 0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN ); + + //DEBUG_PRINTF( "uip_ipchksum: sum 0x%04x\n", sum ); + return( sum == 0 ) ? 0xffff : htons( sum ); + } + #endif + /*---------------------------------------------------------------------------*/ + + static u16_t upper_layer_chksum( u8_t proto ) + { + u16_t upper_layer_len; + u16_t sum; + + #if UIP_CONF_IPV6 + upper_layer_len = ( ((u16_t) (BUF->len[ 0 ]) << 8) + BUF->len[ 1 ] ); + #else /* UIP_CONF_IPV6 */ + upper_layer_len = ( ((u16_t) (BUF->len[ 0 ]) << 8) + BUF->len[ 1 ] ) - UIP_IPH_LEN; + #endif /* UIP_CONF_IPV6 */ + + /* First sum pseudoheader. */ + + /* IP protocol and length fields. This addition cannot carry. */ + sum = upper_layer_len + proto; + + /* Sum IP source and destination addresses. */ + sum = chksum( sum, ( u8_t * ) &BUF->srcipaddr, 2 * sizeof(uip_ipaddr_t) ); + + /* Sum TCP header and data. */ + sum = chksum( sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN], upper_layer_len ); + + return( sum == 0 ) ? 0xffff : htons( sum ); + } + /*---------------------------------------------------------------------------*/ + + #if UIP_CONF_IPV6 + u16_t uip_icmp6chksum( void ) + { + return upper_layer_chksum( UIP_PROTO_ICMP6 ); + } + #endif /* UIP_CONF_IPV6 */ + /*---------------------------------------------------------------------------*/ + + u16_t uip_tcpchksum( void ) + { + return upper_layer_chksum( UIP_PROTO_TCP ); + } + /*---------------------------------------------------------------------------*/ + + #if UIP_UDP_CHECKSUMS + u16_t uip_udpchksum( void ) + { + return upper_layer_chksum( UIP_PROTO_UDP ); + } + #endif /* UIP_UDP_CHECKSUMS */ + +#endif /* UIP_ARCH_CHKSUM */ +/*---------------------------------------------------------------------------*/ + +void uip_init( void ) +{ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + uip_listenports[ c ] = 0; + } + + for( c = 0; c < UIP_CONNS; ++c ) + { + uip_conns[ c ].tcpstateflags = UIP_CLOSED; + } + + #if UIP_ACTIVE_OPEN + lastport = 1024; + #endif /* UIP_ACTIVE_OPEN */ + + #if UIP_UDP + for( c = 0; c < UIP_UDP_CONNS; ++c ) + { + uip_udp_conns[ c ].lport = 0; + } + #endif /* UIP_UDP */ + + /* IPv4 initialization. */ + #if UIP_FIXEDADDR == 0 + /* uip_hostaddr[ 0 ] = uip_hostaddr[ 1 ] = 0;*/ + #endif /* UIP_FIXEDADDR */ +} +/*---------------------------------------------------------------------------*/ + +#if UIP_ACTIVE_OPEN + struct uip_conn *uip_connect( uip_ipaddr_t *ripaddr, u16_t rport ) + { + register struct uip_conn *conn, *cconn; + + /* Find an unused local port. */ + again: + ++lastport; + + if( lastport >= 32000 ) + { + lastport = 4096; + } + + /* Check if this port is already in use, and if so try to find + another one. */ + for( c = 0; c < UIP_CONNS; ++c ) + { + conn = &uip_conns[ c ]; + if( conn->tcpstateflags != UIP_CLOSED && conn->lport == htons(lastport) ) + { + goto again; + } + } + + conn = 0; + for( c = 0; c < UIP_CONNS; ++c ) + { + cconn = &uip_conns[ c ]; + if( cconn->tcpstateflags == UIP_CLOSED ) + { + conn = cconn; + break; + } + + if( cconn->tcpstateflags == UIP_TIME_WAIT ) + { + if( conn == 0 || cconn->timer > conn->timer ) + { + conn = cconn; + } + } + } + + if( conn == 0 ) + { + return 0; + } + + conn->tcpstateflags = UIP_SYN_SENT; + + conn->snd_nxt[ 0 ] = iss[ 0 ]; + conn->snd_nxt[ 1 ] = iss[ 1 ]; + conn->snd_nxt[ 2 ] = iss[ 2 ]; + conn->snd_nxt[ 3 ] = iss[ 3 ]; + + conn->initialmss = conn->mss = UIP_TCP_MSS; + + conn->len = 1; /* TCP length of the SYN is one. */ + conn->nrtx = 0; + conn->timer = 1; /* Send the SYN next time around. */ + conn->rto = UIP_RTO; + conn->sa = 0; + conn->sv = 16; /* Initial value of the RTT variance. */ + conn->lport = htons( lastport ); + conn->rport = rport; + uip_ipaddr_copy( &conn->ripaddr, ripaddr ); + + return conn; + } +/*---------------------------------------------------------------------------*/ +#endif /* UIP_ACTIVE_OPEN */ + +#if UIP_UDP + struct uip_udp_conn *uip_udp_new( const uip_ipaddr_t *ripaddr, u16_t rport ) + { + register struct uip_udp_conn *conn; + + /* Find an unused local port. */ + again: + ++lastport; + + if( lastport >= 32000 ) + { + lastport = 4096; + } + + for( c = 0; c < UIP_UDP_CONNS; ++c ) + { + if( uip_udp_conns[ c ].lport == htons(lastport) ) + { + goto again; + } + } + + conn = 0; + for( c = 0; c < UIP_UDP_CONNS; ++c ) + { + if( uip_udp_conns[ c ].lport == 0 ) + { + conn = &uip_udp_conns[ c ]; + break; + } + } + + if( conn == 0 ) + { + return 0; + } + + conn->lport = HTONS( lastport ); + conn->rport = rport; + if( ripaddr == NULL ) + { + memset( &conn->ripaddr, 0, sizeof(uip_ipaddr_t) ); + } + else + { + uip_ipaddr_copy( &conn->ripaddr, ripaddr ); + } + + conn->ttl = UIP_TTL; + + return conn; + } +/*---------------------------------------------------------------------------*/ +#endif /* UIP_UDP */ + +void uip_unlisten( u16_t port ) +{ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + if( uip_listenports[ c ] == port ) + { + uip_listenports[ c ] = 0; + return; + } + } +} +/*---------------------------------------------------------------------------*/ + +void uip_listen( u16_t port ) +{ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + if( uip_listenports[ c ] == 0 ) + { + uip_listenports[ c ] = port; + return; + } + } +} +/*---------------------------------------------------------------------------*/ + +/* XXX: IP fragment reassembly: not well-tested. */ +#if UIP_REASSEMBLY && !UIP_CONF_IPV6 + #define UIP_REASS_BUFSIZE ( UIP_BUFSIZE - UIP_LLH_LEN ) + static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; + static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / ( 8 * 8 )]; + static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01 }; + static u16_t uip_reasslen; + static u8_t uip_reassflags; + #define UIP_REASS_FLAG_LASTFRAG 0x01 + static u8_t uip_reasstmr; + + #define IP_MF 0x20 + + static u8_t uip_reass( void ) + { + u16_t offset, len; + u16_t i; + + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if( uip_reasstmr == 0 ) + { + memcpy( uip_reassbuf, &BUF->vhl, UIP_IPH_LEN ); + uip_reasstmr = UIP_REASS_MAXAGE; + uip_reassflags = 0; + + /* Clear the bitmap. */ + memset( uip_reassbitmap, 0, sizeof(uip_reassbitmap) ); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if + ( + BUF->srcipaddr[ 0 ] == FBUF->srcipaddr[ 0 ] && + BUF->srcipaddr[ 1 ] == FBUF->srcipaddr[ 1 ] && + BUF->destipaddr[ 0 ] == FBUF->destipaddr[ 0 ] && + BUF->destipaddr[ 1 ] == FBUF->destipaddr[ 1 ] && + BUF->ipid[ 0 ] == FBUF->ipid[ 0 ] && + BUF->ipid[ 1 ] == FBUF->ipid[ 1 ] + ) + { + len = ( BUF->len[ 0 ] << 8 ) + BUF->len[ 1 ] - ( BUF->vhl & 0x0f ) * 4; + offset = ( ((BUF->ipoffset[ 0 ] & 0x3f) << 8) + BUF->ipoffset[ 1 ] ) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if( offset > UIP_REASS_BUFSIZE || offset + len > UIP_REASS_BUFSIZE ) + { + uip_reasstmr = 0; + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + memcpy( &uip_reassbuf[UIP_IPH_LEN + offset], ( char * ) BUF + ( int ) ((BUF->vhl & 0x0f) * 4), len ); + + /* Update the bitmap. */ + if( offset / (8 * 8) == (offset + len) / (8 * 8) ) + { + /* If the two endpoints are in the same byte, we only update + that byte. */ + uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7] &~bitmap_bits[( (offset + len) / 8 ) & 7]; + } + else + { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7]; + for( i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i ) + { + uip_reassbitmap[i] = 0xff; + } + + uip_reassbitmap[( offset + len ) / ( 8 * 8 )] |= ~bitmap_bits[( (offset + len) / 8 ) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + if( (BUF->ipoffset[ 0 ] & IP_MF) == 0 ) + { + uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; + uip_reasslen = offset + len; + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if( uip_reassflags & UIP_REASS_FLAG_LASTFRAG ) + { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + for( i = 0; i < uip_reasslen / (8 * 8) - 1; ++i ) + { + if( uip_reassbitmap[i] != 0xff ) + { + goto nullreturn; + } + } + + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + if( uip_reassbitmap[uip_reasslen / (8 * 8)] != (u8_t)~bitmap_bits[uip_reasslen / 8 & 7] ) + { + goto nullreturn; + } + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + uip_reasstmr = 0; + memcpy( BUF, FBUF, uip_reasslen ); + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + BUF->ipoffset[ 0 ] = BUF->ipoffset[ 1 ] = 0; + BUF->len[ 0 ] = uip_reasslen >> 8; + BUF->len[ 1 ] = uip_reasslen & 0xff; + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + + return uip_reasslen; + } + } + + nullreturn: + + return 0; + } +/*---------------------------------------------------------------------------*/ +#endif /* UIP_REASSEMBLY */ + + +static void uip_add_rcv_nxt( u16_t n ) +{ + uip_add32( uip_conn->rcv_nxt, n ); + uip_conn->rcv_nxt[ 0 ] = uip_acc32[ 0 ]; + uip_conn->rcv_nxt[ 1 ] = uip_acc32[ 1 ]; + uip_conn->rcv_nxt[ 2 ] = uip_acc32[ 2 ]; + uip_conn->rcv_nxt[ 3 ] = uip_acc32[ 3 ]; +} +/*---------------------------------------------------------------------------*/ + +void uip_process( u8_t flag ) +{ + register struct uip_conn *uip_connr = uip_conn; + + #if UIP_UDP + if( flag == UIP_UDP_SEND_CONN ) + { + goto udp_send; + } + #endif /* UIP_UDP */ + + uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN]; + + /* Check if we were invoked because of a poll request for a + particular connection. */ + if( flag == UIP_POLL_REQUEST ) + { + if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED && !uip_outstanding(uip_connr) ) + { + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + + goto drop; + + /* Check if we were invoked because of the perodic timer fireing. */ + } + else if( flag == UIP_TIMER ) + { + #if UIP_REASSEMBLY + if( uip_reasstmr != 0 ) + { + --uip_reasstmr; + } + #endif /* UIP_REASSEMBLY */ + + /* Increase the initial sequence number. */ + if( ++iss[ 3 ] == 0 ) + { + if( ++iss[ 2 ] == 0 ) + { + if( ++iss[ 1 ] == 0 ) + { + ++iss[ 0 ]; + } + } + } + + /* Reset the length variables. */ + uip_len = 0; + uip_slen = 0; + + /* Check if the connection is in a state in which we simply wait + for the connection to time out. If so, we increase the + connection's timer and remove the connection if it times + out. */ + if( uip_connr->tcpstateflags == UIP_TIME_WAIT || uip_connr->tcpstateflags == UIP_FIN_WAIT_2 ) + { + ++( uip_connr->timer ); + if( uip_connr->timer == UIP_TIME_WAIT_TIMEOUT ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + } + } + else if( uip_connr->tcpstateflags != UIP_CLOSED ) + { + /* If the connection has outstanding data, we increase the + connection's timer and see if it has reached the RTO value + in which case we retransmit. */ + if( uip_outstanding(uip_connr) ) + { + if( uip_connr->timer-- == 0 ) + { + if + ( + uip_connr->nrtx == UIP_MAXRTX || + ( + (uip_connr->tcpstateflags == UIP_SYN_SENT || uip_connr->tcpstateflags == UIP_SYN_RCVD) && + uip_connr->nrtx == UIP_MAXSYNRTX + ) + ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + + /* We call UIP_APPCALL() with uip_flags set to + UIP_TIMEDOUT to inform the application that the + connection has timed out. */ + uip_flags = UIP_TIMEDOUT; + UIP_APPCALL(); + + /* We also send a reset packet to the remote host. */ + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + /* Exponential backoff. */ + uip_connr->timer = UIP_RTO << ( uip_connr->nrtx > 4 ? 4 : uip_connr->nrtx ); + ++( uip_connr->nrtx ); + + /* Ok, so we need to retransmit. We do this differently + depending on which state we are in. In ESTABLISHED, we + call upon the application so that it may prepare the + data for the retransmit. In SYN_RCVD, we resend the + SYNACK that we sent earlier and in LAST_ACK we have to + retransmit our FINACK. */ + UIP_STAT( ++uip_stat.tcp.rexmit ); + switch( uip_connr->tcpstateflags & UIP_TS_MASK ) + { + case UIP_SYN_RCVD: + /* In the SYN_RCVD state, we should retransmit our + SYNACK. */ + goto tcp_send_synack; + + #if UIP_ACTIVE_OPEN + case UIP_SYN_SENT: + /* In the SYN_SENT state, we retransmit out SYN. */ + BUF->flags = 0; + goto tcp_send_syn; + #endif /* UIP_ACTIVE_OPEN */ + + case UIP_ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application + to do the actual retransmit after which we jump into + the code for sending out the packet (the apprexmit + label). */ + uip_flags = UIP_REXMIT; + UIP_APPCALL(); + goto apprexmit; + + case UIP_FIN_WAIT_1: + case UIP_CLOSING: + case UIP_LAST_ACK: + /* In all these states we should retransmit a FINACK. */ + goto tcp_send_finack; + } + } + } + else if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED ) + { + /* If there was no need for a retransmission, we poll the + application for new data. */ + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + } + + goto drop; + } + + #if UIP_UDP + if( flag == UIP_UDP_TIMER ) + { + if( uip_udp_conn->lport != 0 ) + { + uip_conn = NULL; + uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + uip_len = uip_slen = 0; + uip_flags = UIP_POLL; + UIP_UDP_APPCALL(); + goto udp_send; + } + else + { + goto drop; + } + } + #endif + + /* This is where the input processing starts. */ + UIP_STAT( ++uip_stat.ip.recv ); + + /* Start of IP input header processing code. */ + #if UIP_CONF_IPV6 + /* Check validity of the IP header. */ + if( (BUF->vtc & 0xf0) != 0x60 ) + { /* IP version and header length. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.vhlerr ); + UIP_LOG( "ipv6: invalid version." ); + goto drop; + } + + #else /* UIP_CONF_IPV6 */ + /* Check validity of the IP header. */ + if( BUF->vhl != 0x45 ) + { /* IP version and header length. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.vhlerr ); + UIP_LOG( "ip: invalid version or header length." ); + goto drop; + } + + #endif /* UIP_CONF_IPV6 */ + + /* Check the size of the packet. If the size reported to us in + uip_len is smaller the size reported in the IP header, we assume + that the packet has been corrupted in transit. If the size of + uip_len is larger than the size reported in the IP packet header, + the packet has been padded and we set uip_len to the correct + value.. */ + if( (BUF->len[ 0 ] << 8) + BUF->len[ 1 ] <= uip_len ) + { + uip_len = ( BUF->len[ 0 ] << 8 ) + BUF->len[ 1 ]; + #if UIP_CONF_IPV6 + /* The length reported in the IPv6 header is the + length of the payload that follows the + header. However, uIP uses the uip_len variable + for holding the size of the entire packet, + including the IP header. For IPv4 this is not a + problem as the length field in the IPv4 header + contains the length of the entire packet. But + for IPv6 we need to add the size of the IPv6 + header (40 bytes). */ + uip_len += 40; + #endif /* UIP_CONF_IPV6 */ + } + else + { + UIP_LOG( "ip: packet shorter than reported in IP header." ); + goto drop; + } + + #if !UIP_CONF_IPV6 + /* Check the fragment flag. */ + if( (BUF->ipoffset[ 0 ] & 0x3f) != 0 || BUF->ipoffset[ 1 ] != 0 ) + { + #if UIP_REASSEMBLY + uip_len = uip_reass(); + if( uip_len == 0 ) + { + goto drop; + } + #else /* UIP_REASSEMBLY */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.fragerr ); + UIP_LOG( "ip: fragment dropped." ); + goto drop; + #endif /* UIP_REASSEMBLY */ + } + #endif /* UIP_CONF_IPV6 */ + + if( uip_ipaddr_cmp(&uip_hostaddr, &uip_all_zeroes_addr) ) + { + /* If we are configured to use ping IP address configuration and + hasn't been assigned an IP address yet, we accept all ICMP + packets. */ + #if UIP_PINGADDRCONF && !UIP_CONF_IPV6 + if( BUF->proto == UIP_PROTO_ICMP ) + { + UIP_LOG( "ip: possible ping config packet received." ); + goto icmp_input; + } + else + { + UIP_LOG( "ip: packet dropped since no address assigned." ); + goto drop; + } + #endif /* UIP_PINGADDRCONF */ + } + else + { + /* If IP broadcast support is configured, we check for a broadcast + UDP packet, which may be destined to us. */ + #if UIP_BROADCAST + //DEBUG_PRINTF( "UDP IP checksum 0x%04x\n", uip_ipchksum() ); + if( BUF->proto == UIP_PROTO_UDP && uip_ipaddr_cmp(&BUF->destipaddr, &uip_broadcast_addr) /*&& uip_ipchksum() == 0xffff*/ ) + { + goto udp_input; + } + #endif /* UIP_BROADCAST */ + + /* Check if the packet is destined for our IP address. */ + #if !UIP_CONF_IPV6 + if( !uip_ipaddr_cmp(&BUF->destipaddr, &uip_hostaddr) ) + { + UIP_STAT( ++uip_stat.ip.drop ); + goto drop; + } + #else /* UIP_CONF_IPV6 */ + /* For IPv6, packet reception is a little trickier as we need to + make sure that we listen to certain multicast addresses (all + hosts multicast address, and the solicited-node multicast + address) as well. However, we will cheat here and accept all + multicast packets that are sent to the ff02::/16 addresses. */ + if( !uip_ipaddr_cmp(&BUF->destipaddr, &uip_hostaddr) && BUF->destipaddr.u16[ 0 ] != HTONS(0xff02) ) + { + UIP_STAT( ++uip_stat.ip.drop ); + goto drop; + } + #endif /* UIP_CONF_IPV6 */ + } + + #if !UIP_CONF_IPV6 + if( uip_ipchksum() != 0xffff ) + { + /* Compute and check the IP header checksum. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.chkerr ); + UIP_LOG( "ip: bad checksum." ); + goto drop; + } + #endif /* UIP_CONF_IPV6 */ + + if( BUF->proto == UIP_PROTO_TCP ) + { + /* Check for TCP packet. If so, proceed with TCP input processing. */ + goto tcp_input; + } + + #if UIP_UDP + if( BUF->proto == UIP_PROTO_UDP ) + { + goto udp_input; + } + #endif /* UIP_UDP */ + + #if !UIP_CONF_IPV6 + /* ICMPv4 processing code follows. */ + if( BUF->proto != UIP_PROTO_ICMP ) + { + /* We only allow ICMP packets from here. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.protoerr ); + UIP_LOG( "ip: neither tcp nor icmp." ); + goto drop; + } + + #if UIP_PINGADDRCONF + icmp_input : + #endif /* UIP_PINGADDRCONF */ + + UIP_STAT( ++uip_stat.icmp.recv ); + + /* ICMP echo (i.e., ping) processing. This is simple, we only change + the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP + checksum before we return the packet. */ + if( ICMPBUF->type != ICMP_ECHO ) + { + UIP_STAT( ++uip_stat.icmp.drop ); + UIP_STAT( ++uip_stat.icmp.typeerr ); + UIP_LOG( "icmp: not icmp echo." ); + goto drop; + } + + /* If we are configured to use ping IP address assignment, we use + the destination IP address of this ping packet and assign it to + ourself. */ + #if UIP_PINGADDRCONF + if( uip_ipaddr_cmp(&uip_hostaddr, &uip_all_zeroes_addr) ) + { + uip_hostaddr = BUF->destipaddr; + } + #endif /* UIP_PINGADDRCONF */ + + ICMPBUF->type = ICMP_ECHO_REPLY; + + if( ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8)) ) + { + ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 ) + 1; + } + else + { + ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 ); + } + + /* Swap IP addresses. */ + uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr ); + uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr ); + + UIP_STAT( ++uip_stat.icmp.sent ); + BUF->ttl = UIP_TTL; + goto ip_send_nolen; + + /* End of IPv4 input header processing code. */ + + #else /* !UIP_CONF_IPV6 */ + + /* This is IPv6 ICMPv6 processing code. */ + + //DEBUG_PRINTF( "icmp6_input: length %d\n", uip_len ); + if( BUF->proto != UIP_PROTO_ICMP6 ) + { + /* We only allow ICMPv6 packets from here. */ + UIP_STAT( ++uip_stat.ip.drop ); + UIP_STAT( ++uip_stat.ip.protoerr ); + UIP_LOG( "ip: neither tcp nor icmp6." ); + goto drop; + } + + UIP_STAT( ++uip_stat.icmp.recv ); + + /* If we get a neighbor solicitation for our address we should send + a neighbor advertisement message back. */ + if( ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION ) + { + if( uip_ipaddr_cmp(&ICMPBUF->icmp6data, &uip_hostaddr) ) + { + if( ICMPBUF->options[ 0 ] == ICMP6_OPTION_SOURCE_LINK_ADDRESS ) + { + /* Save the sender's address in our neighbor list. */ + uip_neighbor_add( &ICMPBUF->srcipaddr, &(ICMPBUF->options[ 2 ]) ); + } + + /* We should now send a neighbor advertisement back to where the + neighbor solicication came from. */ + ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT; + ICMPBUF->flags = ICMP6_FLAG_S; /* Solicited flag. */ + + ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0; + + uip_ipaddr_copy( &ICMPBUF->destipaddr, &ICMPBUF->srcipaddr ); + uip_ipaddr_copy( &ICMPBUF->srcipaddr, &uip_hostaddr ); + ICMPBUF->options[ 0 ] = ICMP6_OPTION_TARGET_LINK_ADDRESS; + ICMPBUF->options[ 1 ] = 1; /* Options length, 1 = 8 bytes. */ + memcpy( &(ICMPBUF->options[ 2 ]), &uip_ethaddr, sizeof(uip_ethaddr) ); + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_icmp6chksum(); + + goto send; + } + + goto drop; + } + else if( ICMPBUF->type == ICMP6_ECHO ) + { + /* ICMP echo (i.e., ping) processing. This is simple, we only + change the ICMP type from ECHO to ECHO_REPLY and update the + ICMP checksum before we return the packet. */ + ICMPBUF->type = ICMP6_ECHO_REPLY; + + uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr ); + uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr ); + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_icmp6chksum(); + + UIP_STAT( ++uip_stat.icmp.sent ); + goto send; + } + else + { + //DEBUG_PRINTF( "Unknown icmp6 message type %d\n", ICMPBUF->type ); + UIP_STAT( ++uip_stat.icmp.drop ); + UIP_STAT( ++uip_stat.icmp.typeerr ); + UIP_LOG( "icmp: unknown ICMP message." ); + goto drop; + } + + /* End of IPv6 ICMP processing. */ + #endif /* !UIP_CONF_IPV6 */ + + #if UIP_UDP + /* UDP input processing. */ + udp_input : + /* UDP processing is really just a hack. We don't do anything to the + UDP/IP headers, but let the UDP application do all the hard + work. If the application sets uip_slen, it has a packet to + send. */ + #if UIP_UDP_CHECKSUMS + uip_len = uip_len - UIP_IPUDPH_LEN; + uip_appdata = &uip_buf[ UIP_LLH_LEN + UIP_IPUDPH_LEN ]; + if( UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff ) + { + UIP_STAT( ++uip_stat.udp.drop ); + UIP_STAT( ++uip_stat.udp.chkerr ); + UIP_LOG( "udp: bad checksum." ); + goto drop; + } + + #else /* UIP_UDP_CHECKSUMS */ + uip_len = uip_len - UIP_IPUDPH_LEN; + #endif /* UIP_UDP_CHECKSUMS */ + + /* Demultiplex this UDP packet between the UDP "connections". */ + for( uip_udp_conn = &uip_udp_conns[ 0 ]; uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; ++uip_udp_conn ) + { + /* If the local UDP port is non-zero, the connection is considered + to be used. If so, the local port number is checked against the + destination port number in the received packet. If the two port + numbers match, the remote port number is checked if the + connection is bound to a remote port. Finally, if the + connection is bound to a remote IP address, the source IP + address of the packet is checked. */ + if + ( + uip_udp_conn->lport != 0 && + UDPBUF->destport == uip_udp_conn->lport && + (uip_udp_conn->rport == 0 || UDPBUF->srcport == uip_udp_conn->rport) && + ( + uip_ipaddr_cmp(&uip_udp_conn->ripaddr, &uip_all_zeroes_addr) || + uip_ipaddr_cmp(&uip_udp_conn->ripaddr, &uip_broadcast_addr) || + uip_ipaddr_cmp(&BUF->srcipaddr, &uip_udp_conn->ripaddr) + ) + ) + { + goto udp_found; + } + } + + UIP_LOG( "udp: no matching connection found" ); + + #if UIP_CONF_ICMP_DEST_UNREACH && !UIP_CONF_IPV6 + + /* Copy fields from packet header into payload of this ICMP packet. */ + memcpy( &(ICMPBUF->payload[ 0 ]), ICMPBUF, UIP_IPH_LEN + 8 ); + + /* Set the ICMP type and code. */ + ICMPBUF->type = ICMP_DEST_UNREACHABLE; + ICMPBUF->icode = ICMP_PORT_UNREACHABLE; + + /* Calculate the ICMP checksum. */ + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_chksum( ( u16_t * ) &(ICMPBUF->type), 36 ); + + /* Set the IP destination address to be the source address of the + original packet. */ + uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr ); + + /* Set our IP address as the source address. */ + uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr ); + + /* The size of the ICMP destination unreachable packet is 36 + the + size of the IP header (20) = 56. */ + uip_len = 36 + UIP_IPH_LEN; + ICMPBUF->len[ 0 ] = 0; + ICMPBUF->len[ 1 ] = ( u8_t ) uip_len; + ICMPBUF->ttl = UIP_TTL; + ICMPBUF->proto = UIP_PROTO_ICMP; + + goto ip_send_nolen; + #else /* UIP_CONF_ICMP_DEST_UNREACH */ + goto drop; + #endif /* UIP_CONF_ICMP_DEST_UNREACH */ + + udp_found : uip_conn = NULL; + uip_flags = UIP_NEWDATA; + uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + uip_slen = 0; + UIP_UDP_APPCALL(); + +udp_send: + if( uip_slen == 0 ) + { + goto drop; + } + + uip_len = uip_slen + UIP_IPUDPH_LEN; + + #if UIP_CONF_IPV6 + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[ 0 ] = ( (uip_len - UIP_IPH_LEN) >> 8 ); + BUF->len[ 1 ] = ( (uip_len - UIP_IPH_LEN) & 0xff ); + #else /* UIP_CONF_IPV6 */ + BUF->len[ 0 ] = ( uip_len >> 8 ); + BUF->len[ 1 ] = ( uip_len & 0xff ); + #endif /* UIP_CONF_IPV6 */ + + BUF->ttl = uip_udp_conn->ttl; + BUF->proto = UIP_PROTO_UDP; + + UDPBUF->udplen = HTONS( uip_slen + UIP_UDPH_LEN ); + UDPBUF->udpchksum = 0; + + BUF->srcport = uip_udp_conn->lport; + BUF->destport = uip_udp_conn->rport; + + uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr ); + uip_ipaddr_copy( &BUF->destipaddr, &uip_udp_conn->ripaddr ); + + uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN]; + + #if UIP_UDP_CHECKSUMS + /* Calculate UDP checksum. */ + UDPBUF->udpchksum = ~( uip_udpchksum() ); + if( UDPBUF->udpchksum == 0 ) + { + UDPBUF->udpchksum = 0xffff; + } + #endif /* UIP_UDP_CHECKSUMS */ + goto ip_send_nolen; + #endif /* UIP_UDP */ + + /* TCP input processing. */ + tcp_input : UIP_STAT( ++uip_stat.tcp.recv ); + + /* Start of TCP input header processing code. */ + if( uip_tcpchksum() != 0xffff ) + { + /* Compute and check the TCP checksum. */ + UIP_STAT( ++uip_stat.tcp.drop ); + UIP_STAT( ++uip_stat.tcp.chkerr ); + UIP_LOG( "tcp: bad checksum." ); + goto drop; + } + + /* Demultiplex this segment. */ + + /* First check any active connections. */ + for( uip_connr = &uip_conns[ 0 ]; uip_connr <= &uip_conns[UIP_CONNS - 1]; ++uip_connr ) + { + if + ( + uip_connr->tcpstateflags != UIP_CLOSED && + BUF->destport == uip_connr->lport && + BUF->srcport == uip_connr->rport && + uip_ipaddr_cmp(&BUF->srcipaddr, &uip_connr->ripaddr) + ) + { + goto found; + } + } + + /* If we didn't find and active connection that expected the packet, + either this packet is an old duplicate, or this is a SYN packet + destined for a connection in LISTEN. If the SYN flag isn't set, + it is an old packet and we send a RST. */ + if( (BUF->flags & TCP_CTL) != TCP_SYN ) + { + goto reset; + } + + tmp16 = BUF->destport; + + /* Next, check listening connections. */ + for( c = 0; c < UIP_LISTENPORTS; ++c ) + { + if( tmp16 == uip_listenports[ c ] ) + { + goto found_listen; + } + } + + /* No matching connection found, so we send a RST packet. */ + UIP_STAT( ++uip_stat.tcp.synrst ); + +reset: + /* We do not send resets in response to resets. */ + if( BUF->flags & TCP_RST ) + { + goto drop; + } + + UIP_STAT( ++uip_stat.tcp.rst ); + + BUF->flags = TCP_RST | TCP_ACK; + uip_len = UIP_IPTCPH_LEN; + BUF->tcpoffset = 5 << 4; + + /* Flip the seqno and ackno fields in the TCP header. */ + c = BUF->seqno[ 3 ]; + BUF->seqno[ 3 ] = BUF->ackno[ 3 ]; + BUF->ackno[ 3 ] = c; + + c = BUF->seqno[ 2 ]; + BUF->seqno[ 2 ] = BUF->ackno[ 2 ]; + BUF->ackno[ 2 ] = c; + + c = BUF->seqno[ 1 ]; + BUF->seqno[ 1 ] = BUF->ackno[ 1 ]; + BUF->ackno[ 1 ] = c; + + c = BUF->seqno[ 0 ]; + BUF->seqno[ 0 ] = BUF->ackno[ 0 ]; + BUF->ackno[ 0 ] = c; + + /* We also have to increase the sequence number we are + acknowledging. If the least significant byte overflowed, we need + to propagate the carry to the other bytes as well. */ + if( ++BUF->ackno[ 3 ] == 0 ) + { + if( ++BUF->ackno[ 2 ] == 0 ) + { + if( ++BUF->ackno[ 1 ] == 0 ) + { + ++BUF->ackno[ 0 ]; + } + } + } + + /* Swap port numbers. */ + tmp16 = BUF->srcport; + BUF->srcport = BUF->destport; + BUF->destport = tmp16; + + /* Swap IP addresses. */ + uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr ); + uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr ); + + /* And send out the RST packet! */ + goto tcp_send_noconn; + + /* This label will be jumped to if we matched the incoming packet + with a connection in LISTEN. In that case, we should create a new + connection and send a SYNACK in return. */ +found_listen: + /* First we check if there are any connections avaliable. Unused + connections are kept in the same table as used connections, but + unused ones have the tcpstate set to CLOSED. Also, connections in + TIME_WAIT are kept track of and we'll use the oldest one if no + CLOSED connections are found. Thanks to Eddie C. Dost for a very + nice algorithm for the TIME_WAIT search. */ + uip_connr = 0; + for( c = 0; c < UIP_CONNS; ++c ) + { + if( uip_conns[ c ].tcpstateflags == UIP_CLOSED ) + { + uip_connr = &uip_conns[ c ]; + break; + } + + if( uip_conns[ c ].tcpstateflags == UIP_TIME_WAIT ) + { + if( uip_connr == 0 || uip_conns[ c ].timer > uip_connr->timer ) + { + uip_connr = &uip_conns[ c ]; + } + } + } + + if( uip_connr == 0 ) + { + /* All connections are used already, we drop packet and hope that + the remote end will retransmit the packet at a time when we + have more spare connections. */ + UIP_STAT( ++uip_stat.tcp.syndrop ); + UIP_LOG( "tcp: found no unused connections." ); + goto drop; + } + + uip_conn = uip_connr; + + /* Fill in the necessary fields for the new connection. */ + uip_connr->rto = uip_connr->timer = UIP_RTO; + uip_connr->sa = 0; + uip_connr->sv = 4; + uip_connr->nrtx = 0; + uip_connr->lport = BUF->destport; + uip_connr->rport = BUF->srcport; + uip_ipaddr_copy( &uip_connr->ripaddr, &BUF->srcipaddr ); + uip_connr->tcpstateflags = UIP_SYN_RCVD; + + uip_connr->snd_nxt[ 0 ] = iss[ 0 ]; + uip_connr->snd_nxt[ 1 ] = iss[ 1 ]; + uip_connr->snd_nxt[ 2 ] = iss[ 2 ]; + uip_connr->snd_nxt[ 3 ] = iss[ 3 ]; + uip_connr->len = 1; + + /* rcv_nxt should be the seqno from the incoming packet + 1. */ + uip_connr->rcv_nxt[ 3 ] = BUF->seqno[ 3 ]; + uip_connr->rcv_nxt[ 2 ] = BUF->seqno[ 2 ]; + uip_connr->rcv_nxt[ 1 ] = BUF->seqno[ 1 ]; + uip_connr->rcv_nxt[ 0 ] = BUF->seqno[ 0 ]; + uip_add_rcv_nxt( 1 ); + + /* Parse the TCP MSS option, if present. */ + if( (BUF->tcpoffset & 0xf0) > 0x50 ) + { + for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; ) + { + opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; + if( opt == TCP_OPT_END ) + { + /* End of options. */ + break; + } + else if( opt == TCP_OPT_NOOP ) + { + ++c; + + /* NOP option. */ + } + else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN ) + { + /* An MSS option with the right option length. */ + tmp16 = ( (u16_t) uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | ( u16_t ) uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16; + + /* And we are done processing options. */ + break; + } + else + { + /* All other options have a length field, so that we easily + can skip past them. */ + if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 ) + { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + /* Our response will be a SYNACK. */ + #if UIP_ACTIVE_OPEN + tcp_send_synack : BUF->flags = TCP_ACK; +tcp_send_syn: + BUF->flags |= TCP_SYN; + #else /* UIP_ACTIVE_OPEN */ + tcp_send_synack : BUF->flags = TCP_SYN | TCP_ACK; + #endif /* UIP_ACTIVE_OPEN */ + + /* We send out the TCP Maximum Segment Size option with our + SYNACK. */ + BUF->optdata[ 0 ] = TCP_OPT_MSS; + BUF->optdata[ 1 ] = TCP_OPT_MSS_LEN; + BUF->optdata[ 2 ] = ( UIP_TCP_MSS ) / 256; + BUF->optdata[ 3 ] = ( UIP_TCP_MSS ) & 255; + uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN; + BUF->tcpoffset = ( (UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4 ) << 4; + goto tcp_send; + + /* This label will be jumped to if we found an active connection. */ +found: + uip_conn = uip_connr; + uip_flags = 0; + + /* We do a very naive form of TCP reset processing; we just accept + any RST and kill our connection. We should in fact check if the + sequence number of this reset is wihtin our advertised window + before we accept the reset. */ + if( BUF->flags & TCP_RST ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + UIP_LOG( "tcp: got reset, aborting connection." ); + uip_flags = UIP_ABORT; + UIP_APPCALL(); + goto drop; + } + + /* Calculate the length of the data, if the application has sent + any data to us. */ + c = ( BUF->tcpoffset >> 4 ) << 2; + + /* uip_len will contain the length of the actual TCP data. This is + calculated by subtracing the length of the TCP header (in + c) and the length of the IP header (20 bytes). */ + uip_len = uip_len - c - UIP_IPH_LEN; + + /* First, check if the sequence number of the incoming packet is + what we're expecting next. If not, we send out an ACK with the + correct numbers in. */ + if( !(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) && ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK))) ) + { + if + ( + (uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) && + ( + BUF->seqno[ 0 ] != uip_connr->rcv_nxt[ 0 ] || + BUF->seqno[ 1 ] != uip_connr->rcv_nxt[ 1 ] || + BUF->seqno[ 2 ] != uip_connr->rcv_nxt[ 2 ] || + BUF->seqno[ 3 ] != uip_connr->rcv_nxt[ 3 ] + ) + ) + { + goto tcp_send_ack; + } + } + + /* Next, check if the incoming segment acknowledges any outstanding + data. If so, we update the sequence number, reset the length of + the outstanding data, calculate RTT estimations, and reset the + retransmission timer. */ + if( (BUF->flags & TCP_ACK) && uip_outstanding(uip_connr) ) + { + uip_add32( uip_connr->snd_nxt, uip_connr->len ); + + if + ( + BUF->ackno[ 0 ] == uip_acc32[ 0 ] && + BUF->ackno[ 1 ] == uip_acc32[ 1 ] && + BUF->ackno[ 2 ] == uip_acc32[ 2 ] && + BUF->ackno[ 3 ] == uip_acc32[ 3 ] + ) + { + /* Update sequence number. */ + uip_connr->snd_nxt[ 0 ] = uip_acc32[ 0 ]; + uip_connr->snd_nxt[ 1 ] = uip_acc32[ 1 ]; + uip_connr->snd_nxt[ 2 ] = uip_acc32[ 2 ]; + uip_connr->snd_nxt[ 3 ] = uip_acc32[ 3 ]; + + /* Do RTT estimation, unless we have done retransmissions. */ + if( uip_connr->nrtx == 0 ) + { + signed char m; + m = uip_connr->rto - uip_connr->timer; + + /* This is taken directly from VJs original code in his paper */ + m = m - ( uip_connr->sa >> 3 ); + uip_connr->sa += m; + if( m < 0 ) + { + m = -m; + } + + m = m - ( uip_connr->sv >> 2 ); + uip_connr->sv += m; + uip_connr->rto = ( uip_connr->sa >> 3 ) + uip_connr->sv; + } + + /* Set the acknowledged flag. */ + uip_flags = UIP_ACKDATA; + + /* Reset the retransmission timer. */ + uip_connr->timer = uip_connr->rto; + + /* Reset length of outstanding data. */ + uip_connr->len = 0; + } + } + + /* Do different things depending on in what state the connection is. */ + switch( uip_connr->tcpstateflags & UIP_TS_MASK ) + { + /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not + implemented, since we force the application to close when the + peer sends a FIN (hence the application goes directly from + ESTABLISHED to LAST_ACK). */ + case UIP_SYN_RCVD: + /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and + we are waiting for an ACK that acknowledges the data we sent + out the last time. Therefore, we want to have the UIP_ACKDATA + flag set. If so, we enter the ESTABLISHED state. */ + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_ESTABLISHED; + uip_flags = UIP_CONNECTED; + uip_connr->len = 0; + if( uip_len > 0 ) + { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt( uip_len ); + } + + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + + goto drop; + + #if UIP_ACTIVE_OPEN + case UIP_SYN_SENT: + /* In SYN_SENT, we wait for a SYNACK that is sent in response to + our SYN. The rcv_nxt is set to sequence number in the SYNACK + plus one, and we send an ACK. We move into the ESTABLISHED + state. */ + if( (uip_flags & UIP_ACKDATA) && (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK) ) + { + /* Parse the TCP MSS option, if present. */ + if( (BUF->tcpoffset & 0xf0) > 0x50 ) + { + for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; ) + { + opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c]; + if( opt == TCP_OPT_END ) + { + /* End of options. */ + break; + } + else if( opt == TCP_OPT_NOOP ) + { + ++c; + + /* NOP option. */ + } + else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN ) + { + /* An MSS option with the right option length. */ + tmp16 = ( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16; + + /* And we are done processing options. */ + break; + } + else + { + /* All other options have a length field, so that we easily + can skip past them. */ + if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 ) + { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + uip_connr->tcpstateflags = UIP_ESTABLISHED; + uip_connr->rcv_nxt[ 0 ] = BUF->seqno[ 0 ]; + uip_connr->rcv_nxt[ 1 ] = BUF->seqno[ 1 ]; + uip_connr->rcv_nxt[ 2 ] = BUF->seqno[ 2 ]; + uip_connr->rcv_nxt[ 3 ] = BUF->seqno[ 3 ]; + uip_add_rcv_nxt( 1 ); + uip_flags = UIP_CONNECTED | UIP_NEWDATA; + uip_connr->len = 0; + uip_len = 0; + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + + /* Inform the application that the connection failed */ + uip_flags = UIP_ABORT; + UIP_APPCALL(); + + /* The connection is closed after we send the RST */ + uip_conn->tcpstateflags = UIP_CLOSED; + goto reset; + #endif /* UIP_ACTIVE_OPEN */ + + case UIP_ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application to feed + data into the uip_buf. If the UIP_ACKDATA flag is set, the + application should put new data into the buffer, otherwise we are + retransmitting an old segment, and the application should put that + data into the buffer. + + If the incoming packet is a FIN, we should close the connection on + this side as well, and we send out a FIN and enter the LAST_ACK + state. We require that there is no outstanding data; otherwise the + sequence numbers will be screwed up. */ + if( BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED) ) + { + if( uip_outstanding(uip_connr) ) + { + goto drop; + } + + uip_add_rcv_nxt( 1 + uip_len ); + uip_flags |= UIP_CLOSE; + if( uip_len > 0 ) + { + uip_flags |= UIP_NEWDATA; + } + + UIP_APPCALL(); + uip_connr->len = 1; + uip_connr->tcpstateflags = UIP_LAST_ACK; + uip_connr->nrtx = 0; + tcp_send_finack: + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* Check the URG flag. If this is set, the segment carries urgent + data that we must pass to the application. */ + if( (BUF->flags & TCP_URG) != 0 ) + { + #if UIP_URGDATA > 0 + uip_urglen = ( BUF->urgp[ 0 ] << 8 ) | BUF->urgp[ 1 ]; + if( uip_urglen > uip_len ) + { + /* There is more urgent data in the next segment to come. */ + uip_urglen = uip_len; + } + + uip_add_rcv_nxt( uip_urglen ); + uip_len -= uip_urglen; + uip_urgdata = uip_appdata; + uip_appdata += uip_urglen; + } + else + { + uip_urglen = 0; + #else /* UIP_URGDATA > 0 */ + uip_appdata = ( ( char * ) uip_appdata ) + ( (BUF->urgp[ 0 ] << 8) | BUF->urgp[ 1 ] ); + uip_len -= ( BUF->urgp[ 0 ] << 8 ) | BUF->urgp[ 1 ]; + #endif /* UIP_URGDATA > 0 */ + } + + /* If uip_len > 0 we have TCP data in the packet, and we flag this + by setting the UIP_NEWDATA flag and update the sequence number + we acknowledge. If the application has stopped the dataflow + using uip_stop(), we must not accept any data packets from the + remote host. */ + if( uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED) ) + { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt( uip_len ); + } + + /* Check if the available buffer space advertised by the other end + is smaller than the initial MSS for this connection. If so, we + set the current MSS to the window size to ensure that the + application does not send more data than the other end can + handle. + + If the remote host advertises a zero window, we set the MSS to + the initial MSS so that the application will send an entire MSS + of data. This data will not be acknowledged by the receiver, + and the application will retransmit it. This is called the + "persistent timer" and uses the retransmission mechanim. + */ + tmp16 = ( (u16_t) BUF->wnd[ 0 ] << 8 ) + ( u16_t ) BUF->wnd[ 1 ]; + if( tmp16 > uip_connr->initialmss || tmp16 == 0 ) + { + tmp16 = uip_connr->initialmss; + } + + uip_connr->mss = tmp16; + + /* If this packet constitutes an ACK for outstanding data (flagged + by the UIP_ACKDATA flag, we should call the application since it + might want to send more data. If the incoming packet had data + from the peer (as flagged by the UIP_NEWDATA flag), the + application must also be notified. + + When the application is called, the global variable uip_len + contains the length of the incoming data. The application can + access the incoming data through the global pointer + uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN + bytes into the uip_buf array. + + If the application wishes to send any data, this data should be + put into the uip_appdata and the length of the data should be + put into uip_len. If the application don't have any data to + send, uip_len must be set to 0. */ + if( uip_flags & (UIP_NEWDATA | UIP_ACKDATA) ) + { + uip_slen = 0; + UIP_APPCALL(); + +appsend: + if( uip_flags & UIP_ABORT ) + { + uip_slen = 0; + uip_connr->tcpstateflags = UIP_CLOSED; + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + if( uip_flags & UIP_CLOSE ) + { + uip_slen = 0; + uip_connr->len = 1; + uip_connr->tcpstateflags = UIP_FIN_WAIT_1; + uip_connr->nrtx = 0; + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* If uip_slen > 0, the application has data to be sent. */ + if( uip_slen > 0 ) + { + /* If the connection has acknowledged data, the contents of + the ->len variable should be discarded. */ + if( (uip_flags & UIP_ACKDATA) != 0 ) + { + uip_connr->len = 0; + } + + /* If the ->len variable is non-zero the connection has + already data in transit and cannot send anymore right + now. */ + if( uip_connr->len == 0 ) + { + /* The application cannot send more than what is allowed by + the mss (the minumum of the MSS and the available + window). */ + if( uip_slen > uip_connr->mss ) + { + uip_slen = uip_connr->mss; + } + + /* Remember how much data we send out now so that we know + when everything has been acknowledged. */ + uip_connr->len = uip_slen; + } + else + { + /* If the application already had unacknowledged data, we + make sure that the application does not send (i.e., + retransmit) out more than it previously sent out. */ + uip_slen = uip_connr->len; + } + } + + uip_connr->nrtx = 0; +apprexmit: + uip_appdata = uip_sappdata; + + /* If the application has data to be sent, or if the incoming + packet had new data in it, we must send out a packet. */ + if( uip_slen > 0 && uip_connr->len > 0 ) + { + /* Add the length of the IP and TCP headers. */ + uip_len = uip_connr->len + UIP_TCPIP_HLEN; + + /* We always set the ACK flag in response packets. */ + BUF->flags = TCP_ACK | TCP_PSH; + + /* Send the packet. */ + goto tcp_send_noopts; + } + + /* If there is no data to send, just send out a pure ACK if + there is newdata. */ + if( uip_flags & UIP_NEWDATA ) + { + uip_len = UIP_TCPIP_HLEN; + BUF->flags = TCP_ACK; + goto tcp_send_noopts; + } + } + + goto drop; + + case UIP_LAST_ACK: + /* We can close this connection if the peer has acknowledged our + FIN. This is indicated by the UIP_ACKDATA flag. */ + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_CLOSED; + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + } + + break; + + case UIP_FIN_WAIT_1: + /* The application has closed the connection, but the remote host + hasn't closed its end yet. Thus we do nothing but wait for a + FIN from the other side. */ + if( uip_len > 0 ) + { + uip_add_rcv_nxt( uip_len ); + } + + if( BUF->flags & TCP_FIN ) + { + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + uip_connr->len = 0; + } + else + { + uip_connr->tcpstateflags = UIP_CLOSING; + } + + uip_add_rcv_nxt( 1 ); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + else if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_FIN_WAIT_2; + uip_connr->len = 0; + goto drop; + } + + if( uip_len > 0 ) + { + goto tcp_send_ack; + } + + goto drop; + + case UIP_FIN_WAIT_2: + if( uip_len > 0 ) + { + uip_add_rcv_nxt( uip_len ); + } + + if( BUF->flags & TCP_FIN ) + { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + uip_add_rcv_nxt( 1 ); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + + if( uip_len > 0 ) + { + goto tcp_send_ack; + } + + goto drop; + + case UIP_TIME_WAIT: + goto tcp_send_ack; + + case UIP_CLOSING: + if( uip_flags & UIP_ACKDATA ) + { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + } + } + + goto drop; + + /* We jump here when we are ready to send the packet, and just want + to set the appropriate TCP sequence numbers in the TCP header. */ +tcp_send_ack: + BUF->flags = TCP_ACK; + +tcp_send_nodata: + uip_len = UIP_IPTCPH_LEN; + +tcp_send_noopts: + BUF->tcpoffset = ( UIP_TCPH_LEN / 4 ) << 4; + + /* We're done with the input processing. We are now ready to send a + reply. Our job is to fill in all the fields of the TCP and IP + headers before calculating the checksum and finally send the + packet. */ +tcp_send: + BUF->ackno[ 0 ] = uip_connr->rcv_nxt[ 0 ]; + BUF->ackno[ 1 ] = uip_connr->rcv_nxt[ 1 ]; + BUF->ackno[ 2 ] = uip_connr->rcv_nxt[ 2 ]; + BUF->ackno[ 3 ] = uip_connr->rcv_nxt[ 3 ]; + + BUF->seqno[ 0 ] = uip_connr->snd_nxt[ 0 ]; + BUF->seqno[ 1 ] = uip_connr->snd_nxt[ 1 ]; + BUF->seqno[ 2 ] = uip_connr->snd_nxt[ 2 ]; + BUF->seqno[ 3 ] = uip_connr->snd_nxt[ 3 ]; + + BUF->proto = UIP_PROTO_TCP; + + BUF->srcport = uip_connr->lport; + BUF->destport = uip_connr->rport; + + uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr ); + uip_ipaddr_copy( &BUF->destipaddr, &uip_connr->ripaddr ); + + if( uip_connr->tcpstateflags & UIP_STOPPED ) + { + /* If the connection has issued uip_stop(), we advertise a zero + window so that the remote host will stop sending data. */ + BUF->wnd[ 0 ] = BUF->wnd[ 1 ] = 0; + } + else + { + BUF->wnd[ 0 ] = ( (UIP_RECEIVE_WINDOW) >> 8 ); + BUF->wnd[ 1 ] = ( (UIP_RECEIVE_WINDOW) & 0xff ); + } + +tcp_send_noconn: + + BUF->ttl = UIP_TTL; + + #if UIP_CONF_IPV6 + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[ 0 ] = ( (uip_len - UIP_IPH_LEN) >> 8 ); + BUF->len[ 1 ] = ( (uip_len - UIP_IPH_LEN) & 0xff ); + #else /* UIP_CONF_IPV6 */ + BUF->len[ 0 ] = ( uip_len >> 8 ); + BUF->len[ 1 ] = ( uip_len & 0xff ); + #endif /* UIP_CONF_IPV6 */ + + BUF->urgp[ 0 ] = BUF->urgp[ 1 ] = 0; + + /* Calculate TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~( uip_tcpchksum() ); + +ip_send_nolen: + #if UIP_CONF_IPV6 + BUF->vtc = 0x60; + BUF->tcflow = 0x00; + BUF->flow = 0x00; + #else /* UIP_CONF_IPV6 */ + BUF->vhl = 0x45; + BUF->tos = 0; + BUF->ipoffset[ 0 ] = BUF->ipoffset[ 1 ] = 0; + ++ipid; + BUF->ipid[ 0 ] = ipid >> 8; + BUF->ipid[ 1 ] = ipid & 0xff; + + /* Calculate IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~( uip_ipchksum() ); + + //DEBUG_PRINTF( "uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum() ); + #endif /* UIP_CONF_IPV6 */ + + UIP_STAT( ++uip_stat.tcp.sent ); + + #if UIP_CONF_IPV6 +send : + #endif /* UIP_CONF_IPV6 */ + + //DEBUG_PRINTF( "Sending packet with length %d (%d)\n", uip_len, (BUF->len[ 0 ] << 8) | BUF->len[ 1 ] ); + UIP_STAT( ++uip_stat.ip.sent ); + + /* Return and let the caller do the actual transmission. */ + uip_flags = 0; + return; + +drop: + uip_len = 0; + uip_flags = 0; + return; +} +/*---------------------------------------------------------------------------*/ + +u16_t htons( u16_t val ) +{ + return HTONS( val ); +} + +u32_t htonl( u32_t val ) +{ + return HTONL( val ); +} +/*---------------------------------------------------------------------------*/ + +void uip_send( const void *data, int len ) +{ + int copylen; + + #define MIN( a, b ) ( (a) < (b) ? (a) : (b) ) + + copylen = MIN( len, UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN - ( int ) + (( char * ) uip_sappdata - ( char * ) &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN]) ); + if( copylen > 0 ) + { + uip_slen = copylen; + if( data != uip_sappdata ) + { + memcpy( uip_sappdata, (data), uip_slen ); + } + } +} +/*---------------------------------------------------------------------------*/ + +/** @} */ +#endif /* UIP_CONF_IPV6 */ diff --git a/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip_arp.c b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip_arp.c new file mode 100644 index 0000000..ab84419 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip_arp.c @@ -0,0 +1,475 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uiparp uIP Address Resolution Protocol + * @{ + * + * The Address Resolution Protocol ARP is used for mapping between IP + * addresses and link level addresses such as the Ethernet MAC + * addresses. ARP uses broadcast queries to ask for the link level + * address of a known IP address and the host which is configured with + * the IP address for which the query was meant, will respond with its + * link level address. + * + * \note This ARP implementation only supports Ethernet. + */ + +/** + * \file + * Implementation of the ARP Address Resolution Protocol. + * \author Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.c,v 1.5 2008/02/07 01:35:00 adamdunkels Exp $ + * + */ +#include "net/uip_arp.h" + +#include + +#include "net/pack_struct_start.h" +struct arp_hdr +{ + struct uip_eth_hdr ethhdr; + u16_t hwtype; + u16_t protocol; + u8_t hwlen; + u8_t protolen; + u16_t opcode; + struct uip_eth_addr shwaddr; + uip_ipaddr_t sipaddr; + struct uip_eth_addr dhwaddr; + uip_ipaddr_t dipaddr; +} + +#include "net/pack_struct_end.h" + +#include "net/pack_struct_start.h" + +struct ethip_hdr +{ + struct uip_eth_hdr ethhdr; + + /* IP header. */ + u8_t vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto; + u16_t ipchksum; + uip_ipaddr_t srcipaddr, destipaddr; +} + +#include "net/pack_struct_end.h" + +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARP_HWTYPE_ETH 1 + +struct arp_entry +{ + uip_ipaddr_t ipaddr; + struct uip_eth_addr ethaddr; + u8_t time; +}; + +static const struct uip_eth_addr broadcast_ethaddr = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; + +static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; +static uip_ipaddr_t ipaddr; +static u8_t i, c; + +static u8_t arptime; +static u8_t tmpage; + +#define BUF ( ( struct arp_hdr * ) &uip_buf[0] ) +#define IPBUF ( ( struct ethip_hdr * ) &uip_buf[0] ) + +#ifdef DEBUG + #undef DEBUG +#endif +#define DEBUG 0 +#if DEBUG +#include +#define PRINTF( ... ) printf( __VA_ARGS__ ) +#else + +//#define PRINTF( ... ) +#endif + +/*-----------------------------------------------------------------------------------*/ + +/** + * Initialize the ARP module. + * + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_init( void ) +{ + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + memset( &arp_table[i].ipaddr, 0, 4 ); + } +} + +/*-----------------------------------------------------------------------------------*/ + +/** + * Periodic ARP processing function. + * + * This function performs periodic timer processing in the ARP module + * and should be called at regular intervals. The recommended interval + * is 10 seconds between the calls. + * + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_timer( void ) +{ + struct arp_entry *tabptr; + + ++arptime; + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( uip_ipaddr_cmp(&tabptr->ipaddr, &uip_all_zeroes_addr) && arptime - tabptr->time >= UIP_ARP_MAXAGE ) + { + memset( &tabptr->ipaddr, 0, 4 ); + } + } +} + +/*-----------------------------------------------------------------------------------*/ +static void uip_arp_update( uip_ipaddr_t *ipaddr, struct uip_eth_addr *ethaddr ) +{ + register struct arp_entry *tabptr; + + /* Walk through the ARP mapping table and try to find an entry to + update. If none is found, the IP -> MAC address mapping is + inserted in the ARP table. */ + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + + /* Only check those entries that are actually in use. */ + if( !uip_ipaddr_cmp(&tabptr->ipaddr, &uip_all_zeroes_addr) ) + { + /* Check if the source IP address of the incoming packet matches + the IP address in this ARP table entry. */ + if( uip_ipaddr_cmp(ipaddr, &tabptr->ipaddr) ) + { + /* An old entry found, update this and return. */ + memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 ); + tabptr->time = arptime; + + return; + } + } + } + + /* If we get here, no existing ARP table entry was found, so we + create one. */ + + /* First, we try to find an unused entry in the ARP table. */ + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( uip_ipaddr_cmp(&tabptr->ipaddr, &uip_all_zeroes_addr) ) + { + break; + } + } + + /* If no unused entry is found, we try to find the oldest entry and + throw it away. */ + if( i == UIP_ARPTAB_SIZE ) + { + tmpage = 0; + c = 0; + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( arptime - tabptr->time > tmpage ) + { + tmpage = arptime - tabptr->time; + c = i; + } + } + + i = c; + tabptr = &arp_table[i]; + } + + /* Now, i is the ARP table entry which we will fill with the new + information. */ + uip_ipaddr_copy( &tabptr->ipaddr, ipaddr ); + memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 ); + tabptr->time = arptime; +} + +/*-----------------------------------------------------------------------------------*/ + +/** + * ARP processing for incoming IP packets + * + * This function should be called by the device driver when an IP + * packet has been received. The function will check if the address is + * in the ARP cache, and if so the ARP cache entry will be + * refreshed. If no ARP cache entry was found, a new one is created. + * + * This function expects an IP packet with a prepended Ethernet header + * in the uip_buf[] buffer, and the length of the packet in the global + * variable uip_len. + */ + +/*-----------------------------------------------------------------------------------*/ +#if 0 +void uip_arp_ipin( void ) +{ + uip_len -= sizeof( struct uip_eth_hdr ); + + /* Only insert/update an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + if( (IPBUF->srcipaddr[0] & uip_netmask[0]) != (uip_hostaddr[0] & uip_netmask[0]) ) + { + return; + } + + if( (IPBUF->srcipaddr[1] & uip_netmask[1]) != (uip_hostaddr[1] & uip_netmask[1]) ) + { + return; + } + + uip_arp_update( IPBUF->srcipaddr, &(IPBUF->ethhdr.src) ); + + return; +} + +#endif /* 0 */ + +/*-----------------------------------------------------------------------------------*/ + +/** + * ARP processing for incoming ARP packets. + * + * This function should be called by the device driver when an ARP + * packet has been received. The function will act differently + * depending on the ARP packet type: if it is a reply for a request + * that we previously sent out, the ARP cache will be filled in with + * the values from the ARP reply. If the incoming ARP packet is an ARP + * request for our IP address, an ARP reply packet is created and put + * into the uip_buf[] buffer. + * + * When the function returns, the value of the global variable uip_len + * indicates whether the device driver should send out a packet or + * not. If uip_len is zero, no packet should be sent. If uip_len is + * non-zero, it contains the length of the outbound packet that is + * present in the uip_buf[] buffer. + * + * This function expects an ARP packet with a prepended Ethernet + * header in the uip_buf[] buffer, and the length of the packet in the + * global variable uip_len. + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_arpin( void ) +{ + if( uip_len < sizeof(struct arp_hdr) ) + { + uip_len = 0; + return; + } + + uip_len = 0; + + switch( BUF->opcode ) + { + case HTONS( ARP_REQUEST ): + /* ARP request. If it asked for our address, we send out a + reply. */ + + /* if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) {*/ + + //PRINTF( "uip_arp_arpin: request for %d.%d.%d.%d (we are %d.%d.%d.%d)\n", BUF->dipaddr.u8[0], BUF->dipaddr.u8[1], BUF->dipaddr.u8[2], + //BUF->dipaddr.u8[3], uip_hostaddr.u8[0], uip_hostaddr.u8[1], uip_hostaddr.u8[2], uip_hostaddr.u8[3] ); + if( uip_ipaddr_cmp(&BUF->dipaddr, &uip_hostaddr) ) + { + /* First, we register the one who made the request in our ARP + table, since it is likely that we will do more communication + with this host in the future. */ + uip_arp_update( &BUF->sipaddr, &BUF->shwaddr ); + + BUF->opcode = HTONS( ARP_REPLY ); + + memcpy( BUF->dhwaddr.addr, BUF->shwaddr.addr, 6 ); + memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 ); + memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 ); + memcpy( BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6 ); + + uip_ipaddr_copy( &BUF->dipaddr, &BUF->sipaddr ); + uip_ipaddr_copy( &BUF->sipaddr, &uip_hostaddr ); + + BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP ); + uip_len = sizeof( struct arp_hdr ); + } + + break; + + case HTONS( ARP_REPLY ): + /* ARP reply. We insert or update the ARP table if it was meant + for us. */ + if( uip_ipaddr_cmp(&BUF->dipaddr, &uip_hostaddr) ) + { + uip_arp_update( &BUF->sipaddr, &BUF->shwaddr ); + } + + break; + } + + return; +} + +/*-----------------------------------------------------------------------------------*/ + +/** + * Prepend Ethernet header to an outbound IP packet and see if we need + * to send out an ARP request. + * + * This function should be called before sending out an IP packet. The + * function checks the destination IP address of the IP packet to see + * what Ethernet MAC address that should be used as a destination MAC + * address on the Ethernet. + * + * If the destination IP address is in the local network (determined + * by logical ANDing of netmask and our IP address), the function + * checks the ARP cache to see if an entry for the destination IP + * address is found. If so, an Ethernet header is prepended and the + * function returns. If no ARP cache entry is found for the + * destination IP address, the packet in the uip_buf[] is replaced by + * an ARP request packet for the IP address. The IP packet is dropped + * and it is assumed that they higher level protocols (e.g., TCP) + * eventually will retransmit the dropped packet. + * + * If the destination IP address is not on the local network, the IP + * address of the default router is used instead. + * + * When the function returns, a packet is present in the uip_buf[] + * buffer, and the length of the packet is in the global variable + * uip_len. + */ + +/*-----------------------------------------------------------------------------------*/ +void uip_arp_out( void ) +{ + struct arp_entry *tabptr; + + /* Find the destination IP address in the ARP table and construct + the Ethernet header. If the destination IP addres isn't on the + local network, we use the default router's IP address instead. + + If not ARP table entry is found, we overwrite the original IP + packet with an ARP request for the IP address. */ + + /* First check if destination is a local broadcast. */ + if( uip_ipaddr_cmp(&IPBUF->destipaddr, &uip_broadcast_addr) ) + { + memcpy( IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6 ); + } + else + { + /* Check if the destination address is on the local network. */ + if( !uip_ipaddr_maskcmp(&IPBUF->destipaddr, &uip_hostaddr, &uip_netmask) ) + { + /* Destination address was not on the local network, so we need to + use the default router's IP address instead of the destination + address when determining the MAC address. */ + uip_ipaddr_copy( &ipaddr, &uip_draddr ); + } + else + { + /* Else, we use the destination IP address. */ + uip_ipaddr_copy( &ipaddr, &IPBUF->destipaddr ); + } + + for( i = 0; i < UIP_ARPTAB_SIZE; ++i ) + { + tabptr = &arp_table[i]; + if( uip_ipaddr_cmp(&ipaddr, &tabptr->ipaddr) ) + { + break; + } + } + + if( i == UIP_ARPTAB_SIZE ) + { + /* The destination address was not in our ARP table, so we + overwrite the IP packet with an ARP request. */ + memset( BUF->ethhdr.dest.addr, 0xff, 6 ); + memset( BUF->dhwaddr.addr, 0x00, 6 ); + memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 ); + memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 ); + + uip_ipaddr_copy( &BUF->dipaddr, &ipaddr ); + uip_ipaddr_copy( &BUF->sipaddr, &uip_hostaddr ); + BUF->opcode = HTONS( ARP_REQUEST ); /* ARP request. */ + BUF->hwtype = HTONS( ARP_HWTYPE_ETH ); + BUF->protocol = HTONS( UIP_ETHTYPE_IP ); + BUF->hwlen = 6; + BUF->protolen = 4; + BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP ); + + uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN]; + + uip_len = sizeof( struct arp_hdr ); + return; + } + + /* Build an ethernet header. */ + memcpy( IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6 ); + } + + memcpy( IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6 ); + + IPBUF->ethhdr.type = HTONS( UIP_ETHTYPE_IP ); + + uip_len += sizeof( struct uip_eth_hdr ); +} + +/*-----------------------------------------------------------------------------------*/ + +/** @} */ + +/** @} */ diff --git a/third_party/FreeRTOS/Demo/Common/include/AltBlckQ.h b/third_party/FreeRTOS/Demo/Common/include/AltBlckQ.h new file mode 100644 index 0000000..490d74b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/AltBlckQ.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef ALT_BLOCK_Q_H +#define ALT_BLOCK_Q_H + +void vStartAltBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreAltBlockingQueuesStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/AltBlock.h b/third_party/FreeRTOS/Demo/Common/include/AltBlock.h new file mode 100644 index 0000000..e0373a6 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/AltBlock.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FAST_BLOCK_TIME_TEST_H +#define FAST_BLOCK_TIME_TEST_H + +void vCreateAltBlockTimeTasks( void ); +portBASE_TYPE xAreAltBlockTimeTestTasksStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/AltPollQ.h b/third_party/FreeRTOS/Demo/Common/include/AltPollQ.h new file mode 100644 index 0000000..62e5e0b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/AltPollQ.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef ALT_POLLED_Q_H +#define ALT_POLLED_Q_H + +void vStartAltPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreAltPollingQueuesStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/AltQTest.h b/third_party/FreeRTOS/Demo/Common/include/AltQTest.h new file mode 100644 index 0000000..afa00dc --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/AltQTest.h @@ -0,0 +1,75 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FAST_GEN_Q_TEST_H +#define FAST_GEN_Q_TEST_H + +void vStartAltGenericQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreAltGenericQueueTasksStillRunning( void ); + +#endif /* GEN_Q_TEST_H */ + + + diff --git a/third_party/FreeRTOS/Demo/Common/include/BlockQ.h b/third_party/FreeRTOS/Demo/Common/include/BlockQ.h new file mode 100644 index 0000000..d82bd93 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/BlockQ.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef BLOCK_Q_H +#define BLOCK_Q_H + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreBlockingQueuesStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/GenQTest.h b/third_party/FreeRTOS/Demo/Common/include/GenQTest.h new file mode 100644 index 0000000..eedbe67 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/GenQTest.h @@ -0,0 +1,75 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef GEN_Q_TEST_H +#define GEN_Q_TEST_H + +void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreGenericQueueTasksStillRunning( void ); + +#endif /* GEN_Q_TEST_H */ + + + diff --git a/third_party/FreeRTOS/Demo/Common/include/IntQueue.h b/third_party/FreeRTOS/Demo/Common/include/IntQueue.h new file mode 100644 index 0000000..01ba70a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/IntQueue.h @@ -0,0 +1,80 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef QUEUE_ACCESS_TEST +#define QUEUE_ACCESS_TEST + +void vStartInterruptQueueTasks( void ); +portBASE_TYPE xAreIntQueueTasksStillRunning( void ); +portBASE_TYPE xFirstTimerHandler( void ); +portBASE_TYPE xSecondTimerHandler( void ); + +#endif /* QUEUE_ACCESS_TEST */ + + + + + + diff --git a/third_party/FreeRTOS/Demo/Common/include/PollQ.h b/third_party/FreeRTOS/Demo/Common/include/PollQ.h new file mode 100644 index 0000000..3cb3636 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/PollQ.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef POLLED_Q_H +#define POLLED_Q_H + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xArePollingQueuesStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/QPeek.h b/third_party/FreeRTOS/Demo/Common/include/QPeek.h new file mode 100644 index 0000000..4a6e55a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/QPeek.h @@ -0,0 +1,75 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef Q_PEEK_TEST_H +#define Q_PEEK_TEST_H + +void vStartQueuePeekTasks( void ); +portBASE_TYPE xAreQueuePeekTasksStillRunning( void ); + +#endif /* Q_PEEK_TEST_H */ + + + diff --git a/third_party/FreeRTOS/Demo/Common/include/TimerDemo.h b/third_party/FreeRTOS/Demo/Common/include/TimerDemo.h new file mode 100644 index 0000000..21f5b00 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/TimerDemo.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef TIMER_DEMO_H +#define TIMER_DEMO_H + +void vStartTimerDemoTask( portTickType xBaseFrequencyIn ); +portBASE_TYPE xAreTimerDemoTasksStillRunning( portTickType xCycleFrequency ); +void vTimerPeriodicISRTests( void ); + +#endif /* TIMER_DEMO_H */ + + + diff --git a/third_party/FreeRTOS/Demo/Common/include/blocktim.h b/third_party/FreeRTOS/Demo/Common/include/blocktim.h new file mode 100644 index 0000000..73ff61b --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/blocktim.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef BLOCK_TIME_TEST_H +#define BLOCK_TIME_TEST_H + +void vCreateBlockTimeTasks( void ); +portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/comtest.h b/third_party/FreeRTOS/Demo/Common/include/comtest.h new file mode 100644 index 0000000..7bb5074 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/comtest.h @@ -0,0 +1,75 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED ); +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); +void vComTestUnsuspendTask( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/comtest2.h b/third_party/FreeRTOS/Demo/Common/include/comtest2.h new file mode 100644 index 0000000..7392535 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/comtest2.h @@ -0,0 +1,73 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/comtest_strings.h b/third_party/FreeRTOS/Demo/Common/include/comtest_strings.h new file mode 100644 index 0000000..63835aa --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/comtest_strings.h @@ -0,0 +1,73 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef COMTEST_STRINGS_H +#define COMTEST_STRINGS_H + +void vStartComTestStringsTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/countsem.h b/third_party/FreeRTOS/Demo/Common/include/countsem.h new file mode 100644 index 0000000..d955f59 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/countsem.h @@ -0,0 +1,73 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef COUNT_SEMAPHORE_TEST_H +#define COUNT_SEMAPHORE_TEST_H + +void vStartCountingSemaphoreTasks( void ); +portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/crflash.h b/third_party/FreeRTOS/Demo/Common/include/crflash.h new file mode 100644 index 0000000..0c2f1f9 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/crflash.h @@ -0,0 +1,85 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef CRFLASH_LED_H +#define CRFLASH_LED_H + +/* + * Create the co-routines used to flash the LED's at different rates. + * + * @param uxPriority The number of 'fixed delay' co-routines to create. This + * also effects the number of LED's that will be utilised. For example, + * passing in 3 will cause LED's 0 to 2 to be utilised. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxPriority ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/crhook.h b/third_party/FreeRTOS/Demo/Common/include/crhook.h new file mode 100644 index 0000000..a032d0f --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/crhook.h @@ -0,0 +1,81 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef CRHOOK_H +#define CRHOOK_H + +/* + * Create the co-routines used to communicate wit the tick hook. + */ +void vStartHookCoRoutines( void ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +portBASE_TYPE xAreHookCoRoutinesStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/death.h b/third_party/FreeRTOS/Demo/Common/include/death.h new file mode 100644 index 0000000..6dc6e07 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/death.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef SUICIDE_TASK_H +#define SUICIDE_TASK_H + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xIsCreateTaskStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/dynamic.h b/third_party/FreeRTOS/Demo/Common/include/dynamic.h new file mode 100644 index 0000000..eb3681d --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/dynamic.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef DYNAMIC_MANIPULATION_H +#define DYNAMIC_MANIPULATION_H + +void vStartDynamicPriorityTasks( void ); +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/fileIO.h b/third_party/FreeRTOS/Demo/Common/include/fileIO.h new file mode 100644 index 0000000..ce2080a --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/fileIO.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FILE_IO_H +#define FILE_OI_H + +void vDisplayMessage( const char * const pcMessageToPrint ); +void vWriteMessageToDisk( const char * const pcMessage ); +void vWriteBufferToDisk( const char * const pcBuffer, unsigned long ulBufferLength ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/flash.h b/third_party/FreeRTOS/Demo/Common/include/flash.h new file mode 100644 index 0000000..0d56ee1 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/flash.h @@ -0,0 +1,72 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FLASH_LED_H +#define FLASH_LED_H + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/flash_timer.h b/third_party/FreeRTOS/Demo/Common/include/flash_timer.h new file mode 100644 index 0000000..92be478 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/flash_timer.h @@ -0,0 +1,79 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FLASH_TIMER_H +#define FLASH_TIMER_H + +/* + * Creates the LED flashing timers. xNumberOfLEDs specifies how many timers to + * create, with each timer toggling a different LED. The first LED to be + * toggled is LED 0, with subsequent LEDs following on in numerical order. Each + * timer uses the exact same callback function, with the timer ID being used + * within the callback function to determine which timer has actually expired + * (and therefore which LED to toggle). + */ +void vStartLEDFlashTimers( unsigned portBASE_TYPE uxNumberOfLEDs ); + +#endif /* FLASH_TIMER_H */ diff --git a/third_party/FreeRTOS/Demo/Common/include/flop.h b/third_party/FreeRTOS/Demo/Common/include/flop.h new file mode 100644 index 0000000..de23659 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/flop.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FLOP_TASKS_H +#define FLOP_TASKS_H + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreMathsTaskStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/integer.h b/third_party/FreeRTOS/Demo/Common/include/integer.h new file mode 100644 index 0000000..d7d62e5 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/integer.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INTEGER_TASKS_H +#define INTEGER_TASKS_H + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/mevents.h b/third_party/FreeRTOS/Demo/Common/include/mevents.h new file mode 100644 index 0000000..01f3118 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/mevents.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef EVENTS_TEST_H +#define EVENTS_TEST_H + +void vStartMultiEventTasks( void ); +portBASE_TYPE xAreMultiEventTasksStillRunning( void ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/partest.h b/third_party/FreeRTOS/Demo/Common/include/partest.h new file mode 100644 index 0000000..461e7f8 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/partest.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PARTEST_H +#define PARTEST_H + +#define partstDEFAULT_PORT_ADDRESS ( ( unsigned short ) 0x378 ) + +void vParTestInitialise( void ); +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ); +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/print.h b/third_party/FreeRTOS/Demo/Common/include/print.h new file mode 100644 index 0000000..0f79fce --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/print.h @@ -0,0 +1,75 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PRINT_H +#define PRINT_H + +void vPrintInitialise( void ); +void vPrintDisplayMessage( const char * const * pcMessageToSend ); +const char *pcPrintGetNextMessage( portTickType xPrintRate ); + +#endif + + diff --git a/third_party/FreeRTOS/Demo/Common/include/recmutex.h b/third_party/FreeRTOS/Demo/Common/include/recmutex.h new file mode 100644 index 0000000..d9745c0 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/recmutex.h @@ -0,0 +1,73 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef RECURSIVE_MUTEX_TEST_H +#define RECURSIVE_MUTEX_TEST_H + +void vStartRecursiveMutexTasks( void ); +portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/semtest.h b/third_party/FreeRTOS/Demo/Common/include/semtest.h new file mode 100644 index 0000000..0fbcbb2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/semtest.h @@ -0,0 +1,73 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef SEMAPHORE_TEST_H +#define SEMAPHORE_TEST_H + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/Common/include/serial.h b/third_party/FreeRTOS/Demo/Common/include/serial.h new file mode 100644 index 0000000..eccffc2 --- /dev/null +++ b/third_party/FreeRTOS/Demo/Common/include/serial.h @@ -0,0 +1,136 @@ +/* + FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef SERIAL_COMMS_H +#define SERIAL_COMMS_H + +typedef void * xComPortHandle; + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ); +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength ); +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime ); +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime ); +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); +void vSerialClose( xComPortHandle xPort ); + +#endif + diff --git a/third_party/FreeRTOS/Demo/readme.txt b/third_party/FreeRTOS/Demo/readme.txt new file mode 100644 index 0000000..813c257 --- /dev/null +++ b/third_party/FreeRTOS/Demo/readme.txt @@ -0,0 +1,16 @@ +Each RTOS port has a demo application to demonstrate it's use. + ++ The Demo/Common directory contains the demo application files as described on +the http://www.FreeRTOS.org WEB site. Each file creates one or more tasks. +The files in the Demo/Common directory are used by every demo application for +every port. + ++ All the other directories contain a project or makefile for the demo +application targeted at a particular microcontroller. + + +For example, if you are interested in the ATMega323 demo application for +the WinAVR tools then the AVR_ATMega323_WinAVR directory contains the +relevant makefile. The makefile includes files from the Demo/ATMega323 +and the Demo/Common directories. If this is the only port you are +interested in then all the other directories can be ignored. -- cgit v1.3.1