From c3e4c9a25c2910d2d66d52215b3406b13d5b23d5 Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Sun, 29 Jun 2014 12:34:32 +0300 Subject: Add more board models --- boards/ek-lm4f232/interrupts/Makefile | 87 +++ boards/ek-lm4f232/interrupts/ccs/.ccsimportspec | 8 + boards/ek-lm4f232/interrupts/ccs/.ccsproject | 10 + boards/ek-lm4f232/interrupts/ccs/.cproject | 191 +++++ boards/ek-lm4f232/interrupts/ccs/.project | 55 ++ .../ccs/.settings/org.eclipse.cdt.codan.core.prefs | 3 + .../ek-lm4f232/interrupts/ccs/Debug/interrupts.bin | Bin 0 -> 6904 bytes .../ek-lm4f232/interrupts/ccs/Debug/interrupts.out | Bin 0 -> 127672 bytes .../ek-lm4f232/interrupts/ccs/macros.ini_initial | 1 + .../ek-lm4f232/interrupts/ccs/target_config.ccxml | 13 + .../ek-lm4f232/interrupts/ewarm/Exe/interrupts.bin | Bin 0 -> 6020 bytes .../ek-lm4f232/interrupts/ewarm/Exe/interrupts.out | Bin 0 -> 106732 bytes boards/ek-lm4f232/interrupts/gcc/interrupts.axf | Bin 0 -> 69084 bytes boards/ek-lm4f232/interrupts/gcc/interrupts.bin | Bin 0 -> 6327 bytes boards/ek-lm4f232/interrupts/interrupts.c | 592 +++++++++++++++ boards/ek-lm4f232/interrupts/interrupts.ewd | 614 ++++++++++++++++ boards/ek-lm4f232/interrupts/interrupts.ewp | 792 +++++++++++++++++++++ boards/ek-lm4f232/interrupts/interrupts.icf | 78 ++ boards/ek-lm4f232/interrupts/interrupts.ld | 57 ++ boards/ek-lm4f232/interrupts/interrupts.sct | 47 ++ boards/ek-lm4f232/interrupts/interrupts.uvopt | 317 +++++++++ boards/ek-lm4f232/interrupts/interrupts.uvproj | 434 +++++++++++ boards/ek-lm4f232/interrupts/interrupts_ccs.cmd | 70 ++ boards/ek-lm4f232/interrupts/readme.txt | 33 + boards/ek-lm4f232/interrupts/rvmdk/interrupts.axf | Bin 0 -> 118404 bytes boards/ek-lm4f232/interrupts/rvmdk/interrupts.bin | Bin 0 -> 6336 bytes boards/ek-lm4f232/interrupts/startup_ccs.c | 304 ++++++++ boards/ek-lm4f232/interrupts/startup_ewarm.c | 335 +++++++++ boards/ek-lm4f232/interrupts/startup_gcc.c | 351 +++++++++ boards/ek-lm4f232/interrupts/startup_rvmdk.S | 360 ++++++++++ 30 files changed, 4752 insertions(+) create mode 100644 boards/ek-lm4f232/interrupts/Makefile create mode 100644 boards/ek-lm4f232/interrupts/ccs/.ccsimportspec create mode 100644 boards/ek-lm4f232/interrupts/ccs/.ccsproject create mode 100644 boards/ek-lm4f232/interrupts/ccs/.cproject create mode 100644 boards/ek-lm4f232/interrupts/ccs/.project create mode 100644 boards/ek-lm4f232/interrupts/ccs/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.bin create mode 100644 boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.out create mode 100644 boards/ek-lm4f232/interrupts/ccs/macros.ini_initial create mode 100644 boards/ek-lm4f232/interrupts/ccs/target_config.ccxml create mode 100644 boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.bin create mode 100644 boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.out create mode 100644 boards/ek-lm4f232/interrupts/gcc/interrupts.axf create mode 100644 boards/ek-lm4f232/interrupts/gcc/interrupts.bin create mode 100644 boards/ek-lm4f232/interrupts/interrupts.c create mode 100644 boards/ek-lm4f232/interrupts/interrupts.ewd create mode 100644 boards/ek-lm4f232/interrupts/interrupts.ewp create mode 100644 boards/ek-lm4f232/interrupts/interrupts.icf create mode 100644 boards/ek-lm4f232/interrupts/interrupts.ld create mode 100644 boards/ek-lm4f232/interrupts/interrupts.sct create mode 100644 boards/ek-lm4f232/interrupts/interrupts.uvopt create mode 100644 boards/ek-lm4f232/interrupts/interrupts.uvproj create mode 100644 boards/ek-lm4f232/interrupts/interrupts_ccs.cmd create mode 100644 boards/ek-lm4f232/interrupts/readme.txt create mode 100644 boards/ek-lm4f232/interrupts/rvmdk/interrupts.axf create mode 100644 boards/ek-lm4f232/interrupts/rvmdk/interrupts.bin create mode 100644 boards/ek-lm4f232/interrupts/startup_ccs.c create mode 100644 boards/ek-lm4f232/interrupts/startup_ewarm.c create mode 100644 boards/ek-lm4f232/interrupts/startup_gcc.c create mode 100644 boards/ek-lm4f232/interrupts/startup_rvmdk.S (limited to 'boards/ek-lm4f232/interrupts') diff --git a/boards/ek-lm4f232/interrupts/Makefile b/boards/ek-lm4f232/interrupts/Makefile new file mode 100644 index 0000000..309d7f6 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/Makefile @@ -0,0 +1,87 @@ +#****************************************************************************** +# +# Makefile - Rules for building the interrupts example. +# +# Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +# +#****************************************************************************** + +# +# Defines the part type that this project uses. +# +PART=TM4C123GH6PGE + +# +# The base directory for TivaWare. +# +ROOT=../../../.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find source files that do not live in this directory. +# +VPATH=../drivers + +# +# Where to find header files that do not live in the source directory. +# +IPATH=.. +IPATH+=../../../.. + +# +# The default rule, which causes the interrupts example to be built. +# +all: ${COMPILER} +all: ${COMPILER}/interrupts.axf + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}: + @mkdir -p ${COMPILER} + +# +# Rules for building the interrupts example. +# +${COMPILER}/interrupts.axf: ${COMPILER}/cfal96x64x16.o +${COMPILER}/interrupts.axf: ${COMPILER}/interrupts.o +${COMPILER}/interrupts.axf: ${COMPILER}/startup_${COMPILER}.o +${COMPILER}/interrupts.axf: ${ROOT}/grlib/${COMPILER}/libgr.a +${COMPILER}/interrupts.axf: ${ROOT}/driverlib/${COMPILER}/libdriver.a +${COMPILER}/interrupts.axf: interrupts.ld +SCATTERgcc_interrupts=interrupts.ld +ENTRY_interrupts=ResetISR +CFLAGSgcc=-DTARGET_IS_TM4C123_RA1 + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/ek-lm4f232/interrupts/ccs/.ccsimportspec b/boards/ek-lm4f232/interrupts/ccs/.ccsimportspec new file mode 100644 index 0000000..9033256 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/.ccsimportspec @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/boards/ek-lm4f232/interrupts/ccs/.ccsproject b/boards/ek-lm4f232/interrupts/ccs/.ccsproject new file mode 100644 index 0000000..e423367 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/.ccsproject @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/boards/ek-lm4f232/interrupts/ccs/.cproject b/boards/ek-lm4f232/interrupts/ccs/.cproject new file mode 100644 index 0000000..0d7ec51 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/.cproject @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ek-lm4f232/interrupts/ccs/.project b/boards/ek-lm4f232/interrupts/ccs/.project new file mode 100644 index 0000000..3b84e41 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/.project @@ -0,0 +1,55 @@ + + + interrupts + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + interrupts.c + 1 + SW_ROOT/examples/boards/ek-lm4f232/interrupts/interrupts.c + + + interrupts_ccs.cmd + 1 + SW_ROOT/examples/boards/ek-lm4f232/interrupts/interrupts_ccs.cmd + + + startup_ccs.c + 1 + SW_ROOT/examples/boards/ek-lm4f232/interrupts/startup_ccs.c + + + drivers/cfal96x64x16.c + 1 + SW_ROOT/examples/boards/ek-lm4f232/drivers/cfal96x64x16.c + + + + + SW_ROOT + $%7BPARENT-5-PROJECT_LOC%7D + + + diff --git a/boards/ek-lm4f232/interrupts/ccs/.settings/org.eclipse.cdt.codan.core.prefs b/boards/ek-lm4f232/interrupts/ccs/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.bin b/boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.bin new file mode 100644 index 0000000..8dce1f5 Binary files /dev/null and b/boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.bin differ diff --git a/boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.out b/boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.out new file mode 100644 index 0000000..8e38403 Binary files /dev/null and b/boards/ek-lm4f232/interrupts/ccs/Debug/interrupts.out differ diff --git a/boards/ek-lm4f232/interrupts/ccs/macros.ini_initial b/boards/ek-lm4f232/interrupts/ccs/macros.ini_initial new file mode 100644 index 0000000..31214b5 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../../../../.. diff --git a/boards/ek-lm4f232/interrupts/ccs/target_config.ccxml b/boards/ek-lm4f232/interrupts/ccs/target_config.ccxml new file mode 100644 index 0000000..c8d43ba --- /dev/null +++ b/boards/ek-lm4f232/interrupts/ccs/target_config.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.bin b/boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.bin new file mode 100644 index 0000000..3ede8df Binary files /dev/null and b/boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.bin differ diff --git a/boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.out b/boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.out new file mode 100644 index 0000000..6805f74 Binary files /dev/null and b/boards/ek-lm4f232/interrupts/ewarm/Exe/interrupts.out differ diff --git a/boards/ek-lm4f232/interrupts/gcc/interrupts.axf b/boards/ek-lm4f232/interrupts/gcc/interrupts.axf new file mode 100644 index 0000000..d6b412a Binary files /dev/null and b/boards/ek-lm4f232/interrupts/gcc/interrupts.axf differ diff --git a/boards/ek-lm4f232/interrupts/gcc/interrupts.bin b/boards/ek-lm4f232/interrupts/gcc/interrupts.bin new file mode 100644 index 0000000..034d8f2 Binary files /dev/null and b/boards/ek-lm4f232/interrupts/gcc/interrupts.bin differ diff --git a/boards/ek-lm4f232/interrupts/interrupts.c b/boards/ek-lm4f232/interrupts/interrupts.c new file mode 100644 index 0000000..7c340f4 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.c @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// interrupts.c - Interrupt preemption and tail-chaining example. +// +// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/fpu.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" +#include "driverlib/systick.h" +#include "driverlib/sysctl.h" +#include "driverlib/rom.h" +#include "grlib/grlib.h" +#include "drivers/cfal96x64x16.h" + +//***************************************************************************** +// +//! \addtogroup example_list +//!

Interrupts (interrupts)

+//! +//! This example application demonstrates the interrupt preemption and +//! tail-chaining capabilities of Cortex-M4 microprocessor and NVIC. Nested +//! interrupts are synthesized when the interrupts have the same priority, +//! increasing priorities, and decreasing priorities. With increasing +//! priorities, preemption will occur; in the other two cases tail-chaining +//! will occur. The currently pending interrupts and the currently executing +//! interrupt will be displayed on the display; GPIO pins D0, D1 and D2 will +//! be asserted upon interrupt handler entry and de-asserted before interrupt +//! handler exit so that the off-to-on time can be observed with a scope or +//! logic analyzer to see the speed of tail-chaining (for the two cases where +//! tail-chaining is occurring). +// +//***************************************************************************** + +//***************************************************************************** +// +// The count of interrupts received. This is incremented as each interrupt +// handler runs, and its value saved into interrupt handler specific values to +// determine the order in which the interrupt handlers were executed. +// +//***************************************************************************** +volatile uint32_t g_ui32Index; + +//***************************************************************************** +// +// The value of g_ui32Index when the INT_GPIOA interrupt was processed. +// +//***************************************************************************** +volatile uint32_t g_ui32GPIOa; + +//***************************************************************************** +// +// The value of g_ui32Index when the INT_GPIOB interrupt was processed. +// +//***************************************************************************** +volatile uint32_t g_ui32GPIOb; + +//***************************************************************************** +// +// The value of g_ui32Index when the INT_GPIOC interrupt was processed. +// +//***************************************************************************** +volatile uint32_t g_ui32GPIOc; + +//***************************************************************************** +// +// Graphics context used to show text on the CSTN display. +// +//***************************************************************************** +tContext g_sContext; + +//***************************************************************************** +// +// The error routine that is called if the driver library encounters an error. +// +//***************************************************************************** +#ifdef DEBUG +void +__error__(char *pcFilename, uint32_t ui32Line) +{ +} +#endif + +//***************************************************************************** +// +// Delay for the specified number of seconds. Depending upon the current +// SysTick value, the delay will be between N-1 and N seconds (i.e. N-1 full +// seconds are guaranteed, along with the remainder of the current second). +// +//***************************************************************************** +void +Delay(uint32_t ui32Seconds) +{ + // + // Loop while there are more seconds to wait. + // + while(ui32Seconds--) + { + // + // Wait until the SysTick value is less than 1000. + // + while(ROM_SysTickValueGet() > 1000) + { + } + + // + // Wait until the SysTick value is greater than 1000. + // + while(ROM_SysTickValueGet() < 1000) + { + } + } +} + +//***************************************************************************** +// +// Display the interrupt state on the CSTN. The currently active and pending +// interrupts are displayed. +// +//***************************************************************************** +void +DisplayIntStatus(void) +{ + uint32_t ui32Temp; + char pcBuffer[6]; + + // + // Display the currently active interrupts. + // + ui32Temp = HWREG(NVIC_ACTIVE0); + pcBuffer[0] = ' '; + pcBuffer[1] = (ui32Temp & 1) ? '1' : ' '; + pcBuffer[2] = (ui32Temp & 2) ? '2' : ' '; + pcBuffer[3] = (ui32Temp & 4) ? '3' : ' '; + pcBuffer[4] = ' '; + pcBuffer[5] = '\0'; + GrStringDraw(&g_sContext, pcBuffer, -1, 48, 32, 1); + + // + // Display the currently pending interrupts. + // + ui32Temp = HWREG(NVIC_PEND0); + pcBuffer[1] = (ui32Temp & 1) ? '1' : ' '; + pcBuffer[2] = (ui32Temp & 2) ? '2' : ' '; + pcBuffer[3] = (ui32Temp & 4) ? '3' : ' '; + GrStringDraw(&g_sContext, pcBuffer, -1, 48, 44, 1); + + // + // Flush the display. + // + GrFlush(&g_sContext); +} + +//***************************************************************************** +// +// This is the handler for INT_GPIOA. It simply saves the interrupt sequence +// number. +// +//***************************************************************************** +void +IntGPIOa(void) +{ + // + // Set PB3 high to indicate entry to this interrupt handler. + // + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, GPIO_PIN_0); + + // + // Put the current interrupt state on the display. + // + DisplayIntStatus(); + + // + // Wait two seconds. + // + Delay(2); + + // + // Save and increment the interrupt sequence number. + // + g_ui32GPIOa = g_ui32Index++; + + // + // Set PB3 low to indicate exit from this interrupt handler. + // + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, 0); +} + +//***************************************************************************** +// +// This is the handler for INT_GPIOB. It triggers INT_GPIOA and saves the +// interrupt sequence number. +// +//***************************************************************************** +void +IntGPIOb(void) +{ + // + // Set PF2 high to indicate entry to this interrupt handler. + // + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, GPIO_PIN_1); + + // + // Put the current interrupt state on the display. + // + DisplayIntStatus(); + + // + // Trigger the INT_GPIOA interrupt. + // + HWREG(NVIC_SW_TRIG) = INT_GPIOA - 16; + + // + // Put the current interrupt state on the display. + // + DisplayIntStatus(); + + // + // Wait two seconds. + // + Delay(2); + + // + // Save and increment the interrupt sequence number. + // + g_ui32GPIOb = g_ui32Index++; + + // + // Set PDF2 low to indicate exit from this interrupt handler. + // + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, 0); +} + +//***************************************************************************** +// +// This is the handler for INT_GPIOC. It triggers INT_GPIOB and saves the +// interrupt sequence number. +// +//***************************************************************************** +void +IntGPIOc(void) +{ + // + // Set PF3 high to indicate entry to this interrupt handler. + // + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, GPIO_PIN_2); + + // + // Put the current interrupt state on the display. + // + DisplayIntStatus(); + + // + // Trigger the INT_GPIOB interrupt. + // + HWREG(NVIC_SW_TRIG) = INT_GPIOB - 16; + + // + // Put the current interrupt state on the display. + // + DisplayIntStatus(); + + // + // Wait two seconds. + // + Delay(2); + + // + // Save and increment the interrupt sequence number. + // + g_ui32GPIOc = g_ui32Index++; + + // + // Set PF3 low to indicate exit from this interrupt handler. + // + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, 0); +} + +//***************************************************************************** +// +// This is the main example program. It checks to see that the interrupts are +// processed in the correct order when they have identical priorities, +// increasing priorities, and decreasing priorities. This exercises interrupt +// preemption and tail chaining. +// +//***************************************************************************** +int +main(void) +{ + tRectangle sRect; + uint_fast8_t ui8Error; + + // + // Enable lazy stacking for interrupt handlers. This allows floating-point + // instructions to be used within interrupt handlers, but at the expense of + // extra stack usage. + // + ROM_FPULazyStackingEnable(); + + // + // Set the clocking to run directly from the crystal. + // + ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | + SYSCTL_XTAL_16MHZ); + + // + // Enable the peripherals used by this example. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + + // + // Initialize the display driver. + // + CFAL96x64x16Init(); + + // + // Initialize the graphics context and find the middle X coordinate. + // + GrContextInit(&g_sContext, &g_sCFAL96x64x16); + + // + // Fill the top part of the screen with blue to create the banner. + // + sRect.i16XMin = 0; + sRect.i16YMin = 0; + sRect.i16XMax = GrContextDpyWidthGet(&g_sContext) - 1; + sRect.i16YMax = 9; + GrContextForegroundSet(&g_sContext, ClrDarkBlue); + GrRectFill(&g_sContext, &sRect); + + // + // Change foreground for white text. + // + GrContextForegroundSet(&g_sContext, ClrWhite); + + // + // Put the application name in the middle of the banner. + // + GrContextFontSet(&g_sContext, g_psFontFixed6x8); + GrStringDrawCentered(&g_sContext, "interrupts", -1, + GrContextDpyWidthGet(&g_sContext) / 2, 4, 0); + GrContextFontSet(&g_sContext, g_psFontFixed6x8); + + // + // Put the status header text on the display. + // + GrStringDraw(&g_sContext, "Active:", -1, 6, 32, 0); + GrStringDraw(&g_sContext, "Pending:", -1, 0, 44, 0); + + // + // Configure the PB0-PB2 to be outputs to indicate entry/exit of one + // of the interrupt handlers. + // + ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | + GPIO_PIN_3); + ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, 0); + + // + // Set up and enable the SysTick timer. It will be used as a reference + // for delay loops in the interrupt handlers. The SysTick timer period + // will be set up for one second. + // + ROM_SysTickPeriodSet(ROM_SysCtlClockGet()); + ROM_SysTickEnable(); + + // + // Reset the error indicator. + // + ui8Error = 0; + + // + // Enable interrupts to the processor. + // + ROM_IntMasterEnable(); + + // + // Enable the interrupts. + // + ROM_IntEnable(INT_GPIOA); + ROM_IntEnable(INT_GPIOB); + ROM_IntEnable(INT_GPIOC); + + // + // Indicate that the equal interrupt priority test is beginning. + // + GrStringDrawCentered(&g_sContext, "Equal Pri", -1, + GrContextDpyWidthGet(&g_sContext) / 2, 20, 1); + + // + // Set the interrupt priorities so they are all equal. + // + ROM_IntPrioritySet(INT_GPIOA, 0x00); + ROM_IntPrioritySet(INT_GPIOB, 0x00); + ROM_IntPrioritySet(INT_GPIOC, 0x00); + + // + // Reset the interrupt flags. + // + g_ui32GPIOa = 0; + g_ui32GPIOb = 0; + g_ui32GPIOc = 0; + g_ui32Index = 1; + + // + // Trigger the interrupt for GPIO C. + // + HWREG(NVIC_SW_TRIG) = INT_GPIOC - 16; + + // + // Put the current interrupt state on the LCD. + // + DisplayIntStatus(); + + // + // Verify that the interrupts were processed in the correct order. + // + if((g_ui32GPIOa != 3) || (g_ui32GPIOb != 2) || (g_ui32GPIOc != 1)) + { + ui8Error |= 1; + } + + // + // Wait two seconds. + // + Delay(2); + + // + // Indicate that the decreasing interrupt priority test is beginning. + // + GrStringDrawCentered(&g_sContext, " Decreasing Pri ", -1, + GrContextDpyWidthGet(&g_sContext) / 2, 20, 1); + + // + // Set the interrupt priorities so that they are decreasing (i.e. C > B > + // A). + // + ROM_IntPrioritySet(INT_GPIOA, 0x80); + ROM_IntPrioritySet(INT_GPIOB, 0x40); + ROM_IntPrioritySet(INT_GPIOC, 0x00); + + // + // Reset the interrupt flags. + // + g_ui32GPIOa = 0; + g_ui32GPIOb = 0; + g_ui32GPIOc = 0; + g_ui32Index = 1; + + // + // Trigger the interrupt for GPIO C. + // + HWREG(NVIC_SW_TRIG) = INT_GPIOC - 16; + + // + // Put the current interrupt state on the CSTN. + // + DisplayIntStatus(); + + // + // Verify that the interrupts were processed in the correct order. + // + if((g_ui32GPIOa != 3) || (g_ui32GPIOb != 2) || (g_ui32GPIOc != 1)) + { + ui8Error |= 2; + } + + // + // Wait two seconds. + // + Delay(2); + + // + // Indicate that the increasing interrupt priority test is beginning. + // + GrStringDrawCentered(&g_sContext, " Increasing Pri ", -1, + GrContextDpyWidthGet(&g_sContext) / 2, 20, 1); + + // + // Set the interrupt priorities so that they are increasing (i.e. C < B < + // A). + // + ROM_IntPrioritySet(INT_GPIOA, 0x00); + ROM_IntPrioritySet(INT_GPIOB, 0x40); + ROM_IntPrioritySet(INT_GPIOC, 0x80); + + // + // Reset the interrupt flags. + // + g_ui32GPIOa = 0; + g_ui32GPIOb = 0; + g_ui32GPIOc = 0; + g_ui32Index = 1; + + // + // Trigger the interrupt for GPIO C. + // + HWREG(NVIC_SW_TRIG) = INT_GPIOC - 16; + + // + // Put the current interrupt state on the CSTN. + // + DisplayIntStatus(); + + // + // Verify that the interrupts were processed in the correct order. + // + if((g_ui32GPIOa != 1) || (g_ui32GPIOb != 2) || (g_ui32GPIOc != 3)) + { + ui8Error |= 4; + } + + // + // Wait two seconds. + // + Delay(2); + + // + // Disable the interrupts. + // + ROM_IntDisable(INT_GPIOA); + ROM_IntDisable(INT_GPIOB); + ROM_IntDisable(INT_GPIOC); + + // + // Disable interrupts to the processor. + // + ROM_IntMasterDisable(); + + // + // Print out results if error occurred. + // + if(ui8Error) + { + GrStringDraw(&g_sContext, "Equal: P ", -1, 0, 32, 1); + GrStringDraw(&g_sContext, " Inc: P ", -1, 0, 44, 1); + GrStringDraw(&g_sContext, " Dec: P ", -1, 0, 56, 1); + if(ui8Error & 1) + { + GrStringDraw(&g_sContext, "F ", -1, 42, 32, 1); + } + if(ui8Error & 2) + { + GrStringDraw(&g_sContext, "F ", -1, 42, 44, 1); + } + if(ui8Error & 4) + { + GrStringDraw(&g_sContext, "F ", -1, 42, 56, 1); + } + } + else + { + GrStringDrawCentered(&g_sContext, " Success! ", -1, + GrContextDpyWidthGet(&g_sContext) / 2, 20, 1); + } + + // + // Flush the display. + // + GrFlush(&g_sContext); + + // + // Loop forever. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f232/interrupts/interrupts.ewd b/boards/ek-lm4f232/interrupts/interrupts.ewd new file mode 100644 index 0000000..5e62dcd --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.ewd @@ -0,0 +1,614 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + diff --git a/boards/ek-lm4f232/interrupts/interrupts.ewp b/boards/ek-lm4f232/interrupts/interrupts.ewp new file mode 100644 index 0000000..249a1a6 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.ewp @@ -0,0 +1,792 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Libraries + + $PROJ_DIR$\..\..\..\..\driverlib\ewarm\Exe\driverlib.a + + + $PROJ_DIR$\..\..\..\..\grlib\ewarm\Exe\grlib.a + + + + Source + + $PROJ_DIR$\..\drivers\cfal96x64x16.c + + + $PROJ_DIR$\interrupts.c + + + $PROJ_DIR$\startup_ewarm.c + + + diff --git a/boards/ek-lm4f232/interrupts/interrupts.icf b/boards/ek-lm4f232/interrupts/interrupts.icf new file mode 100644 index 0000000..e2f1200 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.icf @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// interrupts.icf - Linker configuration file for interrupts. +// +// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0003ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20007fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Indicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place the RAM vector table at the start of SRAM. +// +place at start of SRAM { section VTABLE }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/boards/ek-lm4f232/interrupts/interrupts.ld b/boards/ek-lm4f232/interrupts/interrupts.ld new file mode 100644 index 0000000..5ce7cad --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.ld @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * interrupts.ld - Linker configuration file for interrupts. + * + * Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/ek-lm4f232/interrupts/interrupts.sct b/boards/ek-lm4f232/interrupts/interrupts.sct new file mode 100644 index 0000000..4950f23 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.sct @@ -0,0 +1,47 @@ +;****************************************************************************** +; +; interrupts.sct - Linker configuration file for interrupts. +; +; Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +; +;****************************************************************************** + +LR_IROM 0x00000000 0x00040000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00040000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00008000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} diff --git a/boards/ek-lm4f232/interrupts/interrupts.uvopt b/boards/ek-lm4f232/interrupts/interrupts.uvopt new file mode 100644 index 0000000..9742887 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.uvopt @@ -0,0 +1,317 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + interrupts + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\TM4C123GH6PGE.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4614 -S3 -FO29 + + + 0 + DLGTARM + + + + 0 + ARMDBGFLAGS + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\cfal96x64x16.c + cfal96x64x16.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\interrupts.c + interrupts.c + + + 1 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_rvmdk.S + startup_rvmdk.S + + + + + Libraries + 1 + 0 + 0 + + 2 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + driverlib.lib + + + 2 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\grlib\rvmdk\grlib.lib + grlib.lib + + + + + Documentation + 1 + 0 + 0 + + 3 + 6 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/boards/ek-lm4f232/interrupts/interrupts.uvproj b/boards/ek-lm4f232/interrupts/interrupts.uvproj new file mode 100644 index 0000000..c645e5b --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts.uvproj @@ -0,0 +1,434 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + interrupts + 0x4 + ARM-ADS + + + TM4C123GH6PGE + Texas Instruments + IRAM(0x20000000-0x20007FFF) IROM(0-0x3FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_256 -FS00 -FL040000) + 5919 + LM4Fxxxx.H + + + + + + + + + + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk\ + interrupts + 1 + 0 + 0 + 1 + 1 + .\rvmdk\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\rvmdk\interrupts.bin .\rvmdk\interrupts.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 4 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + --c99 + rvmdk PART_TM4C123GH6PGE TARGET_IS_TM4C123_RA1 + + ..;..\..\..\..; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + interrupts.sct + + + --entry Reset_Handler + + + + + + + + Source + + + cfal96x64x16.c + 1 + ..\drivers\cfal96x64x16.c + + + interrupts.c + 1 + .\interrupts.c + + + startup_rvmdk.S + 2 + .\startup_rvmdk.S + + + + + Libraries + + + driverlib.lib + 4 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + + + grlib.lib + 4 + ..\..\..\..\grlib\rvmdk\grlib.lib + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/boards/ek-lm4f232/interrupts/interrupts_ccs.cmd b/boards/ek-lm4f232/interrupts/interrupts_ccs.cmd new file mode 100644 index 0000000..1cb0583 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/interrupts_ccs.cmd @@ -0,0 +1,70 @@ +/****************************************************************************** + * + * interrupts_ccs.cmd - CCS linker configuration file for interrupts. + * + * Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. + * + *****************************************************************************/ + +--retain=g_pfnVectors + +/* The following command line options are set as part of the CCS project. */ +/* If you are building using the command line, or for some reason want to */ +/* define them here, you can uncomment and modify these lines as needed. */ +/* If you are using CCS for building, it is probably better to make any such */ +/* modifications in your CCS project and leave this file alone. */ +/* */ +/* --heap_size=0 */ +/* --stack_size=256 */ +/* --library=rtsv7M3_T_le_eabi.lib */ + +/* The starting address of the application. Normally the interrupt vectors */ +/* must be located at the beginning of the application. */ +#define APP_BASE 0x00000000 +#define RAM_BASE 0x20000000 + +/* System memory map */ + +MEMORY +{ + /* Application stored in and executes from internal flash */ + FLASH (RX) : origin = APP_BASE, length = 0x00040000 + /* Application uses internal RAM for data */ + SRAM (RWX) : origin = 0x20000000, length = 0x00008000 +} + +/* Section allocation in memory */ + +SECTIONS +{ + .intvecs: > APP_BASE + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .vtable : > RAM_BASE + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} + +__STACK_TOP = __stack + 1024; diff --git a/boards/ek-lm4f232/interrupts/readme.txt b/boards/ek-lm4f232/interrupts/readme.txt new file mode 100644 index 0000000..98658da --- /dev/null +++ b/boards/ek-lm4f232/interrupts/readme.txt @@ -0,0 +1,33 @@ +Interrupts + +This example application demonstrates the interrupt preemption and +tail-chaining capabilities of Cortex-M4 microprocessor and NVIC. Nested +interrupts are synthesized when the interrupts have the same priority, +increasing priorities, and decreasing priorities. With increasing +priorities, preemption will occur; in the other two cases tail-chaining +will occur. The currently pending interrupts and the currently executing +interrupt will be displayed on the display; GPIO pins D0, D1 and D2 will +be asserted upon interrupt handler entry and de-asserted before interrupt +handler exit so that the off-to-on time can be observed with a scope or +logic analyzer to see the speed of tail-chaining (for the two cases where +tail-chaining is occurring). + +------------------------------------------------------------------------------- + +Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + +Texas Instruments (TI) is supplying this software for use solely and +exclusively on TI's microcontroller products. The software is owned by +TI and/or its suppliers, and is protected under applicable copyright +laws. You may not combine this software with "viral" open-source +software in order to form a larger program. + +THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, FOR ANY REASON WHATSOEVER. + +This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. diff --git a/boards/ek-lm4f232/interrupts/rvmdk/interrupts.axf b/boards/ek-lm4f232/interrupts/rvmdk/interrupts.axf new file mode 100644 index 0000000..8c8789b Binary files /dev/null and b/boards/ek-lm4f232/interrupts/rvmdk/interrupts.axf differ diff --git a/boards/ek-lm4f232/interrupts/rvmdk/interrupts.bin b/boards/ek-lm4f232/interrupts/rvmdk/interrupts.bin new file mode 100644 index 0000000..72077ec Binary files /dev/null and b/boards/ek-lm4f232/interrupts/rvmdk/interrupts.bin differ diff --git a/boards/ek-lm4f232/interrupts/startup_ccs.c b/boards/ek-lm4f232/interrupts/startup_ccs.c new file mode 100644 index 0000000..284673a --- /dev/null +++ b/boards/ek-lm4f232/interrupts/startup_ccs.c @@ -0,0 +1,304 @@ +//***************************************************************************** +// +// startup_ccs.c - Startup code for use with TI's Code Composer Studio. +// +// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern uint32_t __STACK_TOP; + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void IntGPIOa(void); +extern void IntGPIOb(void); +extern void IntGPIOc(void); + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".intvecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)&__STACK_TOP), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntGPIOa, // GPIO Port A + IntGPIOb, // GPIO Port B + IntGPIOc, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Jump to the CCS C initialization routine. This will enable the + // floating-point unit as well, so that does not need to be done here. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f232/interrupts/startup_ewarm.c b/boards/ek-lm4f232/interrupts/startup_ewarm.c new file mode 100644 index 0000000..88d0875 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/startup_ewarm.c @@ -0,0 +1,335 @@ +//***************************************************************************** +// +// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, +// version 5. +// +// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void IntGPIOa(void); +extern void IntGPIOb(void); +extern void IntGPIOc(void); + +//***************************************************************************** +// +// The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[256] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + uint32_t ui32Ptr; +} +uVectorEntry; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntGPIOa, // GPIO Port A + IntGPIOb, // GPIO Port B + IntGPIOc, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + __iar_program_start(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f232/interrupts/startup_gcc.c b/boards/ek-lm4f232/interrupts/startup_gcc.c new file mode 100644 index 0000000..7e22222 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/startup_gcc.c @@ -0,0 +1,351 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void IntGPIOa(void); +extern void IntGPIOb(void); +extern void IntGPIOc(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[256]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntGPIOa, // GPIO Port A + IntGPIOb, // GPIO Port B + IntGPIOc, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _etext; +extern uint32_t _data; +extern uint32_t _edata; +extern uint32_t _bss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + uint32_t *pui32Src, *pui32Dest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pui32Src = &_etext; + for(pui32Dest = &_data; pui32Dest < &_edata; ) + { + *pui32Dest++ = *pui32Src++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f232/interrupts/startup_rvmdk.S b/boards/ek-lm4f232/interrupts/startup_rvmdk.S new file mode 100644 index 0000000..77598e3 --- /dev/null +++ b/boards/ek-lm4f232/interrupts/startup_rvmdk.S @@ -0,0 +1,360 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the EK-LM4F232 Firmware Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000400 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; External declarations for the interrupt handlers used by the application. +; +;****************************************************************************** + EXTERN IntGPIOa + EXTERN IntGPIOb + EXTERN IntGPIOc + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; The MPU fault handler + DCD IntDefaultHandler ; The bus fault handler + DCD IntDefaultHandler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall handler + DCD IntDefaultHandler ; Debug monitor handler + DCD 0 ; Reserved + DCD IntDefaultHandler ; The PendSV handler + DCD IntDefaultHandler ; The SysTick handler + DCD IntGPIOa ; GPIO Port A + DCD IntGPIOb ; GPIO Port B + DCD IntGPIOc ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD IntDefaultHandler ; UART0 Rx and Tx + DCD IntDefaultHandler ; UART1 Rx and Tx + DCD IntDefaultHandler ; SSI0 Rx and Tx + DCD IntDefaultHandler ; I2C0 Master and Slave + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder 0 + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog timer + DCD IntDefaultHandler ; Timer 0 subtimer A + DCD IntDefaultHandler ; Timer 0 subtimer B + DCD IntDefaultHandler ; Timer 1 subtimer A + DCD IntDefaultHandler ; Timer 1 subtimer B + DCD IntDefaultHandler ; Timer 2 subtimer A + DCD IntDefaultHandler ; Timer 2 subtimer B + DCD IntDefaultHandler ; Analog Comparator 0 + DCD IntDefaultHandler ; Analog Comparator 1 + DCD IntDefaultHandler ; Analog Comparator 2 + DCD IntDefaultHandler ; System Control (PLL, OSC, BO) + DCD IntDefaultHandler ; FLASH Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; Quadrature Encoder 1 + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + DCD IntDefaultHandler ; ADC1 Sequence 0 + DCD IntDefaultHandler ; ADC1 Sequence 1 + DCD IntDefaultHandler ; ADC1 Sequence 2 + DCD IntDefaultHandler ; ADC1 Sequence 3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; GPIO Port J + DCD IntDefaultHandler ; GPIO Port K + DCD IntDefaultHandler ; GPIO Port L + DCD IntDefaultHandler ; SSI2 Rx and Tx + DCD IntDefaultHandler ; SSI3 Rx and Tx + DCD IntDefaultHandler ; UART3 Rx and Tx + DCD IntDefaultHandler ; UART4 Rx and Tx + DCD IntDefaultHandler ; UART5 Rx and Tx + DCD IntDefaultHandler ; UART6 Rx and Tx + DCD IntDefaultHandler ; UART7 Rx and Tx + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C2 Master and Slave + DCD IntDefaultHandler ; I2C3 Master and Slave + DCD IntDefaultHandler ; Timer 4 subtimer A + DCD IntDefaultHandler ; Timer 4 subtimer B + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; Timer 5 subtimer A + DCD IntDefaultHandler ; Timer 5 subtimer B + DCD IntDefaultHandler ; Wide Timer 0 subtimer A + DCD IntDefaultHandler ; Wide Timer 0 subtimer B + DCD IntDefaultHandler ; Wide Timer 1 subtimer A + DCD IntDefaultHandler ; Wide Timer 1 subtimer B + DCD IntDefaultHandler ; Wide Timer 2 subtimer A + DCD IntDefaultHandler ; Wide Timer 2 subtimer B + DCD IntDefaultHandler ; Wide Timer 3 subtimer A + DCD IntDefaultHandler ; Wide Timer 3 subtimer B + DCD IntDefaultHandler ; Wide Timer 4 subtimer A + DCD IntDefaultHandler ; Wide Timer 4 subtimer B + DCD IntDefaultHandler ; Wide Timer 5 subtimer A + DCD IntDefaultHandler ; Wide Timer 5 subtimer B + DCD IntDefaultHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C4 Master and Slave + DCD IntDefaultHandler ; I2C5 Master and Slave + DCD IntDefaultHandler ; GPIO Port M + DCD IntDefaultHandler ; GPIO Port N + DCD IntDefaultHandler ; Quadrature Encoder 2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; GPIO Port P (Summary or P0) + DCD IntDefaultHandler ; GPIO Port P1 + DCD IntDefaultHandler ; GPIO Port P2 + DCD IntDefaultHandler ; GPIO Port P3 + DCD IntDefaultHandler ; GPIO Port P4 + DCD IntDefaultHandler ; GPIO Port P5 + DCD IntDefaultHandler ; GPIO Port P6 + DCD IntDefaultHandler ; GPIO Port P7 + DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) + DCD IntDefaultHandler ; GPIO Port Q1 + DCD IntDefaultHandler ; GPIO Port Q2 + DCD IntDefaultHandler ; GPIO Port Q3 + DCD IntDefaultHandler ; GPIO Port Q4 + DCD IntDefaultHandler ; GPIO Port Q5 + DCD IntDefaultHandler ; GPIO Port Q6 + DCD IntDefaultHandler ; GPIO Port Q7 + DCD IntDefaultHandler ; GPIO Port R + DCD IntDefaultHandler ; GPIO Port S + DCD IntDefaultHandler ; PWM 1 Generator 0 + DCD IntDefaultHandler ; PWM 1 Generator 1 + DCD IntDefaultHandler ; PWM 1 Generator 2 + DCD IntDefaultHandler ; PWM 1 Generator 3 + DCD IntDefaultHandler ; PWM 1 Fault + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Enable the floating-point unit. This must be done here to handle the + ; case where main() uses floating-point and the function prologue saves + ; floating-point registers (which will fault if floating-point is not + ; enabled). Any configuration of the floating-point unit using + ; DriverLib APIs must be done here prior to the floating-point unit + ; being enabled. + ; + ; Note that this does not use DriverLib since it might not be included + ; in this project. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END -- cgit v1.3.1