From c3e4c9a25c2910d2d66d52215b3406b13d5b23d5 Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Sun, 29 Jun 2014 12:34:32 +0300 Subject: Add more board models --- boards/dk-tm4c129x/udma_demo/Makefile | 92 ++ boards/dk-tm4c129x/udma_demo/ccs/.ccsimportspec | 8 + boards/dk-tm4c129x/udma_demo/ccs/.ccsproject | 10 + boards/dk-tm4c129x/udma_demo/ccs/.cproject | 182 ++++ boards/dk-tm4c129x/udma_demo/ccs/.project | 75 ++ .../ccs/.settings/org.eclipse.cdt.codan.core.prefs | 3 + .../dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.bin | Bin 0 -> 29592 bytes .../dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.out | Bin 0 -> 237618 bytes .../dk-tm4c129x/udma_demo/ccs/macros.ini_initial | 1 + .../dk-tm4c129x/udma_demo/ccs/target_config.ccxml | 13 + .../dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.bin | Bin 0 -> 27048 bytes .../dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.out | Bin 0 -> 213484 bytes boards/dk-tm4c129x/udma_demo/gcc/udma_demo.axf | Bin 0 -> 67580 bytes boards/dk-tm4c129x/udma_demo/gcc/udma_demo.bin | Bin 0 -> 27904 bytes boards/dk-tm4c129x/udma_demo/readme.txt | 25 + boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.axf | Bin 0 -> 204424 bytes boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.bin | Bin 0 -> 27984 bytes boards/dk-tm4c129x/udma_demo/startup_ccs.c | 278 +++++++ boards/dk-tm4c129x/udma_demo/startup_ewarm.c | 309 +++++++ boards/dk-tm4c129x/udma_demo/startup_gcc.c | 325 ++++++++ boards/dk-tm4c129x/udma_demo/startup_rvmdk.S | 334 ++++++++ boards/dk-tm4c129x/udma_demo/udma_demo.c | 924 +++++++++++++++++++++ boards/dk-tm4c129x/udma_demo/udma_demo.ewd | 614 ++++++++++++++ boards/dk-tm4c129x/udma_demo/udma_demo.ewp | 804 ++++++++++++++++++ boards/dk-tm4c129x/udma_demo/udma_demo.icf | 78 ++ boards/dk-tm4c129x/udma_demo/udma_demo.ld | 57 ++ boards/dk-tm4c129x/udma_demo/udma_demo.sct | 47 ++ boards/dk-tm4c129x/udma_demo/udma_demo.uvopt | 373 +++++++++ boards/dk-tm4c129x/udma_demo/udma_demo.uvproj | 454 ++++++++++ boards/dk-tm4c129x/udma_demo/udma_demo_ccs.cmd | 70 ++ 30 files changed, 5076 insertions(+) create mode 100644 boards/dk-tm4c129x/udma_demo/Makefile create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/.ccsimportspec create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/.ccsproject create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/.cproject create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/.project create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.bin create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.out create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/macros.ini_initial create mode 100644 boards/dk-tm4c129x/udma_demo/ccs/target_config.ccxml create mode 100644 boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.bin create mode 100644 boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.out create mode 100644 boards/dk-tm4c129x/udma_demo/gcc/udma_demo.axf create mode 100644 boards/dk-tm4c129x/udma_demo/gcc/udma_demo.bin create mode 100644 boards/dk-tm4c129x/udma_demo/readme.txt create mode 100644 boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.axf create mode 100644 boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.bin create mode 100644 boards/dk-tm4c129x/udma_demo/startup_ccs.c create mode 100644 boards/dk-tm4c129x/udma_demo/startup_ewarm.c create mode 100644 boards/dk-tm4c129x/udma_demo/startup_gcc.c create mode 100644 boards/dk-tm4c129x/udma_demo/startup_rvmdk.S create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.c create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.ewd create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.ewp create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.icf create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.ld create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.sct create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.uvopt create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo.uvproj create mode 100644 boards/dk-tm4c129x/udma_demo/udma_demo_ccs.cmd (limited to 'boards/dk-tm4c129x/udma_demo') diff --git a/boards/dk-tm4c129x/udma_demo/Makefile b/boards/dk-tm4c129x/udma_demo/Makefile new file mode 100644 index 0000000..d5e1ab9 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/Makefile @@ -0,0 +1,92 @@ +#****************************************************************************** +# +# Makefile - Rules for building the uDMA example. +# +# Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +# +#****************************************************************************** + +# +# Defines the part type that this project uses. +# +PART=TM4C129XNCZAD + +# +# The base directory for TivaWare. +# +ROOT=../../../.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find source files that do not live in this directory. +# +VPATH=../drivers +VPATH+=../../../../utils + +# +# Where to find header files that do not live in the source directory. +# +IPATH=.. +IPATH+=../../../.. + +# +# The default rule, which causes the uDMA example to be built. +# +all: ${COMPILER} +all: ${COMPILER}/udma_demo.axf + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}: + @mkdir -p ${COMPILER} + +# +# Rules for building the uDMA example. +# +${COMPILER}/udma_demo.axf: ${COMPILER}/cpu_usage.o +${COMPILER}/udma_demo.axf: ${COMPILER}/frame.o +${COMPILER}/udma_demo.axf: ${COMPILER}/kentec320x240x16_ssd2119.o +${COMPILER}/udma_demo.axf: ${COMPILER}/pinout.o +${COMPILER}/udma_demo.axf: ${COMPILER}/startup_${COMPILER}.o +${COMPILER}/udma_demo.axf: ${COMPILER}/udma_demo.o +${COMPILER}/udma_demo.axf: ${COMPILER}/ustdlib.o +${COMPILER}/udma_demo.axf: ${ROOT}/grlib/${COMPILER}/libgr.a +${COMPILER}/udma_demo.axf: ${ROOT}/driverlib/${COMPILER}/libdriver.a +${COMPILER}/udma_demo.axf: udma_demo.ld +SCATTERgcc_udma_demo=udma_demo.ld +ENTRY_udma_demo=ResetISR +CFLAGSgcc=-DTARGET_IS_TM4C129_RA0 + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/dk-tm4c129x/udma_demo/ccs/.ccsimportspec b/boards/dk-tm4c129x/udma_demo/ccs/.ccsimportspec new file mode 100644 index 0000000..aea8941 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/.ccsimportspec @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/boards/dk-tm4c129x/udma_demo/ccs/.ccsproject b/boards/dk-tm4c129x/udma_demo/ccs/.ccsproject new file mode 100644 index 0000000..59a3400 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/.ccsproject @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/boards/dk-tm4c129x/udma_demo/ccs/.cproject b/boards/dk-tm4c129x/udma_demo/ccs/.cproject new file mode 100644 index 0000000..1fc0fea --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/.cproject @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/dk-tm4c129x/udma_demo/ccs/.project b/boards/dk-tm4c129x/udma_demo/ccs/.project new file mode 100644 index 0000000..b96b6fa --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/.project @@ -0,0 +1,75 @@ + + + udma_demo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + startup_ccs.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/udma_demo/startup_ccs.c + + + udma_demo.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/udma_demo/udma_demo.c + + + udma_demo_ccs.cmd + 1 + SW_ROOT/examples/boards/dk-tm4c129x/udma_demo/udma_demo_ccs.cmd + + + drivers/frame.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/frame.c + + + drivers/kentec320x240x16_ssd2119.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/kentec320x240x16_ssd2119.c + + + drivers/pinout.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/pinout.c + + + utils/cpu_usage.c + 1 + SW_ROOT/utils/cpu_usage.c + + + utils/ustdlib.c + 1 + SW_ROOT/utils/ustdlib.c + + + + + SW_ROOT + $%7BPARENT-5-PROJECT_LOC%7D + + + diff --git a/boards/dk-tm4c129x/udma_demo/ccs/.settings/org.eclipse.cdt.codan.core.prefs b/boards/dk-tm4c129x/udma_demo/ccs/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.bin b/boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.bin new file mode 100644 index 0000000..5a4d0e2 Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.bin differ diff --git a/boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.out b/boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.out new file mode 100644 index 0000000..861f9b8 Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/ccs/Debug/udma_demo.out differ diff --git a/boards/dk-tm4c129x/udma_demo/ccs/macros.ini_initial b/boards/dk-tm4c129x/udma_demo/ccs/macros.ini_initial new file mode 100644 index 0000000..31214b5 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../../../../.. diff --git a/boards/dk-tm4c129x/udma_demo/ccs/target_config.ccxml b/boards/dk-tm4c129x/udma_demo/ccs/target_config.ccxml new file mode 100644 index 0000000..6e5ef45 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/ccs/target_config.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.bin b/boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.bin new file mode 100644 index 0000000..15c0693 Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.bin differ diff --git a/boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.out b/boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.out new file mode 100644 index 0000000..6a1ef26 Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/ewarm/Exe/udma_demo.out differ diff --git a/boards/dk-tm4c129x/udma_demo/gcc/udma_demo.axf b/boards/dk-tm4c129x/udma_demo/gcc/udma_demo.axf new file mode 100644 index 0000000..a2f9a0d Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/gcc/udma_demo.axf differ diff --git a/boards/dk-tm4c129x/udma_demo/gcc/udma_demo.bin b/boards/dk-tm4c129x/udma_demo/gcc/udma_demo.bin new file mode 100644 index 0000000..9ff4e83 Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/gcc/udma_demo.bin differ diff --git a/boards/dk-tm4c129x/udma_demo/readme.txt b/boards/dk-tm4c129x/udma_demo/readme.txt new file mode 100644 index 0000000..65b5f3d --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/readme.txt @@ -0,0 +1,25 @@ +uDMA + +This example application demonstrates the use of the uDMA controller to +transfer data between memory buffers, and to transfer data to and from a +UART. The test runs for 10 seconds before exiting. + +------------------------------------------------------------------------------- + +Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + +Texas Instruments (TI) is supplying this software for use solely and +exclusively on TI's microcontroller products. The software is owned by +TI and/or its suppliers, and is protected under applicable copyright +laws. You may not combine this software with "viral" open-source +software in order to form a larger program. + +THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, FOR ANY REASON WHATSOEVER. + +This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. diff --git a/boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.axf b/boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.axf new file mode 100644 index 0000000..068386f Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.axf differ diff --git a/boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.bin b/boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.bin new file mode 100644 index 0000000..fe2996c Binary files /dev/null and b/boards/dk-tm4c129x/udma_demo/rvmdk/udma_demo.bin differ diff --git a/boards/dk-tm4c129x/udma_demo/startup_ccs.c b/boards/dk-tm4c129x/udma_demo/startup_ccs.c new file mode 100644 index 0000000..672bdc7 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/startup_ccs.c @@ -0,0 +1,278 @@ +//***************************************************************************** +// +// startup_ccs.c - Startup code for use with TI's Code Composer Studio. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern uint32_t __STACK_TOP; + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void SysTickHandler(void); +extern void UART0IntHandler(void); +extern void uDMAIntHandler(void); +extern void uDMAErrorHandler(void); + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".intvecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)&__STACK_TOP), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + SysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + UART0IntHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + uDMAIntHandler, // uDMA Software Transfer + uDMAErrorHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Jump to the CCS C initialization routine. This will enable the + // floating-point unit as well, so that does not need to be done here. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/udma_demo/startup_ewarm.c b/boards/dk-tm4c129x/udma_demo/startup_ewarm.c new file mode 100644 index 0000000..d0b84b2 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/startup_ewarm.c @@ -0,0 +1,309 @@ +//***************************************************************************** +// +// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, +// version 5. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void SysTickHandler(void); +extern void UART0IntHandler(void); +extern void uDMAIntHandler(void); +extern void uDMAErrorHandler(void); + +//***************************************************************************** +// +// The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[256] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + uint32_t ui32Ptr; +} +uVectorEntry; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + SysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + UART0IntHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + uDMAIntHandler, // uDMA Software Transfer + uDMAErrorHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + __iar_program_start(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/udma_demo/startup_gcc.c b/boards/dk-tm4c129x/udma_demo/startup_gcc.c new file mode 100644 index 0000000..e0eaf61 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/startup_gcc.c @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void SysTickHandler(void); +extern void UART0IntHandler(void); +extern void uDMAIntHandler(void); +extern void uDMAErrorHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[256]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + SysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + UART0IntHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + uDMAIntHandler, // uDMA Software Transfer + uDMAErrorHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _etext; +extern uint32_t _data; +extern uint32_t _edata; +extern uint32_t _bss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + uint32_t *pui32Src, *pui32Dest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pui32Src = &_etext; + for(pui32Dest = &_data; pui32Dest < &_edata; ) + { + *pui32Dest++ = *pui32Src++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/udma_demo/startup_rvmdk.S b/boards/dk-tm4c129x/udma_demo/startup_rvmdk.S new file mode 100644 index 0000000..24c63fd --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/startup_rvmdk.S @@ -0,0 +1,334 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000400 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; External declarations for the interrupt handlers used by the application. +; +;****************************************************************************** + EXTERN SysTickHandler + EXTERN UART0IntHandler + EXTERN uDMAIntHandler + EXTERN uDMAErrorHandler + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; The MPU fault handler + DCD IntDefaultHandler ; The bus fault handler + DCD IntDefaultHandler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall handler + DCD IntDefaultHandler ; Debug monitor handler + DCD 0 ; Reserved + DCD IntDefaultHandler ; The PendSV handler + DCD SysTickHandler ; The SysTick handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD UART0IntHandler ; UART0 Rx and Tx + DCD IntDefaultHandler ; UART1 Rx and Tx + DCD IntDefaultHandler ; SSI0 Rx and Tx + DCD IntDefaultHandler ; I2C0 Master and Slave + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder 0 + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog timer + DCD IntDefaultHandler ; Timer 0 subtimer A + DCD IntDefaultHandler ; Timer 0 subtimer B + DCD IntDefaultHandler ; Timer 1 subtimer A + DCD IntDefaultHandler ; Timer 1 subtimer B + DCD IntDefaultHandler ; Timer 2 subtimer A + DCD IntDefaultHandler ; Timer 2 subtimer B + DCD IntDefaultHandler ; Analog Comparator 0 + DCD IntDefaultHandler ; Analog Comparator 1 + DCD IntDefaultHandler ; Analog Comparator 2 + DCD IntDefaultHandler ; System Control (PLL, OSC, BO) + DCD IntDefaultHandler ; FLASH Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD IntDefaultHandler ; Ethernet + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD uDMAIntHandler ; uDMA Software Transfer + DCD uDMAErrorHandler ; uDMA Error + DCD IntDefaultHandler ; ADC1 Sequence 0 + DCD IntDefaultHandler ; ADC1 Sequence 1 + DCD IntDefaultHandler ; ADC1 Sequence 2 + DCD IntDefaultHandler ; ADC1 Sequence 3 + DCD IntDefaultHandler ; External Bus Interface 0 + DCD IntDefaultHandler ; GPIO Port J + DCD IntDefaultHandler ; GPIO Port K + DCD IntDefaultHandler ; GPIO Port L + DCD IntDefaultHandler ; SSI2 Rx and Tx + DCD IntDefaultHandler ; SSI3 Rx and Tx + DCD IntDefaultHandler ; UART3 Rx and Tx + DCD IntDefaultHandler ; UART4 Rx and Tx + DCD IntDefaultHandler ; UART5 Rx and Tx + DCD IntDefaultHandler ; UART6 Rx and Tx + DCD IntDefaultHandler ; UART7 Rx and Tx + DCD IntDefaultHandler ; I2C2 Master and Slave + DCD IntDefaultHandler ; I2C3 Master and Slave + DCD IntDefaultHandler ; Timer 4 subtimer A + DCD IntDefaultHandler ; Timer 4 subtimer B + DCD IntDefaultHandler ; Timer 5 subtimer A + DCD IntDefaultHandler ; Timer 5 subtimer B + DCD IntDefaultHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C4 Master and Slave + DCD IntDefaultHandler ; I2C5 Master and Slave + DCD IntDefaultHandler ; GPIO Port M + DCD IntDefaultHandler ; GPIO Port N + DCD 0 ; Reserved + DCD IntDefaultHandler ; Tamper + DCD IntDefaultHandler ; GPIO Port P (Summary or P0) + DCD IntDefaultHandler ; GPIO Port P1 + DCD IntDefaultHandler ; GPIO Port P2 + DCD IntDefaultHandler ; GPIO Port P3 + DCD IntDefaultHandler ; GPIO Port P4 + DCD IntDefaultHandler ; GPIO Port P5 + DCD IntDefaultHandler ; GPIO Port P6 + DCD IntDefaultHandler ; GPIO Port P7 + DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) + DCD IntDefaultHandler ; GPIO Port Q1 + DCD IntDefaultHandler ; GPIO Port Q2 + DCD IntDefaultHandler ; GPIO Port Q3 + DCD IntDefaultHandler ; GPIO Port Q4 + DCD IntDefaultHandler ; GPIO Port Q5 + DCD IntDefaultHandler ; GPIO Port Q6 + DCD IntDefaultHandler ; GPIO Port Q7 + DCD IntDefaultHandler ; GPIO Port R + DCD IntDefaultHandler ; GPIO Port S + DCD IntDefaultHandler ; SHA/MD5 0 + DCD IntDefaultHandler ; AES 0 + DCD IntDefaultHandler ; DES3DES 0 + DCD IntDefaultHandler ; LCD Controller 0 + DCD IntDefaultHandler ; Timer 6 subtimer A + DCD IntDefaultHandler ; Timer 6 subtimer B + DCD IntDefaultHandler ; Timer 7 subtimer A + DCD IntDefaultHandler ; Timer 7 subtimer B + DCD IntDefaultHandler ; I2C6 Master and Slave + DCD IntDefaultHandler ; I2C7 Master and Slave + DCD IntDefaultHandler ; HIM Scan Matrix Keyboard 0 + DCD IntDefaultHandler ; One Wire 0 + DCD IntDefaultHandler ; HIM PS/2 0 + DCD IntDefaultHandler ; HIM LED Sequencer 0 + DCD IntDefaultHandler ; HIM Consumer IR 0 + DCD IntDefaultHandler ; I2C8 Master and Slave + DCD IntDefaultHandler ; I2C9 Master and Slave + DCD IntDefaultHandler ; GPIO Port T + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Enable the floating-point unit. This must be done here to handle the + ; case where main() uses floating-point and the function prologue saves + ; floating-point registers (which will fault if floating-point is not + ; enabled). Any configuration of the floating-point unit using + ; DriverLib APIs must be done here prior to the floating-point unit + ; being enabled. + ; + ; Note that this does not use DriverLib since it might not be included + ; in this project. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.c b/boards/dk-tm4c129x/udma_demo/udma_demo.c new file mode 100644 index 0000000..c2293a8 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.c @@ -0,0 +1,924 @@ +//***************************************************************************** +// +// udma_demo.c - uDMA example. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/gpio.h" +#include "driverlib/sysctl.h" +#include "driverlib/systick.h" +#include "driverlib/uart.h" +#include "driverlib/udma.h" +#include "driverlib/interrupt.h" +#include "driverlib/rom.h" +#include "driverlib/rom_map.h" +#include "grlib/grlib.h" +#include "utils/cpu_usage.h" +#include "utils/ustdlib.h" +#include "drivers/kentec320x240x16_ssd2119.h" +#include "drivers/frame.h" +#include "drivers/pinout.h" + +//***************************************************************************** +// +//! \addtogroup example_list +//!

uDMA (udma_demo)

+//! +//! This example application demonstrates the use of the uDMA controller to +//! transfer data between memory buffers, and to transfer data to and from a +//! UART. The test runs for 10 seconds before exiting. +// +//***************************************************************************** + + +//***************************************************************************** +// +// The number of SysTick ticks per second used for the SysTick interrupt. +// +//***************************************************************************** +#define SYSTICKS_PER_SECOND 100 + +//***************************************************************************** +// +// The size of the memory transfer source and destination buffers (in words). +// +//***************************************************************************** +#define MEM_BUFFER_SIZE 1024 + +//***************************************************************************** +// +// The size of the UART transmit and receive buffers. They do not need to be +// the same size. +// +//***************************************************************************** +#define UART_TXBUF_SIZE 256 +#define UART_RXBUF_SIZE 256 + +//***************************************************************************** +// +// The system clock frequency in Hz. +// +//***************************************************************************** +volatile uint32_t g_ui32SysClock; + +//***************************************************************************** +// +// Graphics context used to show text on the CSTN display. +// +//***************************************************************************** +static tContext g_sContext; + +//***************************************************************************** +// +// The source and destination buffers used for memory transfers. +// +//***************************************************************************** +static uint32_t g_ui32SrcBuf[MEM_BUFFER_SIZE]; +static uint32_t g_ui32DstBuf[MEM_BUFFER_SIZE]; + +//***************************************************************************** +// +// The transmit and receive buffers used for the UART transfers. There is one +// transmit buffer and a pair of recieve ping-pong buffers. +// +//***************************************************************************** +static uint8_t g_ui8TxBuf[UART_TXBUF_SIZE]; +static uint8_t g_ui8RxBufA[UART_RXBUF_SIZE]; +static uint8_t g_ui8RxBufB[UART_RXBUF_SIZE]; + +//***************************************************************************** +// +// The count of uDMA errors. This value is incremented by the uDMA error +// handler. +// +//***************************************************************************** +static volatile uint32_t g_ui32uDMAErrCount = 0; + +//***************************************************************************** +// +// The count of times the uDMA interrupt occurred but the uDMA transfer was not +// complete. This should remain 0. +// +//***************************************************************************** +static volatile uint32_t g_ui32BadISR = 0; + +//***************************************************************************** +// +// The count of UART buffers filled, one for each ping-pong buffer. +// +//***************************************************************************** +static volatile uint32_t g_ui32RxBufACount = 0; +static volatile uint32_t g_ui32RxBufBCount = 0; + +//***************************************************************************** +// +// The count of memory uDMA transfer blocks. This value is incremented by the +// uDMA interrupt handler whenever a memory block transfer is completed. +// +//***************************************************************************** +static volatile uint32_t g_ui32MemXferCount = 0; + +//***************************************************************************** +// +// The CPU usage in percent, in 16.16 fixed point format. +// +//***************************************************************************** +static volatile uint32_t g_ui32CPUUsage; + +//***************************************************************************** +// +// The number of seconds elapsed since the start of the program. This value is +// maintained by the SysTick interrupt handler. +// +//***************************************************************************** +static volatile uint32_t g_ui32Seconds = 0; + +//***************************************************************************** +// +// The control table used by the uDMA controller. This table must be aligned +// to a 1024 byte boundary. +// +//***************************************************************************** +#if defined(ewarm) +#pragma data_alignment=1024 +uint8_t pui8ControlTable[1024]; +#elif defined(ccs) +#pragma DATA_ALIGN(pui8ControlTable, 1024) +uint8_t pui8ControlTable[1024]; +#else +uint8_t pui8ControlTable[1024] __attribute__ ((aligned(1024))); +#endif + +//***************************************************************************** +// +// The error routine that is called if the driver library encounters an error. +// +//***************************************************************************** +#ifdef DEBUG +void +__error__(char *pcFilename, uint32_t ui32Line) +{ +} +#endif + +//***************************************************************************** +// +// The interrupt handler for the SysTick timer. This handler will increment a +// seconds counter whenever the appropriate number of ticks has occurred. It +// will also call the CPU usage tick function to find the CPU usage percent. +// +//***************************************************************************** +void +SysTickHandler(void) +{ + static uint32_t ui32TickCount = 0; + + // + // Increment the tick counter. + // + ui32TickCount++; + + // + // If the number of ticks per second has occurred, then increment the + // seconds counter. + // + if(!(ui32TickCount % SYSTICKS_PER_SECOND)) + { + g_ui32Seconds++; + } + + // + // Call the CPU usage tick function. This function will compute the amount + // of cycles used by the CPU since the last call and return the result in + // percent in fixed point 16.16 format. + // + g_ui32CPUUsage = CPUUsageTick(); +} + +//***************************************************************************** +// +// The interrupt handler for uDMA errors. This interrupt will occur if the +// uDMA encounters a bus error while trying to perform a transfer. This +// handler just increments a counter if an error occurs. +// +//***************************************************************************** +void +uDMAErrorHandler(void) +{ + uint32_t ui32Status; + + // + // Check for uDMA error bit + // + ui32Status = ROM_uDMAErrorStatusGet(); + + // + // If there is a uDMA error, then clear the error and increment + // the error counter. + // + if(ui32Status) + { + ROM_uDMAErrorStatusClear(); + g_ui32uDMAErrCount++; + } +} + +//***************************************************************************** +// +// The interrupt handler for uDMA interrupts from the memory channel. This +// interrupt will increment a counter, and then restart another memory +// transfer. +// +//***************************************************************************** +void +uDMAIntHandler(void) +{ + uint32_t ui32Mode; + + // + // Check for the primary control structure to indicate complete. + // + ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_SW); + if(ui32Mode == UDMA_MODE_STOP) + { + // + // Increment the count of completed transfers. + // + g_ui32MemXferCount++; + + // + // Configure it for another transfer. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SW, UDMA_MODE_AUTO, + g_ui32SrcBuf, g_ui32DstBuf, + MEM_BUFFER_SIZE); + + // + // Initiate another transfer. + // + ROM_uDMAChannelEnable(UDMA_CHANNEL_SW); + ROM_uDMAChannelRequest(UDMA_CHANNEL_SW); + } + + // + // If the channel is not stopped, then something is wrong. + // + else + { + g_ui32BadISR++; + } +} + +//***************************************************************************** +// +// The interrupt handler for UART0. This interrupt will occur when a DMA +// transfer is complete using the UART0 uDMA channel. It will also be +// triggered if the peripheral signals an error. This interrupt handler will +// switch between receive ping-pong buffers A and B. It will also restart a TX +// uDMA transfer if the prior transfer is complete. This will keep the UART +// running continuously (looping TX data back to RX). +// +//***************************************************************************** +void +UART0IntHandler(void) +{ + uint32_t ui32Status; + uint32_t ui32Mode; + + // + // Read the interrupt status of the UART. + // + ui32Status = ROM_UARTIntStatus(UART0_BASE, 1); + + // + // Clear any pending status, even though there should be none since no UART + // interrupts were enabled. If UART error interrupts were enabled, then + // those interrupts could occur here and should be handled. Since uDMA is + // used for both the RX and TX, then neither of those interrupts should be + // enabled. + // + ROM_UARTIntClear(UART0_BASE, ui32Status); + + // + // Check the DMA control table to see if the ping-pong "A" transfer is + // complete. The "A" transfer uses receive buffer "A", and the primary + // control structure. + // + ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT); + + // + // If the primary control structure indicates stop, that means the "A" + // receive buffer is done. The uDMA controller should still be receiving + // data into the "B" buffer. + // + if(ui32Mode == UDMA_MODE_STOP) + { + // + // Increment a counter to indicate data was received into buffer A. In + // a real application this would be used to signal the main thread that + // data was received so the main thread can process the data. + // + g_ui32RxBufACount++; + + // + // Set up the next transfer for the "A" buffer, using the primary + // control structure. When the ongoing receive into the "B" buffer is + // done, the uDMA controller will switch back to this one. This + // example re-uses buffer A, but a more sophisticated application could + // use a rotating set of buffers to increase the amount of time that + // the main thread has to process the data in the buffer before it is + // reused. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, + UDMA_MODE_PINGPONG, + (void *)(UART0_BASE + UART_O_DR), + g_ui8RxBufA, sizeof(g_ui8RxBufA)); + } + + // + // Check the DMA control table to see if the ping-pong "B" transfer is + // complete. The "B" transfer uses receive buffer "B", and the alternate + // control structure. + // + ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT); + + // + // If the alternate control structure indicates stop, that means the "B" + // receive buffer is done. The uDMA controller should still be receiving + // data into the "A" buffer. + // + if(ui32Mode == UDMA_MODE_STOP) + { + // + // Increment a counter to indicate data was received into buffer A. In + // a real application this would be used to signal the main thread that + // data was received so the main thread can process the data. + // + g_ui32RxBufBCount++; + + // + // Set up the next transfer for the "B" buffer, using the alternate + // control structure. When the ongoing receive into the "A" buffer is + // done, the uDMA controller will switch back to this one. This + // example re-uses buffer B, but a more sophisticated application could + // use a rotating set of buffers to increase the amount of time that + // the main thread has to process the data in the buffer before it is + // reused. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, + UDMA_MODE_PINGPONG, + (void *)(UART0_BASE + UART_O_DR), + g_ui8RxBufB, sizeof(g_ui8RxBufB)); + } + + // + // If the UART0 DMA TX channel is disabled, that means the TX DMA transfer + // is done. + // + if(!ROM_uDMAChannelIsEnabled(UDMA_CHANNEL_UART0TX)) + { + // + // Start another DMA transfer to UART0 TX. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, g_ui8TxBuf, + (void *)(UART0_BASE + UART_O_DR), + sizeof(g_ui8TxBuf)); + + // + // The uDMA TX channel must be re-enabled. + // + ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX); + } +} + +//***************************************************************************** +// +// Initializes the UART0 peripheral and sets up the TX and RX uDMA channels. +// The UART is configured for loopback mode so that any data sent on TX will be +// received on RX. The uDMA channels are configured so that the TX channel +// will copy data from a buffer to the UART TX output. And the uDMA RX channel +// will receive any incoming data into a pair of buffers in ping-pong mode. +// +//***************************************************************************** +void +InitUART0Transfer(void) +{ + uint_fast16_t ui16Idx; + + // + // Fill the TX buffer with a simple data pattern. + // + for(ui16Idx = 0; ui16Idx < UART_TXBUF_SIZE; ui16Idx++) + { + g_ui8TxBuf[ui16Idx] = ui16Idx; + } + + // + // Enable the UART peripheral, and configure it to operate even if the CPU + // is in sleep. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART0); + + // + // Configure the UART communication parameters. + // + ROM_UARTConfigSetExpClk(UART0_BASE, g_ui32SysClock, 115200, + UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE); + + // + // Set both the TX and RX trigger thresholds to 4. This will be used by + // the uDMA controller to signal when more data should be transferred. The + // uDMA TX and RX channels will be configured so that it can transfer 4 + // bytes in a burst when the UART is ready to transfer more data. + // + ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); + + // + // Enable the UART for operation, and enable the uDMA interface for both TX + // and RX channels. + // + ROM_UARTEnable(UART0_BASE); + ROM_UARTDMAEnable(UART0_BASE, UART_DMA_RX | UART_DMA_TX); + + // + // This register write will set the UART to operate in loopback mode. Any + // data sent on the TX output will be received on the RX input. + // + HWREG(UART0_BASE + UART_O_CTL) |= UART_CTL_LBE; + + // + // Put the attributes in a known state for the uDMA UART0RX channel. These + // should already be disabled by default. + // + ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0RX, + UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | + UDMA_ATTR_HIGH_PRIORITY | + UDMA_ATTR_REQMASK); + + // + // Configure the control parameters for the primary control structure for + // the UART RX channel. The primary contol structure is used for the "A" + // part of the ping-pong receive. The transfer data size is 8 bits, the + // source address does not increment since it will be reading from a + // register. The destination address increment is byte 8-bit bytes. The + // arbitration size is set to 4 to match the RX FIFO trigger threshold. + // The uDMA controller will use a 4 byte burst transfer if possible. This + // will be somewhat more effecient that single byte transfers. + // + ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, + UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | + UDMA_ARB_4); + + // + // Configure the control parameters for the alternate control structure for + // the UART RX channel. The alternate contol structure is used for the "B" + // part of the ping-pong receive. The configuration is identical to the + // primary/A control structure. + // + ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, + UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | + UDMA_ARB_4); + + // + // Set up the transfer parameters for the UART RX primary control + // structure. The mode is set to ping-pong, the transfer source is the + // UART data register, and the destination is the receive "A" buffer. The + // transfer size is set to match the size of the buffer. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, + UDMA_MODE_PINGPONG, + (void *)(UART0_BASE + UART_O_DR), + g_ui8RxBufA, sizeof(g_ui8RxBufA)); + + // + // Set up the transfer parameters for the UART RX alternate control + // structure. The mode is set to ping-pong, the transfer source is the + // UART data register, and the destination is the receive "B" buffer. The + // transfer size is set to match the size of the buffer. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, + UDMA_MODE_PINGPONG, + (void *)(UART0_BASE + UART_O_DR), + g_ui8RxBufB, sizeof(g_ui8RxBufB)); + + // + // Put the attributes in a known state for the uDMA UART0TX channel. These + // should already be disabled by default. + // + ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0TX, + UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | + UDMA_ATTR_REQMASK); + + // + // Set the USEBURST attribute for the uDMA UART TX channel. This will + // force the controller to always use a burst when transferring data from + // the TX buffer to the UART. This is somewhat more effecient bus usage + // than the default which allows single or burst transfers. + // + ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_USEBURST); + + // + // Configure the control parameters for the UART TX. The uDMA UART TX + // channel is used to transfer a block of data from a buffer to the UART. + // The data size is 8 bits. The source address increment is 8-bit bytes + // since the data is coming from a buffer. The destination increment is + // none since the data is to be written to the UART data register. The + // arbitration size is set to 4, which matches the UART TX FIFO trigger + // threshold. + // + ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, + UDMA_SIZE_8 | UDMA_SRC_INC_8 | + UDMA_DST_INC_NONE | + UDMA_ARB_4); + + // + // Set up the transfer parameters for the uDMA UART TX channel. This will + // configure the transfer source and destination and the transfer size. + // Basic mode is used because the peripheral is making the uDMA transfer + // request. The source is the TX buffer and the destination is the UART + // data register. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, g_ui8TxBuf, + (void *)(UART0_BASE + UART_O_DR), + sizeof(g_ui8TxBuf)); + + // + // Now both the uDMA UART TX and RX channels are primed to start a + // transfer. As soon as the channels are enabled, the peripheral will + // issue a transfer request and the data transfers will begin. + // + ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0RX); + ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX); + + // + // Enable the UART DMA TX/RX interrupts. + // + ROM_UARTIntEnable(UART0_BASE, UART_INT_DMATX | UART_INT_DMATX); + + // + // Enable the UART peripheral interrupts. + // + ROM_IntEnable(INT_UART0); +} + +//***************************************************************************** +// +// Initializes the uDMA software channel to perform a memory to memory uDMA +// transfer. +// +//***************************************************************************** +void +InitSWTransfer(void) +{ + uint_fast16_t ui16Idx; + + // + // Fill the source memory buffer with a simple incrementing pattern. + // + for(ui16Idx = 0; ui16Idx < MEM_BUFFER_SIZE; ui16Idx++) + { + g_ui32SrcBuf[ui16Idx] = ui16Idx; + } + + // + // Enable interrupts from the uDMA software channel. + // + ROM_IntEnable(INT_UDMA); + + // + // Put the attributes in a known state for the uDMA software channel. + // These should already be disabled by default. + // + ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SW, + UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + (UDMA_ATTR_HIGH_PRIORITY | + UDMA_ATTR_REQMASK)); + + // + // Configure the control parameters for the SW channel. The SW channel + // will be used to transfer between two memory buffers, 32 bits at a time. + // Therefore the data size is 32 bits, and the address increment is 32 bits + // for both source and destination. The arbitration size will be set to 8, + // which causes the uDMA controller to rearbitrate after 8 items are + // transferred. This keeps this channel from hogging the uDMA controller + // once the transfer is started, and allows other channels cycles if they + // are higher priority. + // + ROM_uDMAChannelControlSet(UDMA_CHANNEL_SW | UDMA_PRI_SELECT, + UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | + UDMA_ARB_8); + + // + // Set up the transfer parameters for the software channel. This will + // configure the transfer buffers and the transfer size. Auto mode must be + // used for software transfers. + // + ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SW | UDMA_PRI_SELECT, + UDMA_MODE_AUTO, g_ui32SrcBuf, g_ui32DstBuf, + MEM_BUFFER_SIZE); + + // + // Now the software channel is primed to start a transfer. The channel + // must be enabled. For software based transfers, a request must be + // issued. After this, the uDMA memory transfer begins. + // + ROM_uDMAChannelEnable(UDMA_CHANNEL_SW); + ROM_uDMAChannelRequest(UDMA_CHANNEL_SW); +} + +//***************************************************************************** +// +// This example demonstrates how to use the uDMA controller to transfer data +// between memory buffers and to and from a peripheral, in this case a UART. +// The uDMA controller is configured to repeatedly transfer a block of data +// from one memory buffer to another. It is also set up to repeatedly copy a +// block of data from a buffer to the UART output. The UART data is looped +// back so the same data is received, and the uDMA controlled is configured to +// continuously receive the UART data using ping-pong buffers. +// +// The processor is put to sleep when it is not doing anything, and this allows +// collection of CPU usage data to see how much CPU is being used while the +// data transfers are ongoing. +// +//***************************************************************************** +int +main(void) +{ + static uint32_t ui32PrevSeconds; + static uint32_t ui32PrevXferCount; + static uint32_t ui32PrevUARTCount = 0; + static char pcStrBuf[40]; + uint32_t ui32CenterX; + uint32_t ui32XfersCompleted; + uint32_t ui32BytesTransferred; + + // + // Run from the PLL at 120 MHz. + // + g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | + SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | + SYSCTL_CFG_VCO_480), 120000000); + + // + // Configure the device pins. + // + PinoutSet(); + + // + // Initialize the display driver. + // + Kentec320x240x16_SSD2119Init(g_ui32SysClock); + + // + // Initialize the graphics context. + // + GrContextInit(&g_sContext, &g_sKentec320x240x16_SSD2119); + + // + // Draw the application frame. + // + FrameDraw(&g_sContext, "udma-demo"); + + // + // Enable peripherals to operate when CPU is in sleep. + // + ROM_SysCtlPeripheralClockGating(true); + + // + // Get the center X coordinate of the screen, since it is used a lot. + // + ui32CenterX = GrContextDpyWidthGet(&g_sContext) / 2; + + // + // Show the clock frequency on the display. + // + GrContextFontSet(&g_sContext, g_psFontCmss18b); + usnprintf(pcStrBuf, sizeof(pcStrBuf), "TM4C129X @ %u MHz", + g_ui32SysClock / 1000000); + GrStringDrawCentered(&g_sContext, pcStrBuf, -1, ui32CenterX, 40, 0); + + // + // Show static text and field labels on the display. + // + GrContextFontSet(&g_sContext, g_psFontCmss18b); + GrStringDrawCentered(&g_sContext, "uDMA Mem Transfers", -1, + ui32CenterX, 70, 0); + GrStringDrawCentered(&g_sContext, "uDMA UART Transfers", -1, + ui32CenterX, 124, 0); + + // + // Configure SysTick to occur 100 times per second, to use as a time + // reference. Enable SysTick to generate interrupts. + // + ROM_SysTickPeriodSet(g_ui32SysClock / SYSTICKS_PER_SECOND); + ROM_SysTickIntEnable(); + ROM_SysTickEnable(); + + // + // Initialize the CPU usage measurement routine. + // + CPUUsageInit(g_ui32SysClock, SYSTICKS_PER_SECOND, 2); + + // + // Enable the uDMA controller at the system level. Enable it to continue + // to run while the processor is in sleep. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); + ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA); + + // + // Enable the uDMA controller error interrupt. This interrupt will occur + // if there is a bus error during a transfer. + // + ROM_IntEnable(INT_UDMAERR); + + // + // Enable the uDMA controller. + // + ROM_uDMAEnable(); + + // + // Point at the control table to use for channel control structures. + // + ROM_uDMAControlBaseSet(pui8ControlTable); + + // + // Initialize the uDMA memory to memory transfers. + // + InitSWTransfer(); + + // + // Initialize the uDMA UART transfers. + // + InitUART0Transfer(); + + // + // Remember the current SysTick seconds count. + // + ui32PrevSeconds = g_ui32Seconds; + + // + // Remember the current count of memory buffer transfers. + // + ui32PrevXferCount = g_ui32MemXferCount; + + // + // Loop until 10 seconds have passed. The processor is put to sleep + // in this loop so that CPU utilization can be measured. + // + while(1) + { + // + // Check to see if one second has elapsed. If so, the make some + // updates. + // + if(g_ui32Seconds != ui32PrevSeconds) + { + // + // Print a message to the display showing the CPU usage percent. + // The fractional part of the percent value is ignored. + // + GrContextFontSet(&g_sContext, g_psFontCmss18b); + usnprintf(pcStrBuf, sizeof(pcStrBuf), "CPU utilization %2u%%", + g_ui32CPUUsage >> 16); + GrStringDrawCentered(&g_sContext, pcStrBuf, -1, + ui32CenterX, 180, 1); + + // + // Tell the user how many seconds we have to go before ending. + // + usnprintf(pcStrBuf, sizeof(pcStrBuf), " Test ends in %d seconds ", + 10 - g_ui32Seconds); + GrStringDrawCentered(&g_sContext, pcStrBuf, -1, + ui32CenterX, 220, 1); + + // + // Remember the new seconds count. + // + ui32PrevSeconds = g_ui32Seconds; + + // + // Calculate how many memory transfers have occurred since the last + // second. + // + ui32XfersCompleted = g_ui32MemXferCount - ui32PrevXferCount; + + // + // Remember the new transfer count. + // + ui32PrevXferCount = g_ui32MemXferCount; + + // + // Compute how many bytes were transferred in the memory transfer + // since the last second. + // + ui32BytesTransferred = ui32XfersCompleted * MEM_BUFFER_SIZE * 4; + + // + // Print a message to the display showing the memory transfer rate. + // + GrContextFontSet(&g_sContext, g_psFontCmss16b); + usnprintf(pcStrBuf, sizeof(pcStrBuf), " %8u Bytes/Sec ", + ui32BytesTransferred); + GrStringDrawCentered(&g_sContext, pcStrBuf, -1, + ui32CenterX, 94, 1); + + // + // Calculate how many UART transfers have occurred since the last + // second. This expression is split to prevent a compiler warning + // about undefined order of volatile accesses. + // + ui32XfersCompleted = g_ui32RxBufACount; + ui32XfersCompleted += g_ui32RxBufBCount - ui32PrevUARTCount; + + // + // Remember the new UART transfer count. This expression is split + // to prevent a compiler warning about undefined order of volatile + // accesses. + // + ui32PrevUARTCount = g_ui32RxBufACount; + ui32PrevUARTCount += g_ui32RxBufBCount; + + // + // Compute how many bytes were transferred by the UART. The number + // of bytes received is multiplied by 2 so that the TX bytes + // transferred are also accounted for. + // + ui32BytesTransferred = ui32XfersCompleted * UART_RXBUF_SIZE * 2; + + // + // Print a message to the display showing the UART transfer rate. + // + usnprintf(pcStrBuf, sizeof(pcStrBuf), " %8u Bytes/Sec ", + ui32BytesTransferred); + GrStringDrawCentered(&g_sContext, pcStrBuf, -1, + ui32CenterX, 146, 1); + } + + // + // Put the processor to sleep if there is nothing to do. This allows + // the CPU usage routine to measure the number of free CPU cycles. + // If the processor is sleeping a lot, it can be hard to connect to + // the target with the debugger. + // + ROM_SysCtlSleep(); + + // + // See if we have run long enough and exit the loop if so. + // + if(g_ui32Seconds >= 10) + { + break; + } + } + + // + // Indicate on the display that the example is stopped. + // + GrContextFontSet(&g_sContext, g_psFontCmss18b); + GrContextForegroundSet(&g_sContext, ClrRed); + GrStringDrawCentered(&g_sContext, " Stopped ", -1, + ui32CenterX, 220, 1); + + // + // Disable uDMA and UART interrupts now that the test is complete. + // + ROM_IntDisable(INT_UART0); + ROM_IntDisable(INT_UDMA); + + // + // Loop forever with the CPU not sleeping, so the debugger can connect. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.ewd b/boards/dk-tm4c129x/udma_demo/udma_demo.ewd new file mode 100644 index 0000000..484e41a --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.ewd @@ -0,0 +1,614 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.ewp b/boards/dk-tm4c129x/udma_demo/udma_demo.ewp new file mode 100644 index 0000000..7b9507d --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.ewp @@ -0,0 +1,804 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Libraries + + $PROJ_DIR$\..\..\..\..\driverlib\ewarm\Exe\driverlib.a + + + $PROJ_DIR$\..\..\..\..\grlib\ewarm\Exe\grlib.a + + + + Source + + $PROJ_DIR$\..\..\..\..\utils\cpu_usage.c + + + $PROJ_DIR$\..\drivers\frame.c + + + $PROJ_DIR$\..\drivers\kentec320x240x16_ssd2119.c + + + $PROJ_DIR$\..\drivers\pinout.c + + + $PROJ_DIR$\startup_ewarm.c + + + $PROJ_DIR$\udma_demo.c + + + $PROJ_DIR$\..\..\..\..\utils\ustdlib.c + + + diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.icf b/boards/dk-tm4c129x/udma_demo/udma_demo.icf new file mode 100644 index 0000000..486555b --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.icf @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// udma_demo.icf - Linker configuration file for udma_demo. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x000fffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x2003ffff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Indicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place the RAM vector table at the start of SRAM. +// +place at start of SRAM { section VTABLE }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.ld b/boards/dk-tm4c129x/udma_demo/udma_demo.ld new file mode 100644 index 0000000..20affeb --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.ld @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * udma_demo.ld - Linker configuration file for udma_demo. + * + * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.sct b/boards/dk-tm4c129x/udma_demo/udma_demo.sct new file mode 100644 index 0000000..3d7f9bf --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.sct @@ -0,0 +1,47 @@ +;****************************************************************************** +; +; udma_demo.sct - Linker configuration file for udma_demo. +; +; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** + +LR_IROM 0x00000000 0x00100000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00100000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00040000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.uvopt b/boards/dk-tm4c129x/udma_demo/udma_demo.uvopt new file mode 100644 index 0000000..4b76900 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.uvopt @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + udma_demo + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\TM4C129XNCZAD.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4614 -S1 -FO29 + + + 0 + DLGTARM + + + + 0 + ARMDBGFLAGS + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\utils\cpu_usage.c + cpu_usage.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\frame.c + frame.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\kentec320x240x16_ssd2119.c + kentec320x240x16_ssd2119.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\pinout.c + pinout.c + + + 1 + 5 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_rvmdk.S + startup_rvmdk.S + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\udma_demo.c + udma_demo.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\utils\ustdlib.c + ustdlib.c + + + + + Libraries + 1 + 0 + 0 + + 2 + 8 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + driverlib.lib + + + 2 + 9 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\grlib\rvmdk\grlib.lib + grlib.lib + + + + + Documentation + 1 + 0 + 0 + + 3 + 10 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo.uvproj b/boards/dk-tm4c129x/udma_demo/udma_demo.uvproj new file mode 100644 index 0000000..557a037 --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo.uvproj @@ -0,0 +1,454 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + udma_demo + 0x4 + ARM-ADS + + + TM4C129XNCZAD + Texas Instruments + IRAM(0x20000000-0x2003FFFF) IROM(0-0xFFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_1024 -FS00 -FL0100000) + 5919 + LM4Fxxxx.H + + + + + + + + + + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk\ + udma_demo + 1 + 0 + 0 + 1 + 1 + .\rvmdk\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\rvmdk\udma_demo.bin .\rvmdk\udma_demo.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 4 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + --c99 + rvmdk PART_TM4C129XNCZAD TARGET_IS_TM4C129_RA0 + + ..;..\..\..\..; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + udma_demo.sct + + + --entry Reset_Handler + + + + + + + + Source + + + cpu_usage.c + 1 + ..\..\..\..\utils\cpu_usage.c + + + frame.c + 1 + ..\drivers\frame.c + + + kentec320x240x16_ssd2119.c + 1 + ..\drivers\kentec320x240x16_ssd2119.c + + + pinout.c + 1 + ..\drivers\pinout.c + + + startup_rvmdk.S + 2 + .\startup_rvmdk.S + + + udma_demo.c + 1 + .\udma_demo.c + + + ustdlib.c + 1 + ..\..\..\..\utils\ustdlib.c + + + + + Libraries + + + driverlib.lib + 4 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + + + grlib.lib + 4 + ..\..\..\..\grlib\rvmdk\grlib.lib + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/boards/dk-tm4c129x/udma_demo/udma_demo_ccs.cmd b/boards/dk-tm4c129x/udma_demo/udma_demo_ccs.cmd new file mode 100644 index 0000000..ad8cc9b --- /dev/null +++ b/boards/dk-tm4c129x/udma_demo/udma_demo_ccs.cmd @@ -0,0 +1,70 @@ +/****************************************************************************** + * + * udma_demo_ccs.cmd - CCS linker configuration file for udma_demo. + * + * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * + *****************************************************************************/ + +--retain=g_pfnVectors + +/* The following command line options are set as part of the CCS project. */ +/* If you are building using the command line, or for some reason want to */ +/* define them here, you can uncomment and modify these lines as needed. */ +/* If you are using CCS for building, it is probably better to make any such */ +/* modifications in your CCS project and leave this file alone. */ +/* */ +/* --heap_size=0 */ +/* --stack_size=256 */ +/* --library=rtsv7M3_T_le_eabi.lib */ + +/* The starting address of the application. Normally the interrupt vectors */ +/* must be located at the beginning of the application. */ +#define APP_BASE 0x00000000 +#define RAM_BASE 0x20000000 + +/* System memory map */ + +MEMORY +{ + /* Application stored in and executes from internal flash */ + FLASH (RX) : origin = APP_BASE, length = 0x00100000 + /* Application uses internal RAM for data */ + SRAM (RWX) : origin = 0x20000000, length = 0x00040000 +} + +/* Section allocation in memory */ + +SECTIONS +{ + .intvecs: > APP_BASE + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .vtable : > RAM_BASE + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} + +__STACK_TOP = __stack + 1024; -- cgit v1.3.1