From c3e4c9a25c2910d2d66d52215b3406b13d5b23d5 Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Sun, 29 Jun 2014 12:34:32 +0300 Subject: Add more board models --- boards/dk-tm4c129x/enet_uip/Makefile | 106 ++ boards/dk-tm4c129x/enet_uip/ccs/.ccsimportspec | 10 + boards/dk-tm4c129x/enet_uip/ccs/.ccsproject | 10 + boards/dk-tm4c129x/enet_uip/ccs/.cproject | 205 ++++ boards/dk-tm4c129x/enet_uip/ccs/.project | 100 ++ .../ccs/.settings/org.eclipse.cdt.codan.core.prefs | 3 + boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.bin | Bin 0 -> 38264 bytes boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.out | Bin 0 -> 386272 bytes boards/dk-tm4c129x/enet_uip/ccs/macros.ini_initial | 1 + .../dk-tm4c129x/enet_uip/ccs/target_config.ccxml | 13 + boards/dk-tm4c129x/enet_uip/clock-arch.h | 41 + boards/dk-tm4c129x/enet_uip/enet_uip.c | 1065 ++++++++++++++++++++ boards/dk-tm4c129x/enet_uip/enet_uip.ewd | 614 +++++++++++ boards/dk-tm4c129x/enet_uip/enet_uip.ewp | 831 +++++++++++++++ boards/dk-tm4c129x/enet_uip/enet_uip.icf | 78 ++ boards/dk-tm4c129x/enet_uip/enet_uip.ld | 57 ++ boards/dk-tm4c129x/enet_uip/enet_uip.sct | 47 + boards/dk-tm4c129x/enet_uip/enet_uip.uvopt | 443 ++++++++ boards/dk-tm4c129x/enet_uip/enet_uip.uvproj | 479 +++++++++ boards/dk-tm4c129x/enet_uip/enet_uip_ccs.cmd | 70 ++ boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.bin | Bin 0 -> 35324 bytes boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.out | Bin 0 -> 310236 bytes boards/dk-tm4c129x/enet_uip/gcc/enet_uip.axf | Bin 0 -> 109049 bytes boards/dk-tm4c129x/enet_uip/gcc/enet_uip.bin | Bin 0 -> 37146 bytes boards/dk-tm4c129x/enet_uip/readme.txt | 33 + boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.axf | Bin 0 -> 316940 bytes boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.bin | Bin 0 -> 35764 bytes boards/dk-tm4c129x/enet_uip/startup_ccs.c | 276 +++++ boards/dk-tm4c129x/enet_uip/startup_ewarm.c | 307 ++++++ boards/dk-tm4c129x/enet_uip/startup_gcc.c | 323 ++++++ boards/dk-tm4c129x/enet_uip/startup_rvmdk.S | 332 ++++++ boards/dk-tm4c129x/enet_uip/uip-conf.h | 162 +++ 32 files changed, 5606 insertions(+) create mode 100644 boards/dk-tm4c129x/enet_uip/Makefile create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/.ccsimportspec create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/.ccsproject create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/.cproject create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/.project create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.bin create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.out create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/macros.ini_initial create mode 100644 boards/dk-tm4c129x/enet_uip/ccs/target_config.ccxml create mode 100644 boards/dk-tm4c129x/enet_uip/clock-arch.h create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.c create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.ewd create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.ewp create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.icf create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.ld create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.sct create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.uvopt create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip.uvproj create mode 100644 boards/dk-tm4c129x/enet_uip/enet_uip_ccs.cmd create mode 100644 boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.bin create mode 100644 boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.out create mode 100644 boards/dk-tm4c129x/enet_uip/gcc/enet_uip.axf create mode 100644 boards/dk-tm4c129x/enet_uip/gcc/enet_uip.bin create mode 100644 boards/dk-tm4c129x/enet_uip/readme.txt create mode 100644 boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.axf create mode 100644 boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.bin create mode 100644 boards/dk-tm4c129x/enet_uip/startup_ccs.c create mode 100644 boards/dk-tm4c129x/enet_uip/startup_ewarm.c create mode 100644 boards/dk-tm4c129x/enet_uip/startup_gcc.c create mode 100644 boards/dk-tm4c129x/enet_uip/startup_rvmdk.S create mode 100644 boards/dk-tm4c129x/enet_uip/uip-conf.h (limited to 'boards/dk-tm4c129x/enet_uip') diff --git a/boards/dk-tm4c129x/enet_uip/Makefile b/boards/dk-tm4c129x/enet_uip/Makefile new file mode 100644 index 0000000..f0c0525 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/Makefile @@ -0,0 +1,106 @@ +#****************************************************************************** +# +# Makefile - Rules for building the Ethernet with uIP. +# +# Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +# +#****************************************************************************** + +# +# Defines the part type that this project uses. +# +PART=TM4C129XNCZAD + +# +# The base directory for TivaWare. +# +ROOT=../../../.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find source files that do not live in this directory. +# +VPATH=. +VPATH+=../../../../third_party/uip-1.0/apps/dhcpc +VPATH+=../drivers +VPATH+=../../../../third_party/uip-1.0/apps/httpd +VPATH+=../../../../third_party/uip-1.0/uip +VPATH+=../../../../utils + +# +# Where to find header files that do not live in the source directory. +# +IPATH=. +IPATH+=.. +IPATH+=../../../.. +IPATH+=../../../../third_party/uip-1.0/apps +IPATH+=../../../../third_party/uip-1.0/uip +IPATH+=../../../../third_party/uip-1.0 +IPATH+=../../../../utils + +# +# The default rule, which causes the Ethernet with uIP to be built. +# +all: ${COMPILER} +all: ${COMPILER}/enet_uip.axf + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}: + @mkdir -p ${COMPILER} + +# +# Rules for building the Ethernet with uIP. +# +${COMPILER}/enet_uip.axf: ${COMPILER}/dhcpc.o +${COMPILER}/enet_uip.axf: ${COMPILER}/enet_uip.o +${COMPILER}/enet_uip.axf: ${COMPILER}/frame.o +${COMPILER}/enet_uip.axf: ${COMPILER}/httpd.o +${COMPILER}/enet_uip.axf: ${COMPILER}/kentec320x240x16_ssd2119.o +${COMPILER}/enet_uip.axf: ${COMPILER}/pinout.o +${COMPILER}/enet_uip.axf: ${COMPILER}/startup_${COMPILER}.o +${COMPILER}/enet_uip.axf: ${COMPILER}/uartstdio.o +${COMPILER}/enet_uip.axf: ${COMPILER}/uip.o +${COMPILER}/enet_uip.axf: ${COMPILER}/uip_arp.o +${COMPILER}/enet_uip.axf: ${COMPILER}/uip_timer.o +${COMPILER}/enet_uip.axf: ${COMPILER}/ustdlib.o +${COMPILER}/enet_uip.axf: ${ROOT}/grlib/${COMPILER}/libgr.a +${COMPILER}/enet_uip.axf: ${ROOT}/driverlib/${COMPILER}/libdriver.a +${COMPILER}/enet_uip.axf: enet_uip.ld +SCATTERgcc_enet_uip=enet_uip.ld +ENTRY_enet_uip=ResetISR +CFLAGSgcc=-DTARGET_IS_TM4C129_RA0 -DDEBUG_OUTPUT -DUIP_OFFLOAD_ICMP_CHKSUM + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/dk-tm4c129x/enet_uip/ccs/.ccsimportspec b/boards/dk-tm4c129x/enet_uip/ccs/.ccsimportspec new file mode 100644 index 0000000..a415eb8 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/.ccsimportspec @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/boards/dk-tm4c129x/enet_uip/ccs/.ccsproject b/boards/dk-tm4c129x/enet_uip/ccs/.ccsproject new file mode 100644 index 0000000..59a3400 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/.ccsproject @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/boards/dk-tm4c129x/enet_uip/ccs/.cproject b/boards/dk-tm4c129x/enet_uip/ccs/.cproject new file mode 100644 index 0000000..8fa2006 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/.cproject @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/dk-tm4c129x/enet_uip/ccs/.project b/boards/dk-tm4c129x/enet_uip/ccs/.project new file mode 100644 index 0000000..ddf4617 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/.project @@ -0,0 +1,100 @@ + + + enet_uip + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + enet_uip.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/enet_uip/enet_uip.c + + + enet_uip_ccs.cmd + 1 + SW_ROOT/examples/boards/dk-tm4c129x/enet_uip/enet_uip_ccs.cmd + + + startup_ccs.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/enet_uip/startup_ccs.c + + + drivers/frame.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/frame.c + + + drivers/kentec320x240x16_ssd2119.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/kentec320x240x16_ssd2119.c + + + drivers/pinout.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/pinout.c + + + utils/uartstdio.c + 1 + SW_ROOT/utils/uartstdio.c + + + utils/ustdlib.c + 1 + SW_ROOT/utils/ustdlib.c + + + third_party/uip-1.0/uip/uip.c + 1 + SW_ROOT/third_party/uip-1.0/uip/uip.c + + + third_party/uip-1.0/uip/uip_arp.c + 1 + SW_ROOT/third_party/uip-1.0/uip/uip_arp.c + + + third_party/uip-1.0/uip/uip_timer.c + 1 + SW_ROOT/third_party/uip-1.0/uip/uip_timer.c + + + third_party/uip-1.0/apps/dhcpc/dhcpc.c + 1 + SW_ROOT/third_party/uip-1.0/apps/dhcpc/dhcpc.c + + + third_party/uip-1.0/apps/httpd/httpd.c + 1 + SW_ROOT/third_party/uip-1.0/apps/httpd/httpd.c + + + + + SW_ROOT + $%7BPARENT-5-PROJECT_LOC%7D + + + diff --git a/boards/dk-tm4c129x/enet_uip/ccs/.settings/org.eclipse.cdt.codan.core.prefs b/boards/dk-tm4c129x/enet_uip/ccs/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.bin b/boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.bin new file mode 100644 index 0000000..f54b913 Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.bin differ diff --git a/boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.out b/boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.out new file mode 100644 index 0000000..ef573d9 Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/ccs/Debug/enet_uip.out differ diff --git a/boards/dk-tm4c129x/enet_uip/ccs/macros.ini_initial b/boards/dk-tm4c129x/enet_uip/ccs/macros.ini_initial new file mode 100644 index 0000000..31214b5 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../../../../.. diff --git a/boards/dk-tm4c129x/enet_uip/ccs/target_config.ccxml b/boards/dk-tm4c129x/enet_uip/ccs/target_config.ccxml new file mode 100644 index 0000000..6e5ef45 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/ccs/target_config.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/boards/dk-tm4c129x/enet_uip/clock-arch.h b/boards/dk-tm4c129x/enet_uip/clock-arch.h new file mode 100644 index 0000000..f30285e --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/clock-arch.h @@ -0,0 +1,41 @@ +//***************************************************************************** +// +// clock-arch.h - uIP Project Specific Clock-Architecture header file. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include + +// +// Define how many clock ticks in one second. +// Note: This should match the value of SYSTICKHZ in the main program. +// +#define CLOCK_CONF_SECOND 100 + +// +// Define the clock type used for returning system ticks. +// +typedef uint32_t clock_time_t; + +#endif // __CLOCK_ARCH_H__ diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.c b/boards/dk-tm4c129x/enet_uip/enet_uip.c new file mode 100644 index 0000000..675f9af --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.c @@ -0,0 +1,1065 @@ +//***************************************************************************** +// +// enet_uip.c - Sample WebServer Application for Ethernet Demo +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_emac.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/emac.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" +#include "driverlib/rom.h" +#include "driverlib/rom_map.h" +#include "driverlib/sysctl.h" +#include "driverlib/systick.h" +#include "grlib/grlib.h" +#include "utils/uartstdio.h" +#include "utils/ustdlib.h" +#include "uip/uip.h" +#include "uip/uip_arp.h" +#include "httpd/httpd.h" +#include "dhcpc/dhcpc.h" +#include "drivers/frame.h" +#include "drivers/kentec320x240x16_ssd2119.h" +#include "drivers/pinout.h" + +//***************************************************************************** +// +//! \addtogroup example_list +//!

Ethernet with uIP (enet_uip)

+//! +//! This example application demonstrates the operation of the Tiva C Series +//! Ethernet controller using the uIP TCP/IP Stack. DHCP is used to obtain +//! an Ethernet address. A basic web site is served over the Ethernet port. +//! The web site displays a few lines of text, and a counter that increments +//! each time the page is sent. +//! +//! UART0, connected to the ICDI virtual COM port and running at 115,200, +//! 8-N-1, is used to display messages from this application. +//! +//! For additional details on uIP, refer to the uIP web page at: +//! http://www.sics.se/~adam/uip/ +// +//***************************************************************************** + +//***************************************************************************** +// +// Defines for setting up the system clock. +// +//***************************************************************************** +#define SYSTICKHZ CLOCK_CONF_SECOND +#define SYSTICKMS (1000 / SYSTICKHZ) +#define SYSTICKUS (1000000 / SYSTICKHZ) +#define SYSTICKNS (1000000000 / SYSTICKHZ) + +//***************************************************************************** +// +// Macro for accessing the Ethernet header information in the buffer. +// +//***************************************************************************** +u8_t g_pui8UIPBuffer[UIP_BUFSIZE + 2]; +u8_t *uip_buf = g_pui8UIPBuffer; + +#define BUF ((struct uip_eth_hdr *)uip_buf) + +//***************************************************************************** +// +// Ethernet DMA descriptors. +// +// Although uIP uses a single buffer, the MAC hardware needs a minimum of +// 3 receive descriptors to operate. +// +//***************************************************************************** +#define NUM_TX_DESCRIPTORS 3 +#define NUM_RX_DESCRIPTORS 3 +tEMACDMADescriptor g_psRxDescriptor[NUM_TX_DESCRIPTORS]; +tEMACDMADescriptor g_psTxDescriptor[NUM_RX_DESCRIPTORS]; + +uint32_t g_ui32RxDescIndex; +uint32_t g_ui32TxDescIndex; + +//***************************************************************************** +// +// Transmit and receive buffers. +// +//***************************************************************************** +#define RX_BUFFER_SIZE 1536 +#define TX_BUFFER_SIZE 1536 +uint8_t g_pui8RxBuffer[RX_BUFFER_SIZE]; +uint8_t g_pui8TxBuffer[TX_BUFFER_SIZE]; + +//***************************************************************************** +// +// A set of flags. The flag bits are defined as follows: +// +// 0 -> An indicator that a SysTick interrupt has occurred. +// 1 -> An RX Packet has been received. +// 2 -> A TX packet DMA transfer is pending. +// 3 -> A RX packet DMA transfer is pending. +// +//***************************************************************************** +#define FLAG_SYSTICK 0 +#define FLAG_RXPKT 1 +#define FLAG_TXPKT 2 +#define FLAG_RXPKTPEND 3 +static volatile uint32_t g_ui32Flags; + +//***************************************************************************** +// +// A system tick counter, incremented every SYSTICKMS. +// +//***************************************************************************** +volatile uint32_t g_ui32TickCounter = 0; + +//***************************************************************************** +// +// Default TCP/IP Settings for this application. +// +// Default to Link Local address ... (169.254.1.0 to 169.254.254.255). Note: +// This application does not implement the Zeroconf protocol. No ARP query is +// issued to determine if this static IP address is already in use. +// +// Uncomment the following #define statement to enable STATIC IP +// instead of DHCP. +// +//***************************************************************************** +//#define USE_STATIC_IP + +#ifndef DEFAULT_IPADDR0 +#define DEFAULT_IPADDR0 169 +#endif + +#ifndef DEFAULT_IPADDR1 +#define DEFAULT_IPADDR1 254 +#endif + +#ifndef DEFAULT_IPADDR2 +#define DEFAULT_IPADDR2 19 +#endif + +#ifndef DEFAULT_IPADDR3 +#define DEFAULT_IPADDR3 63 +#endif + +#ifndef DEFAULT_NETMASK0 +#define DEFAULT_NETMASK0 255 +#endif + +#ifndef DEFAULT_NETMASK1 +#define DEFAULT_NETMASK1 255 +#endif + +#ifndef DEFAULT_NETMASK2 +#define DEFAULT_NETMASK2 0 +#endif + +#ifndef DEFAULT_NETMASK3 +#define DEFAULT_NETMASK3 0 +#endif + +//***************************************************************************** +// +// UIP Timers (in MS) +// +//***************************************************************************** +#define UIP_PERIODIC_TIMER_MS 500 +#define UIP_ARP_TIMER_MS 10000 + +//***************************************************************************** +// +// The drawing context used to draw to the screen. +// +//***************************************************************************** +static tContext g_sContext; + +//***************************************************************************** +// +// The vertical position of the status string on the LCD display. +// +//***************************************************************************** +#define STATUS_Y 128 + +//***************************************************************************** +// +// The error routine that is called if the driver library encounters an error. +// +//***************************************************************************** +void +__error__(char *pcFilename, uint32_t ui32Line) +{ +} + +//***************************************************************************** +// +// The interrupt handler for the SysTick interrupt. +// +//***************************************************************************** +void +SysTickIntHandler(void) +{ + // + // Increment the system tick count. + // + g_ui32TickCounter++; + + // + // Indicate that a SysTick interrupt has occurred. + // + HWREGBITW(&g_ui32Flags, FLAG_SYSTICK) = 1; +} + +//***************************************************************************** +// +// When using the timer module in UIP, this function is required to return +// the number of ticks. Note that the file "clock-arch.h" must be provided +// by the application, and define CLOCK_CONF_SECONDS as the number of ticks +// per second, and must also define the typedef "clock_time_t". +// +//***************************************************************************** +clock_time_t +clock_time(void) +{ + return((clock_time_t)g_ui32TickCounter); +} + +//***************************************************************************** +// +// Display a status string on the LCD and also transmit it via the serial port. +// +//***************************************************************************** +void +UpdateStatus(char *pcStatus) +{ + tRectangle sRect; + + // + // Dump that status string to the serial port. + // + UARTprintf("%s\n", pcStatus); + + // + // Clear any previous status message. + // + sRect.i16XMin = 0; + sRect.i16XMax = GrContextDpyWidthGet(&g_sContext) - 1; + sRect.i16YMin = STATUS_Y - 16; + sRect.i16YMax = STATUS_Y + 16; + GrContextForegroundSet(&g_sContext, ClrBlack); + GrRectFill(&g_sContext, &sRect); + + // + // Display the new status string. + // + GrContextFontSet(&g_sContext, g_psFontCmss20); + GrContextForegroundSet(&g_sContext, ClrWhite); + GrStringDrawCentered(&g_sContext, pcStatus, -1, + GrContextDpyWidthGet(&g_sContext) / 2, STATUS_Y, 0); +} + +//***************************************************************************** +// +// Display the current IP address on the screen and transmit it via the UART. +// +//***************************************************************************** +void +ShowIPAddress(const uip_ipaddr_t sIPAddr) +{ + char pcBuffer[24]; + + usprintf(pcBuffer, "IP: %d.%d.%d.%d", sIPAddr[0] & 0xff, + sIPAddr[0] >> 8, sIPAddr[1] & 0xff, sIPAddr[1] >> 8); + UpdateStatus(pcBuffer); +} + +//***************************************************************************** +// +// The interrupt handler for the Ethernet interrupt. +// +//***************************************************************************** +void +EthernetIntHandler(void) +{ + uint32_t ui32Temp; + + // + // Read and Clear the interrupt. + // + ui32Temp = ROM_EMACIntStatus(EMAC0_BASE, true); + ROM_EMACIntClear(EMAC0_BASE, ui32Temp); + + // + // Check to see if an RX Interrupt has occurred. + // + if(ui32Temp & EMAC_INT_RECEIVE) + { + // + // Indicate that a packet has been received. + // + HWREGBITW(&g_ui32Flags, FLAG_RXPKT) = 1; + } + + // + // Has the DMA finished transferring a packet to the transmitter? + // + if(ui32Temp & EMAC_INT_TRANSMIT) + { + // + // Indicate that a packet has been sent. + // + HWREGBITW(&g_ui32Flags, FLAG_TXPKT) = 0; + } +} + +//***************************************************************************** +// +// Callback for when DHCP client has been configured. +// +//***************************************************************************** +void +dhcpc_configured(const struct dhcpc_state *s) +{ + uip_sethostaddr(&s->ipaddr); + uip_setnetmask(&s->netmask); + uip_setdraddr(&s->default_router); + ShowIPAddress(s->ipaddr); +} + +//***************************************************************************** +// +// Read a packet from the DMA receive buffer into the uIP packet buffer. +// +//***************************************************************************** +int32_t +PacketReceive(uint32_t ui32Base, uint8_t *pui8Buf, int32_t i32BufLen) +{ + int_fast32_t i32FrameLen, i32Loop; + + // + // Check the arguments. + // + ASSERT(ui32Base == EMAC0_BASE); + ASSERT(pui8Buf != 0); + ASSERT(i32BufLen > 0); + + // + // By default, we assume we got a bad frame. + // + i32FrameLen = 0; + + // + // Make sure that we own the receive descriptor. + // + if(!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus & DES0_RX_CTRL_OWN)) + { + // + // We own the receive descriptor so check to see if it contains a valid + // frame. Look for a descriptor error, indicating that the incoming + // packet was truncated or, if this is the last frame in a packet, + // the receive error bit. + // + if(!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus & + DES0_RX_STAT_ERR)) + { + // + // We have a valid frame so copy the content to the supplied + // buffer. First check that the "last descriptor" flag is set. We + // sized the receive buffer such that it can always hold a valid + // frame so this flag should never be clear at this point but... + // + if(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus & + DES0_RX_STAT_LAST_DESC) + { + i32FrameLen = + ((g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus & + DES0_RX_STAT_FRAME_LENGTH_M) >> + DES0_RX_STAT_FRAME_LENGTH_S); + + // + // Sanity check. This shouldn't be required since we sized the + // uIP buffer such that it's the same size as the DMA receive + // buffer but, just in case... + // + if(i32FrameLen > i32BufLen) + { + i32FrameLen = i32BufLen; + } + + // + // Copy the data from the DMA receive buffer into the provided + // frame buffer. + // + for(i32Loop = 0; i32Loop < i32FrameLen; i32Loop++) + { + pui8Buf[i32Loop] = g_pui8RxBuffer[i32Loop]; + } + } + } + + // + // Move on to the next descriptor in the chain. + // + g_ui32RxDescIndex++; + if(g_ui32RxDescIndex == NUM_RX_DESCRIPTORS) + { + g_ui32RxDescIndex = 0; + } + + // + // Mark the next descriptor in the ring as available for the receiver + // to write into. + // + g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus = DES0_RX_CTRL_OWN; + } + + // + // Return the Frame Length + // + return(i32FrameLen); +} + +//***************************************************************************** +// +// Transmit a packet from the supplied buffer. +// +//***************************************************************************** +static int32_t +PacketTransmit(uint32_t ui32Base, uint8_t *pui8Buf, int32_t i32BufLen) +{ + int_fast32_t i32Loop; + + // + // Indicate that a packet is being sent. + // + HWREGBITW(&g_ui32Flags, FLAG_TXPKT) = 1; + + // + // Wait for the previous packet to be transmitted. + // + while(g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus & + DES0_TX_CTRL_OWN) + { + // + // Spin and waste time. + // + } + + // + // Check that we're not going to overflow the transmit buffer. This + // shouldn't be necessary since the uIP buffer is smaller than our DMA + // transmit buffer but, just in case... + // + if(i32BufLen > TX_BUFFER_SIZE) + { + i32BufLen = TX_BUFFER_SIZE; + } + + // + // Copy the packet data into the transmit buffer. + // + for(i32Loop = 0; i32Loop < i32BufLen; i32Loop++) + { + g_pui8TxBuffer[i32Loop] = pui8Buf[i32Loop]; + } + + // + // Move to the next descriptor. + // + g_ui32TxDescIndex++; + if(g_ui32TxDescIndex == NUM_TX_DESCRIPTORS) + { + g_ui32TxDescIndex = 0; + } + + // + // Fill in the packet size and tell the transmitter to start work. + // + g_psTxDescriptor[g_ui32TxDescIndex].ui32Count = (uint32_t)i32BufLen; + g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus = + (DES0_TX_CTRL_LAST_SEG | DES0_TX_CTRL_FIRST_SEG | + DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_IP_ALL_CKHSUMS | + DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_OWN); + + // + // Tell the DMA to reacquire the descriptor now that we've filled it in. + // + ROM_EMACTxDMAPollDemand(EMAC0_BASE); + + // + // Return the number of bytes sent. + // + return(i32BufLen); +} + +//***************************************************************************** +// +// Initialize the transmit and receive DMA descriptors. We apparently need +// a minimum of 3 descriptors in each chain. This is overkill since uIP uses +// a single, common transmit and receive buffer so we tag each descriptor +// with the same buffer and will make sure we only hand the DMA one descriptor +// at a time. +// +//***************************************************************************** +void +InitDescriptors(uint32_t ui32Base) +{ + uint32_t ui32Loop; + + // + // Initialize each of the transmit descriptors. Note that we leave the OWN + // bit clear here since we have not set up any transmissions yet. + // + for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++) + { + g_psTxDescriptor[ui32Loop].ui32Count = + (DES1_TX_CTRL_SADDR_INSERT | + (TX_BUFFER_SIZE << DES1_TX_CTRL_BUFF1_SIZE_S)); + g_psTxDescriptor[ui32Loop].pvBuffer1 = g_pui8TxBuffer; + g_psTxDescriptor[ui32Loop].DES3.pLink = + (ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ? + g_psTxDescriptor : &g_psTxDescriptor[ui32Loop + 1]; + g_psTxDescriptor[ui32Loop].ui32CtrlStatus = + (DES0_TX_CTRL_LAST_SEG | DES0_TX_CTRL_FIRST_SEG | + DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_CHAINED | + DES0_TX_CTRL_IP_ALL_CKHSUMS); + } + + // + // Initialize each of the receive descriptors. We clear the OWN bit here + // to make sure that the receiver doesn't start writing anything + // immediately. + // + for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++) + { + g_psRxDescriptor[ui32Loop].ui32CtrlStatus = 0; + g_psRxDescriptor[ui32Loop].ui32Count = + (DES1_RX_CTRL_CHAINED | + (RX_BUFFER_SIZE << DES1_RX_CTRL_BUFF1_SIZE_S)); + g_psRxDescriptor[ui32Loop].pvBuffer1 = g_pui8RxBuffer; + g_psRxDescriptor[ui32Loop].DES3.pLink = + (ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ? + g_psRxDescriptor : &g_psRxDescriptor[ui32Loop + 1]; + } + + // + // Set the descriptor pointers in the hardware. + // + ROM_EMACRxDMADescriptorListSet(ui32Base, g_psRxDescriptor); + ROM_EMACTxDMADescriptorListSet(ui32Base, g_psTxDescriptor); + + // + // Start from the beginning of both descriptor chains. We actually set + // the transmit descriptor index to the last descriptor in the chain + // since it will be incremented before use and this means the first + // transmission we perform will use the correct descriptor. + // + g_ui32RxDescIndex = 0; + g_ui32TxDescIndex = NUM_TX_DESCRIPTORS - 1; +} + +//***************************************************************************** +// +// This example demonstrates the use of the Ethernet Controller with the uIP +// TCP/IP stack. +// +//***************************************************************************** +int +main(void) +{ + uip_ipaddr_t sIPAddr; + static struct uip_eth_addr sTempAddr; + int32_t i32PeriodicTimer, i32ARPTimer; +#ifdef EXTERNAL_RMII_PHY + uint16_t ui16Val; +#endif + uint32_t ui32User0, ui32User1; + uint32_t ui32Temp, ui32PHYConfig, ui32SysClock; + uint8_t ui8PHYAddr; + + // + // Run from the PLL at 120 MHz. + // + ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | + SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | + SYSCTL_CFG_VCO_480), 120000000); + + // + // Configure the device pins. + // + PinoutSet(); + + // + // Initialize the display driver. + // + Kentec320x240x16_SSD2119Init(ui32SysClock); + + // + // Initialize the graphics context. + // + GrContextInit(&g_sContext, &g_sKentec320x240x16_SSD2119); + + // + // Draw the application frame. + // + FrameDraw(&g_sContext, "enet-uip"); + + // + // Initialize the UART. + // + UARTStdioConfig(0, 115200, ui32SysClock); + UARTprintf("Ethernet with uIP\n-----------------\n\n"); + +#ifdef EXTERNAL_RMII_PHY + UpdateStatus("Using RMII PHY."); + ui32PHYConfig = EMAC_PHY_TYPE_EXTERNAL_RMII; + ui8PHYAddr = 0; +#elif defined EXTERNAL_MII_PHY + UpdateStatus("Using MII PHY."); + ui32PHYConfig = EMAC_PHY_TYPE_EXTERNAL_MII; + ui8PHYAddr = 0; +#else + UpdateStatus("Using Internal PHY."); + ui32PHYConfig = (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | + EMAC_PHY_AN_100B_T_FULL_DUPLEX); + ui8PHYAddr = 0; +#endif + + // + // Read the MAC address from the user registers. + // + ROM_FlashUserGet(&ui32User0, &ui32User1); + if((ui32User0 == 0xffffffff) || (ui32User1 == 0xffffffff)) + { + // + // We should never get here. This is an error if the MAC address has + // not been programmed into the device. Exit the program. + // + UpdateStatus("MAC Address Not Programmed!"); + while(1) + { + } + } + + // + // Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC + // address needed to program the hardware registers, then program the MAC + // address into the Ethernet Controller registers. + // + sTempAddr.addr[0] = ((ui32User0 >> 0) & 0xff); + sTempAddr.addr[1] = ((ui32User0 >> 8) & 0xff); + sTempAddr.addr[2] = ((ui32User0 >> 16) & 0xff); + sTempAddr.addr[3] = ((ui32User1 >> 0) & 0xff); + sTempAddr.addr[4] = ((ui32User1 >> 8) & 0xff); + sTempAddr.addr[5] = ((ui32User1 >> 16) & 0xff); + + // + // Configure SysTick for a periodic interrupt. + // + ROM_SysTickPeriodSet(ui32SysClock / SYSTICKHZ); + ROM_SysTickEnable(); + ROM_SysTickIntEnable(); + + // + // Enable and reset the Ethernet modules. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); + ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); + ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); + + // + // Wait for the MAC to be ready. + // + UpdateStatus("Waiting for MAC to be ready..."); + while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0)) + { + } + + // + // Configure for use with the internal PHY. + // + MAP_EMACPHYConfigSet(EMAC0_BASE, ui32PHYConfig); + UpdateStatus("MAC ready."); + + // + // Reset the MAC. + // + ROM_EMACReset(EMAC0_BASE); + + // + // Initialize the MAC and set the DMA mode. + // + ROM_EMACInit(EMAC0_BASE, ui32SysClock, + EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED, 4, 4, + 0); + +#ifdef EXTERNAL_RMII_PHY + // + // When using an external RMII PHY, we need to acquire link before we can + // determine how to configure the MAC. Unfortunately, the bit signalling + // on RMII changes depending upon whether the PHY is configured to use + // 10Mbps or 100Mbps and we need to tell the MAC which signalling method + // to use. + // + // With MII, the signalling is the same for both speeds so we don't need to + // include code to wait for the link to be acquired. + // + + // + // Write the PHY register that tells it to start auto-negotiation. + // + UpdateStatus("Starting autonegotiation..."); + ROM_EMACPHYWrite(EMAC0_BASE, ui8PHYAddr, EPHY_BMCR, + EPHY_BMCR_ANEN | EPHY_BMCR_RESTARTAN); + + // + // Poll, waiting for auto-negotiation to complete. + // + UpdateStatus("Waiting for autonegotiation to complete..."); + do + { + ui16Val = ROM_EMACPHYRead(EMAC0_BASE, ui8PHYAddr, EPHY_BMSR); + ROM_SysCtlDelay(ui32SysClock / (10 * 3)); + } + while(!(ui16Val & EPHY_BMSR_ANC)); + + // + // Wait for link to be acquired. + // + UpdateStatus("Waiting for link..."); + while(!(ui16Val & EPHY_BMSR_LINKSTAT)) + { + ui16Val = ROM_EMACPHYRead(EMAC0_BASE, ui8PHYAddr, EPHY_BMSR); + } + + UpdateStatus("Link acquired."); + + // + // What's the operating speed? + // + ui16Val = ROM_EMACPHYRead(EMAC0_BASE, ui8PHYAddr, EPHY_STS); + + // + // Set the MAC to PHY communication speed and duplex mode accordingly. + // + UARTprintf("Speed is 10%sMbps.\n", (ui16Val & EPHY_STS_SPEED) ? "" : "0"); + + ROM_EMACConfigSet(EMAC0_BASE, + (((ui16Val & EPHY_STS_SPEED) ? 0 : EMAC_CONFIG_100MBPS) | + ((ui16Val & EPHY_STS_DUPLEX) ? EMAC_CONFIG_FULL_DUPLEX : + 0) | + EMAC_CONFIG_FULL_DUPLEX | + EMAC_CONFIG_CHECKSUM_OFFLOAD | + EMAC_CONFIG_7BYTE_PREAMBLE | + EMAC_CONFIG_IF_GAP_96BITS | EMAC_CONFIG_USE_MACADDR0 | + EMAC_CONFIG_SA_FROM_DESCRIPTOR | + EMAC_CONFIG_BO_LIMIT_1024), + (EMAC_MODE_RX_STORE_FORWARD | + EMAC_MODE_TX_STORE_FORWARD | + EMAC_MODE_TX_THRESHOLD_64_BYTES | + EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); +#else + // + // Set MAC configuration options. + // + ROM_EMACConfigSet(EMAC0_BASE, + (EMAC_CONFIG_FULL_DUPLEX | EMAC_CONFIG_CHECKSUM_OFFLOAD | + EMAC_CONFIG_7BYTE_PREAMBLE | EMAC_CONFIG_IF_GAP_96BITS | + EMAC_CONFIG_USE_MACADDR0 | + EMAC_CONFIG_SA_FROM_DESCRIPTOR | + EMAC_CONFIG_BO_LIMIT_1024), + (EMAC_MODE_RX_STORE_FORWARD | + EMAC_MODE_TX_STORE_FORWARD | + EMAC_MODE_TX_THRESHOLD_64_BYTES | + EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); +#endif + + // + // Initialize the Ethernet DMA descriptors. + // + InitDescriptors(EMAC0_BASE); + + // + // Program the hardware with its MAC address (for filtering). + // + ROM_EMACAddrSet(EMAC0_BASE, 0, (uint8_t *)&sTempAddr); + +#ifndef EXTERNAL_RMII_PHY + // + // Wait for the link to become active. If we are using an external + // RMII PHY, we already waited for link to be acquired prior to + // configuring the MAC so don't wait again here. + // + UpdateStatus("Waiting for Link"); + while((ROM_EMACPHYRead(EMAC0_BASE, ui8PHYAddr, EPHY_BMSR) & + EPHY_BMSR_LINKSTAT) == 0) + { + } + UpdateStatus("Link Established"); +#endif + + // + // Set MAC filtering options. We receive all broadcast and multicast + // packets along with those addressed specifically for us. + // + ROM_EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_SADDR | + EMAC_FRMFILTER_PASS_MULTICAST | + EMAC_FRMFILTER_PASS_NO_CTRL)); + + // + // Clear any pending interrupts. + // + ROM_EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false)); + + // + // Initialize the uIP TCP/IP stack. + // + uip_init(); + + // + // Set the local MAC address (for uIP). + // + uip_setethaddr(sTempAddr); +#ifdef USE_STATIC_IP + uip_ipaddr(sIPAddr, DEFAULT_IPADDR0, DEFAULT_IPADDR1, DEFAULT_IPADDR2, + DEFAULT_IPADDR3); + uip_sethostaddr(sIPAddr); + ShowIPAddress(sIPAddr); + uip_ipaddr(sIPAddr, DEFAULT_NETMASK0, DEFAULT_NETMASK1, DEFAULT_NETMASK2, + DEFAULT_NETMASK3); + uip_setnetmask(sIPAddr); +#else + uip_ipaddr(sIPAddr, 0, 0, 0, 0); + uip_sethostaddr(sIPAddr); + UpdateStatus("Waiting for IP address..."); + uip_ipaddr(sIPAddr, 0, 0, 0, 0); + uip_setnetmask(sIPAddr); +#endif + + // + // Enable the Ethernet MAC transmitter and receiver. + // + ROM_EMACTxEnable(EMAC0_BASE); + ROM_EMACRxEnable(EMAC0_BASE); + + // + // Enable the Ethernet interrupt. + // + ROM_IntEnable(INT_EMAC0); + + // + // Enable the Ethernet RX Packet interrupt source. + // + ROM_EMACIntEnable(EMAC0_BASE, EMAC_INT_RECEIVE); + + // + // Mark the first receive descriptor as available to the DMA to start + // the receive processing. + // + g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus |= DES0_RX_CTRL_OWN; + + // + // Initialize the TCP/IP Application (e.g. web server). + // + httpd_init(); + +#ifndef USE_STATIC_IP + // + // Initialize the DHCP Client Application. + // + dhcpc_init(&sTempAddr.addr[0], 6); + dhcpc_request(); +#endif + + // + // Main Application Loop. + // + i32PeriodicTimer = 0; + i32ARPTimer = 0; + while(true) + { + // + // Wait for an event to occur. This can be either a System Tick event, + // or an RX Packet event. + // + while(!g_ui32Flags) + { + } + + // + // If SysTick, Clear the SysTick interrupt flag and increment the + // timers. + // + if(HWREGBITW(&g_ui32Flags, FLAG_SYSTICK) == 1) + { + HWREGBITW(&g_ui32Flags, FLAG_SYSTICK) = 0; + i32PeriodicTimer += SYSTICKMS; + i32ARPTimer += SYSTICKMS; + } + + // + // Check for an RX Packet and read it. + // + if(HWREGBITW(&g_ui32Flags, FLAG_RXPKT)) + { + // + // Clear the RX Packet event flag. + // + HWREGBITW(&g_ui32Flags, FLAG_RXPKT) = 0; + + // Get the packet and set uip_len for uIP stack usage. + // + uip_len = (unsigned short)PacketReceive(EMAC0_BASE, uip_buf, + sizeof(g_pui8UIPBuffer)); + + // + // Process incoming IP packets here. + // + if(BUF->type == htons(UIP_ETHTYPE_IP)) + { + uip_arp_ipin(); + uip_input(); + + // + // If the above function invocation resulted in data that + // should be sent out on the network, the global variable + // uip_len is set to a value > 0. + // + if(uip_len > 0) + { + uip_arp_out(); + PacketTransmit(EMAC0_BASE, uip_buf, uip_len); + uip_len = 0; + } + } + + // + // Process incoming ARP packets here. + // + else if(BUF->type == htons(UIP_ETHTYPE_ARP)) + { + uip_arp_arpin(); + + // + // If the above function invocation resulted in data that + // should be sent out on the network, the global variable + // uip_len is set to a value > 0. + // + if(uip_len > 0) + { + PacketTransmit(EMAC0_BASE, uip_buf, uip_len); + uip_len = 0; + } + } + } + + // + // Process TCP/IP Periodic Timer here. + // + if(i32PeriodicTimer > UIP_PERIODIC_TIMER_MS) + { + i32PeriodicTimer = 0; + for(ui32Temp = 0; ui32Temp < UIP_CONNS; ui32Temp++) + { + uip_periodic(ui32Temp); + + // + // If the above function invocation resulted in data that + // should be sent out on the network, the global variable + // uip_len is set to a value > 0. + // + if(uip_len > 0) + { + uip_arp_out(); + PacketTransmit(EMAC0_BASE, uip_buf, uip_len); + uip_len = 0; + } + } + +#if UIP_UDP + for(ui32Temp = 0; ui32Temp < UIP_UDP_CONNS; ui32Temp++) + { + uip_udp_periodic(ui32Temp); + + // + // If the above function invocation resulted in data that + // should be sent out on the network, the global variable + // uip_len is set to a value > 0. + // + if(uip_len > 0) + { + uip_arp_out(); + PacketTransmit(EMAC0_BASE, uip_buf, uip_len); + uip_len = 0; + } + } +#endif + } + + // + // Process ARP Timer here. + // + if(i32ARPTimer > UIP_ARP_TIMER_MS) + { + i32ARPTimer = 0; + uip_arp_timer(); + } + } +} + +#ifdef UIP_ARCH_IPCHKSUM +// +// Return the IP checksum for the packet in uip_buf. This is a dummy since +// the hardware calculates this for us. +// +u16_t +uip_ipchksum(void) +{ + // + // Dummy function - the hardware calculates and inserts all required + // checksums for us. + // + return(0xffff); +} + +u16_t +uip_chksum(u16_t *data, u16_t len) +{ + return(0xffff); +} + +u16_t +uip_icmp6chksum(void) +{ + return(0xffff); +} + +u16_t +uip_tcpchksum(void) +{ + return(0xffff); +} +#endif diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.ewd b/boards/dk-tm4c129x/enet_uip/enet_uip.ewd new file mode 100644 index 0000000..484e41a --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.ewd @@ -0,0 +1,614 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.ewp b/boards/dk-tm4c129x/enet_uip/enet_uip.ewp new file mode 100644 index 0000000..a4c24c1 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.ewp @@ -0,0 +1,831 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Libraries + + $PROJ_DIR$\..\..\..\..\driverlib\ewarm\Exe\driverlib.a + + + $PROJ_DIR$\..\..\..\..\grlib\ewarm\Exe\grlib.a + + + + Source + + $PROJ_DIR$\..\..\..\..\third_party\uip-1.0\apps\dhcpc\dhcpc.c + + + $PROJ_DIR$\enet_uip.c + + + $PROJ_DIR$\..\drivers\frame.c + + + $PROJ_DIR$\..\..\..\..\third_party\uip-1.0\apps\httpd\httpd.c + + + $PROJ_DIR$\..\drivers\kentec320x240x16_ssd2119.c + + + $PROJ_DIR$\..\drivers\pinout.c + + + $PROJ_DIR$\startup_ewarm.c + + + $PROJ_DIR$\..\..\..\..\utils\uartstdio.c + + + $PROJ_DIR$\..\..\..\..\third_party\uip-1.0\uip\uip.c + + + $PROJ_DIR$\..\..\..\..\third_party\uip-1.0\uip\uip_arp.c + + + $PROJ_DIR$\..\..\..\..\third_party\uip-1.0\uip\uip_timer.c + + + $PROJ_DIR$\..\..\..\..\utils\ustdlib.c + + + diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.icf b/boards/dk-tm4c129x/enet_uip/enet_uip.icf new file mode 100644 index 0000000..9255df7 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.icf @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// enet_uip.icf - Linker configuration file for enet_uip. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x000fffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x2003ffff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Indicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place the RAM vector table at the start of SRAM. +// +place at start of SRAM { section VTABLE }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.ld b/boards/dk-tm4c129x/enet_uip/enet_uip.ld new file mode 100644 index 0000000..beef25d --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.ld @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * enet_uip.ld - Linker configuration file for enet_uip. + * + * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.sct b/boards/dk-tm4c129x/enet_uip/enet_uip.sct new file mode 100644 index 0000000..53e9515 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.sct @@ -0,0 +1,47 @@ +;****************************************************************************** +; +; enet_uip.sct - Linker configuration file for enet_uip. +; +; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** + +LR_IROM 0x00000000 0x00100000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00100000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00040000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.uvopt b/boards/dk-tm4c129x/enet_uip/enet_uip.uvopt new file mode 100644 index 0000000..d77228e --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.uvopt @@ -0,0 +1,443 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + enet_uip + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\TM4C129XNCZAD.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4614 -S1 -FO29 + + + 0 + DLGTARM + + + + 0 + ARMDBGFLAGS + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\third_party\uip-1.0\apps\dhcpc\dhcpc.c + dhcpc.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\enet_uip.c + enet_uip.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\frame.c + frame.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\third_party\uip-1.0\apps\httpd\httpd.c + httpd.c + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\kentec320x240x16_ssd2119.c + kentec320x240x16_ssd2119.c + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\pinout.c + pinout.c + + + 1 + 7 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_rvmdk.S + startup_rvmdk.S + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\utils\uartstdio.c + uartstdio.c + + + 1 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\third_party\uip-1.0\uip\uip.c + uip.c + + + 1 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\third_party\uip-1.0\uip\uip_arp.c + uip_arp.c + + + 1 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\third_party\uip-1.0\uip\uip_timer.c + uip_timer.c + + + 1 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\utils\ustdlib.c + ustdlib.c + + + + + Libraries + 1 + 0 + 0 + + 2 + 13 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + driverlib.lib + + + 2 + 14 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\grlib\rvmdk\grlib.lib + grlib.lib + + + + + Documentation + 1 + 0 + 0 + + 3 + 15 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip.uvproj b/boards/dk-tm4c129x/enet_uip/enet_uip.uvproj new file mode 100644 index 0000000..5b5af9c --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip.uvproj @@ -0,0 +1,479 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + enet_uip + 0x4 + ARM-ADS + + + TM4C129XNCZAD + Texas Instruments + IRAM(0x20000000-0x2003FFFF) IROM(0-0xFFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_1024 -FS00 -FL0100000) + 5919 + LM4Fxxxx.H + + + + + + + + + + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk\ + enet_uip + 1 + 0 + 0 + 1 + 1 + .\rvmdk\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\rvmdk\enet_uip.bin .\rvmdk\enet_uip.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 4 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + --c99 + rvmdk PART_TM4C129XNCZAD TARGET_IS_TM4C129_RA0 DEBUG_OUTPUT UIP_OFFLOAD_ICMP_CHKSUM + + .;..;..\..\..\..;..\..\..\..\third_party\uip-1.0\apps;..\..\..\..\third_party\uip-1.0\uip;..\..\..\..\third_party\uip-1.0;..\..\..\..\utils; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + enet_uip.sct + + + --entry Reset_Handler + + + + + + + + Source + + + dhcpc.c + 1 + ..\..\..\..\third_party\uip-1.0\apps\dhcpc\dhcpc.c + + + enet_uip.c + 1 + .\enet_uip.c + + + frame.c + 1 + ..\drivers\frame.c + + + httpd.c + 1 + ..\..\..\..\third_party\uip-1.0\apps\httpd\httpd.c + + + kentec320x240x16_ssd2119.c + 1 + ..\drivers\kentec320x240x16_ssd2119.c + + + pinout.c + 1 + ..\drivers\pinout.c + + + startup_rvmdk.S + 2 + .\startup_rvmdk.S + + + uartstdio.c + 1 + ..\..\..\..\utils\uartstdio.c + + + uip.c + 1 + ..\..\..\..\third_party\uip-1.0\uip\uip.c + + + uip_arp.c + 1 + ..\..\..\..\third_party\uip-1.0\uip\uip_arp.c + + + uip_timer.c + 1 + ..\..\..\..\third_party\uip-1.0\uip\uip_timer.c + + + ustdlib.c + 1 + ..\..\..\..\utils\ustdlib.c + + + + + Libraries + + + driverlib.lib + 4 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + + + grlib.lib + 4 + ..\..\..\..\grlib\rvmdk\grlib.lib + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/boards/dk-tm4c129x/enet_uip/enet_uip_ccs.cmd b/boards/dk-tm4c129x/enet_uip/enet_uip_ccs.cmd new file mode 100644 index 0000000..ed998cf --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/enet_uip_ccs.cmd @@ -0,0 +1,70 @@ +/****************************************************************************** + * + * enet_uip_ccs.cmd - CCS linker configuration file for enet_uip. + * + * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * + *****************************************************************************/ + +--retain=g_pfnVectors + +/* The following command line options are set as part of the CCS project. */ +/* If you are building using the command line, or for some reason want to */ +/* define them here, you can uncomment and modify these lines as needed. */ +/* If you are using CCS for building, it is probably better to make any such */ +/* modifications in your CCS project and leave this file alone. */ +/* */ +/* --heap_size=0 */ +/* --stack_size=256 */ +/* --library=rtsv7M3_T_le_eabi.lib */ + +/* The starting address of the application. Normally the interrupt vectors */ +/* must be located at the beginning of the application. */ +#define APP_BASE 0x00000000 +#define RAM_BASE 0x20000000 + +/* System memory map */ + +MEMORY +{ + /* Application stored in and executes from internal flash */ + FLASH (RX) : origin = APP_BASE, length = 0x00100000 + /* Application uses internal RAM for data */ + SRAM (RWX) : origin = 0x20000000, length = 0x00040000 +} + +/* Section allocation in memory */ + +SECTIONS +{ + .intvecs: > APP_BASE + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .vtable : > RAM_BASE + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} + +__STACK_TOP = __stack + 512; diff --git a/boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.bin b/boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.bin new file mode 100644 index 0000000..9629b78 Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.bin differ diff --git a/boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.out b/boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.out new file mode 100644 index 0000000..0cb9e40 Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/ewarm/Exe/enet_uip.out differ diff --git a/boards/dk-tm4c129x/enet_uip/gcc/enet_uip.axf b/boards/dk-tm4c129x/enet_uip/gcc/enet_uip.axf new file mode 100644 index 0000000..8583dc1 Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/gcc/enet_uip.axf differ diff --git a/boards/dk-tm4c129x/enet_uip/gcc/enet_uip.bin b/boards/dk-tm4c129x/enet_uip/gcc/enet_uip.bin new file mode 100644 index 0000000..19eafcb Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/gcc/enet_uip.bin differ diff --git a/boards/dk-tm4c129x/enet_uip/readme.txt b/boards/dk-tm4c129x/enet_uip/readme.txt new file mode 100644 index 0000000..d8313dc --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/readme.txt @@ -0,0 +1,33 @@ +Ethernet with uIP + +This example application demonstrates the operation of the Tiva C Series +Ethernet controller using the uIP TCP/IP Stack. DHCP is used to obtain +an Ethernet address. A basic web site is served over the Ethernet port. +The web site displays a few lines of text, and a counter that increments +each time the page is sent. + +UART0, connected to the ICDI virtual COM port and running at 115,200, +8-N-1, is used to display messages from this application. + +For additional details on uIP, refer to the uIP web page at: +http://www.sics.se/~adam/uip/ + +------------------------------------------------------------------------------- + +Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + +Texas Instruments (TI) is supplying this software for use solely and +exclusively on TI's microcontroller products. The software is owned by +TI and/or its suppliers, and is protected under applicable copyright +laws. You may not combine this software with "viral" open-source +software in order to form a larger program. + +THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, FOR ANY REASON WHATSOEVER. + +This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. diff --git a/boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.axf b/boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.axf new file mode 100644 index 0000000..fc04caf Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.axf differ diff --git a/boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.bin b/boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.bin new file mode 100644 index 0000000..f2799ca Binary files /dev/null and b/boards/dk-tm4c129x/enet_uip/rvmdk/enet_uip.bin differ diff --git a/boards/dk-tm4c129x/enet_uip/startup_ccs.c b/boards/dk-tm4c129x/enet_uip/startup_ccs.c new file mode 100644 index 0000000..d2bb22a --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/startup_ccs.c @@ -0,0 +1,276 @@ +//***************************************************************************** +// +// startup_ccs.c - Startup code for use with TI's Code Composer Studio. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern uint32_t __STACK_TOP; + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void EthernetIntHandler(void); +extern void SysTickIntHandler(void); + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".intvecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)&__STACK_TOP), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + SysTickIntHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + EthernetIntHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Jump to the CCS C initialization routine. This will enable the + // floating-point unit as well, so that does not need to be done here. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/enet_uip/startup_ewarm.c b/boards/dk-tm4c129x/enet_uip/startup_ewarm.c new file mode 100644 index 0000000..79a712c --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/startup_ewarm.c @@ -0,0 +1,307 @@ +//***************************************************************************** +// +// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, +// version 5. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void EthernetIntHandler(void); +extern void SysTickIntHandler(void); + +//***************************************************************************** +// +// The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[128] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + uint32_t ui32Ptr; +} +uVectorEntry; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + SysTickIntHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + EthernetIntHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + __iar_program_start(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/enet_uip/startup_gcc.c b/boards/dk-tm4c129x/enet_uip/startup_gcc.c new file mode 100644 index 0000000..2cfa08f --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/startup_gcc.c @@ -0,0 +1,323 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +extern void EthernetIntHandler(void); +extern void SysTickIntHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[128]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + SysTickIntHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + EthernetIntHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _etext; +extern uint32_t _data; +extern uint32_t _edata; +extern uint32_t _bss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + uint32_t *pui32Src, *pui32Dest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pui32Src = &_etext; + for(pui32Dest = &_data; pui32Dest < &_edata; ) + { + *pui32Dest++ = *pui32Src++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/enet_uip/startup_rvmdk.S b/boards/dk-tm4c129x/enet_uip/startup_rvmdk.S new file mode 100644 index 0000000..043a697 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/startup_rvmdk.S @@ -0,0 +1,332 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000200 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; External declarations for the interrupt handlers used by the application. +; +;****************************************************************************** + EXTERN EthernetIntHandler + EXTERN SysTickIntHandler + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; The MPU fault handler + DCD IntDefaultHandler ; The bus fault handler + DCD IntDefaultHandler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall handler + DCD IntDefaultHandler ; Debug monitor handler + DCD 0 ; Reserved + DCD IntDefaultHandler ; The PendSV handler + DCD SysTickIntHandler ; The SysTick handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD IntDefaultHandler ; UART0 Rx and Tx + DCD IntDefaultHandler ; UART1 Rx and Tx + DCD IntDefaultHandler ; SSI0 Rx and Tx + DCD IntDefaultHandler ; I2C0 Master and Slave + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder 0 + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog timer + DCD IntDefaultHandler ; Timer 0 subtimer A + DCD IntDefaultHandler ; Timer 0 subtimer B + DCD IntDefaultHandler ; Timer 1 subtimer A + DCD IntDefaultHandler ; Timer 1 subtimer B + DCD IntDefaultHandler ; Timer 2 subtimer A + DCD IntDefaultHandler ; Timer 2 subtimer B + DCD IntDefaultHandler ; Analog Comparator 0 + DCD IntDefaultHandler ; Analog Comparator 1 + DCD IntDefaultHandler ; Analog Comparator 2 + DCD IntDefaultHandler ; System Control (PLL, OSC, BO) + DCD IntDefaultHandler ; FLASH Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD EthernetIntHandler ; Ethernet + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + DCD IntDefaultHandler ; ADC1 Sequence 0 + DCD IntDefaultHandler ; ADC1 Sequence 1 + DCD IntDefaultHandler ; ADC1 Sequence 2 + DCD IntDefaultHandler ; ADC1 Sequence 3 + DCD IntDefaultHandler ; External Bus Interface 0 + DCD IntDefaultHandler ; GPIO Port J + DCD IntDefaultHandler ; GPIO Port K + DCD IntDefaultHandler ; GPIO Port L + DCD IntDefaultHandler ; SSI2 Rx and Tx + DCD IntDefaultHandler ; SSI3 Rx and Tx + DCD IntDefaultHandler ; UART3 Rx and Tx + DCD IntDefaultHandler ; UART4 Rx and Tx + DCD IntDefaultHandler ; UART5 Rx and Tx + DCD IntDefaultHandler ; UART6 Rx and Tx + DCD IntDefaultHandler ; UART7 Rx and Tx + DCD IntDefaultHandler ; I2C2 Master and Slave + DCD IntDefaultHandler ; I2C3 Master and Slave + DCD IntDefaultHandler ; Timer 4 subtimer A + DCD IntDefaultHandler ; Timer 4 subtimer B + DCD IntDefaultHandler ; Timer 5 subtimer A + DCD IntDefaultHandler ; Timer 5 subtimer B + DCD IntDefaultHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C4 Master and Slave + DCD IntDefaultHandler ; I2C5 Master and Slave + DCD IntDefaultHandler ; GPIO Port M + DCD IntDefaultHandler ; GPIO Port N + DCD 0 ; Reserved + DCD IntDefaultHandler ; Tamper + DCD IntDefaultHandler ; GPIO Port P (Summary or P0) + DCD IntDefaultHandler ; GPIO Port P1 + DCD IntDefaultHandler ; GPIO Port P2 + DCD IntDefaultHandler ; GPIO Port P3 + DCD IntDefaultHandler ; GPIO Port P4 + DCD IntDefaultHandler ; GPIO Port P5 + DCD IntDefaultHandler ; GPIO Port P6 + DCD IntDefaultHandler ; GPIO Port P7 + DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) + DCD IntDefaultHandler ; GPIO Port Q1 + DCD IntDefaultHandler ; GPIO Port Q2 + DCD IntDefaultHandler ; GPIO Port Q3 + DCD IntDefaultHandler ; GPIO Port Q4 + DCD IntDefaultHandler ; GPIO Port Q5 + DCD IntDefaultHandler ; GPIO Port Q6 + DCD IntDefaultHandler ; GPIO Port Q7 + DCD IntDefaultHandler ; GPIO Port R + DCD IntDefaultHandler ; GPIO Port S + DCD IntDefaultHandler ; SHA/MD5 0 + DCD IntDefaultHandler ; AES 0 + DCD IntDefaultHandler ; DES3DES 0 + DCD IntDefaultHandler ; LCD Controller 0 + DCD IntDefaultHandler ; Timer 6 subtimer A + DCD IntDefaultHandler ; Timer 6 subtimer B + DCD IntDefaultHandler ; Timer 7 subtimer A + DCD IntDefaultHandler ; Timer 7 subtimer B + DCD IntDefaultHandler ; I2C6 Master and Slave + DCD IntDefaultHandler ; I2C7 Master and Slave + DCD IntDefaultHandler ; HIM Scan Matrix Keyboard 0 + DCD IntDefaultHandler ; One Wire 0 + DCD IntDefaultHandler ; HIM PS/2 0 + DCD IntDefaultHandler ; HIM LED Sequencer 0 + DCD IntDefaultHandler ; HIM Consumer IR 0 + DCD IntDefaultHandler ; I2C8 Master and Slave + DCD IntDefaultHandler ; I2C9 Master and Slave + DCD IntDefaultHandler ; GPIO Port T + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Enable the floating-point unit. This must be done here to handle the + ; case where main() uses floating-point and the function prologue saves + ; floating-point registers (which will fault if floating-point is not + ; enabled). Any configuration of the floating-point unit using + ; DriverLib APIs must be done here prior to the floating-point unit + ; being enabled. + ; + ; Note that this does not use DriverLib since it might not be included + ; in this project. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/boards/dk-tm4c129x/enet_uip/uip-conf.h b/boards/dk-tm4c129x/enet_uip/uip-conf.h new file mode 100644 index 0000000..5176f49 --- /dev/null +++ b/boards/dk-tm4c129x/enet_uip/uip-conf.h @@ -0,0 +1,162 @@ +//***************************************************************************** +// +// uip-conf.h - uIP Project Specific Configuration File +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +// +// 8 bit datatype +// This typedef defines the 8-bit type used throughout uIP. +// +typedef unsigned char u8_t; + +// +// 16 bit datatype +// This typedef defines the 16-bit type used throughout uIP. +// +typedef unsigned short u16_t; + +// +// Statistics datatype +// This typedef defines the dataype used for keeping statistics in +// uIP. +// +typedef unsigned short uip_stats_t; + +// +// Ping IP address assignment +// Use first incoming "ping" packet to derive host IP address +// +#define UIP_CONF_PINGADDRCONF 0 + +// +// UDP support on or off +// +#define UIP_CONF_UDP 1 + +// +// UDP checksums on or off +// (not currently supported ... should be 0) +// +#define UIP_CONF_UDP_CHECKSUMS 0 + +// +// UDP Maximum Connections +// +#define UIP_CONF_UDP_CONNS 4 + +// +// Maximum number of TCP connections. +// +#define UIP_CONF_MAX_CONNECTIONS 2 + +// +// Maximum number of listening TCP ports. +// +#define UIP_CONF_MAX_LISTENPORTS 4 + +// +// Size of advertised receiver's window +// +//#define UIP_CONF_RECEIVE_WINDOW 400 + +// +// Size of ARP table +// +#define UIP_CONF_ARPTAB_SIZE 8 + +// +// uIP buffer size. +// +#define UIP_CONF_BUFFER_SIZE 1600 + +// +// uIP buffer is defined in the application. +// +#define UIP_CONF_EXTERNAL_BUFFER + +// +// uIP statistics on or off +// +#define UIP_CONF_STATISTICS 1 + +// +// Logging on or off +// +#define UIP_CONF_LOGGING 0 + +// +// Broadcast Support +// +#define UIP_CONF_BROADCAST 0 + +// +// Link-Level Header length +// +#define UIP_CONF_LLH_LEN 14 + +// +// CPU byte order. +// +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +// +// Offload checksum calculation to the hardware. +// +// TODO: Once things are working, turn on hardware checksum calculation and +// make sure the application source includes stubs for uip_ipchksum(), +// uip_tcpchksum() and uip_udpchksum(). uip_icmp6chksum() is also needed if +// IPv6 is in use. +// +#define UIP_ARCH_IPCHKSUM +#define UIP_ARCH_CHKSUM 1 + + +// +// Here we include the header file for the application we are using in +// this example +// +#include "httpd/httpd.h" + +// +// Define the uIP Application State type, based on the httpd.h state variable. +// +typedef struct httpd_state uip_tcp_appstate_t; + +// +// UIP_APPCALL: the name of the application function. This function +// must return void and take no arguments (i.e., C type "void +// appfunc(void)"). +// +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + +// +// Here we include the header file for the DPCP client we are using in +// this example +// +#include "dhcpc/dhcpc.h" + +#endif // __UIP_CONF_H_ -- cgit v1.3.1