From c3e4c9a25c2910d2d66d52215b3406b13d5b23d5 Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Sun, 29 Jun 2014 12:34:32 +0300 Subject: Add more board models --- boards/dk-tm4c129x/aes_gcm_decrypt/Makefile | 91 ++ .../dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.c | 1190 ++++++++++++++++++++ .../aes_gcm_decrypt/aes_gcm_decrypt.ewd | 614 ++++++++++ .../aes_gcm_decrypt/aes_gcm_decrypt.ewp | 801 +++++++++++++ .../aes_gcm_decrypt/aes_gcm_decrypt.icf | 78 ++ .../dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ld | 57 + .../aes_gcm_decrypt/aes_gcm_decrypt.sct | 47 + .../aes_gcm_decrypt/aes_gcm_decrypt.uvopt | 359 ++++++ .../aes_gcm_decrypt/aes_gcm_decrypt.uvproj | 449 ++++++++ .../aes_gcm_decrypt/aes_gcm_decrypt_ccs.cmd | 70 ++ .../dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsimportspec | 8 + boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsproject | 10 + boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.cproject | 191 ++++ boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.project | 70 ++ .../ccs/.settings/org.eclipse.cdt.codan.core.prefs | 3 + .../aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.bin | Bin 0 -> 33376 bytes .../aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.out | Bin 0 -> 251368 bytes .../aes_gcm_decrypt/ccs/macros.ini_initial | 1 + .../aes_gcm_decrypt/ccs/target_config.ccxml | 13 + .../aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.bin | Bin 0 -> 30652 bytes .../aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.out | Bin 0 -> 224512 bytes .../aes_gcm_decrypt/gcc/aes_gcm_decrypt.axf | Bin 0 -> 82943 bytes .../aes_gcm_decrypt/gcc/aes_gcm_decrypt.bin | Bin 0 -> 40924 bytes boards/dk-tm4c129x/aes_gcm_decrypt/readme.txt | 28 + .../aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.axf | Bin 0 -> 224728 bytes .../aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.bin | Bin 0 -> 31408 bytes boards/dk-tm4c129x/aes_gcm_decrypt/startup_ccs.c | 275 +++++ boards/dk-tm4c129x/aes_gcm_decrypt/startup_ewarm.c | 306 +++++ boards/dk-tm4c129x/aes_gcm_decrypt/startup_gcc.c | 322 ++++++ boards/dk-tm4c129x/aes_gcm_decrypt/startup_rvmdk.S | 331 ++++++ 30 files changed, 5314 insertions(+) create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/Makefile create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.c create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewd create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewp create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.icf create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ld create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.sct create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvopt create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvproj create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt_ccs.cmd create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsimportspec create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsproject create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.cproject create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.project create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.bin create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.out create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/macros.ini_initial create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ccs/target_config.ccxml create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.bin create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.out create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.axf create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.bin create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/readme.txt create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.axf create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.bin create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/startup_ccs.c create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/startup_ewarm.c create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/startup_gcc.c create mode 100644 boards/dk-tm4c129x/aes_gcm_decrypt/startup_rvmdk.S (limited to 'boards/dk-tm4c129x/aes_gcm_decrypt') diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/Makefile b/boards/dk-tm4c129x/aes_gcm_decrypt/Makefile new file mode 100644 index 0000000..a41ddc1 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/Makefile @@ -0,0 +1,91 @@ +#****************************************************************************** +# +# Makefile - Rules for building the AES128 and AES256 GCM Decryption Demo. +# +# Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +# +#****************************************************************************** + +# +# Defines the part type that this project uses. +# +PART=TM4C129XNCZAD + +# +# The base directory for TivaWare. +# +ROOT=../../../.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find source files that do not live in this directory. +# +VPATH=../drivers +VPATH+=../../../../utils + +# +# Where to find header files that do not live in the source directory. +# +IPATH=.. +IPATH+=../../../.. + +# +# The default rule, which causes the AES128 and AES256 GCM Decryption Demo to be built. +# +all: ${COMPILER} +all: ${COMPILER}/aes_gcm_decrypt.axf + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}: + @mkdir -p ${COMPILER} + +# +# Rules for building the AES128 and AES256 GCM Decryption Demo. +# +${COMPILER}/aes_gcm_decrypt.axf: ${COMPILER}/aes_gcm_decrypt.o +${COMPILER}/aes_gcm_decrypt.axf: ${COMPILER}/frame.o +${COMPILER}/aes_gcm_decrypt.axf: ${COMPILER}/kentec320x240x16_ssd2119.o +${COMPILER}/aes_gcm_decrypt.axf: ${COMPILER}/pinout.o +${COMPILER}/aes_gcm_decrypt.axf: ${COMPILER}/startup_${COMPILER}.o +${COMPILER}/aes_gcm_decrypt.axf: ${COMPILER}/uartstdio.o +${COMPILER}/aes_gcm_decrypt.axf: ${ROOT}/grlib/${COMPILER}/libgr.a +${COMPILER}/aes_gcm_decrypt.axf: ${ROOT}/driverlib/${COMPILER}/libdriver.a +${COMPILER}/aes_gcm_decrypt.axf: aes_gcm_decrypt.ld +SCATTERgcc_aes_gcm_decrypt=aes_gcm_decrypt.ld +ENTRY_aes_gcm_decrypt=ResetISR +CFLAGSgcc=-DTARGET_IS_TM4C129_RA0 + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.c b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.c new file mode 100644 index 0000000..0cb11b7 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.c @@ -0,0 +1,1190 @@ +//***************************************************************************** +// +// aes_gcm_decrypt.c - Simple AES GCM decryption demo. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include +#include "inc/hw_aes.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "driverlib/aes.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/rom.h" +#include "driverlib/rom_map.h" +#include "driverlib/sysctl.h" +#include "driverlib/uart.h" +#include "driverlib/udma.h" +#include "grlib/grlib.h" +#include "drivers/frame.h" +#include "drivers/kentec320x240x16_ssd2119.h" +#include "drivers/pinout.h" +#include "utils/uartstdio.h" + +//***************************************************************************** +// +//! \addtogroup example_list +//!

AES128 and AES256 GCM Decryption Demo (aes_gcm_decrypt)

+//! +//! Simple demo showing authenticated decryption operations using the AES +//! module in GCM mode. The test vectors are from the gcm_revised_spec.pdf +//! document. +//! +//! Please note that the use of interrupts and uDMA is not required for the +//! operation of the module. It is only done for demonstration purposes. +// +//***************************************************************************** + +//***************************************************************************** +// +// Configuration defines. +// +//***************************************************************************** +#define CCM_LOOP_TIMEOUT 500000 + +//***************************************************************************** +// +// The DMA control structure table. +// +//***************************************************************************** +#if defined(ewarm) +#pragma data_alignment=1024 +tDMAControlTable g_psDMAControlTable[64]; +#elif defined(ccs) +#pragma DATA_ALIGN(g_psDMAControlTable, 1024) +tDMAControlTable g_psDMAControlTable[64]; +#else +tDMAControlTable g_psDMAControlTable[64] __attribute__((aligned(1024))); +#endif + +//***************************************************************************** +// +// Structure for NIST AES GCM tests +// +//***************************************************************************** +typedef struct AESTestVectorStruct +{ + uint32_t ui32KeySize; + uint32_t pui32Key[8]; + uint32_t ui32IVLength; + uint32_t pui32IV[64]; + uint32_t ui32DataLength; + uint32_t pui32PlainText[64]; + uint32_t ui32AuthDataLength; + uint32_t pui32AuthData[64]; + uint32_t pui32CipherText[64]; + uint32_t pui32Tag[4]; +} +tAESGCMTestVector; + +//***************************************************************************** +// +// Test Cases from NIST GCM Revised Spec. +// +//***************************************************************************** +tAESGCMTestVector g_psAESGCMTestVectors[] = +{ + // + // Test Case #1 + // This is a special case that cannot use the GCM mode because the + // data and AAD lengths are both zero. The work around is to perform + // an ECB encryption on Y0. + // + { + AES_CFG_KEY_SIZE_128BIT, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 12, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 0, + { 0 }, + 0, + { 0 }, + { 0 }, + { 0xcefce258, 0x61307efa, 0x571d7f36, 0x5a45e7a4 } + }, + + // + // Test Case #2 + // This is the first test in which the AAD length is zero. + // + { + AES_CFG_KEY_SIZE_128BIT, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 12, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 16, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 0, + { 0 }, + { 0xceda8803, 0x92a3b660, 0xb9c228f3, 0x78feb271 }, + { 0xd4476eab, 0xbd13ec2c, 0xb2673af5, 0xdfbd5712 } + }, + + // + // Test Case #3 + // + { + AES_CFG_KEY_SIZE_128BIT, + { 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067 }, + 12, + { 0xbebafeca, 0xaddbcefa, 0x88f8cade, 0x00000000 }, + 64, + { 0x253231d9, 0xe50684f8, 0xc50959a5, 0x9a26f5af, + 0x53a9a786, 0xdaf73415, 0x3d304c2e, 0x728a318a, + 0x950c3c1c, 0x53096895, 0x240ecf2f, 0x25b5a649, + 0xf5ed6ab1, 0x57e60daa, 0x397b63ba, 0x55d2af1a }, + 0, + { 0 }, + { 0xc21e8342, 0x24747721, 0xb721724b, 0x9cd4d084, + 0x2f21aae3, 0xe0a4022c, 0x237ec135, 0x2ea1ac29, + 0xb214d521, 0x1c936654, 0x5a6a8f7d, 0x05aa84ac, + 0x390ba31b, 0x97ac0a6a, 0x91e0583d, 0x85593f47 }, + { 0xf32a5c4d, 0xa664cd27, 0xbd5af32c, 0xb4faa62b } + }, + + // + // Test Case #4 + // When the data lengths do not align with the block + // boundary, we need to pad with zeros to ensure unknown + // data is not copied with uDMA. + // + { + AES_CFG_KEY_SIZE_128BIT, + { 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067 }, + 12, + { 0xbebafeca, 0xaddbcefa, 0x88f8cade, 0x00000000 }, + 60, + { 0x253231d9, 0xe50684f8, 0xc50959a5, 0x9a26f5af, + 0x53a9a786, 0xdaf73415, 0x3d304c2e, 0x728a318a, + 0x950c3c1c, 0x53096895, 0x240ecf2f, 0x25b5a649, + 0xf5ed6ab1, 0x57e60daa, 0x397b63ba, 0x00000000 }, + 20, + { 0xcefaedfe, 0xefbeadde, 0xcefaedfe, 0xefbeadde, + 0xd2daadab, 0x00000000, 0x00000000, 0x00000000 }, + { 0xc21e8342, 0x24747721, 0xb721724b, 0x9cd4d084, + 0x2f21aae3, 0xe0a4022c, 0x237ec135, 0x2ea1ac29, + 0xb214d521, 0x1c936654, 0x5a6a8f7d, 0x05aa84ac, + 0x390ba31b, 0x97ac0a6a, 0x91e0583d, 0x00000000 }, + { 0xbc4fc95b, 0xdba52132, 0x5ae9fa94, 0x471a12e7 } + }, + + // + // Test Case #5 + // This is the first case in which IV is less than + // 96 bits. + // + { + AES_CFG_KEY_SIZE_128BIT, + { 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067 }, + 8, + { 0xbebafeca, 0xaddbcefa, 0x00000000, 0x00000000 }, + 60, + { 0x253231d9, 0xe50684f8, 0xc50959a5, 0x9a26f5af, + 0x53a9a786, 0xdaf73415, 0x3d304c2e, 0x728a318a, + 0x950c3c1c, 0x53096895, 0x240ecf2f, 0x25b5a649, + 0xf5ed6ab1, 0x57e60daa, 0x397b63ba, 0x00000000 }, + 20, + { 0xcefaedfe, 0xefbeadde, 0xcefaedfe, 0xefbeadde, + 0xd2daadab, 0x00000000, 0x00000000, 0x00000000 }, + { 0x4c3b3561, 0x4a930628, 0x1ff57f77, 0x55472aa2, + 0x712a9b69, 0xf8c6cd4f, 0xf9e56637, 0x23746c7b, + 0x00698073, 0xb2249fe4, 0x4475092b, 0x426b89d4, + 0xe1b58949, 0x070faceb, 0x98453fc2, 0x00000000 }, + { 0xe7d21236, 0x85073b9e, 0x4ae11b56, 0xcbfca2ac } + }, + + // + // Test Case #6 + // This is the first case in which IV is more than + // 96 bits. + // + { + AES_CFG_KEY_SIZE_128BIT, + { 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067 }, + 60, + { 0x5d221393, 0xe50684f8, 0x5a9c9055, 0xaa6952ff, + 0x38957a6a, 0xa17d4f53, 0xd203c3e4, 0x28a718a3, + 0x51c9c0c3, 0x39958056, 0x42e2f0fc, 0x54526b9a, + 0xf5dbae16, 0x576adea0, 0x9bb337a6, 0x00000000 }, + 60, + { 0x253231d9, 0xe50684f8, 0xc50959a5, 0x9a26f5af, + 0x53a9a786, 0xdaf73415, 0x3d304c2e, 0x728a318a, + 0x950c3c1c, 0x53096895, 0x240ecf2f, 0x25b5a649, + 0xf5ed6ab1, 0x57e60daa, 0x397b63ba, 0x00000000 }, + 20, + { 0xcefaedfe, 0xefbeadde, 0xcefaedfe, 0xefbeadde, + 0xd2daadab }, + { 0x9849e28c, 0xb6155662, 0xac33a003, 0x94b83fa1, + 0xa51291be, 0xa811a2c3, 0x3c2a26ba, 0xa72c7eca, + 0xa4a9e401, 0x903ca4fb, 0x81b2dccc, 0x6f7c8cd4, + 0xd27528d6, 0x0317a4ac, 0xe5ae344c, 0x00000000 }, + { 0xaec59c61, 0xfa0bfeff, 0x3cf42a46, 0x50d09916 } + }, + + // + // The following test cases use 256bit Keys. + // + // Test Case #7 - Test Case 13 from the doc + // This is a special case that cannot use the GCM mode because the + // data and AAD lengths are both zero. The work around is to perform + // an ECB encryption on Y0. + // + { + AES_CFG_KEY_SIZE_256BIT, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 12, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 0, + { 0 }, + 0, + { 0 }, + { 0 }, + { 0xfb8a0f53, 0xb93645c7, 0xf1b463a9, 0x8b73cbc4 } + }, + + // + // Test Case #8, - Test Case 14 from the doc + // This is the first test in which the AAD length is zero. + // + { + AES_CFG_KEY_SIZE_256BIT, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 12, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 16, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + 0, + { 0 }, + { 0x3d40a7ce, 0x6e6b604d, 0xd3c54e07, 0x189df3ba }, + { 0xa7c8d1d0, 0xf06b9999, 0xb5985b26, 0x19b98ad4 } + }, + + // + // Test Case #9, - Test Case 15 from the doc + // + { + AES_CFG_KEY_SIZE_256BIT, + { 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067, + 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067 }, + 12, + { 0xbebafeca, 0xaddbcefa, 0x88f8cade, 0x00000000 }, + 64, + { 0x253231d9, 0xe50684f8, 0xc50959a5, 0x9a26f5af, + 0x53a9a786, 0xdaf73415, 0x3d304c2e, 0x728a318a, + 0x950c3c1c, 0x53096895, 0x240ecf2f, 0x25b5a649, + 0xf5ed6ab1, 0x57e60daa, 0x397b63ba, 0x55d2af1a }, + 0, + { 0 }, + { 0xf0c12d52, 0x077d5699, 0xa3377ff4, 0x7d42842a, + 0xdc8c3a64, 0xc9c0e5bf, 0xbda29875, 0xaad15525, + 0x488eb08c, 0x3dbb0d59, 0x108bb0a7, 0x38888256, + 0x631ef6c5, 0x0a7aba93, 0x62f6c9bc, 0xad158089 }, + { 0xc5da94b0, 0xbd7134d9, 0x22501aec, 0x6ccce370 } + }, + + // + // Test Case #10 - Test Case 16 from the doc + // When the data lengths do not align with the block + // boundary, we need to pad with zeros to ensure unknown + // data is not copied with uDMA. + // + { + AES_CFG_KEY_SIZE_256BIT, + { 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067, + 0x92e9fffe, 0x1c736586, 0x948f6a6d, 0x08833067 }, + 12, + { 0xbebafeca, 0xaddbcefa, 0x88f8cade, 0x00000000 }, + 60, + { 0x253231d9, 0xe50684f8, 0xc50959a5, 0x9a26f5af, + 0x53a9a786, 0xdaf73415, 0x3d304c2e, 0x728a318a, + 0x950c3c1c, 0x53096895, 0x240ecf2f, 0x25b5a649, + 0xf5ed6ab1, 0x57e60daa, 0x397b63ba, 0x00000000 }, + 20, + { 0xcefaedfe, 0xefbeadde, 0xcefaedfe, 0xefbeadde, + 0xd2daadab, 0x00000000, 0x00000000, 0x00000000 }, + { 0xf0c12d52, 0x077d5699, 0xa3377ff4, 0x7d42842a, + 0xdc8c3a64, 0xc9c0e5bf, 0xbda29875, 0xaad15525, + 0x488eb08c, 0x3dbb0d59, 0x108bb0a7, 0x38888256, + 0x631ef6c5, 0x0a7aba93, 0x62f6c9bc, 0x00000000 }, + { 0xce6efc76, 0x68174e0f, 0x5388dfcd, 0x1b552dbb } + } +}; + +//***************************************************************************** +// +// The error routine that is called if the driver library encounters an error. +// +//***************************************************************************** +#ifdef DEBUG +void +__error__(char *pcFilename, uint32_t ui32Line) +{ +} +#endif + +//***************************************************************************** +// +// Round up length to nearest 16 byte boundary. This is needed because all +// four data registers must be written at once. This is handled in the AES +// driver, but if using uDMA, the length must rounded up. +// +//***************************************************************************** +uint32_t +LengthRoundUp(uint32_t ui32Length) +{ + uint32_t ui32Remainder; + + ui32Remainder = ui32Length % 16; + if(ui32Remainder == 0) + { + return(ui32Length); + } + else + { + return(ui32Length + (16 - ui32Remainder)); + } +} + +//***************************************************************************** +// +// The AES interrupt handler and interrupt flags. +// +//***************************************************************************** +static volatile bool g_bContextInIntFlag; +static volatile bool g_bDataInIntFlag; +static volatile bool g_bContextOutIntFlag; +static volatile bool g_bDataOutIntFlag; +static volatile bool g_bContextInDMADoneIntFlag; +static volatile bool g_bDataInDMADoneIntFlag; +static volatile bool g_bContextOutDMADoneIntFlag; +static volatile bool g_bDataOutDMADoneIntFlag; + +void +AESIntHandler(void) +{ + uint32_t ui32IntStatus; + + // + // Read the AES masked interrupt status. + // + ui32IntStatus = ROM_AESIntStatus(AES_BASE, true); + + // + // Print a different message depending on the interrupt source. + // + if(ui32IntStatus & AES_INT_CONTEXT_IN) + { + ROM_AESIntDisable(AES_BASE, AES_INT_CONTEXT_IN); + g_bContextInIntFlag = true; + UARTprintf("Context input registers are ready.\n"); + } + if(ui32IntStatus & AES_INT_DATA_IN) + { + ROM_AESIntDisable(AES_BASE, AES_INT_DATA_IN); + g_bDataInIntFlag = true; + UARTprintf("Data FIFO is ready to receive data.\n"); + } + if(ui32IntStatus & AES_INT_CONTEXT_OUT) + { + ROM_AESIntDisable(AES_BASE, AES_INT_CONTEXT_OUT); + g_bContextOutIntFlag = true; + UARTprintf("Context output registers are ready.\n"); + } + if(ui32IntStatus & AES_INT_DATA_OUT) + { + ROM_AESIntDisable(AES_BASE, AES_INT_DATA_OUT); + g_bDataOutIntFlag = true; + UARTprintf("Data FIFO is ready to provide data.\n"); + } + if(ui32IntStatus & AES_INT_DMA_CONTEXT_IN) + { + ROM_AESIntClear(AES_BASE, AES_INT_DMA_CONTEXT_IN); + g_bContextInDMADoneIntFlag = true; + UARTprintf("DMA completed a context write to the internal\n"); + UARTprintf("registers.\n"); + } + if(ui32IntStatus & AES_INT_DMA_DATA_IN) + { + ROM_AESIntClear(AES_BASE, AES_INT_DMA_DATA_IN); + g_bDataInDMADoneIntFlag = true; + UARTprintf("DMA has written the last word of input data to\n"); + UARTprintf("the internal FIFO of the engine.\n"); + } + if(ui32IntStatus & AES_INT_DMA_CONTEXT_OUT) + { + ROM_AESIntClear(AES_BASE, AES_INT_DMA_CONTEXT_OUT); + g_bContextOutDMADoneIntFlag = true; + UARTprintf("DMA completed the output context movement from\n"); + UARTprintf("the internal registers.\n"); + } + if(ui32IntStatus & AES_INT_DMA_DATA_OUT) + { + ROM_AESIntClear(AES_BASE, AES_INT_DMA_DATA_OUT); + g_bDataOutDMADoneIntFlag = true; + UARTprintf("DMA has written the last word of process result.\n"); + } +} + +//***************************************************************************** +// +// Perform an ECB encryption operation. +// +//***************************************************************************** +bool +AESECBEncrypt(uint32_t ui32Keysize, uint32_t *pui32Src, uint32_t *pui32Dst, + uint32_t *pui32Key, uint32_t ui32Length) +{ + // + // Perform a soft reset. + // + ROM_AESReset(AES_BASE); + + // + // Configure the AES module. + // + ROM_AESConfigSet(AES_BASE, (ui32Keysize | AES_CFG_DIR_ENCRYPT | + AES_CFG_MODE_ECB)); + + // + // Write the key. + // + ROM_AESKey1Set(AES_BASE, pui32Key, ui32Keysize); + + // + // Perform the encryption. + // + ROM_AESDataProcess(AES_BASE, pui32Src, pui32Dst, ui32Length); + + return(true); +} + +//***************************************************************************** +// +// Calculate hash subkey with the given key. +// This is performed by encrypting 128 zeroes with the key. +// +//***************************************************************************** +void +AESHashSubkeyGet(uint32_t ui32Keysize, uint32_t *pui32Key, + uint32_t *pui32HashSubkey) +{ + uint32_t pui32ZeroArray[8]; + + // + // Put zeroes into the first 4 words of the array. + // + pui32ZeroArray[0] = 0x0; + pui32ZeroArray[1] = 0x0; + pui32ZeroArray[2] = 0x0; + pui32ZeroArray[3] = 0x0; + + // + // Put zeroes into the next 4 words if the key size is 256bit + // + if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) + { + pui32ZeroArray[4] = 0x0; + pui32ZeroArray[5] = 0x0; + pui32ZeroArray[6] = 0x0; + pui32ZeroArray[7] = 0x0; + } + + // + // Perform the encryption. + // + AESECBEncrypt(ui32Keysize, pui32ZeroArray, pui32HashSubkey, pui32Key, + (ui32Keysize == AES_CFG_KEY_SIZE_128BIT?16:32)); +} + +//***************************************************************************** +// +// Perform a basic GHASH operation with the hashsubkey and IV. This is +// used to get Y0 when the IV is not 96 bits. To use this GCM mode, the +// operation direction must not be set and the counter should be disabled. +// +//***************************************************************************** +void +AESGHASH(uint32_t ui32Keysize, uint32_t *pui32HashSubkey, uint32_t *pui32IV, + uint32_t ui32IVLength, uint32_t *pui32Result) +{ + uint32_t ui32Count; + + // + // Perform a soft reset. + // + ROM_AESReset(AES_BASE); + + // + // Configure the AES module. + // + ROM_AESConfigSet(AES_BASE, (ui32Keysize | AES_CFG_MODE_GCM_HLY0ZERO)); + + // + // Set the hash subkey. + // + ROM_AESKey2Set(AES_BASE, pui32HashSubkey, ui32Keysize); + + // + // Write the lengths + // + ROM_AESLengthSet(AES_BASE, (uint64_t)ui32IVLength); + ROM_AESAuthLengthSet(AES_BASE, 0); + + // + // Write the data. + // + for(ui32Count = 0; ui32Count < ui32IVLength; ui32Count += 16) + { + // + // Write the data registers. + // + ROM_AESDataWrite(AES_BASE, pui32IV + (ui32Count / 4)); + } + + // + // Read the hash tag value. + // + AESTagRead(AES_BASE, pui32Result); +} + +//***************************************************************************** +// +// Calculate the Y0 value that needs to be written into the IV registers. +// Note: Y0 will always be 128 bits. +// +//***************************************************************************** +void +AESGCMY0Get(uint32_t ui32Keysize, uint32_t *pui32IV, uint32_t ui32IVLength, + uint32_t *pui32Key, uint32_t *pui32Y0) +{ + uint32_t pui32HashSubkey[8]; + + // + // If the length is 96 bits, then just set the last bit of the IV to 1. + // + if(ui32IVLength == 12) + { + pui32Y0[0] = pui32IV[0]; + pui32Y0[1] = pui32IV[1]; + pui32Y0[2] = pui32IV[2]; + pui32Y0[3] = 0x01000000; + } + + // + // If the length is not 96 bits, then peform a basic GHASH on the IV. + // + else + { + // + // First, get the hash subkey or H. + // + AESHashSubkeyGet(ui32Keysize, pui32Key, pui32HashSubkey); + + // + // Next, perform the GHASH operation. + // + AESGHASH(ui32Keysize, pui32HashSubkey, pui32IV, ui32IVLength, pui32Y0); + } +} + +//***************************************************************************** +// +// Perform an GCM decryption operation. +// +//***************************************************************************** +bool +AESGCMDecrypt(uint32_t ui32Keysize, uint32_t *pui32Src, uint32_t *pui32Dst, + uint32_t ui32Length, uint32_t *pui32Key, uint32_t *pui32IV, + uint32_t *pui32AAD, uint32_t ui32AADLength, uint32_t *pui32Tag, + bool bUseDMA) +{ + // + // Perform a soft reset. + // + ROM_AESReset(AES_BASE); + + // + // Clear the interrupt flags. + // + g_bContextInIntFlag = false; + g_bDataInIntFlag = false; + g_bContextOutIntFlag = false; + g_bDataOutIntFlag = false; + g_bContextInDMADoneIntFlag = false; + g_bDataInDMADoneIntFlag = false; + g_bContextOutDMADoneIntFlag = false; + g_bDataOutDMADoneIntFlag = false; + + // + // Enable all interrupts. + // + ROM_AESIntEnable(AES_BASE, (AES_INT_CONTEXT_IN | AES_INT_CONTEXT_OUT | + AES_INT_DATA_IN | AES_INT_DATA_OUT)); + + // + // Wait for the context in flag. + // + while(!g_bContextInIntFlag) + { + } + + // + // Configure the AES module. + // + ROM_AESConfigSet(AES_BASE, (ui32Keysize | AES_CFG_DIR_DECRYPT | + AES_CFG_MODE_GCM_HY0CALC)); + + // + // Write the initialization value + // + ROM_AESIVSet(AES_BASE, pui32IV); + + // + // Write the keys. + // + ROM_AESKey1Set(AES_BASE, pui32Key, ui32Keysize); + + // + // Depending on the argument, perform the decryption + // with or without uDMA. + // + if(bUseDMA) + { + // + // Enable DMA interrupts. + // + ROM_AESIntEnable(AES_BASE, (AES_INT_DMA_CONTEXT_IN | + AES_INT_DMA_DATA_IN | + AES_INT_DMA_CONTEXT_OUT | + AES_INT_DMA_DATA_OUT)); + + if(ui32AADLength != 0) + { + // + // Setup the DMA module to copy auth data in. + // + ROM_uDMAChannelAssign(UDMA_CH14_AES0DIN); + ROM_uDMAChannelAttributeDisable(UDMA_CH14_AES0DIN, + UDMA_ATTR_ALTSELECT | + UDMA_ATTR_USEBURST | + UDMA_ATTR_HIGH_PRIORITY | + UDMA_ATTR_REQMASK); + ROM_uDMAChannelControlSet(UDMA_CH14_AES0DIN | UDMA_PRI_SELECT, + UDMA_SIZE_32 | UDMA_SRC_INC_32 | + UDMA_DST_INC_NONE | UDMA_ARB_4 | + UDMA_DST_PROT_PRIV); + ROM_uDMAChannelTransferSet(UDMA_CH14_AES0DIN | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, (void *)pui32AAD, + (void *)(AES_BASE + AES_O_DATA_IN_0), + LengthRoundUp(ui32AADLength) / 4); + UARTprintf("Data in DMA request enabled.\n"); + } + + // + // Setup the DMA module to copy the data out. + // + ROM_uDMAChannelAssign(UDMA_CH15_AES0DOUT); + ROM_uDMAChannelAttributeDisable(UDMA_CH15_AES0DOUT, + UDMA_ATTR_ALTSELECT | + UDMA_ATTR_USEBURST | + UDMA_ATTR_HIGH_PRIORITY | + UDMA_ATTR_REQMASK); + ROM_uDMAChannelControlSet(UDMA_CH15_AES0DOUT | UDMA_PRI_SELECT, + UDMA_SIZE_32 | UDMA_SRC_INC_NONE | + UDMA_DST_INC_32 | UDMA_ARB_4 | + UDMA_SRC_PROT_PRIV); + ROM_uDMAChannelTransferSet(UDMA_CH15_AES0DOUT | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, + (void *)(AES_BASE + AES_O_DATA_IN_0), + (void *)pui32Dst, + LengthRoundUp(ui32Length) / 4); + UARTprintf("Data out DMA request enabled.\n"); + + // + // Write the plaintext length + // + ROM_AESLengthSet(AES_BASE, (uint64_t)ui32Length); + + // + // Write the auth length registers to start the process. + // + ROM_AESAuthLengthSet(AES_BASE, ui32AADLength); + + // + // Enable the DMA channels to start the transfers. This must be done after + // writing the length to prevent data from copying before the context is + // truly ready. + // + if(ui32AADLength != 0) + { + ROM_uDMAChannelEnable(UDMA_CH14_AES0DIN); + } + ROM_uDMAChannelEnable(UDMA_CH15_AES0DOUT); + + // + // Enable DMA requests + // + ROM_AESDMAEnable(AES_BASE, AES_DMA_DATA_IN | AES_DMA_DATA_OUT); + + if(ui32AADLength != 0) + { + // + // Wait for the data in DMA done interrupt. + // + while(!g_bDataInDMADoneIntFlag) + { + } + } + + if(ui32Length != 0) + { + // + // Setup the uDMA to copy the plaintext data. + // + ROM_uDMAChannelAssign(UDMA_CH14_AES0DIN); + ROM_uDMAChannelAttributeDisable(UDMA_CH14_AES0DIN, + UDMA_ATTR_ALTSELECT | + UDMA_ATTR_USEBURST | + UDMA_ATTR_HIGH_PRIORITY | + UDMA_ATTR_REQMASK); + ROM_uDMAChannelControlSet(UDMA_CH14_AES0DIN | UDMA_PRI_SELECT, + UDMA_SIZE_32 | UDMA_SRC_INC_32 | + UDMA_DST_INC_NONE | UDMA_ARB_4 | + UDMA_DST_PROT_PRIV); + ROM_uDMAChannelTransferSet(UDMA_CH14_AES0DIN | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, (void *)pui32Src, + (void *)(AES_BASE + AES_O_DATA_IN_0), + LengthRoundUp(ui32Length) / 4); + ROM_uDMAChannelEnable(UDMA_CH14_AES0DIN); + UARTprintf("Data in DMA request enabled.\n"); + + // + // Wait for the data out DMA done interrupt. + // + while(!g_bDataOutDMADoneIntFlag) + { + } + } + + // + // Read out the tag. + // + AESTagRead(AES_BASE, pui32Tag); + } + else + { + // + // Perform the decryption. + // + ROM_AESDataProcessAuth(AES_BASE, pui32Src, pui32Dst, ui32Length, + pui32AAD, ui32AADLength, pui32Tag); + } + + return(true); +} + +//***************************************************************************** +// +// Initialize the AES and CCM modules. +// +//***************************************************************************** +bool +AESInit(void) +{ + uint32_t ui32Loop; + + // + // Check that the CCM peripheral is present. + // + if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_CCM0)) + { + UARTprintf("No CCM peripheral found!\n"); + + // + // Return failure. + // + return(false); + } + + // + // The hardware is available, enable it. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_CCM0); + + // + // Wait for the peripheral to be ready. + // + ui32Loop = 0; + while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0)) + { + // + // Increment our poll counter. + // + ui32Loop++; + + if(ui32Loop > CCM_LOOP_TIMEOUT) + { + // + // Timed out, notify and spin. + // + UARTprintf("Time out on CCM ready after enable.\n"); + + // + // Return failure. + // + return(false); + } + } + + // + // Reset the peripheral to ensure we are starting from a known condition. + // + ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_CCM0); + + // + // Wait for the peripheral to be ready again. + // + ui32Loop = 0; + while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0)) + { + // + // Increment our poll counter. + // + ui32Loop++; + + if(ui32Loop > CCM_LOOP_TIMEOUT) + { + // + // Timed out, spin. + // + UARTprintf("Time out on CCM ready after reset.\n"); + + // + // Return failure. + // + return(false); + } + } + + // + // Return initialization success. + // + return(true); +} + +//***************************************************************************** +// +// Configure the UART and its pins. This must be called before UARTprintf(). +// +//***************************************************************************** +void +ConfigureUART(void) +{ + // + // Enable UART0 + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + // + // Use the internal 16MHz oscillator as the UART clock source. + // + ROM_UARTClockSourceSet(UART0_BASE, UART_CLOCK_PIOSC); + + // + // Initialize the UART for console I/O. + // + UARTStdioConfig(0, 115200, 16000000); +} + +//***************************************************************************** +// +// This example decrypts blocks ciphertext using AES128 and AES256 in GCM +// mode. It does the decryption first without uDMA and then with uDMA. +// The results are checked after each operation. +// +//***************************************************************************** +int +main(void) +{ + uint32_t pui32PlainText[64], pui32Tag[4], pui32Y0[4], ui32Errors, ui32Idx; + uint32_t *pui32Key, ui32IVLength, *pui32IV, ui32DataLength; + uint32_t *pui32ExpPlainText, ui32AuthDataLength, *pui32AuthData; + uint32_t *pui32CipherText, *pui32ExpTag; + uint32_t ui32KeySize; + uint32_t ui32SysClock; + uint8_t ui8Vector; + tContext sContext; + + // + // Run from the PLL at 120 MHz. + // + ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | + SYSCTL_OSC_MAIN | + SYSCTL_USE_PLL | + SYSCTL_CFG_VCO_480), 120000000); + + // + // Configure the device pins. + // + PinoutSet(); + + // + // Initialize the display driver. + // + Kentec320x240x16_SSD2119Init(ui32SysClock); + + // + // Initialize the graphics context. + // + GrContextInit(&sContext, &g_sKentec320x240x16_SSD2119); + + // + // Draw the application frame. + // + FrameDraw(&sContext, "aes-gcm-decrypt"); + + // + // Show some instructions on the display + // + GrContextFontSet(&sContext, g_psFontCm20); + GrContextForegroundSet(&sContext, ClrWhite); + GrStringDrawCentered(&sContext, "Connect a terminal to", -1, + GrContextDpyWidthGet(&sContext) / 2, 60, false); + GrStringDrawCentered(&sContext, "UART0 (115200,N,8,1)", -1, + GrContextDpyWidthGet(&sContext) / 2, 80, false); + GrStringDrawCentered(&sContext, "for more information.", -1, + GrContextDpyWidthGet(&sContext) / 2, 100, false); + + // + // Initialize local variables. + // + ui32Errors = 0; + for(ui32Idx = 0; ui32Idx < 16; ui32Idx++) + { + pui32PlainText[ui32Idx] = 0; + } + for(ui32Idx = 0; ui32Idx < 4; ui32Idx++) + { + pui32Tag[ui32Idx] = 0; + } + + // + // Enable stacking for interrupt handlers. This allows floating-point + // instructions to be used within interrupt handlers, but at the expense of + // extra stack usage. + // + ROM_FPUStackingEnable(); + + // + // Enable AES interrupts. + // + ROM_IntEnable(INT_AES0); + + // + // Enable debug output on UART0 and print a welcome message. + // + ConfigureUART(); + UARTprintf("Starting AES GCM decryption demo.\n"); + GrStringDrawCentered(&sContext, "Starting demo...", -1, + GrContextDpyWidthGet(&sContext) / 2, 140, false); + + // + // Enable the uDMA module. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); + + // + // Setup the control table. + // + ROM_uDMAEnable(); + ROM_uDMAControlBaseSet(g_psDMAControlTable); + + // + // Initialize the CCM and AES modules. + // + if(!AESInit()) + { + UARTprintf("Initialization of the AES module failed.\n"); + ui32Errors |= 0x00000001; + } + + // + // Loop through all the given vectors. + // + for(ui8Vector = 0; + (ui8Vector < + (sizeof(g_psAESGCMTestVectors) / sizeof(g_psAESGCMTestVectors[0]))) && + (ui32Errors == 0); + ui8Vector++) + { + UARTprintf("Starting vector #%d\n", ui8Vector); + + // + // Get the current vector's data members. + // + ui32KeySize = g_psAESGCMTestVectors[ui8Vector].ui32KeySize; + pui32Key = g_psAESGCMTestVectors[ui8Vector].pui32Key; + ui32IVLength = g_psAESGCMTestVectors[ui8Vector].ui32IVLength; + pui32IV = g_psAESGCMTestVectors[ui8Vector].pui32IV; + ui32DataLength = g_psAESGCMTestVectors[ui8Vector].ui32DataLength; + pui32ExpPlainText = g_psAESGCMTestVectors[ui8Vector].pui32PlainText; + ui32AuthDataLength = + g_psAESGCMTestVectors[ui8Vector].ui32AuthDataLength; + pui32AuthData = g_psAESGCMTestVectors[ui8Vector].pui32AuthData; + pui32CipherText = g_psAESGCMTestVectors[ui8Vector].pui32CipherText; + pui32ExpTag = g_psAESGCMTestVectors[ui8Vector].pui32Tag; + + // + // If both the data lengths are zero, then it's a special case. + // + if((ui32DataLength == 0) && (ui32AuthDataLength == 0)) + { + UARTprintf("Performing decryption without uDMA.\n"); + + // + // Figure out the value of Y0 depending on the IV length. + // + AESGCMY0Get(ui32KeySize, pui32IV, ui32IVLength, pui32Key, pui32Y0); + + // + // Perform the basic encryption. + // + AESECBEncrypt(ui32KeySize, pui32Y0, pui32Tag, pui32Key, 16); + } + else + { + // + // Figure out the value of Y0 depending on the IV length. + // + AESGCMY0Get(ui32KeySize, pui32IV, ui32IVLength, pui32Key, pui32Y0); + + // + // Perform the decryption without uDMA. + // + UARTprintf("Performing decryption without uDMA.\n"); + AESGCMDecrypt(ui32KeySize, pui32CipherText, pui32PlainText, + ui32DataLength, pui32Key, pui32Y0, pui32AuthData, + ui32AuthDataLength, pui32Tag, false); + } + + // + // Check the results. + // + for(ui32Idx = 0; ui32Idx < (ui32DataLength / 4); ui32Idx++) + { + if(pui32ExpPlainText[ui32Idx] != pui32PlainText[ui32Idx]) + { + UARTprintf("Plaintext mismatch on word %d. Exp: 0x%x, Act: " + "0x%x\n", ui32Idx, pui32ExpPlainText[ui32Idx], + pui32PlainText[ui32Idx]); + ui32Errors |= (ui32Idx << 16) | 0x00000002; + } + } + for(ui32Idx = 0; ui32Idx < 4; ui32Idx++) + { + if(pui32ExpTag[ui32Idx] != pui32Tag[ui32Idx]) + { + UARTprintf("Tag mismatch on word %d. Exp: 0x%x, Act: 0x%x\n", + ui32Idx, pui32ExpTag[ui32Idx], pui32Tag[ui32Idx]); + ui32Errors |= (ui32Idx << 16) | 0x00000003; + } + } + + // + // Clear the arrays containing the ciphertext and tag to ensure things + // are working correctly. + // + for(ui32Idx = 0; ui32Idx < 16; ui32Idx++) + { + pui32PlainText[ui32Idx] = 0; + } + for(ui32Idx = 0; ui32Idx < 4; ui32Idx++) + { + pui32Tag[ui32Idx] = 0; + } + + // + // Only use DMA with the vectors that have data. + // + if((ui32DataLength != 0) || (ui32AuthDataLength != 0)) + { + // + // Perform the decryption with uDMA. + // + UARTprintf("Performing decryption with uDMA.\n"); + AESGCMDecrypt(ui32KeySize, pui32CipherText, pui32PlainText, + ui32DataLength, pui32Key, pui32Y0, pui32AuthData, + ui32AuthDataLength, pui32Tag, true); + + // + // Check the result. + // + for(ui32Idx = 0; ui32Idx < (ui32DataLength / 4); ui32Idx++) + { + if(pui32ExpPlainText[ui32Idx] != pui32PlainText[ui32Idx]) + { + UARTprintf("Plaintext mismatch on word %d. Exp: 0x%x, " + "Act: 0x%x\n", ui32Idx, + pui32ExpPlainText[ui32Idx], + pui32PlainText[ui32Idx]); + ui32Errors |= (ui32Idx << 16) | 0x00000002; + } + } + for(ui32Idx = 0; ui32Idx < 4; ui32Idx++) + { + if(pui32ExpTag[ui32Idx] != pui32Tag[ui32Idx]) + { + UARTprintf("Tag mismatch on word %d. Exp: 0x%x, Act: " + "0x%x\n", ui32Idx, pui32ExpTag[ui32Idx], + pui32Tag[ui32Idx]); + ui32Errors |= (ui32Idx << 16) | 0x00000003; + } + } + } + } + + // + // Finished. + // + if(ui32Errors) + { + UARTprintf("Demo failed with error code 0x%x.\n", ui32Errors); + GrStringDrawCentered(&sContext, "Demo failed.", -1, + GrContextDpyWidthGet(&sContext) / 2, 180, false); + } + else + { + UARTprintf("Demo completed successfully.\n"); + GrStringDrawCentered(&sContext, "Demo passed.", -1, + GrContextDpyWidthGet(&sContext) / 2, 180, false); + } + + // + // Wait forever. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewd b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewd new file mode 100644 index 0000000..484e41a --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewd @@ -0,0 +1,614 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewp b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewp new file mode 100644 index 0000000..f38cf74 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ewp @@ -0,0 +1,801 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Libraries + + $PROJ_DIR$\..\..\..\..\driverlib\ewarm\Exe\driverlib.a + + + $PROJ_DIR$\..\..\..\..\grlib\ewarm\Exe\grlib.a + + + + Source + + $PROJ_DIR$\aes_gcm_decrypt.c + + + $PROJ_DIR$\..\drivers\frame.c + + + $PROJ_DIR$\..\drivers\kentec320x240x16_ssd2119.c + + + $PROJ_DIR$\..\drivers\pinout.c + + + $PROJ_DIR$\startup_ewarm.c + + + $PROJ_DIR$\..\..\..\..\utils\uartstdio.c + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.icf b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.icf new file mode 100644 index 0000000..0019c3f --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.icf @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// aes_gcm_decrypt.icf - Linker configuration file for aes_gcm_decrypt. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x000fffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x2003ffff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Indicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place the RAM vector table at the start of SRAM. +// +place at start of SRAM { section VTABLE }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ld b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ld new file mode 100644 index 0000000..0bc9a25 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.ld @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * aes_gcm_decrypt.ld - Linker configuration file for aes_gcm_decrypt. + * + * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.sct b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.sct new file mode 100644 index 0000000..2bf4320 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.sct @@ -0,0 +1,47 @@ +;****************************************************************************** +; +; aes_gcm_decrypt.sct - Linker configuration file for aes_gcm_decrypt. +; +; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** + +LR_IROM 0x00000000 0x00100000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00100000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00040000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvopt b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvopt new file mode 100644 index 0000000..c47e7a9 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvopt @@ -0,0 +1,359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + aes_gcm_decrypt + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\TM4C129XNCZAD.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4614 -S1 -FO29 + + + 0 + DLGTARM + + + + 0 + ARMDBGFLAGS + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\aes_gcm_decrypt.c + aes_gcm_decrypt.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\frame.c + frame.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\kentec320x240x16_ssd2119.c + kentec320x240x16_ssd2119.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\drivers\pinout.c + pinout.c + + + 1 + 5 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_rvmdk.S + startup_rvmdk.S + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\utils\uartstdio.c + uartstdio.c + + + + + Libraries + 1 + 0 + 0 + + 2 + 7 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + driverlib.lib + + + 2 + 8 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\grlib\rvmdk\grlib.lib + grlib.lib + + + + + Documentation + 1 + 0 + 0 + + 3 + 9 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvproj b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvproj new file mode 100644 index 0000000..6856f2f --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.uvproj @@ -0,0 +1,449 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + aes_gcm_decrypt + 0x4 + ARM-ADS + + + TM4C129XNCZAD + Texas Instruments + IRAM(0x20000000-0x2003FFFF) IROM(0-0xFFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_1024 -FS00 -FL0100000) + 5919 + LM4Fxxxx.H + + + + + + + + + + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk\ + aes_gcm_decrypt + 1 + 0 + 0 + 1 + 1 + .\rvmdk\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\rvmdk\aes_gcm_decrypt.bin .\rvmdk\aes_gcm_decrypt.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 4 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + --c99 + rvmdk PART_TM4C129XNCZAD TARGET_IS_TM4C129_RA0 + + ..;..\..\..\..; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + aes_gcm_decrypt.sct + + + --entry Reset_Handler + + + + + + + + Source + + + aes_gcm_decrypt.c + 1 + .\aes_gcm_decrypt.c + + + frame.c + 1 + ..\drivers\frame.c + + + kentec320x240x16_ssd2119.c + 1 + ..\drivers\kentec320x240x16_ssd2119.c + + + pinout.c + 1 + ..\drivers\pinout.c + + + startup_rvmdk.S + 2 + .\startup_rvmdk.S + + + uartstdio.c + 1 + ..\..\..\..\utils\uartstdio.c + + + + + Libraries + + + driverlib.lib + 4 + ..\..\..\..\driverlib\rvmdk\driverlib.lib + + + grlib.lib + 4 + ..\..\..\..\grlib\rvmdk\grlib.lib + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt_ccs.cmd b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt_ccs.cmd new file mode 100644 index 0000000..790c3a8 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt_ccs.cmd @@ -0,0 +1,70 @@ +/****************************************************************************** + * + * aes_gcm_decrypt_ccs.cmd - CCS linker configuration file for aes_gcm_decrypt. + * + * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * + *****************************************************************************/ + +--retain=g_pfnVectors + +/* The following command line options are set as part of the CCS project. */ +/* If you are building using the command line, or for some reason want to */ +/* define them here, you can uncomment and modify these lines as needed. */ +/* If you are using CCS for building, it is probably better to make any such */ +/* modifications in your CCS project and leave this file alone. */ +/* */ +/* --heap_size=0 */ +/* --stack_size=256 */ +/* --library=rtsv7M3_T_le_eabi.lib */ + +/* The starting address of the application. Normally the interrupt vectors */ +/* must be located at the beginning of the application. */ +#define APP_BASE 0x00000000 +#define RAM_BASE 0x20000000 + +/* System memory map */ + +MEMORY +{ + /* Application stored in and executes from internal flash */ + FLASH (RX) : origin = APP_BASE, length = 0x00100000 + /* Application uses internal RAM for data */ + SRAM (RWX) : origin = 0x20000000, length = 0x00040000 +} + +/* Section allocation in memory */ + +SECTIONS +{ + .intvecs: > APP_BASE + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .vtable : > RAM_BASE + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} + +__STACK_TOP = __stack + 1024; diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsimportspec b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsimportspec new file mode 100644 index 0000000..c0a5a25 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsimportspec @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsproject b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsproject new file mode 100644 index 0000000..59a3400 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.ccsproject @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.cproject b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.cproject new file mode 100644 index 0000000..7c834ab --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.cproject @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.project b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.project new file mode 100644 index 0000000..66b532f --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.project @@ -0,0 +1,70 @@ + + + aes_gcm_decrypt + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + aes_gcm_decrypt.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt.c + + + aes_gcm_decrypt_ccs.cmd + 1 + SW_ROOT/examples/boards/dk-tm4c129x/aes_gcm_decrypt/aes_gcm_decrypt_ccs.cmd + + + startup_ccs.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ccs.c + + + drivers/frame.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/frame.c + + + drivers/kentec320x240x16_ssd2119.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/kentec320x240x16_ssd2119.c + + + drivers/pinout.c + 1 + SW_ROOT/examples/boards/dk-tm4c129x/drivers/pinout.c + + + utils/uartstdio.c + 1 + SW_ROOT/utils/uartstdio.c + + + + + SW_ROOT + $%7BPARENT-5-PROJECT_LOC%7D + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.settings/org.eclipse.cdt.codan.core.prefs b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.bin b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.bin new file mode 100644 index 0000000..dc8f56d Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.bin differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.out b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.out new file mode 100644 index 0000000..8a9809d Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/Debug/aes_gcm_decrypt.out differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/macros.ini_initial b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/macros.ini_initial new file mode 100644 index 0000000..31214b5 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../../../../.. diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/target_config.ccxml b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/target_config.ccxml new file mode 100644 index 0000000..6e5ef45 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/ccs/target_config.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.bin b/boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.bin new file mode 100644 index 0000000..f854d57 Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.bin differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.out b/boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.out new file mode 100644 index 0000000..bf5f245 Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/ewarm/Exe/aes_gcm_decrypt.out differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.axf b/boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.axf new file mode 100644 index 0000000..761a928 Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.axf differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.bin b/boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.bin new file mode 100644 index 0000000..b1e0be5 Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/gcc/aes_gcm_decrypt.bin differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/readme.txt b/boards/dk-tm4c129x/aes_gcm_decrypt/readme.txt new file mode 100644 index 0000000..314d5b2 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/readme.txt @@ -0,0 +1,28 @@ +AES128 and AES256 GCM Decryption Demo + +Simple demo showing authenticated decryption operations using the AES +module in GCM mode. The test vectors are from the gcm_revised_spec.pdf +document. + +Please note that the use of interrupts and uDMA is not required for the +operation of the module. It is only done for demonstration purposes. + +------------------------------------------------------------------------------- + +Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + +Texas Instruments (TI) is supplying this software for use solely and +exclusively on TI's microcontroller products. The software is owned by +TI and/or its suppliers, and is protected under applicable copyright +laws. You may not combine this software with "viral" open-source +software in order to form a larger program. + +THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, FOR ANY REASON WHATSOEVER. + +This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.axf b/boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.axf new file mode 100644 index 0000000..02697ff Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.axf differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.bin b/boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.bin new file mode 100644 index 0000000..a466050 Binary files /dev/null and b/boards/dk-tm4c129x/aes_gcm_decrypt/rvmdk/aes_gcm_decrypt.bin differ diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ccs.c b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ccs.c new file mode 100644 index 0000000..882868b --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ccs.c @@ -0,0 +1,275 @@ +//***************************************************************************** +// +// startup_ccs.c - Startup code for use with TI's Code Composer Studio. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern uint32_t __STACK_TOP; + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void AESIntHandler(void); + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".intvecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)&__STACK_TOP), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + AESIntHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Jump to the CCS C initialization routine. This will enable the + // floating-point unit as well, so that does not need to be done here. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ewarm.c b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ewarm.c new file mode 100644 index 0000000..b08ccba --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_ewarm.c @@ -0,0 +1,306 @@ +//***************************************************************************** +// +// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, +// version 5. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void AESIntHandler(void); + +//***************************************************************************** +// +// The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[256] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + uint32_t ui32Ptr; +} +uVectorEntry; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + AESIntHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + __iar_program_start(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/startup_gcc.c b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_gcc.c new file mode 100644 index 0000000..f1c5730 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_gcc.c @@ -0,0 +1,322 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// +//***************************************************************************** + +#include +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void AESIntHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static uint32_t pui32Stack[256]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + AESIntHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler // GPIO Port T +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _etext; +extern uint32_t _data; +extern uint32_t _edata; +extern uint32_t _bss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + uint32_t *pui32Src, *pui32Dest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pui32Src = &_etext; + for(pui32Dest = &_data; pui32Dest < &_edata; ) + { + *pui32Dest++ = *pui32Src++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/dk-tm4c129x/aes_gcm_decrypt/startup_rvmdk.S b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_rvmdk.S new file mode 100644 index 0000000..558dc08 --- /dev/null +++ b/boards/dk-tm4c129x/aes_gcm_decrypt/startup_rvmdk.S @@ -0,0 +1,331 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000400 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; External declaration for the interrupt handler used by the application. +; +;****************************************************************************** + EXTERN AESIntHandler + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; The MPU fault handler + DCD IntDefaultHandler ; The bus fault handler + DCD IntDefaultHandler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall handler + DCD IntDefaultHandler ; Debug monitor handler + DCD 0 ; Reserved + DCD IntDefaultHandler ; The PendSV handler + DCD IntDefaultHandler ; The SysTick handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD IntDefaultHandler ; UART0 Rx and Tx + DCD IntDefaultHandler ; UART1 Rx and Tx + DCD IntDefaultHandler ; SSI0 Rx and Tx + DCD IntDefaultHandler ; I2C0 Master and Slave + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder 0 + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog timer + DCD IntDefaultHandler ; Timer 0 subtimer A + DCD IntDefaultHandler ; Timer 0 subtimer B + DCD IntDefaultHandler ; Timer 1 subtimer A + DCD IntDefaultHandler ; Timer 1 subtimer B + DCD IntDefaultHandler ; Timer 2 subtimer A + DCD IntDefaultHandler ; Timer 2 subtimer B + DCD IntDefaultHandler ; Analog Comparator 0 + DCD IntDefaultHandler ; Analog Comparator 1 + DCD IntDefaultHandler ; Analog Comparator 2 + DCD IntDefaultHandler ; System Control (PLL, OSC, BO) + DCD IntDefaultHandler ; FLASH Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD IntDefaultHandler ; Ethernet + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + DCD IntDefaultHandler ; ADC1 Sequence 0 + DCD IntDefaultHandler ; ADC1 Sequence 1 + DCD IntDefaultHandler ; ADC1 Sequence 2 + DCD IntDefaultHandler ; ADC1 Sequence 3 + DCD IntDefaultHandler ; External Bus Interface 0 + DCD IntDefaultHandler ; GPIO Port J + DCD IntDefaultHandler ; GPIO Port K + DCD IntDefaultHandler ; GPIO Port L + DCD IntDefaultHandler ; SSI2 Rx and Tx + DCD IntDefaultHandler ; SSI3 Rx and Tx + DCD IntDefaultHandler ; UART3 Rx and Tx + DCD IntDefaultHandler ; UART4 Rx and Tx + DCD IntDefaultHandler ; UART5 Rx and Tx + DCD IntDefaultHandler ; UART6 Rx and Tx + DCD IntDefaultHandler ; UART7 Rx and Tx + DCD IntDefaultHandler ; I2C2 Master and Slave + DCD IntDefaultHandler ; I2C3 Master and Slave + DCD IntDefaultHandler ; Timer 4 subtimer A + DCD IntDefaultHandler ; Timer 4 subtimer B + DCD IntDefaultHandler ; Timer 5 subtimer A + DCD IntDefaultHandler ; Timer 5 subtimer B + DCD IntDefaultHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C4 Master and Slave + DCD IntDefaultHandler ; I2C5 Master and Slave + DCD IntDefaultHandler ; GPIO Port M + DCD IntDefaultHandler ; GPIO Port N + DCD 0 ; Reserved + DCD IntDefaultHandler ; Tamper + DCD IntDefaultHandler ; GPIO Port P (Summary or P0) + DCD IntDefaultHandler ; GPIO Port P1 + DCD IntDefaultHandler ; GPIO Port P2 + DCD IntDefaultHandler ; GPIO Port P3 + DCD IntDefaultHandler ; GPIO Port P4 + DCD IntDefaultHandler ; GPIO Port P5 + DCD IntDefaultHandler ; GPIO Port P6 + DCD IntDefaultHandler ; GPIO Port P7 + DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) + DCD IntDefaultHandler ; GPIO Port Q1 + DCD IntDefaultHandler ; GPIO Port Q2 + DCD IntDefaultHandler ; GPIO Port Q3 + DCD IntDefaultHandler ; GPIO Port Q4 + DCD IntDefaultHandler ; GPIO Port Q5 + DCD IntDefaultHandler ; GPIO Port Q6 + DCD IntDefaultHandler ; GPIO Port Q7 + DCD IntDefaultHandler ; GPIO Port R + DCD IntDefaultHandler ; GPIO Port S + DCD IntDefaultHandler ; SHA/MD5 0 + DCD AESIntHandler ; AES 0 + DCD IntDefaultHandler ; DES3DES 0 + DCD IntDefaultHandler ; LCD Controller 0 + DCD IntDefaultHandler ; Timer 6 subtimer A + DCD IntDefaultHandler ; Timer 6 subtimer B + DCD IntDefaultHandler ; Timer 7 subtimer A + DCD IntDefaultHandler ; Timer 7 subtimer B + DCD IntDefaultHandler ; I2C6 Master and Slave + DCD IntDefaultHandler ; I2C7 Master and Slave + DCD IntDefaultHandler ; HIM Scan Matrix Keyboard 0 + DCD IntDefaultHandler ; One Wire 0 + DCD IntDefaultHandler ; HIM PS/2 0 + DCD IntDefaultHandler ; HIM LED Sequencer 0 + DCD IntDefaultHandler ; HIM Consumer IR 0 + DCD IntDefaultHandler ; I2C8 Master and Slave + DCD IntDefaultHandler ; I2C9 Master and Slave + DCD IntDefaultHandler ; GPIO Port T + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Enable the floating-point unit. This must be done here to handle the + ; case where main() uses floating-point and the function prologue saves + ; floating-point registers (which will fault if floating-point is not + ; enabled). Any configuration of the floating-point unit using + ; DriverLib APIs must be done here prior to the floating-point unit + ; being enabled. + ; + ; Note that this does not use DriverLib since it might not be included + ; in this project. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END -- cgit v1.3.1