From 44b979ac3dc53b29ee8176517b7d9a10935630c0 Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Mon, 29 Oct 2012 21:36:23 +0200 Subject: Initial code --- driverlib/Makefile | 50 + driverlib/Makefile.driverlib-cm3 | 106 + driverlib/Makefile.driverlib-cm4f | 106 + driverlib/adc.c | 1565 + driverlib/adc.h | 311 + driverlib/can.c | 2265 + driverlib/can.h | 465 + driverlib/ccs-cm3/.ccsproject | 11 + driverlib/ccs-cm3/.cproject | 159 + driverlib/ccs-cm3/.project | 236 + .../.settings/org.eclipse.cdt.codan.core.prefs | 3 + driverlib/ccs-cm3/Debug/driverlib-cm3.lib | Bin 0 -> 1426902 bytes driverlib/ccs-cm3/macros.ini_initial | 1 + driverlib/ccs-cm4f/.ccsproject | 11 + driverlib/ccs-cm4f/.cproject | 144 + driverlib/ccs-cm4f/.project | 236 + .../.settings/org.eclipse.cdt.codan.core.prefs | 3 + driverlib/ccs-cm4f/Debug/driverlib-cm4f.lib | Bin 0 -> 1372220 bytes driverlib/ccs-cm4f/macros.ini_initial | 1 + driverlib/comp.c | 451 + driverlib/comp.h | 145 + driverlib/cpu.c | 457 + driverlib/cpu.h | 75 + driverlib/debug.h | 68 + driverlib/driverlib-cm3.ewp | 857 + driverlib/driverlib-cm3.sgxx | Bin 0 -> 3485 bytes driverlib/driverlib-cm3.uvopt | 636 + driverlib/driverlib-cm3.uvproj | 550 + driverlib/driverlib-cm4f.ewp | 857 + driverlib/driverlib-cm4f.sgxx | Bin 0 -> 3505 bytes driverlib/driverlib-cm4f.uvopt | 636 + driverlib/driverlib-cm4f.uvproj | 550 + driverlib/eeprom.c | 1140 + driverlib/eeprom.h | 279 + driverlib/epi.c | 1190 + driverlib/epi.h | 319 + driverlib/ethernet.c | 1381 + driverlib/ethernet.h | 187 + driverlib/ewarm-cm3/Exe/driverlib-cm3.a | Bin 0 -> 1328232 bytes driverlib/ewarm-cm4f/Exe/driverlib-cm4f.a | Bin 0 -> 1362980 bytes driverlib/fan.c | 649 + driverlib/fan.h | 216 + driverlib/flash.c | 929 + driverlib/flash.h | 126 + driverlib/fpu.c | 299 + driverlib/fpu.h | 112 + driverlib/gcc-cm3/libdriver-cm3.a | Bin 0 -> 178134 bytes driverlib/gcc-cm4f/libdriver-cm4f.a | Bin 0 -> 178330 bytes driverlib/gpio.c | 2076 + driverlib/gpio.h | 199 + driverlib/hibernate.c | 1354 + driverlib/hibernate.h | 167 + driverlib/i2c.c | 1590 + driverlib/i2c.h | 224 + driverlib/i2s.c | 1149 + driverlib/i2s.h | 169 + driverlib/interrupt.c | 837 + driverlib/interrupt.h | 93 + driverlib/lpc.c | 1548 + driverlib/lpc.h | 485 + driverlib/mpu.c | 460 + driverlib/mpu.h | 162 + driverlib/peci.c | 1000 + driverlib/peci.h | 241 + driverlib/pin_map.h | 61811 +++++++++++++++++++ driverlib/pwm.c | 1880 + driverlib/pwm.h | 298 + driverlib/qei.c | 633 + driverlib/qei.h | 127 + driverlib/readme.txt | 36 + driverlib/rom.h | 6744 ++ driverlib/rom_map.h | 5075 ++ driverlib/rtos_bindings.h | 107 + driverlib/rvmdk-cm3/driverlib-cm3.lib | Bin 0 -> 2903488 bytes driverlib/rvmdk-cm4f/driverlib-cm4f.lib | Bin 0 -> 2942232 bytes driverlib/ssi.c | 870 + driverlib/ssi.h | 151 + driverlib/sysctl.c | 3147 + driverlib/sysctl.h | 642 + driverlib/sysexc.c | 256 + driverlib/sysexc.h | 89 + driverlib/systick.c | 275 + driverlib/systick.h | 78 + driverlib/timer.c | 1549 + driverlib/timer.h | 236 + driverlib/uart.c | 1948 + driverlib/uart.h | 275 + driverlib/udma.c | 1383 + driverlib/udma.h | 755 + driverlib/usb.c | 4066 ++ driverlib/usb.h | 587 + driverlib/watchdog.c | 628 + driverlib/watchdog.h | 95 + 93 files changed, 123277 insertions(+) create mode 100644 driverlib/Makefile create mode 100644 driverlib/Makefile.driverlib-cm3 create mode 100644 driverlib/Makefile.driverlib-cm4f create mode 100644 driverlib/adc.c create mode 100644 driverlib/adc.h create mode 100644 driverlib/can.c create mode 100644 driverlib/can.h create mode 100644 driverlib/ccs-cm3/.ccsproject create mode 100644 driverlib/ccs-cm3/.cproject create mode 100644 driverlib/ccs-cm3/.project create mode 100644 driverlib/ccs-cm3/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 driverlib/ccs-cm3/Debug/driverlib-cm3.lib create mode 100644 driverlib/ccs-cm3/macros.ini_initial create mode 100644 driverlib/ccs-cm4f/.ccsproject create mode 100644 driverlib/ccs-cm4f/.cproject create mode 100644 driverlib/ccs-cm4f/.project create mode 100644 driverlib/ccs-cm4f/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 driverlib/ccs-cm4f/Debug/driverlib-cm4f.lib create mode 100644 driverlib/ccs-cm4f/macros.ini_initial create mode 100644 driverlib/comp.c create mode 100644 driverlib/comp.h create mode 100644 driverlib/cpu.c create mode 100644 driverlib/cpu.h create mode 100644 driverlib/debug.h create mode 100644 driverlib/driverlib-cm3.ewp create mode 100644 driverlib/driverlib-cm3.sgxx create mode 100644 driverlib/driverlib-cm3.uvopt create mode 100644 driverlib/driverlib-cm3.uvproj create mode 100644 driverlib/driverlib-cm4f.ewp create mode 100644 driverlib/driverlib-cm4f.sgxx create mode 100644 driverlib/driverlib-cm4f.uvopt create mode 100644 driverlib/driverlib-cm4f.uvproj create mode 100644 driverlib/eeprom.c create mode 100644 driverlib/eeprom.h create mode 100644 driverlib/epi.c create mode 100644 driverlib/epi.h create mode 100644 driverlib/ethernet.c create mode 100644 driverlib/ethernet.h create mode 100644 driverlib/ewarm-cm3/Exe/driverlib-cm3.a create mode 100644 driverlib/ewarm-cm4f/Exe/driverlib-cm4f.a create mode 100644 driverlib/fan.c create mode 100644 driverlib/fan.h create mode 100644 driverlib/flash.c create mode 100644 driverlib/flash.h create mode 100644 driverlib/fpu.c create mode 100644 driverlib/fpu.h create mode 100644 driverlib/gcc-cm3/libdriver-cm3.a create mode 100644 driverlib/gcc-cm4f/libdriver-cm4f.a create mode 100644 driverlib/gpio.c create mode 100644 driverlib/gpio.h create mode 100644 driverlib/hibernate.c create mode 100644 driverlib/hibernate.h create mode 100644 driverlib/i2c.c create mode 100644 driverlib/i2c.h create mode 100644 driverlib/i2s.c create mode 100644 driverlib/i2s.h create mode 100644 driverlib/interrupt.c create mode 100644 driverlib/interrupt.h create mode 100644 driverlib/lpc.c create mode 100644 driverlib/lpc.h create mode 100644 driverlib/mpu.c create mode 100644 driverlib/mpu.h create mode 100644 driverlib/peci.c create mode 100644 driverlib/peci.h create mode 100644 driverlib/pin_map.h create mode 100644 driverlib/pwm.c create mode 100644 driverlib/pwm.h create mode 100644 driverlib/qei.c create mode 100644 driverlib/qei.h create mode 100644 driverlib/readme.txt create mode 100644 driverlib/rom.h create mode 100644 driverlib/rom_map.h create mode 100644 driverlib/rtos_bindings.h create mode 100644 driverlib/rvmdk-cm3/driverlib-cm3.lib create mode 100644 driverlib/rvmdk-cm4f/driverlib-cm4f.lib create mode 100644 driverlib/ssi.c create mode 100644 driverlib/ssi.h create mode 100644 driverlib/sysctl.c create mode 100644 driverlib/sysctl.h create mode 100644 driverlib/sysexc.c create mode 100644 driverlib/sysexc.h create mode 100644 driverlib/systick.c create mode 100644 driverlib/systick.h create mode 100644 driverlib/timer.c create mode 100644 driverlib/timer.h create mode 100644 driverlib/uart.c create mode 100644 driverlib/uart.h create mode 100644 driverlib/udma.c create mode 100644 driverlib/udma.h create mode 100644 driverlib/usb.c create mode 100644 driverlib/usb.h create mode 100644 driverlib/watchdog.c create mode 100644 driverlib/watchdog.h (limited to 'driverlib') diff --git a/driverlib/Makefile b/driverlib/Makefile new file mode 100644 index 0000000..fe65ae7 --- /dev/null +++ b/driverlib/Makefile @@ -0,0 +1,50 @@ +#****************************************************************************** +# +# Makefile - Rules for building the driver library. +# +# Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# This is part of revision 9453 of the Stellaris Peripheral Driver Library. +# +#****************************************************************************** + +all: + @make -f Makefile.driverlib-cm3 + @make -f Makefile.driverlib-cm4f + +clean: + @make -f Makefile.driverlib-cm3 clean + @make -f Makefile.driverlib-cm4f clean + +realclean: + @make -f Makefile.driverlib-cm3 realclean + @make -f Makefile.driverlib-cm4f realclean diff --git a/driverlib/Makefile.driverlib-cm3 b/driverlib/Makefile.driverlib-cm3 new file mode 100644 index 0000000..0bf1a72 --- /dev/null +++ b/driverlib/Makefile.driverlib-cm3 @@ -0,0 +1,106 @@ +#****************************************************************************** +# +# Makefile.driverlib-cm3 - Rules for building the driver library. +# +# Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 9453 of the Stellaris Peripheral Driver Library. +# +#****************************************************************************** + +# +# Defines the directory suffix that this project uses. +# +SUFFIX=-cm3 + +# +# Set the processor variant. +# +VARIANT=cm3 + +# +# The base directory for StellarisWare. +# +ROOT=.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find header files that do not live in the source directory. +# +IPATH=.. + +# +# The default rule, which causes the driver library to be built. +# +all: ${COMPILER}-cm3 +all: ${COMPILER}-cm3/libdriver-cm3.a + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER}-cm3 ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}-cm3: + @mkdir -p ${COMPILER}-cm3 + +# +# Rules for building the driver library. +# +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/adc.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/can.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/comp.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/cpu.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/eeprom.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/epi.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/ethernet.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/fan.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/flash.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/fpu.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/gpio.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/hibernate.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/i2c.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/i2s.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/interrupt.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/lpc.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/mpu.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/peci.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/pwm.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/qei.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/ssi.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/sysctl.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/sysexc.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/systick.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/timer.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/uart.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/udma.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/usb.o +${COMPILER}-cm3/libdriver-cm3.a: ${COMPILER}-cm3/watchdog.o + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}-cm3/*.d} __dummy__ +endif diff --git a/driverlib/Makefile.driverlib-cm4f b/driverlib/Makefile.driverlib-cm4f new file mode 100644 index 0000000..ddd11df --- /dev/null +++ b/driverlib/Makefile.driverlib-cm4f @@ -0,0 +1,106 @@ +#****************************************************************************** +# +# Makefile.driverlib-cm4f - Rules for building the driver library. +# +# Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 9453 of the Stellaris Peripheral Driver Library. +# +#****************************************************************************** + +# +# Defines the directory suffix that this project uses. +# +SUFFIX=-cm4f + +# +# Set the processor variant. +# +VARIANT=cm4f + +# +# The base directory for StellarisWare. +# +ROOT=.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find header files that do not live in the source directory. +# +IPATH=.. + +# +# The default rule, which causes the driver library to be built. +# +all: ${COMPILER}-cm4f +all: ${COMPILER}-cm4f/libdriver-cm4f.a + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER}-cm4f ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}-cm4f: + @mkdir -p ${COMPILER}-cm4f + +# +# Rules for building the driver library. +# +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/adc.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/can.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/comp.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/cpu.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/eeprom.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/epi.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/ethernet.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/fan.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/flash.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/fpu.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/gpio.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/hibernate.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/i2c.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/i2s.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/interrupt.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/lpc.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/mpu.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/peci.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/pwm.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/qei.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/ssi.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/sysctl.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/sysexc.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/systick.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/timer.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/uart.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/udma.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/usb.o +${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/watchdog.o + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}-cm4f/*.d} __dummy__ +endif diff --git a/driverlib/adc.c b/driverlib/adc.c new file mode 100644 index 0000000..aebdf12 --- /dev/null +++ b/driverlib/adc.c @@ -0,0 +1,1565 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_adc.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_sysctl.h" +#include "driverlib/adc.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// These defines are used by the ADC driver to simplify access to the ADC +// sequencer's registers. +// +//***************************************************************************** +#define ADC_SEQ (ADC_O_SSMUX0) +#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0) +#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0) +#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0) +#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0) +#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0) +#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0) +#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0) +#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0) + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +static unsigned char g_pucOversampleFactor[3]; + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; the sequence interrupt must be enabled with +//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) : + (INT_ADC1SS0 + ulSequenceNum)); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller; the sequence interrupt +//! must be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) : + (INT_ADC1SS0 + ulSequenceNum)); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); +} + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified sample +//! sequence. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +unsigned long +ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, + tBoolean bMasked) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum); + } + else + { + ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum)); + + // + // If the digital comparator status bit is set, reflect it to the + // appropriate sequence bit. + // + if(ulTemp & 0x10000) + { + ulTemp |= 0xF0000; + ulTemp &= ~(0x10000 << ulSequenceNum); + } + } + + // + // Return the interrupt status + // + return(ulTemp); +} + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep +//! the interrupt from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence should be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); +} + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulTrigger is the trigger source that initiates the sample sequence; +//! must be one of the \b ADC_TRIGGER_* values. +//! \param ulPriority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequencers range from zero to three; sequencer zero captures +//! up to eight samples, sequencers one and two capture up to four samples, +//! and sequencer three captures a single sample. The trigger condition and +//! priority (with respect to other sample sequencer execution) are set. +//! +//! The \e ulTrigger parameter can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. Note that some microcontrollers can +//! select from any GPIO using the +//! GPIOADCTriggerEnable() function. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! Note that not all trigger sources are available on all Stellaris family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents +//! the highest priority and 3 the lowest. Note that when programming the +//! priority among a set of sample sequences, each must have unique priority; +//! it is up to the caller to guarantee the uniqueness of the priorities. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulTrigger, unsigned long ulPriority) +{ + // + // Check the arugments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || + (ulTrigger == ADC_TRIGGER_COMP0) || + (ulTrigger == ADC_TRIGGER_COMP1) || + (ulTrigger == ADC_TRIGGER_COMP2) || + (ulTrigger == ADC_TRIGGER_EXTERNAL) || + (ulTrigger == ADC_TRIGGER_TIMER) || + (ulTrigger == ADC_TRIGGER_PWM0) || + (ulTrigger == ADC_TRIGGER_PWM1) || + (ulTrigger == ADC_TRIGGER_PWM2) || + (ulTrigger == ADC_TRIGGER_PWM3) || + (ulTrigger == ADC_TRIGGER_ALWAYS)); + ASSERT(ulPriority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ulSequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & + ~(0xf << ulSequenceNum)) | + ((ulTrigger & 0xf) << ulSequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & + ~(0xf << ulSequenceNum)) | + ((ulPriority & 0x3) << ulSequenceNum)); +} + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step; must be a logical OR of +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of +//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). +//! +//! This function configures the ADC for one step of a sample sequence. The +//! ADC can be configured for single-ended or differential operation +//! (the \b ADC_CTL_D bit selects differential operation when set), the +//! channel to be sampled can be chosen (the \b ADC_CTL_CH0 through +//! \b ADC_CTL_CH23 values), and the internal temperature sensor can be +//! selected (the \b ADC_CTL_TS bit). Additionally, this step can be defined +//! as the last in the sequence (the \b ADC_CTL_END bit) and it can be +//! configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). If the digital comparators are present on the device, +//! this step may also be configured to send the ADC sample to the selected +//! comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration +//! is used by the ADC at the appropriate time when the trigger for +//! this sequence occurs. +//! +//! \note If the Digital Comparator is present and enabled using the +//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT +//! written into the ADC sequence data FIFO. +//! +//! The \e ulStep parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequencer, from zero to three for the second and +//! third sample sequencer, and can only be zero for the fourth sample +//! sequencer. +//! +//! Differential mode only works with adjacent channel pairs (for example, 0 +//! and 1). The channel select must be the number of the channel pair to +//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 +//! and 3) or undefined results are returned by the ADC. Additionally, if +//! differential mode is selected when the temperature sensor is being sampled, +//! undefined results are returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulStep, unsigned long ulConfig) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || + ((ulSequenceNum == 1) && (ulStep < 4)) || + ((ulSequenceNum == 2) && (ulStep < 4)) || + ((ulSequenceNum == 3) && (ulStep < 1))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the upper bits of the analog mux value for this step. + // + HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf00) >> 8) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + + // + // Enable digital comparator if specified in the ulConfig bit-fields. + // + if(ulConfig & 0x000F0000) + { + // + // Program the comparator for the specified step. + // + ulTemp = HWREG(ulBase + ADC_SSDC); + ulTemp &= ~(0xF << ulStep); + ulTemp |= (((ulConfig & 0x00070000) >> 16) << ulStep); + HWREG(ulBase + ADC_SSDC) = ulTemp; + + // + // Enable the comparator. + // + ulTemp = HWREG(ulBase + ADC_SSOP); + ulTemp |= (1 << ulStep); + HWREG(ulBase + ADC_SSOP) = ulTemp; + } + + // + // Disable digital comparator if not specified. + // + else + { + ulTemp = HWREG(ulBase + ADC_SSOP); + ulTemp &= ~(1 << ulStep); + HWREG(ulBase + ADC_SSOP) = ulTemp; + } +} + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function determines if a sample sequence overflow has occurred. +//! Overflow happens if the captured samples are not read from the FIFO before +//! the next trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +long +ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); +} + +//***************************************************************************** +// +//! Clears the overflow condition on a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function clears an overflow condition on one of the sample sequences. +//! The overflow condition must be cleared in order to detect a subsequent +//! overflow condition (it otherwise causes no harm). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear the overflow condition for this sequence. + // + HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function determines if a sample sequence underflow has occurred. +//! Underflow happens if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +long +ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); +} + +//***************************************************************************** +// +//! Clears the underflow condition on a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function clears an underflow condition on one of the sample sequencers. +//! The underflow condition must be cleared in order to detect a subsequent +//! underflow condition (it otherwise causes no harm). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear the underflow condition for this sequence. + // + HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequencer output FIFO +//! to a memory resident buffer. The number of samples available in the +//! hardware FIFO are copied into the buffer, which is assumed to be large +//! enough to hold that many samples. This function only returns the samples +//! that are presently available, which may not be the entire sample sequence +//! if it is in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +long +ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer) +{ + unsigned long ulCount; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ulCount = 0; + while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO); + + // + // Increment the count of samples read. + // + ulCount++; + } + + // + // Return the number of samples read. + // + return(ulCount); +} + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number, with +//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If +//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the +//! processor-initiated trigger is delayed until a later processor-initiated +//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL, +//! allowing multiple ADCs to start from a processor-initiated trigger in a +//! synchronous manner. +//! +//! \return None. +// +//***************************************************************************** +void +ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT((ulSequenceNum & 0xf) < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ulBase + ADC_O_PSSI) |= ((ulSequenceNum & 0xffff0000) | + (1 << (ulSequenceNum & 0xf))); +} + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (that is, the fourth sample sequencer is not +//! supported). Oversampling by 2x (for example) divides the depth of the +//! sample sequencer by two; so 2x oversampling on the first sample sequencer +//! can only provide four samples per trigger. This also means that 8x +//! oversampling is only available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && + ((ulSequenceNum == 0) || (ulFactor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Save the shift factor. + // + g_pucOversampleFactor[ulSequenceNum] = ulValue; +} + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; + ulSequenceNum; ulSequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the upper bits of the analog mux value for this step. + // + HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf00) >> 8) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + if(ulSequenceNum != 1) + { + HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 | + ADC_SSCTL0_END0) << ulStep); + } + + // + // Go to the next hardware step. + // + ulStep += 4; + } +} + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! \param ulCount is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items, +//! then incorrect results are returned. It is the caller's responsibility to +//! read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer, unsigned long ulCount) +{ + unsigned long ulIdx, ulAccum; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ulCount--) + { + // + // Compute the sum of the samples. + // + ulAccum = 0; + for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ulAccum += HWREG(ulBase + ADC_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; + } +} + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero disables hardware +//! oversampling. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequencer FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 K samples/second ADC to 62.5 K samples/second. +//! +//! \return None. +// +//***************************************************************************** +void +ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || + (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || + (ulFactor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ulBase + ADC_O_SAC) = ulValue; +} + +//***************************************************************************** +// +//! Configures an ADC digital comparator. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function configures a comparator. The \e ulConfig parameter is +//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and +//! \b ADC_COMP_INT_xxx values. +//! +//! The \b ADC_COMP_TRIG_xxx term can take on the following values: +//! +//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition. +//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when +//! ADC output is in the low-band. +//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC +//! output transitions into the low-band. +//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when +//! ADC output is in the low-band only if ADC output has been in the high-band +//! since the last trigger output. +//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC +//! output transitions into low-band only if ADC output has been in the +//! high-band since the last trigger output. +//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when +//! ADC output is in the mid-band. +//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC +//! output transitions into the mid-band. +//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when +//! ADC output is in the high-band. +//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC +//! output transitions into the high-band. +//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when +//! ADC output is in the high-band only if ADC output has been in the low-band +//! since the last trigger output. +//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC +//! output transitions into high-band only if ADC output has been in the +//! low-band since the last trigger output. +//! +//! The \b ADC_COMP_INT_xxx term can take on the following values: +//! +//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt. +//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC +//! output is in the low-band. +//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output +//! transitions into the low-band. +//! - \b ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC +//! output is in the low-band only if ADC output has been in the high-band +//! since the last trigger output. +//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output +//! transitions into low-band only if ADC output has been in the high-band +//! since the last trigger output. +//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC +//! output is in the mid-band. +//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output +//! transitions into the mid-band. +//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC +//! output is in the high-band. +//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output +//! transitions into the high-band. +//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC +//! output is in the high-band only if ADC output has been in the low-band +//! since the last trigger output. +//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output +//! transitions into high-band only if ADC output has been in the low-band +//! since the last trigger output. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulComp < 8); + + // + // Save the new setting. + // + HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig; +} + +//***************************************************************************** +// +//! Defines the ADC digital comparator regions. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulLowRef is the reference point for the low/mid band threshold. +//! \param ulHighRef is the reference point for the mid/high band threshold. +//! +//! The ADC digital comparator operation is based on three ADC value regions: +//! - \b low-band is defined as any ADC value less than or equal to the +//! \e ulLowRef value. +//! - \b mid-band is defined as any ADC value greater than the \e ulLowRef +//! value but less than or equal to the \e ulHighRef value. +//! - \b high-band is defined as any ADC value greater than the \e ulHighRef +//! value. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp, + unsigned long ulLowRef, unsigned long ulHighRef) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulComp < 8); + ASSERT((ulLowRef < 1024) && (ulLowRef <= ulHighRef)); + ASSERT(ulHighRef < 1024); + + // + // Save the new region settings. + // + HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef; +} + +//***************************************************************************** +// +//! Resets the current ADC digital comparator conditions. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulComp is the index of the comparator. +//! \param bTrigger is the flag to indicate reset of Trigger conditions. +//! \param bInterrupt is the flag to indicate reset of Interrupt conditions. +//! +//! Because the digital comparator uses current and previous ADC values, this +//! function allows the comparator to be reset to its initial +//! value to prevent stale data from being used when a sequence is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorReset(unsigned long ulBase, unsigned long ulComp, + tBoolean bTrigger, tBoolean bInterrupt) +{ + unsigned long ulTemp = 0; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulComp < 8); + + // + // Set the appropriate bits to reset the trigger and/or interrupt + // comparator conditions. + // + if(bTrigger) + { + ulTemp |= (1 << (16 + ulComp)); + } + if(bInterrupt) + { + ulTemp |= (1 << ulComp); + } + + HWREG(ulBase + ADC_O_DCRIC) = ulTemp; +} + +//***************************************************************************** +// +//! Disables a sample sequence comparator interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence comparator interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence comparator interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum); +} + +//***************************************************************************** +// +//! Enables a sample sequence comparator interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence comparator interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Gets the current comparator interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! +//! This function returns the digital comparator interrupt status bits. This +//! status is sequence agnostic. +//! +//! \return The current comparator interrupt status. +// +//***************************************************************************** +unsigned long +ADCComparatorIntStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + + // + // Return the digital comparator interrupt status. + // + return(HWREG(ulBase + ADC_O_DCISC)); +} + +//***************************************************************************** +// +//! Clears sample sequence comparator interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulStatus is the bit-mapped interrupts status to clear. +//! +//! The specified interrupt status is cleared. +//! +//! \return None. +// +//***************************************************************************** +void +ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_DCISC) = ulStatus; +} + +//***************************************************************************** +// +//! Selects the ADC reference. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulRef is the reference to use. +//! +//! The ADC reference is set as specified by \e ulRef. It must be one of +//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or +//! external reference. If \b ADC_REF_INT is chosen, then an internal 3V +//! reference is used and no external reference is needed. If +//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the +//! AVREF pin. If \b ADC_REF_EXT_1V is chosen, then a 1V external reference +//! must be supplied to the AVREF pin. +//! +//! \note The ADC reference can only be selected on parts that have an external +//! reference. Consult the data sheet for your part to determine if there is +//! an external reference. +//! +//! \return None. +// +//***************************************************************************** +void +ADCReferenceSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V) || + (ulRef == ADC_REF_EXT_1V)); + + // + // Set the reference. + // + HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) | + ulRef; +} + +//***************************************************************************** +// +//! Returns the current setting of the ADC reference. +//! +//! \param ulBase is the base address of the ADC module. +//! +//! Returns the value of the ADC reference setting. The returned value is one +//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V. +//! +//! \note The value returned by this function is only meaningful if used on a +//! part that is capable of using an external reference. Consult the data +//! sheet for your part to determine if it has an external reference input. +//! +//! \return The current setting of the ADC reference. +// +//***************************************************************************** +unsigned long +ADCReferenceGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + + // + // Return the value of the reference. + // + return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF_M); +} + +//***************************************************************************** +// +//! Selects the ADC resolution. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulResolution is the ADC bit resolution. +//! +//! The ADC resolution is set as specified by \e ulResolution. It must be one +//! of \b ADC_RES_12BIT or \b ADC_RES_10BIT. +//! +//! \note The ADC resolution can only be set on parts that are capable of +//! changing ADC resolution mode. Consult the data sheet for your part to +//! determine if it is capable of operating in more than one resolution mode. +//! +//! \return None. +// +//***************************************************************************** +void +ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT((ulResolution == ADC_RES_10BIT) || (ulResolution == ADC_RES_12BIT)); + + // + // Set the resolution. + // + HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) | + ulResolution; +} + +//***************************************************************************** +// +//! Gets the setting of ADC resolution. +//! +//! \param ulBase is the base address of the ADC module. +//! +//! The ADC resolution is returned as one of \b ADC_RES_12BIT or +//! \b ADC_RES_10BIT. +//! +//! \note The value returned by this function is only meaningful if used on a +//! part that is capable of changing ADC resolution mode. Consult the +//! data sheet for your part to determine if it is capable of operating in +//! more than one resolution mode. +//! +//! \return The current setting of the ADC resolution. +// +//***************************************************************************** +unsigned long +ADCResolutionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + + // + // Get the resolution and return it to the caller. + // + return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_RES); +} + +//***************************************************************************** +// +//! Sets the phase delay between a trigger and the start of a sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulPhase is the phase delay, specified as one of \b ADC_PHASE_0, +//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, +//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, +//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, +//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. +//! +//! This function sets the phase delay between the detection of an ADC trigger +//! event and the start of the sample sequence. By selecting a different phase +//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and +//! \b ADC_PHASE_180) and having each ADC module sample the same analog input, +//! it is possible to increase the sampling rate of the analog input (with +//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1, +//! N+3, N+5, and so on, coming from the second ADC). The ADC module has a +//! single phase delay that is applied to all sample sequences within that +//! module. +//! +//! \note This capability is not available on all parts. +//! +//! \return None. +// +//***************************************************************************** +void +ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT((ulPhase == ADC_PHASE_0) || (ulPhase == ADC_PHASE_22_5) || + (ulPhase == ADC_PHASE_45) || (ulPhase == ADC_PHASE_67_5) || + (ulPhase == ADC_PHASE_90) || (ulPhase == ADC_PHASE_112_5) || + (ulPhase == ADC_PHASE_135) || (ulPhase == ADC_PHASE_157_5) || + (ulPhase == ADC_PHASE_180) || (ulPhase == ADC_PHASE_202_5) || + (ulPhase == ADC_PHASE_225) || (ulPhase == ADC_PHASE_247_5) || + (ulPhase == ADC_PHASE_270) || (ulPhase == ADC_PHASE_292_5) || + (ulPhase == ADC_PHASE_315) || (ulPhase == ADC_PHASE_337_5)); + + // + // Set the phase delay. + // + HWREG(ulBase + ADC_O_SPC) = ulPhase; +} + +//***************************************************************************** +// +//! Gets the phase delay between a trigger and the start of a sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! +//! This function gets the current phase delay between the detection of an ADC +//! trigger event and the start of the sample sequence. +//! +//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0, +//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, +//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, +//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, +//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. +// +//***************************************************************************** +unsigned long +ADCPhaseDelayGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + + // + // Return the phase delay. + // + return(HWREG(ulBase + ADC_O_SPC)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/adc.h b/driverlib/adc.h new file mode 100644 index 0000000..1371da3 --- /dev/null +++ b/driverlib/adc.h @@ -0,0 +1,311 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 +#define ADC_CTL_CH8 0x00000008 // Input channel 8 +#define ADC_CTL_CH9 0x00000009 // Input channel 9 +#define ADC_CTL_CH10 0x0000000A // Input channel 10 +#define ADC_CTL_CH11 0x0000000B // Input channel 11 +#define ADC_CTL_CH12 0x0000000C // Input channel 12 +#define ADC_CTL_CH13 0x0000000D // Input channel 13 +#define ADC_CTL_CH14 0x0000000E // Input channel 14 +#define ADC_CTL_CH15 0x0000000F // Input channel 15 +#define ADC_CTL_CH16 0x00000100 // Input channel 16 +#define ADC_CTL_CH17 0x00000101 // Input channel 17 +#define ADC_CTL_CH18 0x00000102 // Input channel 18 +#define ADC_CTL_CH19 0x00000103 // Input channel 19 +#define ADC_CTL_CH20 0x00000104 // Input channel 20 +#define ADC_CTL_CH21 0x00000105 // Input channel 21 +#define ADC_CTL_CH22 0x00000106 // Input channel 22 +#define ADC_CTL_CH23 0x00000107 // Input channel 23 +#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 +#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 +#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 +#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 +#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 +#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 +#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 +#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 + +//***************************************************************************** +// +// Values that can be passed to ADCComparatorConfigure as part of the +// ulConfig parameter. +// +//***************************************************************************** +#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled +#define ADC_COMP_TRIG_LOW_ALWAYS \ + 0x00001000 // Trigger Low Always +#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once +#define ADC_COMP_TRIG_LOW_HALWAYS \ + 0x00001200 // Trigger Low Always (Hysteresis) +#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) +#define ADC_COMP_TRIG_MID_ALWAYS \ + 0x00001400 // Trigger Mid Always +#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once +#define ADC_COMP_TRIG_HIGH_ALWAYS \ + 0x00001C00 // Trigger High Always +#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once +#define ADC_COMP_TRIG_HIGH_HALWAYS \ + 0x00001E00 // Trigger High Always (Hysteresis) +#define ADC_COMP_TRIG_HIGH_HONCE \ + 0x00001F00 // Trigger High Once (Hysteresis) + +#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled +#define ADC_COMP_INT_LOW_ALWAYS \ + 0x00000010 // Interrupt Low Always +#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once +#define ADC_COMP_INT_LOW_HALWAYS \ + 0x00000012 // Interrupt Low Always + // (Hysteresis) +#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) +#define ADC_COMP_INT_MID_ALWAYS \ + 0x00000014 // Interrupt Mid Always +#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once +#define ADC_COMP_INT_HIGH_ALWAYS \ + 0x0000001C // Interrupt High Always +#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once +#define ADC_COMP_INT_HIGH_HALWAYS \ + 0x0000001E // Interrupt High Always + // (Hysteresis) +#define ADC_COMP_INT_HIGH_HONCE \ + 0x0000001F // Interrupt High Once (Hysteresis) + +//***************************************************************************** +// +// Values that can be used to modify the sequence number passed to +// ADCProcessorTrigger in order to get cross-module synchronous processor +// triggers. +// +//***************************************************************************** +#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger +#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger + +//***************************************************************************** +// +// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and +// returned from ADCPhaseDelayGet. +// +//***************************************************************************** +#define ADC_PHASE_0 0x00000000 // 0 degrees +#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees +#define ADC_PHASE_45 0x00000002 // 45 degrees +#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees +#define ADC_PHASE_90 0x00000004 // 90 degrees +#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees +#define ADC_PHASE_135 0x00000006 // 135 degrees +#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees +#define ADC_PHASE_180 0x00000008 // 180 degrees +#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees +#define ADC_PHASE_225 0x0000000A // 225 degrees +#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees +#define ADC_PHASE_270 0x0000000C // 270 degrees +#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees +#define ADC_PHASE_315 0x0000000E // 315 degrees +#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees + +//***************************************************************************** +// +// Values that can be passed to ADCReferenceSet as the ulRef parameter. +// +//***************************************************************************** +#define ADC_REF_INT 0x00000000 // Internal reference +#define ADC_REF_EXT_3V 0x00000001 // External 3V reference +#define ADC_REF_EXT_1V 0x00000003 // External 1V reference + +//***************************************************************************** +// +// Values that can be passed to ADCResolutionSet as the ulResolution parameter. +// +//***************************************************************************** +#define ADC_RES_10BIT 0x00000000 // 10-bit resolution +#define ADC_RES_12BIT 0x00000010 // 12-bit resolution + +//***************************************************************************** +// +// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), +// ADCIntClearEx() and ADCIntStatusEx(). +// +//***************************************************************************** +#define ADC_INT_SS0 0x00000001 +#define ADC_INT_SS1 0x00000002 +#define ADC_INT_SS2 0x00000004 +#define ADC_INT_SS3 0x00000008 +#define ADC_INT_DMA_SS0 0x00000100 +#define ADC_INT_DMA_SS1 0x00000200 +#define ADC_INT_DMA_SS2 0x00000400 +#define ADC_INT_DMA_SS3 0x00000800 +#define ADC_INT_DCON_SS0 0x00010000 +#define ADC_INT_DCON_SS1 0x00020000 +#define ADC_INT_DCON_SS2 0x00040000 +#define ADC_INT_DCON_SS3 0x00080000 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceOverflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceUnderflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); +extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp, + unsigned long ulLowRef, + unsigned long ulHighRef); +extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp, + tBoolean bTrigger, tBoolean bInterrupt); +extern void ADCComparatorIntDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCComparatorIntEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern unsigned long ADCComparatorIntStatus(unsigned long ulBase); +extern void ADCComparatorIntClear(unsigned long ulBase, + unsigned long ulStatus); +extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef); +extern unsigned long ADCReferenceGet(unsigned long ulBase); +extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution); +extern unsigned long ADCResolutionGet(unsigned long ulBase); +extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase); +extern unsigned long ADCPhaseDelayGet(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/driverlib/can.c b/driverlib/can.c new file mode 100644 index 0000000..d55ee80 --- /dev/null +++ b/driverlib/can.c @@ -0,0 +1,2265 @@ +//***************************************************************************** +// +// can.c - Driver for the CAN module. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_can.h" +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/can.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// This is the maximum number that can be stored as an 11bit Message +// identifier. +// +//***************************************************************************** +#define CAN_MAX_11BIT_MSG_ID 0x7ff + +//***************************************************************************** +// +// This is used as the loop delay for accessing the CAN controller registers. +// +//***************************************************************************** +#define CAN_RW_DELAY 5 + +//***************************************************************************** +// +// The maximum CAN bit timing divisor is 19. +// +//***************************************************************************** +#define CAN_MAX_BIT_DIVISOR 19 + +//***************************************************************************** +// +// The minimum CAN bit timing divisor is 4. +// +//***************************************************************************** +#define CAN_MIN_BIT_DIVISOR 4 + +//***************************************************************************** +// +// The maximum CAN pre-divisor is 1024. +// +//***************************************************************************** +#define CAN_MAX_PRE_DIVISOR 1024 + +//***************************************************************************** +// +// The minimum CAN pre-divisor is 1. +// +//***************************************************************************** +#define CAN_MIN_PRE_DIVISOR 1 + +//***************************************************************************** +// +// Converts a set of CAN bit timing values into the value that needs to be +// programmed into the CAN_BIT register to achieve those timings. +// +//***************************************************************************** +#define CAN_BIT_VALUE(seg1, seg2, sjw) \ + ((((seg1 - 1) << CAN_BIT_TSEG1_S) & \ + CAN_BIT_TSEG1_M) | \ + (((seg2 - 1) << CAN_BIT_TSEG2_S) & \ + CAN_BIT_TSEG2_M) | \ + (((sjw - 1) << CAN_BIT_SJW_S) & \ + CAN_BIT_SJW_M)) + +//***************************************************************************** +// +// This table is used by the CANBitRateSet() API as the register defaults for +// the bit timing values. +// +//***************************************************************************** +static const unsigned short g_usCANBitValues[] = +{ + CAN_BIT_VALUE(2, 1, 1), // 4 clocks/bit + CAN_BIT_VALUE(3, 1, 1), // 5 clocks/bit + CAN_BIT_VALUE(3, 2, 2), // 6 clocks/bit + CAN_BIT_VALUE(4, 2, 2), // 7 clocks/bit + CAN_BIT_VALUE(4, 3, 3), // 8 clocks/bit + CAN_BIT_VALUE(5, 3, 3), // 9 clocks/bit + CAN_BIT_VALUE(5, 4, 4), // 10 clocks/bit + CAN_BIT_VALUE(6, 4, 4), // 11 clocks/bit + CAN_BIT_VALUE(6, 5, 4), // 12 clocks/bit + CAN_BIT_VALUE(7, 5, 4), // 13 clocks/bit + CAN_BIT_VALUE(7, 6, 4), // 14 clocks/bit + CAN_BIT_VALUE(8, 6, 4), // 15 clocks/bit + CAN_BIT_VALUE(8, 7, 4), // 16 clocks/bit + CAN_BIT_VALUE(9, 7, 4), // 17 clocks/bit + CAN_BIT_VALUE(9, 8, 4), // 18 clocks/bit + CAN_BIT_VALUE(10, 8, 4) // 19 clocks/bit +}; + +//***************************************************************************** +// +//! \internal +//! Checks a CAN base address. +//! +//! \param ulBase is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +CANBaseValid(unsigned long ulBase) +{ + return((ulBase == CAN0_BASE) || (ulBase == CAN1_BASE) || + (ulBase == CAN2_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Returns the CAN controller interrupt number. +//! +//! \param ulBase is the base address of the selected CAN controller +//! +//! Given a CAN controller base address, this function returns the +//! corresponding interrupt number. +//! +//! This function replaces the original CANGetIntNumber() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return Returns a CAN interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +static long +CANIntNumberGet(unsigned long ulBase) +{ + long lIntNumber; + + // + // Return the interrupt number for the given CAN controller. + // + switch(ulBase) + { + // + // Return the interrupt number for CAN 0 + // + case CAN0_BASE: + { + lIntNumber = INT_CAN0; + break; + } + + // + // Return the interrupt number for CAN 1 + // + case CAN1_BASE: + { + lIntNumber = INT_CAN1; + break; + } + + // + // Return the interrupt number for CAN 2 + // + case CAN2_BASE: + { + lIntNumber = INT_CAN2; + break; + } + + // + // Return -1 to indicate a bad address was passed in. + // + default: + { + lIntNumber = -1; + } + } + return(lIntNumber); +} + +//***************************************************************************** +// +//! \internal +//! +//! Reads a CAN controller register. +//! +//! \param ulRegAddress is the full address of the CAN register to be read. +//! +//! This function performs the necessary synchronization to read from a CAN +//! controller register. +//! +//! This function replaces the original CANReadReg() API and performs the same +//! actions. A macro is provided in can.h to map the original API to +//! this API. +//! +//! \note This function provides the delay required to access CAN registers. +//! This delay is required when accessing CAN registers directly. +//! +//! \return Returns the value read from the register. +// +//***************************************************************************** +static unsigned long +CANRegRead(unsigned long ulRegAddress) +{ + volatile unsigned long ulDelay; + unsigned long ulRetVal; + unsigned long ulIntNumber; + unsigned long ulReenableInts; + + // + // Get the CAN interrupt number from the register base address. + // + ulIntNumber = CANIntNumberGet(ulRegAddress & 0xfffff000); + + // + // Make sure that the CAN base address was valid. + // + ASSERT(ulIntNumber != (unsigned long)-1); + + // + // Remember current state so that CAN interrupts are only re-enabled if + // they were already enabled. + // + ulReenableInts = HWREG(NVIC_EN1) & (1 << (ulIntNumber - 48)); + + // + // If the CAN interrupt was enabled then disable it. + // + if(ulReenableInts) + { + IntDisable(ulIntNumber); + } + + // + // Trigger the initial read to the CAN controller. The value returned at + // this point is not valid. + // + HWREG(ulRegAddress); + + // + // This delay is necessary for the CAN have the correct data on the bus. + // + for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++) + { + } + + // + // Do the final read that has the valid value of the register. + // + ulRetVal = HWREG(ulRegAddress); + + // + // Enable CAN interrupts if they were enabled before this call. + // + if(ulReenableInts) + { + IntEnable(ulIntNumber); + } + + return(ulRetVal); +} + +//***************************************************************************** +// +//! \internal +//! +//! Writes a CAN controller register. +//! +//! \param ulRegAddress is the full address of the CAN register to be written. +//! \param ulRegValue is the value to write into the register specified by +//! \e ulRegAddress. +//! +//! This function takes care of the synchronization necessary to write to a +//! CAN controller register. +//! +//! This function replaces the original CANWriteReg() API and performs the same +//! actions. A macro is provided in can.h to map the original API to +//! this API. +//! +//! \note The delays in this function are required when accessing CAN registers +//! directly. +//! +//! \return None. +// +//***************************************************************************** +static void +CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue) +{ + volatile unsigned long ulDelay; + + // + // Trigger the initial write to the CAN controller. The value will not make + // it out to the CAN controller for CAN_RW_DELAY cycles. + // + HWREG(ulRegAddress) = ulRegValue; + + // + // Delay to allow the CAN controller to receive the new data. + // + for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++) + { + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pucData is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param pulRegister is an unsigned long pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b + +//! \b CAN_O_IF1DA1. +//! \param iSize is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageSet() +//! function. +//! +//! This function replaces the original CANWriteDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +static void +CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, + unsigned long ulSize) +{ + unsigned long ulIdx, ulValue; + + // + // Loop always copies 1 or 2 bytes per iteration. + // + for(ulIdx = 0; ulIdx < ulSize; ) + { + + // + // Write out the data 16 bits at a time since this is how the registers + // are aligned in memory. + // + ulValue = pucData[ulIdx++]; + + // + // Only write the second byte if needed otherwise it will be zero. + // + if(ulIdx < ulSize) + { + ulValue |= (pucData[ulIdx++] << 8); + } + CANRegWrite((unsigned long)(pulRegister++), ulValue); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pucData is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param pulRegister is an unsigned long pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b + +//! \b CAN_O_IF1DA1. +//! \param iSize is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageGet() +//! function. +//! +//! This function replaces the original CANReadDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +static void +CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, + unsigned long ulSize) +{ + unsigned long ulIdx, ulValue; + + // + // Loop always copies 1 or 2 bytes per iteration. + // + for(ulIdx = 0; ulIdx < ulSize; ) + { + // + // Read out the data 16 bits at a time since this is how the registers + // are aligned in memory. + // + ulValue = CANRegRead((unsigned long)(pulRegister++)); + + // + // Store the first byte. + // + pucData[ulIdx++] = (unsigned char)ulValue; + + // + // Only read the second byte if needed. + // + if(ulIdx < ulSize) + { + pucData[ulIdx++] = (unsigned char)(ulValue >> 8); + } + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller after reset. +//! +//! \param ulBase is the base address of the CAN controller. +//! +//! After reset, the CAN controller is left in the disabled state. However, +//! the memory used for message objects contains undefined values and must be +//! cleared prior to enabling the CAN controller the first time. This prevents +//! unwanted transmission or reception of data before the message objects are +//! configured. This function must be called before enabling the controller +//! the first time. +//! +//! \return None. +// +//***************************************************************************** +void +CANInit(unsigned long ulBase) +{ + unsigned long ulMsg; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + CANRegWrite(ulBase + CAN_O_CTL, CAN_CTL_INIT); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB | + CAN_IF1CMSK_CONTROL); + CANRegWrite(ulBase + CAN_O_IF1ARB2, 0); + CANRegWrite(ulBase + CAN_O_IF1MCTL, 0); + + // + // Loop through to program all 32 message objects + // + for(ulMsg = 1; ulMsg <= 32; ulMsg++) + { + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Initiate programming the message object + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg); + } + + // + // Make sure that the interrupt and new data flags are updated for the + // message objects. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_NEWDAT | + CAN_IF1CMSK_CLRINTPND); + + // + // Loop through to program all 32 message objects + // + for(ulMsg = 1; ulMsg <= 32; ulMsg++) + { + // + // Wait for busy bit to clear. + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Initiate programming the message object + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg); + } + + // + // Acknowledge any pending status interrupts. + // + CANRegRead(ulBase + CAN_O_STS); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller automatically transmits any pending frames, and processes any +//! received frames. The controller can be stopped by calling CANDisable(). +//! Prior to calling CANEnable(), CANInit() should have been called to +//! initialize the controller and the CAN bus clock should be configured by +//! calling CANBitTimingSet(). +//! +//! \return None. +// +//***************************************************************************** +void +CANEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Clear the init bit in the control register. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) & ~CAN_CTL_INIT); +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller no longer automatically processes data on the CAN bus. The +//! controller can be restarted by calling CANEnable(). The state of the CAN +//! controller and the message objects in the controller are left as they were +//! before this call was made. +//! +//! \return None. +// +//***************************************************************************** +void +CANDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Set the init bit in the control register. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) | CAN_CTL_INIT); +} + +//***************************************************************************** +// +//! Reads the current settings for the CAN controller bit timing. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pClkParms is a pointer to a structure to hold the timing parameters. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing and stores the resulting information in the structure +//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the +//! values that are returned in the structure pointed to by \e pClkParms. +//! +//! This function replaces the original CANGetBitTiming() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms) +{ + unsigned long ulBitReg; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT(pClkParms != 0); + + // + // Read out all the bit timing values from the CAN controller registers. + // + ulBitReg = CANRegRead(ulBase + CAN_O_BIT); + + // + // Set the phase 2 segment. + // + pClkParms->ulPhase2Seg = + ((ulBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1; + + // + // Set the phase 1 segment. + // + pClkParms->ulSyncPropPhase1Seg = + ((ulBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1; + + // + // Set the synchronous jump width. + // + pClkParms->ulSJW = ((ulBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1; + + // + // Set the pre-divider for the CAN bus bit clock. + // + pClkParms->ulQuantumPrescaler = + ((ulBitReg & CAN_BIT_BRP_M) | + ((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1; +} + +//***************************************************************************** +// +//! Sets the CAN bit timing values to a nominal setting based on a desired +//! bit rate. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulSourceClock is the system clock for the device in Hz. +//! \param ulBitRate is the desired bit rate. +//! +//! This function sets the CAN bit timing for the bit rate passed in the +//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Because the +//! CAN clock is based off of the system clock, the calling function should pass +//! in the source clock rate either by retrieving it from SysCtlClockGet() or +//! using a specific value in Hz. The CAN bit timing is calculated assuming a +//! minimal amount of propagation delay, which works for most cases where +//! the network length is short. If tighter timing requirements or longer +//! network lengths are needed, then the CANBitTimingSet() function is +//! available for full customization of all of the CAN bit timing values. +//! Because not all bit rates can be matched exactly, the bit rate is set to +//! the value closest to the desired bit rate without being higher than the +//! \e ulBitRate value. +//! +//! \note On some devices the source clock is fixed at 8MHz so the +//! \e ulSourceClock should be set to 8000000. +//! +//! \return This function returns the bit rate that the CAN controller was +//! configured to use or it returns 0 to indicate that the bit rate was not +//! changed because the requested bit rate was not valid. +//! +//***************************************************************************** +unsigned long +CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock, + unsigned long ulBitRate) +{ + unsigned long ulDesiredRatio; + unsigned long ulCANBits; + unsigned long ulPreDivide; + unsigned long ulRegValue; + unsigned short usCANCTL; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT(ulSourceClock != 0); + ASSERT(ulBitRate != 0); + + // + // Calculate the desired clock rate. + // + ulDesiredRatio = ulSourceClock / ulBitRate; + + // + // Make sure that the ratio of CAN bit rate to processor clock is not too + // small or too large. + // + ASSERT(ulDesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)); + ASSERT(ulDesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)); + + // + // Make sure that the Desired Ratio is not too large. This enforces the + // requirement that the bit rate is larger than requested. + // + if((ulSourceClock / ulDesiredRatio) > ulBitRate) + { + ulDesiredRatio += 1; + } + + // + // Check all possible values to find a matching value. + // + while(ulDesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)) + { + // + // Loop through all possible CAN bit divisors. + // + for(ulCANBits = CAN_MAX_BIT_DIVISOR; ulCANBits >= CAN_MIN_BIT_DIVISOR; + ulCANBits--) + { + // + // For a given CAN bit divisor save the pre divisor. + // + ulPreDivide = ulDesiredRatio / ulCANBits; + + // + // If the calculated divisors match the desired clock ratio then + // return these bit rate and set the CAN bit timing. + // + if((ulPreDivide * ulCANBits) == ulDesiredRatio) + { + // + // Start building the bit timing value by adding the bit timing + // in time quanta. + // + ulRegValue = g_usCANBitValues[ulCANBits - CAN_MIN_BIT_DIVISOR]; + + // + // To set the bit timing register, the controller must be placed + // in init mode (if not already), and also configuration change + // bit enabled. The state of the register should be saved + // so it can be restored. + // + usCANCTL = CANRegRead(ulBase + CAN_O_CTL); + CANRegWrite(ulBase + CAN_O_CTL, + usCANCTL | CAN_CTL_INIT | CAN_CTL_CCE); + + // + // Now add in the pre-scalar on the bit rate. + // + ulRegValue |= ((ulPreDivide - 1) & CAN_BIT_BRP_M); + + // + // Set the clock bits in the and the lower bits of the + // pre-scalar. + // + CANRegWrite(ulBase + CAN_O_BIT, ulRegValue); + + // + // Set the divider upper bits in the extension register. + // + CANRegWrite(ulBase + CAN_O_BRPE, + ((ulPreDivide - 1) >> 6) & CAN_BRPE_BRPE_M); + + // + // Restore the saved CAN Control register. + // + CANRegWrite(ulBase + CAN_O_CTL, usCANCTL); + + // + // Return the computed bit rate. + // + return(ulSourceClock / ( ulPreDivide * ulCANBits)); + } + } + + // + // Move the divisor up one and look again. Only in rare cases are + // more than 2 loops required to find the value. + // + ulDesiredRatio++; + } + + // + // A valid combination could not be found, so return 0 to indicate that the + // bit rate was not changed. + // + return(0); +} + +//***************************************************************************** +// +//! Configures the CAN controller bit timing. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pClkParms points to the structure with the clock parameters. +//! +//! Configures the various timing parameters for the CAN bus bit timing: +//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and +//! the Synchronization Jump Width. The values for Propagation and Phase +//! Buffer 1 segments are derived from the combination +//! \e pClkParms->ulSyncPropPhase1Seg parameter. Phase Buffer 2 is determined +//! from the \e pClkParms->ulPhase2Seg parameter. These two parameters, along +//! with \e pClkParms->ulSJW are based in units of bit time quanta. The actual +//! quantum time is determined by the \e pClkParms->ulQuantumPrescaler value, +//! which specifies the divisor for the CAN module clock. +//! +//! The total bit time, in quanta, is the sum of the two Seg parameters, +//! as follows: +//! +//! bit_time_q = ulSyncPropPhase1Seg + ulPhase2Seg + 1 +//! +//! Note that the Sync_Seg is always one quantum in duration, and is added +//! to derive the correct duration of Prop_Seg and Phase1_Seg. +//! +//! The equation to determine the actual bit rate is as follows: +//! +//! CAN Clock / +//! ((\e ulSyncPropPhase1Seg + \e ulPhase2Seg + 1) * (\e ulQuantumPrescaler)) +//! +//! Thus with \e ulSyncPropPhase1Seg = 4, \e ulPhase2Seg = 1, +//! \e ulQuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is +//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. +//! +//! This function replaces the original CANSetBitTiming() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms) +{ + unsigned long ulBitReg, ulSavedInit; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT(pClkParms != 0); + + // + // The phase 1 segment must be in the range from 2 to 16. + // + ASSERT((pClkParms->ulSyncPropPhase1Seg >= 2) && + (pClkParms->ulSyncPropPhase1Seg <= 16)); + + // + // The phase 2 segment must be in the range from 1 to 8. + // + ASSERT((pClkParms->ulPhase2Seg >= 1) && (pClkParms->ulPhase2Seg <= 8)); + + // + // The synchronous jump windows must be in the range from 1 to 4. + // + ASSERT((pClkParms->ulSJW >= 1) && (pClkParms->ulSJW <= 4)); + + // + // The CAN clock pre-divider must be in the range from 1 to 1024. + // + ASSERT((pClkParms->ulQuantumPrescaler <= 1024) && + (pClkParms->ulQuantumPrescaler >= 1)); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. State + // of the init bit should be saved so it can be restored at the end. + // + ulSavedInit = CANRegRead(ulBase + CAN_O_CTL); + CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit | CAN_CTL_INIT | CAN_CTL_CCE); + + // + // Set the bit fields of the bit timing register according to the parms. + // + ulBitReg = (((pClkParms->ulPhase2Seg - 1) << CAN_BIT_TSEG2_S) & + CAN_BIT_TSEG2_M); + ulBitReg |= (((pClkParms->ulSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) & + CAN_BIT_TSEG1_M); + ulBitReg |= ((pClkParms->ulSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M; + ulBitReg |= (pClkParms->ulQuantumPrescaler - 1) & CAN_BIT_BRP_M; + CANRegWrite(ulBase + CAN_O_BIT, ulBitReg); + + // + // Set the divider upper bits in the extension register. + // + CANRegWrite(ulBase + CAN_O_BRPE, + ((pClkParms->ulQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M); + + // + // Clear the config change bit, and restore the init bit. + // + ulSavedInit &= ~CAN_CTL_CCE; + + // + // If Init was not set before, then clear it. + // + if(ulSavedInit & CAN_CTL_INIT) + { + ulSavedInit &= ~CAN_CTL_INIT; + } + CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled CAN interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables CAN interrupts on the interrupt controller; specific CAN +//! interrupt sources must be enabled using CANIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! CANIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable CAN interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulIntNumber; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Get the actual interrupt number for this CAN controller. + // + ulIntNumber = CANIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntRegister(ulIntNumber, pfnHandler); + + // + // Enable the Ethernet interrupt. + // + IntEnable(ulIntNumber); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the CAN controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntUnregister(unsigned long ulBase) +{ + unsigned long ulIntNumber; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Get the actual interrupt number for this CAN controller. + // + ulIntNumber = CANIntNumberGet(ulBase); + + // + // Disable the CAN interrupt. + // + IntDisable(ulIntNumber); + + // + // Register the interrupt handler. + // + IntUnregister(ulIntNumber); +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables specific interrupt sources of the CAN controller. +//! Only enabled sources cause a processor interrupt. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts +//! +//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled. +//! Further, for any particular transaction from a message object to generate +//! an interrupt, that message object must have interrupts enabled (see +//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the +//! controller enters the ``bus off'' condition, or if the error counters reach +//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few +//! status conditions and may provide more interrupts than the application +//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine +//! the cause. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + + // + // Enable the specified interrupts. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) | ulIntFlags); +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e ulIntFlags parameter has the same definition as in the +//! CANIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + + // + // Disable the specified interrupts. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) & ~(ulIntFlags)); +} + +//***************************************************************************** +// +//! Returns the current CAN controller interrupt status. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param eIntStsReg indicates which interrupt status register to read +//! +//! This function returns the value of one of two interrupt status registers. +//! The interrupt status register read is determined by the \e eIntStsReg +//! parameter, which can have one of the following values: +//! +//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt +//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message +//! objects +//! +//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register +//! and indicates the cause of the interrupt. The value returned is +//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, +//! the status register should be read with the CANStatusGet() function. +//! Calling this function to read the status also clears the status +//! interrupt. If the value of the interrupt register is in the range 1-32, +//! then this indicates the number of the highest priority message object that +//! has an interrupt pending. The message object interrupt can be cleared by +//! using the CANIntClear() function, or by reading the message using +//! CANMessageGet() in the case of a received message. The interrupt handler +//! can read the interrupt status again to make sure all pending interrupts are +//! cleared before returning from the interrupt. +//! +//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects +//! have pending interrupts. This value can be used to discover all of the +//! pending interrupts at once, as opposed to repeatedly reading the interrupt +//! register by using \b CAN_INT_STS_CAUSE. +//! +//! \return Returns the value of one of the interrupt status registers. +// +//***************************************************************************** +unsigned long +CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // See which status the caller is looking for. + // + switch(eIntStsReg) + { + // + // The caller wants the global interrupt status for the CAN controller + // specified by ulBase. + // + case CAN_INT_STS_CAUSE: + { + ulStatus = CANRegRead(ulBase + CAN_O_INT); + break; + } + + // + // The caller wants the current message status interrupt for all + // messages. + // + case CAN_INT_STS_OBJECT: + { + // + // Read and combine both 16 bit values into one 32bit status. + // + ulStatus = (CANRegRead(ulBase + CAN_O_MSG1INT) & + CAN_MSG1INT_INTPND_M); + ulStatus |= (CANRegRead(ulBase + CAN_O_MSG2INT) << 16); + break; + } + + // + // Request was for unknown status so just return 0. + // + default: + { + ulStatus = 0; + break; + } + } + + // + // Return the interrupt status value + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulIntClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e ulIntClr parameter should be one of the following values: +//! +//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt. +//! - 1-32 - Clears the specified message object interrupt +//! +//! It is not necessary to use this function to clear an interrupt. This +//! function should only be used if the application wants to clear an interrupt +//! source without taking the normal interrupt action. +//! +//! Normally, the status interrupt is cleared by reading the controller status +//! using CANStatusGet(). A specific message object interrupt is normally +//! cleared by reading the message object using CANMessageGet(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +CANIntClear(unsigned long ulBase, unsigned long ulIntClr) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulIntClr == CAN_INT_INTID_STATUS) || + ((ulIntClr>=1) && (ulIntClr <=32))); + + if(ulIntClr == CAN_INT_INTID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + CANRegRead(ulBase + CAN_O_STS); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMSK_CLRINTPND bit. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_CLRINTPND); + + // + // Send the clear pending interrupt command to the CAN controller. + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IF1CRQ_MNUM_M); + + // + // Wait to be sure that this interface is not busy. + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + } +} + +//***************************************************************************** +// +//! Sets the CAN controller automatic retransmission behavior. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param bAutoRetry enables automatic retransmission. +//! +//! This function enables or disables automatic retransmission of messages with +//! detected errors. If \e bAutoRetry is \b true, then automatic +//! retransmission is enabled, otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry) +{ + unsigned long ulCtlReg; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + ulCtlReg = CANRegRead(ulBase + CAN_O_CTL); + + // + // Conditionally set the DAR bit to enable/disable auto-retry. + // + if(bAutoRetry) + { + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + ulCtlReg &= ~CAN_CTL_DAR; + } + else + { + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + ulCtlReg |= CAN_CTL_DAR; + } + + CANRegWrite(ulBase + CAN_O_CTL, ulCtlReg); +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param ulBase is the base address of the CAN controller. +//! +//! This function reads the current setting for automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +tBoolean +CANRetryGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + if(CANRegRead(ulBase + CAN_O_CTL) & CAN_CTL_DAR) + { + // + // Automatic data retransmission is not enabled. + // + return(false); + } + + // + // Automatic data retransmission is enabled. + // + return(true); +} + +//***************************************************************************** +// +//! Reads one of the controller status registers. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param eStatusReg is the status register to read. +//! +//! This function reads a status register of the CAN controller and returns it +//! to the caller. +//! The different status registers are: +//! +//! - \b CAN_STS_CONTROL - the main controller status +//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission +//! - \b CAN_STS_NEWDAT - bit mask of objects with new data +//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration +//! +//! When reading the main controller status register, a pending status +//! interrupt is cleared. This parameter should be used in the interrupt +//! handler for the CAN controller if the cause is a status interrupt. The +//! controller status register fields are as follows: +//! +//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition +//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 +//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state +//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of +//! any message filtering). +//! - \b CAN_STATUS_TXOK - a message was successfully transmitted +//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits) +//! - \b CAN_STATUS_LEC_NONE - no error +//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected +//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part +//! of a message +//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged +//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in +//! recessive mode +//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in +//! dominant mode +//! - \b CAN_STATUS_LEC_CRC - CRC error in received message +//! +//! The remaining status registers consist of 32-bit-wide bit maps to the +//! message objects. They can be used to quickly obtain information about the +//! status of all the message objects without needing to query each one. They +//! contain the following information: +//! +//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a +//! transmission is pending on that object. The application can use this +//! information to determine which objects are still waiting to send a +//! message. +//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new +//! message has been received in that object, and has not yet been picked up +//! by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object +//! has a valid configuration programmed. The host application can use this +//! information to determine which message objects are empty/unused. +//! +//! \return Returns the value of the status register. +// +//***************************************************************************** +unsigned long +CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + switch(eStatusReg) + { + // + // Just return the global CAN status register since that is what was + // requested. + // + case CAN_STS_CONTROL: + { + ulStatus = CANRegRead(ulBase + CAN_O_STS); + CANRegWrite(ulBase + CAN_O_STS, + ~(CAN_STS_RXOK | CAN_STS_TXOK | CAN_STS_LEC_M)); + break; + } + + // + // Combine the Transmit status bits into one 32bit value. + // + case CAN_STS_TXREQUEST: + { + ulStatus = CANRegRead(ulBase + CAN_O_TXRQ1); + ulStatus |= CANRegRead(ulBase + CAN_O_TXRQ2) << 16; + break; + } + + // + // Combine the New Data status bits into one 32bit value. + // + case CAN_STS_NEWDAT: + { + ulStatus = CANRegRead(ulBase + CAN_O_NWDA1); + ulStatus |= CANRegRead(ulBase + CAN_O_NWDA2) << 16; + break; + } + + // + // Combine the Message valid status bits into one 32bit value. + // + case CAN_STS_MSGVAL: + { + ulStatus = CANRegRead(ulBase + CAN_O_MSG1VAL); + ulStatus |= CANRegRead(ulBase + CAN_O_MSG2VAL) << 16; + break; + } + + // + // Unknown CAN status requested so return 0. + // + default: + { + ulStatus = 0; + break; + } + } + return(ulStatus); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pulRxCount is a pointer to storage for the receive error counter. +//! \param pulTxCount is a pointer to storage for the transmit error counter. +//! +//! This function reads the error counter register and returns the transmit and +//! receive error counts to the caller along with a flag indicating if the +//! controller receive counter has reached the error passive limit. The values +//! of the receive and transmit error counters are returned through the +//! pointers provided as parameters. +//! +//! After this call, \e *pulRxCount holds the current receive error count +//! and \e *pulTxCount holds the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +tBoolean +CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, + unsigned long *pulTxCount) +{ + unsigned long ulCANError; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Read the current count of transmit/receive errors. + // + ulCANError = CANRegRead(ulBase + CAN_O_ERR); + + // + // Extract the error numbers from the register value. + // + *pulRxCount = (ulCANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S; + *pulTxCount = (ulCANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S; + + if(ulCANError & CAN_ERR_RP) + { + return(true); + } + return(false); +} + +//***************************************************************************** +// +//! Configures a message object in the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulObjID is the object number to configure (1-32). +//! \param pMsgObject is a pointer to a structure containing message object +//! settings. +//! \param eMsgType indicates the type of message for this object. +//! +//! This function is used to configure any one of the 32 message objects in the +//! CAN controller. A message object can be configured to be any type of CAN +//! message object as well as to use automatic transmission and reception. +//! This call also allows the message object to be configured to generate +//! interrupts on completion of message receipt or transmission. The +//! message object can also be configured with a filter/mask so that actions +//! are only taken when a message that meets certain parameters is seen on the +//! CAN bus. +//! +//! The \e eMsgType parameter must be one of the following values: +//! +//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object. +//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object. +//! - \b MSG_OBJ_TYPE_RX - CAN receive message object. +//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object. +//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then +//! transmit message object. +//! +//! The message object pointed to by \e pMsgObject must be populated by the +//! caller, as follows: +//! +//! - \e ulMsgID - contains the message ID, either 11 or 29 bits. +//! - \e ulMsgIDMask - mask of bits from \e ulMsgID that must match if +//! identifier filtering is enabled. +//! - \e ulFlags +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission. +//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the +//! identifier mask specified by \e ulMsgIDMask. +//! - \e ulMsgLen - the number of bytes in the message data. This parameter +//! should be non-zero even for a remote frame; it should match the expected +//! bytes of data in the responding data frame. +//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a +//! data frame. +//! +//! \b Example: To send a data frame or remote frame (in response to a remote +//! request), take the following steps: +//! +//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. +//! -# Set \e pMsgObject->ulMsgID to the message ID. +//! -# Set \e pMsgObject->ulFlags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to +//! allow an interrupt to be generated when the message is sent. +//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the data frame. +//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes +//! to send in the message. +//! -# Call this function with \e ulObjID set to one of the 32 object buffers. +//! +//! \b Example: To receive a specific data frame, take the following steps: +//! +//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX. +//! -# Set \e pMsgObject->ulMsgID to the full message ID, or a partial mask to +//! use partial ID matching. +//! -# Set \e pMsgObject->ulMsgIDMask bits that should be used for masking +//! during comparison. +//! -# Set \e pMsgObject->ulFlags as follows: +//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data frame +//! is received. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based filtering. +//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data +//! frame. +//! -# The buffer pointed to by \e pMsgObject->pucMsgData is not used by this +//! call as no data is present at the time of the call. +//! -# Call this function with \e ulObjID set to one of the 32 object buffers. +//! +//! If you specify a message object buffer that already contains a message +//! definition, it is overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageSet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType) +{ + unsigned short usCmdMaskReg; + unsigned short usMaskReg0, usMaskReg1; + unsigned short usArbReg0, usArbReg1; + unsigned short usMsgCtrl; + tBoolean bTransferData; + tBoolean bUseExtendedID; + + bTransferData = 0; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulObjID <= 32) && (ulObjID != 0)); + ASSERT((eMsgType == MSG_OBJ_TYPE_TX) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RX) || + (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE)); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // See if we need to use an extended identifier or not. + // + if((pMsgObject->ulMsgID > CAN_MAX_11BIT_MSG_ID) || + (pMsgObject->ulFlags & MSG_OBJ_EXTENDED_ID)) + { + bUseExtendedID = 1; + } + else + { + bUseExtendedID = 0; + } + + // + // This is always a write to the Message object as this call is setting a + // message object. This call will also always set all size bits so it sets + // both data bits. The call will use the CONTROL register to set control + // bits so this bit needs to be set as well. + // + usCmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | + CAN_IF1CMSK_CONTROL); + + // + // Initialize the values to a known state before filling them in based on + // the type of message object that is being configured. + // + usArbReg0 = 0; + usArbReg1 = 0; + usMsgCtrl = 0; + usMaskReg0 = 0; + usMaskReg1 = 0; + + switch(eMsgType) + { + // + // Transmit message object. + // + case MSG_OBJ_TYPE_TX: + { + // + // Set the TXRQST bit and the reset the rest of the register. + // + usMsgCtrl |= CAN_IF1MCTL_TXRQST; + usArbReg1 = CAN_IF1ARB2_DIR; + bTransferData = 1; + break; + } + + // + // Transmit remote request message object + // + case MSG_OBJ_TYPE_TX_REMOTE: + { + // + // Set the TXRQST bit and the reset the rest of the register. + // + usMsgCtrl |= CAN_IF1MCTL_TXRQST; + usArbReg1 = 0; + break; + } + + // + // Receive message object. + // + case MSG_OBJ_TYPE_RX: + { + // + // This clears the DIR bit along with everything else. The TXRQST + // bit was cleared by defaulting usMsgCtrl to 0. + // + usArbReg1 = 0; + break; + } + + // + // Receive remote request message object. + // + case MSG_OBJ_TYPE_RX_REMOTE: + { + // + // The DIR bit is set to one for remote receivers. The TXRQST bit + // was cleared by defaulting usMsgCtrl to 0. + // + usArbReg1 = CAN_IF1ARB2_DIR; + + // + // Set this object so that it only indicates that a remote frame + // was received and allow for software to handle it by sending back + // a data frame. + // + usMsgCtrl = CAN_IF1MCTL_UMASK; + + // + // Use the full Identifier by default. + // + usMaskReg0 = 0xffff; + usMaskReg1 = 0x1fff; + + // + // Make sure to send the mask to the message object. + // + usCmdMaskReg |= CAN_IF1CMSK_MASK; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Oddly the DIR bit is set to one for remote receivers. + // + usArbReg1 = CAN_IF1ARB2_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + usMsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; + + // + // The data to be returned needs to be filled in. + // + bTransferData = 1; + break; + } + + // + // This case should never happen due to the ASSERT statement at the + // beginning of this function. + // + default: + { + return; + } + } + + // + // Configure the Mask Registers. + // + if(pMsgObject->ulFlags & MSG_OBJ_USE_ID_FILTER) + { + if(bUseExtendedID) + { + // + // Set the 29 bits of Identifier mask that were requested. + // + usMaskReg0 = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M; + usMaskReg1 = ((pMsgObject->ulMsgIDMask >> 16) & + CAN_IF1MSK2_IDMSK_M); + } + else + { + // + // Lower 16 bit are unused so set them to zero. + // + usMaskReg0 = 0; + + // + // Put the 11 bit Mask Identifier into the upper bits of the field + // in the register. + // + usMaskReg1 = ((pMsgObject->ulMsgIDMask << 2) & + CAN_IF1MSK2_IDMSK_M); + } + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + if((pMsgObject->ulFlags & MSG_OBJ_USE_EXT_FILTER) == + MSG_OBJ_USE_EXT_FILTER) + { + usMaskReg1 |= CAN_IF1MSK2_MXTD; + } + + // + // The caller wants to filter on the message direction field. + // + if((pMsgObject->ulFlags & MSG_OBJ_USE_DIR_FILTER) == + MSG_OBJ_USE_DIR_FILTER) + { + usMaskReg1 |= CAN_IF1MSK2_MDIR; + } + + if(pMsgObject->ulFlags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | + MSG_OBJ_USE_EXT_FILTER)) + { + // + // Set the UMASK bit to enable using the mask register. + // + usMsgCtrl |= CAN_IF1MCTL_UMASK; + + // + // Set the MASK bit so that this gets transferred to the Message Object. + // + usCmdMaskReg |= CAN_IF1CMSK_MASK; + } + + // + // Set the Arb bit so that this gets transferred to the Message object. + // + usCmdMaskReg |= CAN_IF1CMSK_ARB; + + // + // Configure the Arbitration registers. + // + if(bUseExtendedID) + { + // + // Set the 29 bit version of the Identifier for this message object. + // + usArbReg0 |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M; + usArbReg1 |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M; + + // + // Mark the message as valid and set the extended ID bit. + // + usArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD; + } + else + { + // + // Set the 11 bit version of the Identifier for this message object. + // The lower 18 bits are set to zero. + // + usArbReg1 |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M; + + // + // Mark the message as valid. + // + usArbReg1 |= CAN_IF1ARB2_MSGVAL; + } + + // + // Set the data length since this is set for all transfers. This is also a + // single transfer and not a FIFO transfer so set EOB bit. + // + usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M); + + // + // Mark this as the last entry if this is not the last entry in a FIFO. + // + if((pMsgObject->ulFlags & MSG_OBJ_FIFO) == 0) + { + usMsgCtrl |= CAN_IF1MCTL_EOB; + } + + // + // Enable transmit interrupts if they should be enabled. + // + if(pMsgObject->ulFlags & MSG_OBJ_TX_INT_ENABLE) + { + usMsgCtrl |= CAN_IF1MCTL_TXIE; + } + + // + // Enable receive interrupts if they should be enabled. + // + if(pMsgObject->ulFlags & MSG_OBJ_RX_INT_ENABLE) + { + usMsgCtrl |= CAN_IF1MCTL_RXIE; + } + + // + // Write the data out to the CAN Data registers if needed. + // + if(bTransferData) + { + CANDataRegWrite(pMsgObject->pucMsgData, + (unsigned long *)(ulBase + CAN_O_IF1DA1), + pMsgObject->ulMsgLen); + } + + // + // Write out the registers to program the message object. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, usCmdMaskReg); + CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg0); + CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg1); + CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg0); + CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg1); + CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl); + + // + // Transfer the message object to the message object specified by ulObjID. + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); +} + +//***************************************************************************** +// +//! Reads a CAN message from one of the message object buffers. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulObjID is the object number to read (1-32). +//! \param pMsgObject points to a structure containing message object fields. +//! \param bClrPendingInt indicates whether an associated interrupt should be +//! cleared. +//! +//! This function is used to read the contents of one of the 32 message objects +//! in the CAN controller and return it to the caller. The data returned is +//! stored in the fields of the caller-supplied structure pointed to by +//! \e pMsgObject. The data consists of all of the parts of a CAN message, +//! plus some control and status information. +//! +//! Normally, this function is used to read a message object that has received +//! and stored a CAN message with a certain identifier. However, this function +//! could also be used to read the contents of a message object in order to +//! load the fields of the structure in case only part of the structure must +//! be changed from a previous setting. +//! +//! When using CANMessageGet(), all of the same fields of the structure are +//! populated in the same way as when the CANMessageSet() function is used, +//! with the following exceptions: +//! +//! \e pMsgObject->ulFlags: +//! +//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it +//! was read +//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on +//! this message object and not read by the host before being overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageGet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tBoolean bClrPendingInt) +{ + unsigned short usCmdMaskReg; + unsigned short usMaskReg0, usMaskReg1; + unsigned short usArbReg0, usArbReg1; + unsigned short usMsgCtrl; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulObjID <= 32) && (ulObjID != 0)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + usCmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | + CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | CAN_IF1CMSK_ARB); + + // + // Clear a pending interrupt and new data in a message object. + // + if(bClrPendingInt) + { + usCmdMaskReg |= CAN_IF1CMSK_CLRINTPND; + } + + // + // Set up the request for data from the message object. + // + CANRegWrite(ulBase + CAN_O_IF2CMSK, usCmdMaskReg); + + // + // Transfer the message object to the message object specified by ulObjID. + // + CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Read out the IF Registers. + // + usMaskReg0 = CANRegRead(ulBase + CAN_O_IF2MSK1); + usMaskReg1 = CANRegRead(ulBase + CAN_O_IF2MSK2); + usArbReg0 = CANRegRead(ulBase + CAN_O_IF2ARB1); + usArbReg1 = CANRegRead(ulBase + CAN_O_IF2ARB2); + usMsgCtrl = CANRegRead(ulBase + CAN_O_IF2MCTL); + + pMsgObject->ulFlags = MSG_OBJ_NO_FLAGS; + + // + // Determine if this is a remote frame by checking the TXRQST and DIR bits. + // + if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) && (usArbReg1 & CAN_IF1ARB2_DIR)) || + ((usMsgCtrl & CAN_IF1MCTL_TXRQST) && (!(usArbReg1 & CAN_IF1ARB2_DIR)))) + { + pMsgObject->ulFlags |= MSG_OBJ_REMOTE_FRAME; + } + + // + // Get the identifier out of the register, the format depends on size of + // the mask. + // + if(usArbReg1 & CAN_IF1ARB2_XTD) + { + // + // Set the 29 bit version of the Identifier for this message object. + // + pMsgObject->ulMsgID = ((usArbReg1 & CAN_IF1ARB2_ID_M) << 16) | + usArbReg0; + + pMsgObject->ulFlags |= MSG_OBJ_EXTENDED_ID; + } + else + { + // + // The Identifier is an 11 bit value. + // + pMsgObject->ulMsgID = (usArbReg1 & CAN_IF1ARB2_ID_M) >> 2; + } + + // + // Indicate that we lost some data. + // + if(usMsgCtrl & CAN_IF1MCTL_MSGLST) + { + pMsgObject->ulFlags |= MSG_OBJ_DATA_LOST; + } + + // + // Set the flag to indicate if ID masking was used. + // + if(usMsgCtrl & CAN_IF1MCTL_UMASK) + { + if(usArbReg1 & CAN_IF1ARB2_XTD) + { + // + // The Identifier Mask is assumed to also be a 29 bit value. + // + pMsgObject->ulMsgIDMask = + ((usMaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg0; + + // + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + // + if((pMsgObject->ulMsgIDMask != 0x1fffffff) || + ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER; + } + } + else + { + // + // The Identifier Mask is assumed to also be an 11 bit value. + // + pMsgObject->ulMsgIDMask = ((usMaskReg1 & CAN_IF1MSK2_IDMSK_M) >> + 2); + + // + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + // + if((pMsgObject->ulMsgIDMask != 0x7ff) || + ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER; + } + } + + // + // Indicate if the extended bit was used in filtering. + // + if(usMaskReg1 & CAN_IF1MSK2_MXTD) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_EXT_FILTER; + } + + // + // Indicate if direction filtering was enabled. + // + if(usMaskReg1 & CAN_IF1MSK2_MDIR) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_DIR_FILTER; + } + } + + // + // Set the interrupt flags. + // + if(usMsgCtrl & CAN_IF1MCTL_TXIE) + { + pMsgObject->ulFlags |= MSG_OBJ_TX_INT_ENABLE; + } + if(usMsgCtrl & CAN_IF1MCTL_RXIE) + { + pMsgObject->ulFlags |= MSG_OBJ_RX_INT_ENABLE; + } + + // + // See if there is new data available. + // + if(usMsgCtrl & CAN_IF1MCTL_NEWDAT) + { + // + // Get the amount of data needed to be read. + // + pMsgObject->ulMsgLen = (usMsgCtrl & CAN_IF1MCTL_DLC_M); + + // + // Don't read any data for a remote frame, there is nothing valid in + // that buffer anyway. + // + if((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0) + { + // + // Read out the data from the CAN registers. + // + CANDataRegRead(pMsgObject->pucMsgData, + (unsigned long *)(ulBase + CAN_O_IF2DA1), + pMsgObject->ulMsgLen); + } + + // + // Now clear out the new data flag. + // + CANRegWrite(ulBase + CAN_O_IF2CMSK, CAN_IF1CMSK_NEWDAT); + + // + // Transfer the message object to the message object specified by + // ulObjID. + // + CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Indicate that there is new data in this message. + // + pMsgObject->ulFlags |= MSG_OBJ_NEW_DATA; + } + else + { + // + // Along with the MSG_OBJ_NEW_DATA not being set the amount of data + // needs to be set to zero if none was available. + // + pMsgObject->ulMsgLen = 0; + } +} + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulObjID is the message object number to disable (1-32). +//! +//! This function frees the specified message object from use. Once a message +//! object has been ``cleared,'' it no longer automatically sends or +//! receives messages, nor does it generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageClear(unsigned long ulBase, unsigned long ulObjID) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulObjID >= 1) && (ulObjID <= 32)); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB); + CANRegWrite(ulBase + CAN_O_IF1ARB1, 0); + CANRegWrite(ulBase + CAN_O_IF1ARB2, 0); + + // + // Initiate programming the message object + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/can.h b/driverlib/can.h new file mode 100644 index 0000000..f2c032a --- /dev/null +++ b/driverlib/can.h @@ -0,0 +1,465 @@ +//***************************************************************************** +// +// can.h - Defines and Macros for the CAN controller. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CAN_H__ +#define __CAN_H__ + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** + +//***************************************************************************** +// +// These are the flags used by the tCANMsgObject.ulFlags value when calling the +// CANMessageSet() and CANMessageGet() functions. +// +//***************************************************************************** + +// +//! This definition is used with the tCANMsgObject ulFlags value and indicates +//! that transmit interrupts should be enabled, or are enabled. +// +#define MSG_OBJ_TX_INT_ENABLE 0x00000001 + +// +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +// +#define MSG_OBJ_RX_INT_ENABLE 0x00000002 + +// +//! This indicates that a message object will use or is using an extended +//! identifier. +// +#define MSG_OBJ_EXTENDED_ID 0x00000004 + +// +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +// +#define MSG_OBJ_USE_ID_FILTER 0x00000008 + +// +//! This indicates that new data was available in the message object. +// +#define MSG_OBJ_NEW_DATA 0x00000080 + +// +//! This indicates that data was lost since this message object was last +//! read. +// +#define MSG_OBJ_DATA_LOST 0x00000100 + +// +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. If the direction filtering is +//! used, then ID filtering must also be enabled. +// +#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER) + +// +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. If the extended +//! identifier filtering is used, then ID filtering must also be enabled. +// +#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER) + +// +//! This indicates that a message object is a remote frame. +// +#define MSG_OBJ_REMOTE_FRAME 0x00000040 + +// +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +// +#define MSG_OBJ_FIFO 0x00000200 + +// +//! This indicates that a message object has no flags set. +// +#define MSG_OBJ_NO_FLAGS 0x00000000 + +//***************************************************************************** +// +//! This define is used with the flag values to allow checking only status +//! flags and not configuration flags. +// +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +// +//! The structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +// +//***************************************************************************** +typedef struct +{ + // + //! The CAN message identifier used for 11 or 29 bit identifiers. + // + unsigned long ulMsgID; + + // + //! The message identifier mask used when identifier filtering is enabled. + // + unsigned long ulMsgIDMask; + + // + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + // + unsigned long ulFlags; + + // + //! This value is the number of bytes of data in the message object. + // + unsigned long ulMsgLen; + + // + //! This is a pointer to the message object's data. + // + unsigned char *pucMsgData; +} +tCANMsgObject; + +//***************************************************************************** +// +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +// +//***************************************************************************** +typedef struct +{ + // + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + // + unsigned long ulSyncPropPhase1Seg; + + // + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + // + unsigned long ulPhase2Seg; + + // + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + // + unsigned long ulSJW; + + // + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + // + unsigned long ulQuantumPrescaler; +} +tCANBitClkParms; + +//***************************************************************************** +// +//! This data type is used to identify the interrupt status register. This is +//! used when calling the CANIntStatus() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the CAN interrupt status information. + // + CAN_INT_STS_CAUSE, + + // + //! Read a message object's interrupt status. + // + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +// +//! This data type is used to identify which of several status registers to +//! read when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the full CAN controller status. + // + CAN_STS_CONTROL, + + // + //! Read the full 32-bit mask of message objects with a transmit request + //! set. + // + CAN_STS_TXREQUEST, + + // + //! Read the full 32-bit mask of message objects with new data available. + // + CAN_STS_NEWDAT, + + // + //! Read the full 32-bit mask of message objects that are enabled. + // + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to CANIntEnable() +// and CANIntDisable(). +// +//***************************************************************************** +// +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +// +#define CAN_INT_ERROR 0x00000008 + +// +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +// +#define CAN_INT_STATUS 0x00000004 + +// +//! This flag is used to allow a CAN controller to generate any CAN +//! interrupts. If this is not set, then no interrupts will be generated +//! by the CAN controller. +// +#define CAN_INT_MASTER 0x00000002 + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CANMessageSet() API. +// +//***************************************************************************** +typedef enum +{ + // + //! Transmit message object. + // + MSG_OBJ_TYPE_TX, + + // + //! Transmit remote request message object + // + MSG_OBJ_TYPE_TX_REMOTE, + + // + //! Receive message object. + // + MSG_OBJ_TYPE_RX, + + // + //! Receive remote request message object. + // + MSG_OBJ_TYPE_RX_REMOTE, + + // + //! Remote frame receive remote, with auto-transmit message object. + // + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// +// The following enumeration contains all error or status indicators that can +// be returned when calling the CANStatusGet() function. +// +//***************************************************************************** +// +//! CAN controller has entered a Bus Off state. +// +#define CAN_STATUS_BUS_OFF 0x00000080 + +// +//! CAN controller error level has reached warning level. +// +#define CAN_STATUS_EWARN 0x00000040 + +// +//! CAN controller error level has reached error passive level. +// +#define CAN_STATUS_EPASS 0x00000020 + +// +//! A message was received successfully since the last read of this status. +// +#define CAN_STATUS_RXOK 0x00000010 + +// +//! A message was transmitted successfully since the last read of this +//! status. +// +#define CAN_STATUS_TXOK 0x00000008 + +// +//! This is the mask for the last error code field. +// +#define CAN_STATUS_LEC_MSK 0x00000007 + +// +//! There was no error. +// +#define CAN_STATUS_LEC_NONE 0x00000000 + +// +//! A bit stuffing error has occurred. +// +#define CAN_STATUS_LEC_STUFF 0x00000001 + +// +//! A formatting error has occurred. +// +#define CAN_STATUS_LEC_FORM 0x00000002 + +// +//! An acknowledge error has occurred. +// +#define CAN_STATUS_LEC_ACK 0x00000003 + +// +//! The bus remained a bit level of 1 for longer than is allowed. +// +#define CAN_STATUS_LEC_BIT1 0x00000004 + +// +//! The bus remained a bit level of 0 for longer than is allowed. +// +#define CAN_STATUS_LEC_BIT0 0x00000005 + +// +//! A CRC error has occurred. +// +#define CAN_STATUS_LEC_CRC 0x00000006 + +// +//! This is the mask for the CAN Last Error Code (LEC). +// +#define CAN_STATUS_LEC_MASK 0x00000007 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern unsigned long CANBitRateSet(unsigned long ulBase, + unsigned long ulSourceClock, + unsigned long ulBitRate); +extern void CANDisable(unsigned long ulBase); +extern void CANEnable(unsigned long ulBase); +extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, + unsigned long *pulTxCount); +extern void CANInit(unsigned long ulBase); +extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); +extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern unsigned long CANIntStatus(unsigned long ulBase, + tCANIntStsReg eIntStsReg); +extern void CANIntUnregister(unsigned long ulBase); +extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); +extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); +extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType); +extern tBoolean CANRetryGet(unsigned long ulBase); +extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); +extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); + +//***************************************************************************** +// +// Several CAN APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#define CANSetBitTiming(a, b) CANBitTimingSet(a, b) +#define CANGetBitTiming(a, b) CANBitTimingGet(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // __CAN_H__ diff --git a/driverlib/ccs-cm3/.ccsproject b/driverlib/ccs-cm3/.ccsproject new file mode 100644 index 0000000..1273946 --- /dev/null +++ b/driverlib/ccs-cm3/.ccsproject @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/driverlib/ccs-cm3/.cproject b/driverlib/ccs-cm3/.cproject new file mode 100644 index 0000000..fb0654f --- /dev/null +++ b/driverlib/ccs-cm3/.cproject @@ -0,0 +1,159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/driverlib/ccs-cm3/.project b/driverlib/ccs-cm3/.project new file mode 100644 index 0000000..7ec9ab6 --- /dev/null +++ b/driverlib/ccs-cm3/.project @@ -0,0 +1,236 @@ + + + driverlib-cm3 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -k + + + org.eclipse.cdt.make.core.buildCommand + ${CCS_UTILS_DIR}/bin/gmake + + + org.eclipse.cdt.make.core.buildLocation + ${BuildDirectory} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + adc.c + 1 + SW_ROOT/driverlib/adc.c + + + can.c + 1 + SW_ROOT/driverlib/can.c + + + comp.c + 1 + SW_ROOT/driverlib/comp.c + + + cpu.c + 1 + SW_ROOT/driverlib/cpu.c + + + eeprom.c + 1 + SW_ROOT/driverlib/eeprom.c + + + epi.c + 1 + SW_ROOT/driverlib/epi.c + + + ethernet.c + 1 + SW_ROOT/driverlib/ethernet.c + + + fan.c + 1 + SW_ROOT/driverlib/fan.c + + + flash.c + 1 + SW_ROOT/driverlib/flash.c + + + fpu.c + 1 + SW_ROOT/driverlib/fpu.c + + + gpio.c + 1 + SW_ROOT/driverlib/gpio.c + + + hibernate.c + 1 + SW_ROOT/driverlib/hibernate.c + + + i2c.c + 1 + SW_ROOT/driverlib/i2c.c + + + i2s.c + 1 + SW_ROOT/driverlib/i2s.c + + + interrupt.c + 1 + SW_ROOT/driverlib/interrupt.c + + + lpc.c + 1 + SW_ROOT/driverlib/lpc.c + + + mpu.c + 1 + SW_ROOT/driverlib/mpu.c + + + peci.c + 1 + SW_ROOT/driverlib/peci.c + + + pwm.c + 1 + SW_ROOT/driverlib/pwm.c + + + qei.c + 1 + SW_ROOT/driverlib/qei.c + + + ssi.c + 1 + SW_ROOT/driverlib/ssi.c + + + sysctl.c + 1 + SW_ROOT/driverlib/sysctl.c + + + sysexc.c + 1 + SW_ROOT/driverlib/sysexc.c + + + systick.c + 1 + SW_ROOT/driverlib/systick.c + + + timer.c + 1 + SW_ROOT/driverlib/timer.c + + + uart.c + 1 + SW_ROOT/driverlib/uart.c + + + udma.c + 1 + SW_ROOT/driverlib/udma.c + + + usb.c + 1 + SW_ROOT/driverlib/usb.c + + + watchdog.c + 1 + SW_ROOT/driverlib/watchdog.c + + + + + SW_ROOT + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/driverlib/ccs-cm3/.settings/org.eclipse.cdt.codan.core.prefs b/driverlib/ccs-cm3/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/driverlib/ccs-cm3/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/driverlib/ccs-cm3/Debug/driverlib-cm3.lib b/driverlib/ccs-cm3/Debug/driverlib-cm3.lib new file mode 100644 index 0000000..ffa75ed Binary files /dev/null and b/driverlib/ccs-cm3/Debug/driverlib-cm3.lib differ diff --git a/driverlib/ccs-cm3/macros.ini_initial b/driverlib/ccs-cm3/macros.ini_initial new file mode 100644 index 0000000..08b716d --- /dev/null +++ b/driverlib/ccs-cm3/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../.. diff --git a/driverlib/ccs-cm4f/.ccsproject b/driverlib/ccs-cm4f/.ccsproject new file mode 100644 index 0000000..b16ea80 --- /dev/null +++ b/driverlib/ccs-cm4f/.ccsproject @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/driverlib/ccs-cm4f/.cproject b/driverlib/ccs-cm4f/.cproject new file mode 100644 index 0000000..184f49a --- /dev/null +++ b/driverlib/ccs-cm4f/.cproject @@ -0,0 +1,144 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/driverlib/ccs-cm4f/.project b/driverlib/ccs-cm4f/.project new file mode 100644 index 0000000..dde8b15 --- /dev/null +++ b/driverlib/ccs-cm4f/.project @@ -0,0 +1,236 @@ + + + driverlib-cm4f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -k + + + org.eclipse.cdt.make.core.buildCommand + ${CCS_UTILS_DIR}/bin/gmake + + + org.eclipse.cdt.make.core.buildLocation + ${BuildDirectory} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + adc.c + 1 + SW_ROOT/driverlib/adc.c + + + can.c + 1 + SW_ROOT/driverlib/can.c + + + comp.c + 1 + SW_ROOT/driverlib/comp.c + + + cpu.c + 1 + SW_ROOT/driverlib/cpu.c + + + eeprom.c + 1 + SW_ROOT/driverlib/eeprom.c + + + epi.c + 1 + SW_ROOT/driverlib/epi.c + + + ethernet.c + 1 + SW_ROOT/driverlib/ethernet.c + + + fan.c + 1 + SW_ROOT/driverlib/fan.c + + + flash.c + 1 + SW_ROOT/driverlib/flash.c + + + fpu.c + 1 + SW_ROOT/driverlib/fpu.c + + + gpio.c + 1 + SW_ROOT/driverlib/gpio.c + + + hibernate.c + 1 + SW_ROOT/driverlib/hibernate.c + + + i2c.c + 1 + SW_ROOT/driverlib/i2c.c + + + i2s.c + 1 + SW_ROOT/driverlib/i2s.c + + + interrupt.c + 1 + SW_ROOT/driverlib/interrupt.c + + + lpc.c + 1 + SW_ROOT/driverlib/lpc.c + + + mpu.c + 1 + SW_ROOT/driverlib/mpu.c + + + peci.c + 1 + SW_ROOT/driverlib/peci.c + + + pwm.c + 1 + SW_ROOT/driverlib/pwm.c + + + qei.c + 1 + SW_ROOT/driverlib/qei.c + + + ssi.c + 1 + SW_ROOT/driverlib/ssi.c + + + sysctl.c + 1 + SW_ROOT/driverlib/sysctl.c + + + sysexc.c + 1 + SW_ROOT/driverlib/sysexc.c + + + systick.c + 1 + SW_ROOT/driverlib/systick.c + + + timer.c + 1 + SW_ROOT/driverlib/timer.c + + + uart.c + 1 + SW_ROOT/driverlib/uart.c + + + udma.c + 1 + SW_ROOT/driverlib/udma.c + + + usb.c + 1 + SW_ROOT/driverlib/usb.c + + + watchdog.c + 1 + SW_ROOT/driverlib/watchdog.c + + + + + SW_ROOT + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/driverlib/ccs-cm4f/.settings/org.eclipse.cdt.codan.core.prefs b/driverlib/ccs-cm4f/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/driverlib/ccs-cm4f/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/driverlib/ccs-cm4f/Debug/driverlib-cm4f.lib b/driverlib/ccs-cm4f/Debug/driverlib-cm4f.lib new file mode 100644 index 0000000..160f2fa Binary files /dev/null and b/driverlib/ccs-cm4f/Debug/driverlib-cm4f.lib differ diff --git a/driverlib/ccs-cm4f/macros.ini_initial b/driverlib/ccs-cm4f/macros.ini_initial new file mode 100644 index 0000000..08b716d --- /dev/null +++ b/driverlib/ccs-cm4f/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../.. diff --git a/driverlib/comp.c b/driverlib/comp.c new file mode 100644 index 0000000..ca1e05a --- /dev/null +++ b/driverlib/comp.c @@ -0,0 +1,451 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_comp.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/comp.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function configures a comparator. The \e ulConfig parameter is the +//! result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! - \b COMP_OUTPUT_NONE is deprecated and behaves the same as +//! \b COMP_OUTPUT_NORMAL. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Configure this comparator. + // + HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulRef is the desired reference voltage. +//! +//! This function sets the internal reference voltage value. The voltage is +//! specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ulBase + COMP_O_ACREFCTL) = ulRef; +} + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +tBoolean +ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT0_OVAL) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This function sets the handler to be called when the comparator interrupt occurs +//! and enables the interrupt in the interrupt controller. It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0 + ulComp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0 + ulComp); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp; +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function clears the handler to be called when a comparator interrupt +//! occurs. This function also masks off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0 + ulComp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0 + ulComp); +} + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only enabled comparator interrupts can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp; +} + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only enabled comparator interrupts can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the comparator. Either the raw or +//! the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +tBoolean +ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ulBase + COMP_O_ACMIS) >> ulComp) & 1) ? true : false); + } + else + { + return(((HWREG(ulBase + COMP_O_ACRIS) >> ulComp) & 1) ? true : false); + } +} + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! fucntion must be called in the interrupt handler to keep the handler from +//! being called again immediately upon exit. Note that for a level-triggered +//! interrupt, the interrupt cannot be cleared until it stops asserting. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Clear the interrupt. + // + HWREG(ulBase + COMP_O_ACMIS) = 1 << ulComp; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/comp.h b/driverlib/comp.h new file mode 100644 index 0000000..1c976bf --- /dev/null +++ b/driverlib/comp.h @@ -0,0 +1,145 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and combined together with values from the other +// groups via a logical OR. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#ifndef DEPRECATED +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#endif +#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/driverlib/cpu.c b/driverlib/cpu.c new file mode 100644 index 0000000..f21b7a8 --- /dev/null +++ b/driverlib/cpu.c @@ -0,0 +1,457 @@ +//***************************************************************************** +// +// cpu.c - Instruction wrappers for special CPU instructions needed by the +// drivers. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "driverlib/cpu.h" + +//***************************************************************************** +// +// Wrapper function for the CPSID instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +unsigned long __attribute__((naked)) +CPUcpsid(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#endif +#if defined(ccs) +unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function returning the state of PRIMASK (indicating whether +// interrupts are enabled or disabled). +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +unsigned long __attribute__((naked)) +CPUprimask(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm unsigned long +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + bx lr +} +#endif +#if defined(ccs) +unsigned long +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +unsigned long __attribute__((naked)) +CPUcpsie(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#endif +#if defined(ccs) +unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the WFI instruction. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + wfi; + bx lr +} +#endif +#if defined(ccs) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n"); +} +#endif + +//***************************************************************************** +// +// Wrapper function for writing the BASEPRI register. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +CPUbasepriSet(unsigned long ulNewBasepri) +{ + + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + msr BASEPRI, r0; + bx lr +} +#endif +#if defined(ccs) +void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n"); +} +#endif + +//***************************************************************************** +// +// Wrapper function for reading the BASEPRI register. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +unsigned long __attribute__((naked)) +CPUbasepriGet(void) +{ + unsigned long ulRet; + + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + mrs r0, BASEPRI; + bx lr +} +#endif +#if defined(ccs) +unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif diff --git a/driverlib/cpu.h b/driverlib/cpu.h new file mode 100644 index 0000000..6b51910 --- /dev/null +++ b/driverlib/cpu.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern unsigned long CPUcpsid(void); +extern unsigned long CPUcpsie(void); +extern unsigned long CPUprimask(void); +extern void CPUwfi(void); +extern unsigned long CPUbasepriGet(void); +extern void CPUbasepriSet(unsigned long ulNewBasepri); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ diff --git a/driverlib/debug.h b/driverlib/debug.h new file mode 100644 index 0000000..58f94b0 --- /dev/null +++ b/driverlib/debug.h @@ -0,0 +1,68 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/driverlib/driverlib-cm3.ewp b/driverlib/driverlib-cm3.ewp new file mode 100644 index 0000000..863fa1f --- /dev/null +++ b/driverlib/driverlib-cm3.ewp @@ -0,0 +1,857 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Source + + $PROJ_DIR$\adc.c + + + $PROJ_DIR$\can.c + + + $PROJ_DIR$\comp.c + + + $PROJ_DIR$\cpu.c + + + $PROJ_DIR$\eeprom.c + + + $PROJ_DIR$\epi.c + + + $PROJ_DIR$\ethernet.c + + + $PROJ_DIR$\fan.c + + + $PROJ_DIR$\flash.c + + + $PROJ_DIR$\fpu.c + + + $PROJ_DIR$\gpio.c + + + $PROJ_DIR$\hibernate.c + + + $PROJ_DIR$\i2c.c + + + $PROJ_DIR$\i2s.c + + + $PROJ_DIR$\interrupt.c + + + $PROJ_DIR$\lpc.c + + + $PROJ_DIR$\mpu.c + + + $PROJ_DIR$\peci.c + + + $PROJ_DIR$\pwm.c + + + $PROJ_DIR$\qei.c + + + $PROJ_DIR$\ssi.c + + + $PROJ_DIR$\sysctl.c + + + $PROJ_DIR$\sysexc.c + + + $PROJ_DIR$\systick.c + + + $PROJ_DIR$\timer.c + + + $PROJ_DIR$\uart.c + + + $PROJ_DIR$\udma.c + + + $PROJ_DIR$\usb.c + + + $PROJ_DIR$\watchdog.c + + + diff --git a/driverlib/driverlib-cm3.sgxx b/driverlib/driverlib-cm3.sgxx new file mode 100644 index 0000000..f46498c Binary files /dev/null and b/driverlib/driverlib-cm3.sgxx differ diff --git a/driverlib/driverlib-cm3.uvopt b/driverlib/driverlib-cm3.uvopt new file mode 100644 index 0000000..38f910a --- /dev/null +++ b/driverlib/driverlib-cm3.uvopt @@ -0,0 +1,636 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + driverlib-cm3 + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk-cm3\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\LM3S101.PDF + + + + SARMCM3.DLL + + DLM.DLL + -pLM3S101 + SARMCM3.DLL + + TLM.DLL + -pLM3S101 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4622 -S3 -FO29 + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\adc.c + adc.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\can.c + can.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\comp.c + comp.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\cpu.c + cpu.c + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\eeprom.c + eeprom.c + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\epi.c + epi.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\ethernet.c + ethernet.c + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\fan.c + fan.c + + + 1 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\flash.c + flash.c + + + 1 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\fpu.c + fpu.c + + + 1 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\gpio.c + gpio.c + + + 1 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\hibernate.c + hibernate.c + + + 1 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\i2c.c + i2c.c + + + 1 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\i2s.c + i2s.c + + + 1 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\interrupt.c + interrupt.c + + + 1 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\lpc.c + lpc.c + + + 1 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\mpu.c + mpu.c + + + 1 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\peci.c + peci.c + + + 1 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\pwm.c + pwm.c + + + 1 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\qei.c + qei.c + + + 1 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\ssi.c + ssi.c + + + 1 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\sysctl.c + sysctl.c + + + 1 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\sysexc.c + sysexc.c + + + 1 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\systick.c + systick.c + + + 1 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\timer.c + timer.c + + + 1 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\uart.c + uart.c + + + 1 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\udma.c + udma.c + + + 1 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\usb.c + usb.c + + + 1 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\watchdog.c + watchdog.c + + + + + Documentation + 1 + 0 + 0 + + 2 + 30 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/driverlib/driverlib-cm3.uvproj b/driverlib/driverlib-cm3.uvproj new file mode 100644 index 0000000..216e103 --- /dev/null +++ b/driverlib/driverlib-cm3.uvproj @@ -0,0 +1,550 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + driverlib-cm3 + 0x4 + ARM-ADS + + + LM3S101 + Texas Instruments + IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000) + 4079 + LM3Sxxx.H + + + + + + + + + + SFD\Luminary\LM3S101.SFR + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk-cm3\ + driverlib-cm3 + 0 + 1 + 0 + 1 + 1 + .\rvmdk-cm3\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DLM.DLL + -pLM3S101 + SARMCM3.DLL + + TLM.DLL + -pLM3S101 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 3 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4097 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x800 + + + 1 + 0x0 + 0x2000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x2000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x800 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + rvmdk + + ..; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source + + + adc.c + 1 + .\adc.c + + + can.c + 1 + .\can.c + + + comp.c + 1 + .\comp.c + + + cpu.c + 1 + .\cpu.c + + + eeprom.c + 1 + .\eeprom.c + + + epi.c + 1 + .\epi.c + + + ethernet.c + 1 + .\ethernet.c + + + fan.c + 1 + .\fan.c + + + flash.c + 1 + .\flash.c + + + fpu.c + 1 + .\fpu.c + + + gpio.c + 1 + .\gpio.c + + + hibernate.c + 1 + .\hibernate.c + + + i2c.c + 1 + .\i2c.c + + + i2s.c + 1 + .\i2s.c + + + interrupt.c + 1 + .\interrupt.c + + + lpc.c + 1 + .\lpc.c + + + mpu.c + 1 + .\mpu.c + + + peci.c + 1 + .\peci.c + + + pwm.c + 1 + .\pwm.c + + + qei.c + 1 + .\qei.c + + + ssi.c + 1 + .\ssi.c + + + sysctl.c + 1 + .\sysctl.c + + + sysexc.c + 1 + .\sysexc.c + + + systick.c + 1 + .\systick.c + + + timer.c + 1 + .\timer.c + + + uart.c + 1 + .\uart.c + + + udma.c + 1 + .\udma.c + + + usb.c + 1 + .\usb.c + + + watchdog.c + 1 + .\watchdog.c + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/driverlib/driverlib-cm4f.ewp b/driverlib/driverlib-cm4f.ewp new file mode 100644 index 0000000..2e466a0 --- /dev/null +++ b/driverlib/driverlib-cm4f.ewp @@ -0,0 +1,857 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Source + + $PROJ_DIR$\adc.c + + + $PROJ_DIR$\can.c + + + $PROJ_DIR$\comp.c + + + $PROJ_DIR$\cpu.c + + + $PROJ_DIR$\eeprom.c + + + $PROJ_DIR$\epi.c + + + $PROJ_DIR$\ethernet.c + + + $PROJ_DIR$\fan.c + + + $PROJ_DIR$\flash.c + + + $PROJ_DIR$\fpu.c + + + $PROJ_DIR$\gpio.c + + + $PROJ_DIR$\hibernate.c + + + $PROJ_DIR$\i2c.c + + + $PROJ_DIR$\i2s.c + + + $PROJ_DIR$\interrupt.c + + + $PROJ_DIR$\lpc.c + + + $PROJ_DIR$\mpu.c + + + $PROJ_DIR$\peci.c + + + $PROJ_DIR$\pwm.c + + + $PROJ_DIR$\qei.c + + + $PROJ_DIR$\ssi.c + + + $PROJ_DIR$\sysctl.c + + + $PROJ_DIR$\sysexc.c + + + $PROJ_DIR$\systick.c + + + $PROJ_DIR$\timer.c + + + $PROJ_DIR$\uart.c + + + $PROJ_DIR$\udma.c + + + $PROJ_DIR$\usb.c + + + $PROJ_DIR$\watchdog.c + + + diff --git a/driverlib/driverlib-cm4f.sgxx b/driverlib/driverlib-cm4f.sgxx new file mode 100644 index 0000000..9a490af Binary files /dev/null and b/driverlib/driverlib-cm4f.sgxx differ diff --git a/driverlib/driverlib-cm4f.uvopt b/driverlib/driverlib-cm4f.uvopt new file mode 100644 index 0000000..9b33e69 --- /dev/null +++ b/driverlib/driverlib-cm4f.uvopt @@ -0,0 +1,636 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + driverlib-cm4f + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk-cm4f\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\LM4F110B2QR.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4622 -S3 -FO29 + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\adc.c + adc.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\can.c + can.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\comp.c + comp.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\cpu.c + cpu.c + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\eeprom.c + eeprom.c + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\epi.c + epi.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\ethernet.c + ethernet.c + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\fan.c + fan.c + + + 1 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\flash.c + flash.c + + + 1 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\fpu.c + fpu.c + + + 1 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\gpio.c + gpio.c + + + 1 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\hibernate.c + hibernate.c + + + 1 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\i2c.c + i2c.c + + + 1 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\i2s.c + i2s.c + + + 1 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\interrupt.c + interrupt.c + + + 1 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\lpc.c + lpc.c + + + 1 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\mpu.c + mpu.c + + + 1 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\peci.c + peci.c + + + 1 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\pwm.c + pwm.c + + + 1 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\qei.c + qei.c + + + 1 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\ssi.c + ssi.c + + + 1 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\sysctl.c + sysctl.c + + + 1 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\sysexc.c + sysexc.c + + + 1 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\systick.c + systick.c + + + 1 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\timer.c + timer.c + + + 1 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\uart.c + uart.c + + + 1 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\udma.c + udma.c + + + 1 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\usb.c + usb.c + + + 1 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\watchdog.c + watchdog.c + + + + + Documentation + 1 + 0 + 0 + + 2 + 30 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/driverlib/driverlib-cm4f.uvproj b/driverlib/driverlib-cm4f.uvproj new file mode 100644 index 0000000..0366e50 --- /dev/null +++ b/driverlib/driverlib-cm4f.uvproj @@ -0,0 +1,550 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + driverlib-cm4f + 0x4 + ARM-ADS + + + LM4F110B2QR + Texas Instruments + IRAM(0x20000000-0x20002FFF) IROM(0-0x7FFF) CLOCK(8000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_32 -FS00 -FL08000) + 5919 + LM4Fxxxx.H + + + + + + + + + + SFD\Luminary\LM4F110B2QR.SFR + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk-cm4f\ + driverlib-cm4f + 0 + 1 + 0 + 1 + 1 + .\rvmdk-cm4f\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 3 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4097 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + rvmdk + + ..; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source + + + adc.c + 1 + .\adc.c + + + can.c + 1 + .\can.c + + + comp.c + 1 + .\comp.c + + + cpu.c + 1 + .\cpu.c + + + eeprom.c + 1 + .\eeprom.c + + + epi.c + 1 + .\epi.c + + + ethernet.c + 1 + .\ethernet.c + + + fan.c + 1 + .\fan.c + + + flash.c + 1 + .\flash.c + + + fpu.c + 1 + .\fpu.c + + + gpio.c + 1 + .\gpio.c + + + hibernate.c + 1 + .\hibernate.c + + + i2c.c + 1 + .\i2c.c + + + i2s.c + 1 + .\i2s.c + + + interrupt.c + 1 + .\interrupt.c + + + lpc.c + 1 + .\lpc.c + + + mpu.c + 1 + .\mpu.c + + + peci.c + 1 + .\peci.c + + + pwm.c + 1 + .\pwm.c + + + qei.c + 1 + .\qei.c + + + ssi.c + 1 + .\ssi.c + + + sysctl.c + 1 + .\sysctl.c + + + sysexc.c + 1 + .\sysexc.c + + + systick.c + 1 + .\systick.c + + + timer.c + 1 + .\timer.c + + + uart.c + 1 + .\uart.c + + + udma.c + 1 + .\udma.c + + + usb.c + 1 + .\usb.c + + + watchdog.c + 1 + .\watchdog.c + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/driverlib/eeprom.c b/driverlib/eeprom.c new file mode 100644 index 0000000..0cc31fb --- /dev/null +++ b/driverlib/eeprom.c @@ -0,0 +1,1140 @@ +//***************************************************************************** +// +// eeprom.c - Driver for programming the on-chip EEPROM. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "inc/hw_eeprom.h" +#include "inc/hw_flash.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "driverlib/eeprom.h" + +//***************************************************************************** +// +//! \addtogroup eeprom_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Useful macros to extract the number of EEPROM blocks available on the target +// device and the total EEPROM storage in bytes from the EESIZE register. +// +//***************************************************************************** +#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >> \ + EEPROM_EESIZE_BLKCNT_S) +#define SIZE_FROM_EESIZE(x) ((((x) & EEPROM_EESIZE_WORDCNT_M) >> \ + EEPROM_EESIZE_WORDCNT_S) * 4) + +//***************************************************************************** +// +// Useful macro to extract the offset from a linear address. +// +//***************************************************************************** +#define OFFSET_FROM_ADDR(x) (((x) >> 2) & 0x0F) + +//***************************************************************************** +// +// The key value required to initiate a mass erase. +// +//***************************************************************************** +#define EEPROM_MASS_ERASE_KEY ((unsigned long)0xE37B << EEPROM_EEDBGME_KEY_S) + +//***************************************************************************** +// +// This function implements a workaround for a bug in Blizzard rev A silicon. +// It ensures that only the 1KB flash sector containing a given EEPROM address +// is erased if an erase/copy operation is required as a result of a following +// EEPROM write. +// +//***************************************************************************** +static void +EEPROMSetSectorMask(unsigned long ulAddress) +{ + unsigned long ulMask; + + // + // Determine which page contains the passed EEPROM address. The 2KB EEPROM + // is implemented in 16KB of flash with each 1KB sector of flash holding + // values for 32 consecutive EEPROM words (or 128 bytes). + // + ulMask = ~(1 << (ulAddress >> 7)); + + SysCtlDelay(10); + HWREG(0x400FD0FC) = 3; + SysCtlDelay(10); + HWREG(0x400AE2C0) = ulMask; + SysCtlDelay(10); + HWREG(0x400FD0FC) = 0; + SysCtlDelay(10); +} + +//***************************************************************************** +// +// Clear the FSM sector erase mask to ensure that any following main array +// flash erase operations operate as expected. +// +//***************************************************************************** +static void +EEPROMClearSectorMask(void) +{ + SysCtlDelay(10); + HWREG(0x400FD0FC) = 3; + SysCtlDelay(10); + HWREG(0x400AE2C0) = 0; + SysCtlDelay(10); + HWREG(0x400FD0FC) = 0; + SysCtlDelay(10); +} + +//***************************************************************************** +// +// Block until the EEPROM peripheral is not busy. +// +//***************************************************************************** +static void +EEPROMWaitForDone(void) +{ + // + // Is the EEPROM still busy? + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Spin while EEPROM is busy. + // + } +} + +//***************************************************************************** +// +//! Performs any necessary recovery in case of power failures during write. +//! +//! This function must be called after SysCtlPeripheralEnable() and before +//! the EEPROM is accessed to check for errors resulting from power failure +//! during a previous write operation. The function detects these errors +//! and performs as much recovery as possible before returning information to +//! the caller on whether or not a previous data write was lost and must +//! be retried. +//! +//! In cases where \b EEPROM_INIT_RETRY is returned, the application is +//! responsible for determining which data write may have been lost and +//! rewriting this data. If \b EEPROM_INIT_ERROR is returned, the EEPROM was +//! unable to recover its state. This condition may or may not be resolved on +//! future resets depending upon the cause of the fault. For example, if the +//! supply voltage is unstable, retrying the operation once the voltage is +//! stabilized may clear the error. +//! +//! Failure to call this function after a reset may lead to permanent data loss +//! if the EEPROM is later written! +//! +//! \return Returns \b EEPROM_INIT_OK if no errors were detected, +//! \b EEPROM_INIT_RETRY if a previous write operation may have been +//! interrupted by a power or reset event or \b EEPROM_INIT_ERROR if the EEPROM +//! peripheral cannot currently recover from an interrupted write or erase +//! operation. +// +//***************************************************************************** +unsigned long +EEPROMInit(void) +{ + unsigned long ulStatus; + + // + // Insert a small delay (6 cycles + call overhead) to guard against the + // possibility that this function is called immediately after the EEPROM + // peripheral is enabled. Without this delay, there is a slight chance + // that the first EEPROM register read will fault if you are using a + // compiler with a ridiculously good optimizer! + // + SysCtlDelay(2); + + // + // Make sure the EEPROM has finished its reset processing. + // + EEPROMWaitForDone(); + + // + // Read the EESUPP register to see if any errors have been reported. + // + ulStatus = HWREG(EEPROM_EESUPP); + + // + // Did an error of some sort occur during a previous attempt to write to + // the EEPROM? + // + if(ulStatus & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) + { + // + // Perform a second reset to allow the EEPROM a chance to correct + // the errors. + // + SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); + + // + // Wait for the EEPROM to complete it's reset processing once again. + // + SysCtlDelay(2); + EEPROMWaitForDone(); + + // + // Read EESUPP once again to determine if the error conditions are + // cleared. + // + ulStatus = HWREG(EEPROM_EESUPP); + if(ulStatus & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) + { + return(EEPROM_INIT_ERROR); + } + else + { + return(EEPROM_INIT_RETRY); + } + } + + // + // The EEPROM does not indicate that any error occurred. + // + return(EEPROM_INIT_OK); +} + +//***************************************************************************** +// +//! Determines the size of the EEPROM. +//! +//! This function returns the size of the EEPROM in bytes. +//! +//! \return Returns the total number of bytes in the EEPROM. +// +//***************************************************************************** +unsigned long +EEPROMSizeGet(void) +{ + // + // Return the size of the EEPROM in bytes. + // + return(SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); +} + +//***************************************************************************** +// +//! Determines the number of blocks in the EEPROM. +//! +//! This function may be called to determine the number of blocks in the +//! EEPROM. Each block is the same size and the number of bytes of storage +//! contained in a block may be determined by dividing the size of the device, +//! obtained via a call to the EEPROMSizeGet() function, by the number of +//! blocks returned by this function. +//! +//! \return Returns the total number of bytes in the device EEPROM. +// +//***************************************************************************** +unsigned long +EEPROMBlockCountGet(void) +{ + // + // Extract the number of blocks and return it to the caller. + // + return(BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); +} + +//***************************************************************************** +// +//! Reads data from the EEPROM. +//! +//! \param pulData is a pointer to storage for the data read from the EEPROM. +//! This pointer must point to at least \e ulCount bytes of available memory. +//! \param ulAddress is the byte address within the EEPROM from which data is +//! to be read. This value must be a multiple of 4. +//! \param ulCount is the number of bytes of data to read from the EEPROM. +//! This value must be a multiple of 4. +//! +//! This function may be called to read a number of words of data from a +//! word-aligned address within the EEPROM. Data read is copied into the +//! buffer pointed to by the \e pulData parameter. +//! +//! \return None. +// +//***************************************************************************** +void +EEPROMRead(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check parameters in a debug build. + // + ASSERT(pulData); + ASSERT(ulAddress < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress + ulCount) <= SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress & 3) == 0); + ASSERT((ulCount & 3) == 0); + + // + // Set the block and offset appropriately to read the first word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ulAddress); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ulAddress); + + // + // Convert the byte count to a word count. + // + ulCount /= 4; + + // + // Read each word in turn. + // + while(ulCount) + { + // + // Read the next word through the autoincrementing register. + // + *pulData = HWREG(EEPROM_EERDWRINC); + + // + // Move on to the next word. + // + pulData++; + ulCount--; + + // + // Do we need to move to the next block? This is the case if the + // offset register has just wrapped back to 0. + // + if(HWREG(EEPROM_EEOFFSET) == 0) + { + HWREG(EEPROM_EEBLOCK) += 1; + } + } +} + +//***************************************************************************** +// +//! Writes data to the EEPROM. +//! +//! \param pulData points to the first word of data to write to the EEPROM. +//! \param ulAddress defines the byte address within the EEPROM that the data +//! is to be written to. This value must be a multiple of 4. +//! \param ulCount defines the number of bytes of data that is to be written. +//! This value must be a multiple of 4. +//! +//! This function may be called to write data into the EEPROM at a given +//! word-aligned address. The call is synchronous and returns only after +//! all data has been written or an error occurs. +//! +//! \return Returns 0 on success or non-zero values on failure. Failure codes +//! are logical OR combinations of \b EEPROM_RC_INVPL, \b EEPROM_RC_WRBUSY, +//! \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and +//! \b EEPROM_RC_WORKING. +// +//***************************************************************************** +unsigned long +EEPROMProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + unsigned long ulStatus; + + // + // Check parameters in a debug build. + // + ASSERT(pulData); + ASSERT(ulAddress < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress + ulCount) <= SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress & 3) == 0); + ASSERT((ulCount & 3) == 0); + + // + // Make sure the EEPROM is idle before we start. + // + do + { + // + // Read the status. + // + ulStatus = HWREG(EEPROM_EEDONE); + } + while(ulStatus & EEPROM_EEDONE_WORKING); + + // + // Set the block and offset appropriately to program the first word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ulAddress); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ulAddress); + + // + // Convert the byte count to a word count. + // + ulCount /= 4; + + // + // Write each word in turn. + // + while(ulCount) + { + // + // This is a workaround for a silicon problem on Blizzard rev A. We + // need to do this before every word write to ensure that we don't + // have problems in multi-word writes that span multiple flash sectors. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMSetSectorMask(ulAddress); + ulAddress += 4; + } + + // + // Write the next word through the autoincrementing register. + // + HWREG(EEPROM_EERDWRINC) = *pulData; + + // + // Wait for the write to complete. + // + do + { + // + // Read the status. + // + ulStatus = HWREG(EEPROM_EEDONE); + } + while(ulStatus & EEPROM_EEDONE_WORKING); + + // + // Make sure we completed the write without errors. Note that we + // must check this per-word because write permission can be set per + // block resulting in only a section of the write not being performed. + // + if(ulStatus & (EEPROM_EEDONE_NOPERM | EEPROM_EEDONE_INVPL)) + { + // + // An error was reported that would prevent the values from + // being written correctly. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + return(ulStatus); + } + + // + // Move on to the next word. + // + pulData++; + ulCount--; + + // + // Do we need to move to the next block? This is the case if the + // offset register has just wrapped back to 0. + // + if(HWREG(EEPROM_EEOFFSET) == 0) + { + HWREG(EEPROM_EEBLOCK) += 1; + } + } + + // + // Clear the sector protection bits to prevent possible problems when + // programming the main flash array later. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + + // + // Return the current status to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Writes a word to the EEPROM. +//! +//! \param ulData is the word to write to the EEPROM. +//! \param ulAddress defines the byte address within the EEPROM to which the +//! data is to be written. This value must be a multiple of 4. +//! +//! This function is intended to allow EEPROM programming under interrupt +//! control. It may be called to start the process of writing a single word of +//! data into the EEPROM at a given word-aligned address. The call is +//! asynchronous and returna immediately without waiting for the write to +//! complete. Completion of the operation is signaled by means of an +//! interrupt from the EEPROM module. The EEPROM peripheral shares a single +//! interrupt vector with the flash memory subsystem, \e INT_FLASH. +//! +//! \return Returns status and error information in the form of a logical OR +//! combinations of \b EEPROM_RC_INVPL, \b EEPROM_RC_WRBUSY, +//! \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE and +//! \b EEPROM_RC_WORKING. Flags \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and +//! \b EEPROM_RC_WORKING are expected in normal operation and do not indicate +//! an error. +// +//***************************************************************************** +unsigned long +EEPROMProgramNonBlocking(unsigned long ulData, unsigned long ulAddress) +{ + // + // Check parameters in a debug build. + // + ASSERT(ulAddress < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress & 3) == 0); + + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMSetSectorMask(ulAddress); + } + + // + // Set the block and offset appropriately to program the desired word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ulAddress); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ulAddress); + + // + // Write the new word using the auto-incrementing register just in case + // the caller wants to write follow-on words using direct register access + // + HWREG(EEPROM_EERDWRINC) = ulData; + + // + // Return the current status to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Erases the EEPROM and returns it to the factory default condition. +//! +//! This function completely erases the EEPROM and removes any and +//! all access protection on its blocks, leaving the device in the factory +//! default condition. After this operation, all EEPROM words contain the +//! value 0xFFFFFFFF and all blocks are accessible for both read and write +//! operations in all CPU modes. No passwords are active. +//! +//! The function is synchronous and does not return until the erase operation +//! has completed. +//! +//! \return Returns 0 on success or non-zero values on failure. Failure codes +//! are logical OR combinations of \b EEPROM_RC_INVPL, \b EEPROM_RC_WRBUSY, +//! \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and +//! \b EEPROM_RC_WORKING. +// +//***************************************************************************** +unsigned long +EEPROMMassErase(void) +{ + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + + // + // Start the mass erase processing + // + HWREG(EEPROM_EEDBGME) = EEPROM_MASS_ERASE_KEY | EEPROM_EEDBGME_ME; + + // + // Wait for completion. + // + EEPROMWaitForDone(); + + // + // Reset the peripheral. This is required so that all protection + // mechanisms and passwords are reset now that the EEPROM data has been + // scrubbed. + // + SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); + + // + // Wait for completion again. + // + SysCtlDelay(2); + EEPROMWaitForDone(); + + // + // Pass any error codes back to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Returns the current protection level for an EEPROM block. +//! +//! \param ulBlock is the block number for which the protection level is to be +//! queried. +//! +//! This function returns the current protection settings for a given +//! EEPROM block. If block 0 is currently locked, it must be unlocked prior +//! to calling this function to query the protection setting for other blocks. +//! +//! \return Returns one of \b EEPROM_PROT_RW_LRO_URW, \b EEPROM_PROT_NA_LNA_URW +//! or \b EEPROM_PROT_RO_LNA_URO optionally OR-ed with +//! \b EEPROM_PROT_SUPERVISOR_ONLY. +// +//***************************************************************************** +unsigned long +EEPROMBlockProtectGet(unsigned long ulBlock) +{ + // + // Parameter validity check. + // + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Set the current block. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Return the protection flags for this block. + // + return(HWREG(EEPROM_EEPROT)); +} + +//***************************************************************************** +// +//! Set the current protection options for an EEPROM block. +//! +//! \param ulBlock is the block number for which the protection options are to +//! be set. +//! \param ulProtect consists of one of the values \b EEPROM_PROT_RW_LRO_URW, +//! \b EEPROM_PROT_NA_LNA_URW or \b EEPROM_PROT_RO_LNA_URO optionally ORed with +//! \b EEPROM_PROT_SUPERVISOR_ONLY. +//! +//! This function sets the protection settings for a given EEPROM block +//! assuming no protection settings have previously been written. Note that +//! protection settings applied to block 0 have special meaning and control +//! access to the EEPROM peripheral as a whole. Protection settings applied to +//! blocks numbered 1 and above are layered above any protection set on block 0 +//! such that the effective protection on each block is the logical OR of the +//! protection flags set for block 0 and for the target block. This protocol +//! allows global protection options to be set for the whole device via block +//! 0 and more restrictive protection settings to be set on a block-by-block +//! basis. +//! +//! The protection flags indicate access permissions as follow: +//! +//! \b EEPROM_PROT_SUPERVISOR_ONLY restricts access to the block to threads +//! running in supervisor mode. If clear, both user and supervisor threads +//! can access the block. +//! +//! \b EEPROM_PROT_RW_LRO_URW provides read/write access to the block if no +//! password is set or if a password is set and the block is unlocked. If the +//! block is locked, only read access is permitted. +//! +//! \b EEPROM_PROT_NA_LNA_URW provides neither read nor write access unless +//! a password is set and the block is unlocked. If the block is unlocked, +//! both read and write access are permitted. +//! +//! \b EEPROM_PROT_RO_LNA_URO provides read access to the block if no password +//! is set or if a password is set and the block is unlocked. If the block is +//! password protected and locked, neither read nor write access is permitted. +//! +//! \return Returns a logical OR combination of \b EEPROM_RC_INVPL, +//! \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, +//! \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING to indicate status and error +//! conditions. +// +//***************************************************************************** +unsigned long +EEPROMBlockProtectSet(unsigned long ulBlock, unsigned long ulProtect) +{ + // + // Parameter validity check. + // + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Set the current block. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Set the protection options for this block. + // + HWREG(EEPROM_EEPROT) = ulProtect; + + // + // Wait for the write to complete. + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Still working. + // + } + + // + // Pass any error codes back to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Sets the password used to protect an EEPROM block. +//! +//! \param ulBlock is the EEPROM block number for which the password is to be +//! set. +//! \param pulPassword points to an array of unsigned long values comprising +//! the password to set. Each element may be any 32-bit value other than +//! 0xFFFFFFFF. This array must contain the number of elements given by the +//! \b ulCount parameter. +//! \param ulCount provides the number of unsigned longs in the \b ulPassword. +//! Valid values are 1, 2 and 3. +//! +//! This function allows the password used to unlock an EEPROM block to be +//! set. Valid passwords may be either 32, 64 or 96 bits comprising words +//! with any value other than 0xFFFFFFFF. The password may only be set once. +//! Any further attempts to set the password result in an error. Once the +//! password is set, the block remains unlocked until EEPROMBlockLock() is +//! called for that block or block 0, or a reset occurs. +//! +//! If a password is set on block 0, this affects locking of the peripheral as +//! a whole. When block 0 is locked, all other EEPROM blocks are inaccessible +//! until block 0 is unlocked. Once block 0 is unlocked, other blocks +//! become accessible according to any passwords set on those blocks and the +//! protection set for that block via a call to EEPROMBlockProtectSet(). +//! +//! \return Returns a logical OR combination of \b EEPROM_RC_INVPL, +//! \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, +//! \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING to indicate status and error +//! conditions. +// +//***************************************************************************** +unsigned long +EEPROMBlockPasswordSet(unsigned long ulBlock, unsigned long *pulPassword, + unsigned long ulCount) +{ + unsigned long ulReg; + + // + // Check parameters in a debug build. + // + ASSERT(pulPassword); + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT(ulCount <= 3); + + // + // Set the block number whose password we are about to write. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Start with the first password word. + // + ulReg = EEPROM_EEPASS0; + + // + // Write the password. + // + while(ulCount) + { + // + // Start the process of writing the password. + // + HWREG(ulReg) = *pulPassword; + + // + // Update values in preparation for writing the next word. + // + pulPassword++; + ulReg += 4; + ulCount--; + + // + // Wait for the last word write to complete or an error to be reported. + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Still working. + // + } + } + + // + // Return the final write status. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Locks a password-protected EEPROM block. +//! +//! \param ulBlock is the EEPROM block number which is to be locked. +//! +//! This function locks an EEPROM block that has previously been protected by +//! writing a password. Access to the block once it is locked is determined +//! by the protection settings applied via a previous call to the +//! EEPROMBlockProtectSet() function. If no password has previously been set +//! for the block, this function has no effect. +//! +//! Locking block 0 has the effect of making all other blocks in the EEPROM +//! inaccessible. +//! +//! \return Returns the lock state for the block on exit, 1 if unlocked (as +//! would be the case if no password was set) or 0 if locked. +//! +//***************************************************************************** +unsigned long +EEPROMBlockLock(unsigned long ulBlock) +{ + // + // Check parameters in a debug build. + // + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Select the block we are going to lock. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Lock the block. + // + HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; + + // + // Return the current lock state. + // + return(HWREG(EEPROM_EEUNLOCK)); +} + +//***************************************************************************** +// +//! Unlocks a password-protected EEPROM block. +//! +//! \param ulBlock is the EEPROM block number which is to be unlocked. +//! \param pulPassword points to an array of unsigned long values containing +//! the password for the blockt. Each element must match the password +//! originally set via a call to EEPROMBlockPasswordSet(). +//! \param ulCount provides the number of unsigned longs in the \b pulPassword +//! array and must match the value originally passed to +//! EEPROMBlockPasswordSet(). Valid values are 1, 2 and 3. +//! +//! This function unlocks an EEPROM block that has previously been protected by +//! writing a password. Access to the block once it is unlocked is determined +//! by the protection settings applied via a previous call to the +//! EEPROMBlockProtectSet() function. +//! +//! To successfully unlock an EEPROM block, the password provided must match +//! the password provided on the original call to EEPROMBlockPasswordSet(). If +//! an incorrect password is provided, the block remains locked. +//! +//! Unlocking block 0 has the effect of making all other blocks in the device +//! accessible according to their own access protection settings. When block +//! 0 is locked, all other EEPROM blocks are inaccessible. +//! +//! \return Returns the lock state for the block on exit, 1 if unlocked or 0 if +//! locked. +//! +//***************************************************************************** +unsigned long +EEPROMBlockUnlock(unsigned long ulBlock, unsigned long *pulPassword, + unsigned long ulCount) +{ + // + // Check parameters in a debug build. + // + ASSERT(pulPassword); + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT(ulCount <= 3); + + // + // Set the block that we are trying to unlock. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Write the unlock register with 0xFFFFFFFF to reset the unlock + // sequence just in case a short password was previously used to try to + // unlock the block. + // + HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; + + // + // We need to write the password words in the opposite order when unlocking + // compared to locking so start at the end of the array. + // + pulPassword += (ulCount - 1); + + // + // Write the supplied password to unlock the block. + // + while(ulCount) + { + HWREG(EEPROM_EEUNLOCK) = *pulPassword--; + ulCount--; + } + + // + // Let the caller know if their password worked. + // + return(HWREG(EEPROM_EEUNLOCK)); +} + +//***************************************************************************** +// +//! Hides an EEPROM block until the next reset. +//! +//! \param ulBlock is the EEPROM block number which is to be hidden. +//! +//! This function hides an EEPROM block other than block 0. Once hidden, a +//! block is completely inaccessible until the next reset. This mechanism +//! allows initialization code to have access to data which is to be hidden +//! from the rest of the application. Unlike applications using passwords, an +//! application making using of block hiding need not contain any embedded +//! passwords which could be found through disassembly. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMBlockHide(unsigned long ulBlock) +{ + // + // Check parameters in a debug build. + // + ASSERT(!ulBlock); + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Hide the requested block. + // + HWREG(EEPROM_EEHIDE) = (1 << ulBlock); +} + +//***************************************************************************** +// +//! Enables the EEPROM interrupt. +//! +//! \param ulIntFlags indicates which EEPROM interrupt source to enable. This +//! must be \b EEPROM_INT_PROGRAM currently. +//! +//! This function enables the EEPROM interrupt. When enabled, an interrupt +//! is generated when any EEPROM write or erase operation completes. The +//! EEPROM peripheral shares a single interrupt vector with the flash memory +//! subsystem, \b INT_FLASH. This function is provided as a convenience but +//! the EEPROM interrupt can also be enabled using a call to FlashIntEnable() +//! passing FLASH_INT_EEPROM in the \b ulIntFlags parameter. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntEnable(unsigned long ulIntFlags) +{ + // + // Look for valid interrupt sources. + // + ASSERT(ulIntFlags == EEPROM_INT_PROGRAM); + + // + // Enable interrupts from the EEPROM module. + // + HWREG(EEPROM_EEINT) |= EEPROM_EEINT_INT; + + // + // Enable the EEPROM interrupt in the flash controller module. + // + HWREG(FLASH_FCIM) |= FLASH_FCRIS_ERIS; +} + +//***************************************************************************** +// +//! Disables the EEPROM interrupt. +//! +//! \param ulIntFlags indicates which EEPROM interrupt source to disable. This +//! must be \b EEPROM_INT_PROGRAM currently. +//! +//! This function disables the EEPROM interrupt and prevents calls to the +//! interrupt vector when any EEPROM write or erase operation completes. The +//! EEPROM peripheral shares a single interrupt vector with the flash memory +//! subsystem, \e INT_FLASH. This function is provided as a convenience but +//! the EEPROM interrupt can also be disabled using a call to FlashIntDisable() +//! passing FLASH_INT_EEPROM in the \b ulIntFlags parameter. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntDisable(unsigned long ulIntFlags) +{ + // + // Look for valid interrupt sources. + // + ASSERT(ulIntFlags == EEPROM_INT_PROGRAM); + + // + // Disable the EEPROM interrupt in the flash controller module. + // + HWREG(FLASH_FCIM) &= ~FLASH_FCIM_EMASK; + + // + // Disable interrupts from the EEPROM module. + // + HWREG(EEPROM_EEINT) &= ~EEPROM_EEINT_INT; +} + +//***************************************************************************** +// +//! Reports the state of the EEPROM interrupt. +//! +//! \param bMasked determines whether the masked or unmasked state of the +//! interrupt is to be returned. If bMasked is \e true, the masked state is +//! returned, otherwise the unmasked state is returned. +//! +//! This function allows an application to query the state of the EEPROM +//! interrupt. If active, the interrupt may be cleared by calling +//! EEPROMIntClear(). +//! +//! \return Returns \b EEPROM_INT_PROGRAM if an interrupt is being signaled or +//! 0 otherwise. +// +//***************************************************************************** +unsigned long +EEPROMIntStatus(tBoolean bMasked) +{ + if(bMasked) + { + // + // If asked for the masked interrupt status, we check to see if the + // relevant interrupt is pending in the flash controller then return + // the appropriate EEPROM flag if it is. + // + return((HWREG(FLASH_FCMISC) & FLASH_FCMISC_EMISC) ? + EEPROM_INT_PROGRAM : 0); + } + else + { + // + // If asked for the unmasked interrupt status, infer that an interrupt + // is pending if the WORKING bit of the EEDONE register is clear. The + // actual interrupt fires on the high to low transition of this bit + // but we don't have access to an unmasked interrupt status for the + // EEPROM because it's handled via the flash controller so we have to + // make do with this instead. + // + return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ? + 0 : EEPROM_INT_PROGRAM); + } +} + +//***************************************************************************** +// +//! Clears the EEPROM interrupt. +//! +//! \param ulIntFlags indicates which interrupt sources to clear. Currently, +//! the only valid value is \b EEPROM_INT_PROGRAM. +//! +//! This function allows an application to clear the EEPROM interrupt. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_EMISC; + + // + // Clear the sector protection bits to prevent possible problems when + // programming the main flash array later. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } +} + +//***************************************************************************** +// +//! Returns status on the last EEPROM program or erase operation. +//! +//! This function returns the current status of the last program or erase +//! operation performed by the EEPROM. It is intended to provide error +//! information to applications programming or setting EEPROM protection +//! options under interrupt control. +//! +//! \return Returns 0 if the last program or erase operation completed without +//! any errors. If an operation is ongoing or an error occurred, the return +//! value is a logical OR combination of \b EEPROM_RC_INVPL, +//! \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, +//! \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. +//! +//***************************************************************************** +unsigned long +EEPROMStatusGet(void) +{ + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/eeprom.h b/driverlib/eeprom.h new file mode 100644 index 0000000..ee07f26 --- /dev/null +++ b/driverlib/eeprom.h @@ -0,0 +1,279 @@ +//***************************************************************************** +// +// eeprom.h - Prototypes for the EEPROM driver. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __EEPROM_H__ +#define __EEPROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eeprom_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Values returned by EEPROMInit. +// +//***************************************************************************** + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that +//! no previous write operations were interrupted by a reset event and that the +//! EEPROM peripheral is ready for use. +// +#define EEPROM_INIT_OK 0 + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that +//! a previous data or protection write operation was interrupted by a reset +//! event. The EEPROM peripheral has recovered its state but the last write +//! operation may have been lost. The application must check the validity of +//! data it has written and retry any writes as required. +// +#define EEPROM_INIT_RETRY 1 + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that a +//! previous data or protection write operation was interrupted by a reset +//! event and that the EEPROM peripheral was unable to clean up after the +//! problem. This situation may be resolved with another reset or may be fatal +//! depending upon the cause of the problem. For example, if the voltage to +//! the part is unstable, retrying once the voltage has stabilized may clear +//! the error. +// +#define EEPROM_INIT_ERROR 2 + +//***************************************************************************** +// +// Error indicators returned by various EEPROM API calls. These will be ORed +// together into the final return code. +// +//***************************************************************************** + +// +//! This return code bit indicates that the EEPROM programming state machine +//! failed to write a value due to the voltage level dropping below that +//! required for EEPROM programming. The operation may be retried once the +//! voltage stabilizes. +// +#define EEPROM_RC_INVPL 0x00000100 + +// +//! This return code bit indicates that an attempt was made to read from +//! the EEPROM while a write operation was in progress. +// +#define EEPROM_RC_WRBUSY 0x00000020 + +// +//! This return code bit indicates that an attempt was made to write a +//! value but the destination permissions disallow write operations. This +//! may be due to the destination block being locked, access protection set +//! to prohibit writes or an attempt to write a password when one is already +//! written. +// +#define EEPROM_RC_NOPERM 0x00000010 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently copying to or from the internal copy buffer to make room for +//! a newly written value. It is provided as a status indicator and does not +//! indicate an error. +// +#define EEPROM_RC_WKCOPY 0x00000008 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently erasing the internal copy buffer. It is provided as a +//! status indicator and does not indicate an error. +// +#define EEPROM_RC_WKERASE 0x00000004 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently working. No new write operations should be attempted until +//! this bit is clear. +// +#define EEPROM_RC_WORKING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EEPROMBlockProtectSet() in the ulProtect +// parameter, and returned by EEPROMBlockProtectGet(). +// +//***************************************************************************** + +// +//! This bit may be ORed with the protection option passed to +//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It +//! restricts EEPROM access to threads running in supervisor mode and prevents +//! access to an EEPROM block when the CPU is in user mode. +// +#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer +//! read/write access when no password is set or when a password is set and +//! the block is unlocked, and read-only access when a password is set but +//! the block is locked. +// +#define EEPROM_PROT_RW_LRO_URW 0x00000000 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer neither +//! read nor write access unless it is protected by a password and unlocked. +// +#define EEPROM_PROT_NA_LNA_URW 0x00000001 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer +//! read-only access when no password is set or when a password is set and the +//! block is unlocked. When a password is set and the block is locked, neither +//! read nor write access is permitted. +// +#define EEPROM_PROT_RO_LNA_URO 0x00000002 + +//***************************************************************************** +// +//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is +//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being +//! signaled. +// +//***************************************************************************** +#define EEPROM_INT_PROGRAM 0x00000004 + +//***************************************************************************** +// +//! Returns the EEPROM block number containing a given offset address. +//! +//! \param ulAddr is the linear, byte address of the EEPROM location whose +//! block number is to be returned. This is a zero-based offset from the start +//! of the EEPROM storage. +//! +//! This macro may be used to translate an EEPROM address offset into a +//! block number suitable for use in any of the driver's block protection +//! functions. The address provided is expressed as a byte offset from the +//! base of the EEPROM. +//! +//! \return Returns the zero-based block number which contains the passed +//! address. +// +//***************************************************************************** +#define EEPROMBlockFromAddr(ulAddr) ((ulAddr) >> 6) + +//***************************************************************************** +// +//! Returns the offset address of the first word in an EEPROM block. +//! +//! \param ulBlock is the index of the EEPROM block whose first word address +//! is to be returned. +//! +//! This macro may be used to determine the address of the first word in a +//! given EEPROM block. The address returned is expressed as a byte offset +//! from the base of EEPROM storage. +//! +//! \return Returns the address of the first word in the given EEPROM block. +// +//***************************************************************************** +#define EEPROMAddrFromBlock(ulBlock) ((ulBlock) << 6) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long EEPROMInit(void); +extern unsigned long EEPROMSizeGet(void); +extern unsigned long EEPROMBlockCountGet(void); +extern void EEPROMRead(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern unsigned long EEPROMProgram(unsigned long *pulData, + unsigned long ulAddress, + unsigned long ulCount); +extern unsigned long EEPROMProgramNonBlocking(unsigned long ulData, + unsigned long ulAddress); +extern unsigned long EEPROMStatusGet(void); +extern unsigned long EEPROMMassErase(void); +extern unsigned long EEPROMBlockProtectGet(unsigned long ulBlock); +extern unsigned long EEPROMBlockProtectSet(unsigned long ulBlock, + unsigned long ulProtect); +extern unsigned long EEPROMBlockPasswordSet(unsigned long ulBlock, + unsigned long *pulPassword, + unsigned long ulCount); +extern unsigned long EEPROMBlockLock(unsigned long ulBlock); +extern unsigned long EEPROMBlockUnlock(unsigned long ulBlock, + unsigned long *pulPassword, + unsigned long ulCount); +extern void EEPROMBlockHide(unsigned long ulBlock); +extern void EEPROMIntEnable(unsigned long ulIntFlags); +extern void EEPROMIntDisable(unsigned long ulIntFlags); +extern unsigned long EEPROMIntStatus(tBoolean bMasked); +extern void EEPROMIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EEPROM_H__ diff --git a/driverlib/epi.c b/driverlib/epi.c new file mode 100644 index 0000000..552c2b2 --- /dev/null +++ b/driverlib/epi.c @@ -0,0 +1,1190 @@ +//***************************************************************************** +// +// epi.c - Driver for the EPI module. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "inc/hw_epi.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/epi.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! \addtogroup epi_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sets the usage mode of the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! \param ulMode is the usage mode of the EPI module. +//! +//! This functions sets the operating mode of the EPI module. The parameter +//! \e ulMode must be one of the following: +//! +//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation +//! - \b EPI_MODE_SDRAM - use with SDRAM device +//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface +//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface +//! - \b EPI_MODE_DISABLE - disable the EPI module +//! +//! Selection of any of the above modes enables the EPI module, except +//! for \b EPI_MODE_DISABLE which should be used to disable the module. +//! +//! \return None. +// +//***************************************************************************** +void +EPIModeSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT((ulMode == EPI_MODE_GENERAL) || + (ulMode == EPI_MODE_SDRAM) || + (ulMode == EPI_MODE_HB8) || + (ulMode == EPI_MODE_HB16) || + (ulMode == EPI_MODE_DISABLE)); + + // + // Write the mode word to the register. + // + HWREG(ulBase + EPI_O_CFG) = ulMode; +} + +//***************************************************************************** +// +//! Sets the clock divider for the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! \param ulDivider is the value of the clock divider to be applied to +//! the external interface (0-65535). +//! +//! This function sets the clock divider(s) that is used to determine the +//! clock rate of the external interface. The \e ulDivider value is used to +//! derive the EPI clock rate from the system clock based on the following +//! formula. +//! +//! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) +//! +//! For example, a divider value of 1 results in an EPI clock rate of half +//! the system clock, value of 2 or 3 yields one quarter of the system clock and +//! a value of 4 results in one sixth of the system clock rate. +//! +//! In cases where a dual chip select mode is in use and different clock rates +//! are required for each chip select, the \e ulDivider parameter must contain +//! two dividers. The lower 16 bits define the divider to be used with CS0n +//! and the upper 16 bits define the divider for CS1n. +//! +//! \return None. +// +//***************************************************************************** +void +EPIDividerSet(unsigned long ulBase, unsigned long ulDivider) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Write the divider value to the register. + // + HWREG(ulBase + EPI_O_BAUD) = ulDivider; +} + +//***************************************************************************** +// +//! Configures the SDRAM mode of operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the SDRAM interface configuration. +//! \param ulRefresh is the refresh count in core clocks (0-2047). +//! +//! This function is used to configure the SDRAM interface, when the SDRAM +//! mode is chosen with the function EPIModeSet(). The parameter \e ulConfig +//! is the logical OR of several sets of choices: +//! +//! The processor core frequency must be specified with one of the following: +//! +//! - \b EPI_SDRAM_CORE_FREQ_0_15 - core clock is 0 MHz < clk <= 15 MHz +//! - \b EPI_SDRAM_CORE_FREQ_15_30 - core clock is 15 MHz < clk <= 30 MHz +//! - \b EPI_SDRAM_CORE_FREQ_30_50 - core clock is 30 MHz < clk <= 50 MHz +//! - \b EPI_SDRAM_CORE_FREQ_50_100 - core clock is 50 MHz < clk <= 100 MHz +//! +//! The low power mode is specified with one of the following: +//! +//! - \b EPI_SDRAM_LOW_POWER - enter low power, self-refresh state +//! - \b EPI_SDRAM_FULL_POWER - normal operating state +//! +//! The SDRAM device size is specified with one of the following: +//! +//! - \b EPI_SDRAM_SIZE_64MBIT - 64 Mbit device (8 MB) +//! - \b EPI_SDRAM_SIZE_128MBIT - 128 Mbit device (16 MB) +//! - \b EPI_SDRAM_SIZE_256MBIT - 256 Mbit device (32 MB) +//! - \b EPI_SDRAM_SIZE_512MBIT - 512 Mbit device (64 MB) +//! +//! The parameter \e ulRefresh sets the refresh counter in units of core +//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulRefresh) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulRefresh < 2048); + + // + // Fill in the refresh count field of the configuration word. + // + ulConfig &= ~EPI_SDRAMCFG_RFSH_M; + ulConfig |= ulRefresh << EPI_SDRAMCFG_RFSH_S; + + // + // Write the SDRAM configuration register. + // + HWREG(ulBase + EPI_O_SDRAMCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the interface for Host-bus 8 operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the interface configuration. +//! \param ulMaxWait is the maximum number of external clocks to wait +//! if a FIFO ready signal is holding off the transaction. +//! +//! This function is used to configure the interface when used in Host-bus 8 +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ulConfig is the logical OR of any of the following: +//! +//! - one of \b EPI_HB8_MODE_ADMUX, \b EPI_HB8_MODE_ADDEMUX, +//! \b EPI_HB8_MODE_SRAM, or \b EPI_HB8_MODE_FIFO to select the HB8 mode +//! - \b EPI_HB8_USE_TXEMPTY - enable TXEMPTY signal with FIFO +//! - \b EPI_HB8_USE_RXFULL - enable RXFULL signal with FIFO +//! - \b EPI_HB8_WRHIGH - use active high write strobe, otherwise it is +//! active low +//! - \b EPI_HB8_RDHIGH - use active high read strobe, otherwise it is +//! active low +//! - one of \b EPI_HB8_WRWAIT_0, \b EPI_HB8_WRWAIT_1, \b EPI_HB8_WRWAIT_2, +//! or \b EPI_HB8_WRWAIT_3 to select the number of write wait states (default +//! is 0 wait states) +//! - one of \b EPI_HB8_RDWAIT_0, \b EPI_HB8_RDWAIT_1, \b EPI_HB8_RDWAIT_2, +//! or \b EPI_HB8_RDWAIT_3 to select the number of read wait states (default +//! is 0 wait states) +//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the +//! correct byte lanes allowing data to be stored in bits [31:8]. If absent, +//! all data transfers use bits [7:0]. +//! - \b EPI_HB8_CSBAUD_DUAL - use different baud rates when accessing devices +//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the +//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the +//! upper 16 bits. If this option is absent, both chip selects use the baud +//! rate resulting from the divider in the lower 16 bits of the parameter passed +//! to EPIDividerSet(). +//! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE, +//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL_CS. +//! \b EPI_HB8_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal. +//! \b EPI_HB8_CSCFG_ALE sets EPI30 to operate as an address latch (ALE). +//! \b EPI_HB8_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n +//! with the asserted chip select determined from the most significant address +//! bit for the respective external address map. \b EPI_HB8_CSCFG_ALE_DUAL_CS +//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with +//! the asserted chip select determined from the most significant address bit +//! for the respective external address map. +//! +//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a +//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this +//! parameter determines the maximum number of clocks to wait when the +//! transaction is being held off by by the FIFO using one of these ready +//! signals. A value of 0 means to wait forever. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulMaxWait < 256); + + // + // Determine the CS and word access modes. + // + HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ? + EPI_HB8CFG2_WORD : 0) | + ((ulConfig & EPI_HB8_CSBAUD_DUAL) ? + EPI_HB8CFG2_CSBAUD : 0) | + ((ulConfig & EPI_HB8_CSCFG_MASK) << 15)); + // + // Fill in the max wait field of the configuration word. + // + ulConfig &= ~EPI_HB8CFG_MAXWAIT_M; + ulConfig |= ulMaxWait << EPI_HB8CFG_MAXWAIT_S; + + // + // Write the main HostBus8 configuration register. + // + HWREG(ulBase + EPI_O_HB8CFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the interface for Host-bus 16 operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the interface configuration. +//! \param ulMaxWait is the maximum number of external clocks to wait +//! if a FIFO ready signal is holding off the transaction. +//! +//! This function is used to configure the interface when used in Host-bus 16 +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ulConfig is the logical OR of any of the following: +//! +//! - one of \b EPI_HB16_MODE_ADMUX, \b EPI_HB16_MODE_ADDEMUX, +//! \b EPI_HB16_MODE_SRAM, or \b EPI_HB16_MODE_FIFO to select the HB16 mode +//! - \b EPI_HB16_USE_TXEMPTY - enable TXEMPTY signal with FIFO +//! - \b EPI_HB16_USE_RXFULL - enable RXFULL signal with FIFO +//! - \b EPI_HB16_WRHIGH - use active high write strobe, otherwise it is +//! active low +//! - \b EPI_HB16_RDHIGH - use active high read strobe, otherwise it is +//! active low +//! - one of \b EPI_HB16_WRWAIT_0, \b EPI_HB16_WRWAIT_1, \b EPI_HB16_WRWAIT_2, +//! or \b EPI_HB16_WRWAIT_3 to select the number of write wait states (default +//! is 0 wait states) +//! - one of \b EPI_HB16_RDWAIT_0, \b EPI_HB16_RDWAIT_1, \b EPI_HB16_RDWAIT_2, +//! or \b EPI_HB16_RDWAIT_3 to select the number of read wait states (default +//! is 0 wait states) +//! - \b EPI_HB16_WORD_ACCESS - use Word Access mode to route bytes to the +//! correct byte lanes allowing data to be stored in bits [31:16]. If absent, +//! all data transfers use bits [15:0]. +//! - \b EPI_HB16_BSEL - enables byte selects. In this mode, two EPI signals +//! operate as byte selects allowing 8-bit transfers. If this flag is not +//! specified, data must be read and written using only 16-bit transfers. +//! - \b EPI_HB16_CSBAUD_DUAL - use different baud rates when accessing devices +//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the +//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the +//! upper 16 bits. If this option is absent, both chip selects use the baud +//! rate resulting from the divider in the lower 16 bits of the parameter passed +//! to EPIDividerSet(). +//! - one of \b EPI_HB16_CSCFG_CS, \b EPI_HB16_CSCFG_ALE, +//! \b EPI_HB16_CSCFG_DUAL_CS or \b EPI_HB16_CSCFG_ALE_DUAL_CS. +//! \b EPI_HB16_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal. +//! \b EPI_HB16_CSCFG_ALE sets EPI30 to operate as an address latch (ALE). +//! \b EPI_HB16_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n +//! with the asserted chip select determined from the most significant address +//! bit for the respective external address map. \b EPI_HB16_CSCFG_ALE_DUAL_CS +//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with +//! the asserted chip select determined from the most significant address bit +//! for the respective external address map. +//! +//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a +//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this +//! parameter determines the maximum number of clocks to wait when the +//! transaction is being held off by by the FIFO using one of these ready +//! signals. A value of 0 means to wait forever. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulMaxWait < 256); + + // + // Determine the CS and word access modes. + // + HWREG(ulBase + EPI_O_HB16CFG2) = (((ulConfig & EPI_HB16_WORD_ACCESS) ? + EPI_HB16CFG2_WORD : 0) | + ((ulConfig & EPI_HB16_CSBAUD_DUAL) ? + EPI_HB16CFG2_CSBAUD : 0) | + ((ulConfig & EPI_HB16_CSCFG_MASK) << 15)); + + // + // Fill in the max wait field of the configuration word. + // + ulConfig &= ~EPI_HB16CFG_MAXWAIT_M; + ulConfig |= ulMaxWait << EPI_HB16CFG_MAXWAIT_S; + + // + // Write the main HostBus16 configuration register. + // + HWREG(ulBase + EPI_O_HB16CFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the interface for general-purpose mode operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the interface configuration. +//! \param ulFrameCount is the frame size in clocks, if the frame signal +//! is used (0-15). +//! \param ulMaxWait is the maximum number of external clocks to wait +//! when the external clock enable is holding off the transaction (0-255). +//! +//! This function is used to configure the interface when used in +//! general-purpose operation as chosen with the function EPIModeSet(). The +//! parameter \e ulConfig is the logical OR of any of the following: +//! +//! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin +//! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction, +//! otherwise it is free-running +//! - \b EPI_GPMODE_RDYEN - the external peripheral drives an iRDY signal into +//! pin EPI0S27. If absent, the peripheral is assumed to be ready at all times. +//! This flag may only be used with a free-running clock (\b EPI_GPMODE_CLKGATE +//! is absent). +//! - \b EPI_GPMODE_FRAMEPIN - framing signal is emitted on a pin +//! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it +//! is a pulse +//! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins +//! - \b EPI_GPMODE_WRITE2CYCLE - a two-cycle write is used, otherwise a +//! single-cycle write is used +//! - \b EPI_GPMODE_READ2CYCLE - a two-cycle read is used, otherwise a +//! single-cycle read is used +//! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4, +//! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address +//! bus or an address bus size of 4, 12, or 20 bits +//! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16, +//! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus +//! size of 8, 16, 24, or 32 bits +//! - \b EPI_GPMODE_WORD_ACCESS - use Word Access mode to route bytes to the +//! correct byte lanes allowing data to be stored in the upper bits of the word +//! when necessary. +//! +//! The parameter \e ulFrameCount is the number of clocks used to form the +//! framing signal, if the framing signal is used. The behavior depends on +//! whether the frame signal is a pulse or a 50/50 duty cycle. This value +//! is not used if the framing signal is not enabled with the option +//! \b EPI_GPMODE_FRAMEPIN. +//! +//! The parameter \e ulMaxWait is used if the external clock enable is turned +//! on with the \b EPI_GPMODE_CLKENA option is used. In the case that +//! external clock enable is used, this parameter determines the maximum +//! number of clocks to wait when the external clock enable signal is holding +//! off a transaction. A value of 0 means to wait forever. If a non-zero +//! value is used and exceeded, an interrupt occurs and the transaction +//! aborted. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulFrameCount, unsigned long ulMaxWait) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulFrameCount < 16); + ASSERT(ulMaxWait < 256); + + // + // Set the word access mode. + // + HWREG(ulBase + EPI_O_GPCFG2) = ((ulConfig & EPI_GPMODE_WORD_ACCESS) ? + EPI_GPCFG2_WORD : 0); + + // + // Fill in the frame count field of the configuration word. + // + ulConfig &= ~EPI_GPCFG_FRMCNT_M; + ulConfig |= ulFrameCount << EPI_GPCFG_FRMCNT_S; + + // + // Fill in the max wait field of the configuration word. + // + ulConfig &= ~EPI_GPCFG_MAXWAIT_M; + ulConfig |= ulMaxWait << EPI_GPCFG_MAXWAIT_S; + + // + // Write the non-moded configuration register. + // + HWREG(ulBase + EPI_O_GPCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the address map for the external interface. +//! +//! \param ulBase is the EPI module base address. +//! \param ulMap is the address mapping configuration. +//! +//! This function is used to configure the address mapping for the external +//! interface. This determines the base address of the external memory or +//! device within the processor peripheral and/or memory space. +//! +//! The parameter \e ulMap is the logical OR of the following: +//! +//! - \b EPI_ADDR_PER_SIZE_256B, \b EPI_ADDR_PER_SIZE_64KB, +//! \b EPI_ADDR_PER_SIZE_16MB, or \b EPI_ADDR_PER_SIZE_512MB to choose a +//! peripheral address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes +//! - \b EPI_ADDR_PER_BASE_NONE, \b EPI_ADDR_PER_BASE_A, or +//! \b EPI_ADDR_PER_BASE_C to choose the base address of the peripheral +//! space as none, 0xA0000000, or 0xC0000000 +//! - \b EPI_ADDR_RAM_SIZE_256B, \b EPI_ADDR_RAM_SIZE_64KB, +//! \b EPI_ADDR_RAM_SIZE_16MB, or \b EPI_ADDR_RAM_SIZE_512MB to choose a +//! RAM address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes +//! - \b EPI_ADDR_RAM_BASE_NONE, \b EPI_ADDR_RAM_BASE_6, or +//! \b EPI_ADDR_RAM_BASE_8 to choose the base address of the RAM space +//! as none, 0x60000000, or 0x80000000 +//! +//! \return None. +// +//***************************************************************************** +void +EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulMap < 0x100); + + // + // Set the value of the address mapping register. + // + HWREG(ulBase + EPI_O_ADDRMAP) = ulMap; +} + +//***************************************************************************** +// +//! Configures a non-blocking read transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! \param ulDataSize is the size of the data items to read. +//! \param ulAddress is the starting address to read. +//! +//! This function is used to configure a non-blocking read channel for a +//! transaction. Two channels are available which can be used in a ping-pong +//! method for continuous reading. It is not necessary to use both channels +//! to perform a non-blocking read. +//! +//! The parameter \e ulDataSize is one of \b EPI_NBCONFIG_SIZE_8, +//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit, +//! or 32-bit sized data transfers. +//! +//! The parameter \e ulAddress is the starting address for the read, relative +//! to the external device. The start of the device is address 0. +//! +//! Once configured, the non-blocking read is started by calling +//! EPINonBlockingReadStart(). If the addresses to be read from the device +//! are in a sequence, it is not necessary to call this function multiple +//! times. Until it is changed, the EPI module stores the last address +//! that was used for a non-blocking read (per channel). +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDataSize, unsigned long ulAddress) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + ASSERT(ulDataSize < 4); + ASSERT(ulAddress < 0x20000000); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RSIZE1 - EPI_O_RSIZE0); + + // + // Write the data size register for the channel. + // + HWREG(ulBase + EPI_O_RSIZE0 + ulOffset) = ulDataSize; + + // + // Write the starting address register for the channel. + // + HWREG(ulBase + EPI_O_RADDR0 + ulOffset) = ulAddress; +} + +//***************************************************************************** +// +//! Starts a non-blocking read transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! \param ulCount is the number of items to read (1-4095). +//! +//! This function starts a non-blocking read that was previously configured +//! with the function EPINonBlockingReadConfigure(). Once this function is +//! called, the EPI module begins reading data from the external device +//! into the read FIFO. The EPI stops reading when the FIFO fills up +//! and resumes reading when the application drains the FIFO, until the +//! total specified count of data items has been read. +//! +//! Once a read transaction is completed and the FIFO drained, another +//! transaction can be started from the next address by calling this +//! function again. +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulCount) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + ASSERT(ulCount < 4096); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Write to the read count register. + // + HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = ulCount; +} + +//***************************************************************************** +// +//! Stops a non-blocking read transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! +//! This function cancels a non-blocking read transaction that is already +//! in progress. +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Write a 0 to the read count register, which cancels the transaction. + // + HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0; +} + +//***************************************************************************** +// +//! Get the count remaining for a non-blocking transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! +//! This function gets the remaining count of items for a non-blocking read +//! transaction. +//! +//! \return The number of items remaining in the non-blocking read transaction. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadCount(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Read the count remaining and return the value to the caller. + // + return(HWREG(ulBase + EPI_O_RPSTD0 + ulOffset)); +} + +//***************************************************************************** +// +//! Get the count of items available in the read FIFO. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function gets the number of items that are available to read in +//! the read FIFO. The read FIFO is filled by a non-blocking read transaction +//! which is configured by the functions EPINonBlockingReadConfigure() and +//! EPINonBlockingReadStart(). +//! +//! \return The number of items available to read in the read FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Read the FIFO count and return it to the caller. + // + return(HWREG(ulBase + EPI_O_RFIFOCNT)); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 32-bit data items. +//! +//! \param ulBase is the EPI module base address. +//! \param ulCount is the maximum count of items to read. +//! \param pulBuf is the caller supplied buffer where the read data should +//! be stored. +//! +//! This function reads 32-bit data items from the read FIFO and stores +//! the values in a caller-supplied buffer. The function reads and stores +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ulCount. The actual +//! count of items is returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount, + unsigned long *pulBuf) +{ + unsigned long ulCountRead = 0; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulCount < 4096); + ASSERT(pulBuf); + + // + // Read from the FIFO while there are any items to read and + // the caller's specified count is not exceeded. + // + while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pulBuf = HWREG(ulBase + EPI_O_READFIFO); + + // + // Update the caller's buffer pointer and the count of items read. + // + pulBuf++; + ulCountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ulCountRead); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 16-bit data items. +//! +//! \param ulBase is the EPI module base address. +//! \param ulCount is the maximum count of items to read. +//! \param pusBuf is the caller-supplied buffer where the read data should +//! be stored. +//! +//! This function reads 16-bit data items from the read FIFO and stores +//! the values in a caller-supplied buffer. The function reads and stores +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ulCount. The actual +//! count of items is returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount, + unsigned short *pusBuf) +{ + unsigned long ulCountRead = 0; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulCount < 4096); + ASSERT(pusBuf); + + // + // Read from the FIFO while there are any items to read, and + // the caller's specified count is not exceeded. + // + while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) + { + // + // Read from the FIFO and store in the caller-supplied buffer. + // + *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO); + + // + // Update the caller's buffer pointer and the count of items read. + // + pusBuf++; + ulCountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ulCountRead); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 8-bit data items. +//! +//! \param ulBase is the EPI module base address. +//! \param ulCount is the maximum count of items to read. +//! \param pucBuf is the caller-supplied buffer where the read data should +//! be stored. +//! +//! This function reads 8-bit data items from the read FIFO and stores +//! the values in a caller-supplied buffer. The function reads and stores +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ulCount. The actual +//! count of items is returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount, + unsigned char *pucBuf) +{ + unsigned long ulCountRead = 0; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulCount < 4096); + ASSERT(pucBuf); + + // + // Read from the FIFO while there are any items to read, and + // the caller's specified count is not exceeded. + // + while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pucBuf = (unsigned char)HWREG(ulBase + EPI_O_READFIFO); + + // + // Update the caller's buffer pointer and the count of items read. + // + pucBuf++; + ulCountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ulCountRead); +} + +//***************************************************************************** +// +//! Configures the read FIFO. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the FIFO configuration. +//! +//! This function configures the FIFO trigger levels and error +//! generation. The parameter \e ulConfig is the logical OR of the +//! following: +//! +//! - \b EPI_FIFO_CONFIG_WTFULLERR - enables an error interrupt when a write is +//! attempted and the write FIFO is full +//! - \b EPI_FIFO_CONFIG_RSTALLERR - enables an error interrupt when a read is +//! stalled due to an interleaved write or other reason +//! - \b EPI_FIFO_CONFIG_TX_EMPTY, \b EPI_FIFO_CONFIG_TX_1_4, +//! \b EPI_FIFO_CONFIG_TX_1_2, or \b EPI_FIFO_CONFIG_TX_3_4 to set the +//! TX FIFO trigger level to empty, 1/4, 1/2, or 3/4 level +//! - \b EPI_FIFO_CONFIG_RX_1_8, \b EPI_FIFO_CONFIG_RX_1_4, +//! \b EPI_FIFO_CONFIG_RX_1_2, \b EPI_FIFO_CONFIG_RX_3_4, +//! \b EPI_FIFO_CONFIG_RX_7_8, or \b EPI_FIFO_CONFIG_RX_FULL to set the +//! RX FIFO trigger level to 1/8, 1/4, 1/2, 3/4, 7/8 or full level +//! +//! \return None. +// +//***************************************************************************** +void +EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulConfig == (ulConfig & 0x00030077)); + + // + // Load the configuration into the FIFO config reg. + // + HWREG(ulBase + EPI_O_FIFOLVL) = ulConfig; +} + +//***************************************************************************** +// +//! Reads the number of empty slots in the write transaction FIFO. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function returns the number of slots available in the transaction +//! FIFO. It can be used in a polling method to avoid attempting a write +//! that would stall. +//! +//! \return The number of empty slots in the transaction FIFO. +// +//***************************************************************************** +unsigned long +EPIWriteFIFOCountGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Read the FIFO count and return it to the caller. + // + return(HWREG(ulBase + EPI_O_WFIFOCNT)); +} + +//***************************************************************************** +// +//! Enables EPI interrupt sources. +//! +//! \param ulBase is the EPI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the specified EPI sources to generate interrupts. +//! The \e ulIntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b EPI_INT_TXREQ - transmit FIFO is below the trigger level +//! - \b EPI_INT_RXREQ - read FIFO is above the trigger level +//! - \b EPI_INT_ERR - an error condition occurred +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulIntFlags < 16); + + // + // Write the interrupt flags mask to the mask register. + // + HWREG(ulBase + EPI_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables EPI interrupt sources. +//! +//! \param ulBase is the EPI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the specified EPI sources for interrupt +//! generation. The \e ulIntFlags parameter can be the logical OR +//! of any of the following values: \b EPI_INT_RXREQ, \b EPI_INT_TXREQ, or +//! \b I2S_INT_ERR. +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulIntFlags < 16); + + // + // Write the interrupt flags mask to the mask register. + // + HWREG(ulBase + EPI_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the EPI interrupt status. +//! +//! \param ulBase is the EPI module base address. +//! \param bMasked is set \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the EPI interrupt status. It can return either +//! the raw or masked interrupt status. +//! +//! \return Returns the masked or raw EPI interrupt status, as a bit field +//! of any of the following values: \b EPI_INT_TXREQ, \b EPI_INT_RXREQ, +//! or \b EPI_INT_ERR +// +//***************************************************************************** +unsigned long +EPIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + EPI_O_MIS)); + } + else + { + return(HWREG(ulBase + EPI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Gets the EPI error interrupt status. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function returns the error status of the EPI. If the return value of +//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this +//! function can be used to determine the cause of the error. +//! +//! This function returns a bit mask of error flags, which can be the logical +//! OR of any of the following: +//! +//! - \b EPI_INT_ERR_WTFULL - occurs when a write stalled when the transaction +//! FIFO was full +//! - \b EPI_INT_ERR_RSTALL - occurs when a read stalled +//! - \b EPI_INT_ERR_TIMEOUT - occurs when the external clock enable held +//! off a transaction longer than the configured maximum wait time +//! +//! \return Returns the interrupt error flags as the logical OR of any of +//! the following: \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or +//! \b EPI_INT_ERR_TIMEOUT. +// +//***************************************************************************** +unsigned long +EPIIntErrorStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Read the error status and return to caller. + // + return(HWREG(ulBase + EPI_O_EISC)); +} + +//***************************************************************************** +// +//! Clears pending EPI error sources. +//! +//! \param ulBase is the EPI module base address. +//! \param ulErrFlags is a bit mask of the error sources to be cleared. +//! +//! This function clears the specified pending EPI errors. The \e ulErrFlags +//! parameter can be the logical OR of any of the following values: +//! \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or \b EPI_INT_ERR_TIMEOUT. +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulErrFlags < 16); + + // + // Write the error flags to the register to clear the pending errors. + // + HWREG(ulBase + EPI_O_EISC) = ulErrFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This sets and enables the handler to be called when the EPI module +//! generates an interrupt. Specific EPI interrupts must still be enabled +//! with the EPIIntEnable() function. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_EPI0, pfnHandler); + + // + // Enable the EPI interface interrupt. + // + IntEnable(INT_EPI0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function disables and clears the handler to be called when the +//! EPI interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EPIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Disable the EPI interface interrupt. + // + IntDisable(INT_EPI0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_EPI0); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/epi.h b/driverlib/epi.h new file mode 100644 index 0000000..387472c --- /dev/null +++ b/driverlib/epi.h @@ -0,0 +1,319 @@ +//***************************************************************************** +// +// epi.h - Prototypes and macros for the EPI module. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __EPI_H__ +#define __EPI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EPIModeSet() +// +//***************************************************************************** +#define EPI_MODE_GENERAL 0x00000010 +#define EPI_MODE_SDRAM 0x00000011 +#define EPI_MODE_HB8 0x00000012 +#define EPI_MODE_HB16 0x00000013 +#define EPI_MODE_DISABLE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigSDRAMSet() +// +//***************************************************************************** +#define EPI_SDRAM_CORE_FREQ_0_15 0x00000000 +#define EPI_SDRAM_CORE_FREQ_15_30 0x40000000 +#define EPI_SDRAM_CORE_FREQ_30_50 0x80000000 +#define EPI_SDRAM_CORE_FREQ_50_100 0xC0000000 +#define EPI_SDRAM_LOW_POWER 0x00000200 +#define EPI_SDRAM_FULL_POWER 0x00000000 +#define EPI_SDRAM_SIZE_64MBIT 0x00000000 +#define EPI_SDRAM_SIZE_128MBIT 0x00000001 +#define EPI_SDRAM_SIZE_256MBIT 0x00000002 +#define EPI_SDRAM_SIZE_512MBIT 0x00000003 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigGPModeSet() +// +//***************************************************************************** +#define EPI_GPMODE_CLKPIN 0x80000000 +#define EPI_GPMODE_CLKGATE 0x40000000 +#define EPI_GPMODE_RDYEN 0x10000000 +#define EPI_GPMODE_FRAMEPIN 0x08000000 +#define EPI_GPMODE_FRAME50 0x04000000 +#define EPI_GPMODE_READWRITE 0x00200000 +#define EPI_GPMODE_WRITE2CYCLE 0x00080000 +#define EPI_GPMODE_READ2CYCLE 0x00040000 +#define EPI_GPMODE_ASIZE_NONE 0x00000000 +#define EPI_GPMODE_ASIZE_4 0x00000010 +#define EPI_GPMODE_ASIZE_12 0x00000020 +#define EPI_GPMODE_ASIZE_20 0x00000030 +#define EPI_GPMODE_DSIZE_8 0x00000000 +#define EPI_GPMODE_DSIZE_16 0x00000001 +#define EPI_GPMODE_DSIZE_24 0x00000002 +#define EPI_GPMODE_DSIZE_32 0x00000003 +#define EPI_GPMODE_WORD_ACCESS 0x00000100 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB8ModeSet() +// +//***************************************************************************** +#define EPI_HB8_USE_TXEMPTY 0x00800000 +#define EPI_HB8_USE_RXFULL 0x00400000 +#define EPI_HB8_WRHIGH 0x00200000 +#define EPI_HB8_RDHIGH 0x00100000 +#define EPI_HB8_WRWAIT_0 0x00000000 +#define EPI_HB8_WRWAIT_1 0x00000040 +#define EPI_HB8_WRWAIT_2 0x00000080 +#define EPI_HB8_WRWAIT_3 0x000000C0 +#define EPI_HB8_RDWAIT_0 0x00000000 +#define EPI_HB8_RDWAIT_1 0x00000010 +#define EPI_HB8_RDWAIT_2 0x00000020 +#define EPI_HB8_RDWAIT_3 0x00000030 +#define EPI_HB8_MODE_ADMUX 0x00000000 +#define EPI_HB8_MODE_ADDEMUX 0x00000001 +#define EPI_HB8_MODE_SRAM 0x00000002 +#define EPI_HB8_MODE_FIFO 0x00000003 +#define EPI_HB8_WORD_ACCESS 0x00000100 +#define EPI_HB8_CSCFG_ALE 0x00000000 +#define EPI_HB8_CSCFG_CS 0x00000200 +#define EPI_HB8_CSCFG_DUAL_CS 0x00000400 +#define EPI_HB8_CSCFG_ALE_DUAL_CS 0x00000600 +#define EPI_HB8_CSBAUD_DUAL 0x00000800 + +#define EPI_HB8_CSCFG_MASK 0x00000600 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB16ModeSet() +// +//***************************************************************************** +#define EPI_HB16_USE_TXEMPTY 0x00800000 +#define EPI_HB16_USE_RXFULL 0x00400000 +#define EPI_HB16_WRHIGH 0x00200000 +#define EPI_HB16_RDHIGH 0x00100000 +#define EPI_HB16_WRWAIT_0 0x00000000 +#define EPI_HB16_WRWAIT_1 0x00000040 +#define EPI_HB16_WRWAIT_2 0x00000080 +#define EPI_HB16_WRWAIT_3 0x000000C0 +#define EPI_HB16_RDWAIT_0 0x00000000 +#define EPI_HB16_RDWAIT_1 0x00000010 +#define EPI_HB16_RDWAIT_2 0x00000020 +#define EPI_HB16_RDWAIT_3 0x00000030 +#define EPI_HB16_MODE_ADMUX 0x00000000 +#define EPI_HB16_MODE_ADDEMUX 0x00000001 +#define EPI_HB16_MODE_SRAM 0x00000002 +#define EPI_HB16_MODE_FIFO 0x00000003 +#define EPI_HB16_BSEL 0x00000004 +#define EPI_HB16_WORD_ACCESS 0x00000100 +#define EPI_HB16_CSCFG_ALE 0x00000000 +#define EPI_HB16_CSCFG_CS 0x00000200 +#define EPI_HB16_CSCFG_DUAL_CS 0x00000400 +#define EPI_HB16_CSCFG_ALE_DUAL_CS 0x00000600 +#define EPI_HB16_CSBAUD_DUAL 0x00000800 + +#define EPI_HB16_CSCFG_MASK 0x00000600 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigSDRAMSet() +// +//***************************************************************************** +#define EPI_ADDR_PER_SIZE_256B 0x00000000 +#define EPI_ADDR_PER_SIZE_64KB 0x00000040 +#define EPI_ADDR_PER_SIZE_16MB 0x00000080 +#define EPI_ADDR_PER_SIZE_256MB 0x000000C0 +#define EPI_ADDR_PER_BASE_NONE 0x00000000 +#define EPI_ADDR_PER_BASE_A 0x00000010 +#define EPI_ADDR_PER_BASE_C 0x00000020 +#define EPI_ADDR_RAM_SIZE_256B 0x00000000 +#define EPI_ADDR_RAM_SIZE_64KB 0x00000004 +#define EPI_ADDR_RAM_SIZE_16MB 0x00000008 +#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C +#define EPI_ADDR_RAM_BASE_NONE 0x00000000 +#define EPI_ADDR_RAM_BASE_6 0x00000001 +#define EPI_ADDR_RAM_BASE_8 0x00000002 + +//***************************************************************************** +// +// Values that can be passed to EPINonBlockingReadConfigure() +// +//***************************************************************************** +#define EPI_NBCONFIG_SIZE_8 1 +#define EPI_NBCONFIG_SIZE_16 2 +#define EPI_NBCONFIG_SIZE_32 3 + +//***************************************************************************** +// +// Values that can be passed to EPIFIFOConfig() +// +//***************************************************************************** +#define EPI_FIFO_CONFIG_WTFULLERR 0x00020000 +#define EPI_FIFO_CONFIG_RSTALLERR 0x00010000 +#define EPI_FIFO_CONFIG_TX_EMPTY 0x00000000 +#define EPI_FIFO_CONFIG_TX_1_4 0x00000020 +#define EPI_FIFO_CONFIG_TX_1_2 0x00000030 +#define EPI_FIFO_CONFIG_TX_3_4 0x00000040 +#define EPI_FIFO_CONFIG_RX_1_8 0x00000001 +#define EPI_FIFO_CONFIG_RX_1_4 0x00000002 +#define EPI_FIFO_CONFIG_RX_1_2 0x00000003 +#define EPI_FIFO_CONFIG_RX_3_4 0x00000004 +#define EPI_FIFO_CONFIG_RX_7_8 0x00000005 +#define EPI_FIFO_CONFIG_RX_FULL 0x00000006 + +//***************************************************************************** +// +// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned +// as flags from EPIIntStatus() +// +//***************************************************************************** +#define EPI_INT_TXREQ 0x00000004 +#define EPI_INT_RXREQ 0x00000002 +#define EPI_INT_ERR 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EPIIntErrorClear(), or returned as flags from +// EPIIntErrorStatus() +// +//***************************************************************************** +#define EPI_INT_ERR_WTFULL 0x00000004 +#define EPI_INT_ERR_RSTALL 0x00000002 +#define EPI_INT_ERR_TIMEOUT 0x00000001 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void EPIModeSet(unsigned long ulBase, unsigned long ulMode); +extern void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider); +extern void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulRefresh); +extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulFrameCount, + unsigned long ulMaxWait); +extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait); +extern void EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait); +extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap); +extern void EPINonBlockingReadConfigure(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulDataSize, + unsigned long ulAddress); +extern void EPINonBlockingReadStart(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulCount); +extern void EPINonBlockingReadStop(unsigned long ulBase, + unsigned long ulChannel); +extern unsigned long EPINonBlockingReadCount(unsigned long ulBase, + unsigned long ulChannel); +extern unsigned long EPINonBlockingReadAvail(unsigned long ulBase); +extern unsigned long EPINonBlockingReadGet32(unsigned long ulBase, + unsigned long ulCount, + unsigned long *pulBuf); +extern unsigned long EPINonBlockingReadGet16(unsigned long ulBase, + unsigned long ulCount, + unsigned short *pusBuf); +extern unsigned long EPINonBlockingReadGet8(unsigned long ulBase, + unsigned long ulCount, + unsigned char *pucBuf); +extern void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long EPIWriteFIFOCountGet(unsigned long ulBase); +extern void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long EPIIntErrorStatus(unsigned long ulBase); +extern void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags); +extern void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void EPIIntUnregister(unsigned long ulBase); + +//***************************************************************************** +// +// Several EPI APIs and labels have been renamed, with the original definition +// name being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#define EPI_MODE_NONE EPI_MODE_GENERAL +#define EPI_NONMODE_CLKPIN EPI_GPMODE_CLKPIN +#define EPI_NONMODE_CLKSTOP EPI_GPMODE_CLKGATE +#define EPI_NONMODE_CLKENA EPI_GPMODE_RDYEN +#define EPI_NONMODE_FRAMEPIN EPI_GPMODE_FRAMEPIN +#define EPI_NONMODE_FRAME50 EPI_GPMODE_FRAME50 +#define EPI_NONMODE_READWRITE EPI_GPMODE_READWRITE +#define EPI_NONMODE_WRITE2CYCLE EPI_GPMODE_WRITE2CYCLE +#define EPI_NONMODE_READ2CYCLE EPI_GPMODE_READ2CYCLE +#define EPI_NONMODE_ASIZE_NONE EPI_GPMODE_ASIZE_NONE +#define EPI_NONMODE_ASIZE_4 EPI_GPMODE_ASIZE_4 +#define EPI_NONMODE_ASIZE_12 EPI_GPMODE_ASIZE_12 +#define EPI_NONMODE_ASIZE_20 EPI_GPMODE_ASIZE_20 +#define EPI_NONMODE_DSIZE_8 EPI_GPMODE_DSIZE_8 +#define EPI_NONMODE_DSIZE_16 EPI_GPMODE_DSIZE_16 +#define EPI_NONMODE_DSIZE_24 EPI_GPMODE_DSIZE_24 +#define EPI_NONMODE_DSIZE_32 EPI_GPMODE_DSIZE_32 +#define EPI_NONMODE_WORD_ACCESS EPI_GPMODE_WORD_ACCESS + +#define EPINonBlockingWriteCount(a) EPIWriteFIFOCountGet(a) +#define EPIConfigNoModeSet(a, b, c, d) EPIConfigGPModeSet((a), (b), (c), (d)) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EPI_H__ diff --git a/driverlib/ethernet.c b/driverlib/ethernet.c new file mode 100644 index 0000000..e68adac --- /dev/null +++ b/driverlib/ethernet.c @@ -0,0 +1,1381 @@ +//***************************************************************************** +// +// ethernet.c - Driver for the Integrated Ethernet Controller +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ethernet_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ethernet.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/ethernet.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Initializes the Ethernet controller for operation. +//! +//! \param ulBase is the base address of the controller. +//! \param ulEthClk is the rate of the clock supplied to the Ethernet module. +//! +//! This function prepares the Ethernet controller for first-time use in +//! a given hardware/software configuration. This function should be called +//! before any other Ethernet API functions are called. +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! This function replaces the original EthernetInit() API and performs the +//! same actions. A macro is provided in ethernet.h to map the +//! original API to this API. +//! +//! \note If the device configuration is changed (for example, the system clock +//! is reprogrammed to a different speed), then the Ethernet controller must be +//! disabled by calling the EthernetDisable() function and the controller must +//! be reinitialized by calling the EthernetInitExpClk() function again. After +//! the controller has been reinitialized, the controller should be +//! reconfigured using the appropriate Ethernet API calls. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk) +{ + unsigned long ulDiv; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Set the Management Clock Divider register for access to the PHY + // register set (via EthernetPHYRead/Write). + // + // The MDC clock divided down from the system clock using the following + // formula. A maximum of 2.5MHz is allowed for F(mdc). + // + // F(mdc) = F(sys) / (2 * (div + 1)) + // div = (F(sys) / (2 * F(mdc))) - 1 + // div = (F(sys) / 2 / F(mdc)) - 1 + // + // Note: Because we should round up, to ensure we don't violate the + // maximum clock speed, we can simplify this as follows: + // + // div = F(sys) / 2 / F(mdc) + // + // For example, given a system clock of 6.0MHz, and a div value of 1, + // the mdc clock would be programmed as 1.5 MHz. + // + ulDiv = (ulEthClk / 2) / 2500000; + HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M); +} + +//***************************************************************************** +// +//! Sets the configuration of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param ulConfig is the configuration for the controller. +//! +//! After the EthernetInitExpClk() function has been called, this API function +//! can be used to configure the various features of the Ethernet controller. +//! +//! The Ethernet controller provides three control registers that are used +//! to configure the controller's operation. The transmit control register +//! provides settings to enable full-duplex operation, to auto-generate the +//! frame check sequence, and to pad the transmit packets to the minimum +//! length as required by the IEEE standard. The receive control register +//! provides settings to enable reception of packets with bad frame check +//! sequence values and to enable multi-cast or promiscuous modes. The +//! timestamp control register provides settings that enable support logic in +//! the controller that allow the use of the General Purpose Timer 3 to capture +//! timestamps for the transmitted and received packets. Note that not all +//! devices support this functionality; see the data sheet to determine if +//! this feature is supported. +//! +//! The \e ulConfig parameter is the logical OR of the following values: +//! +//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer +//! inputs +//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC +//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets) +//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets +//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode +//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation +//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size +//! +//! These bit-mapped values are programmed into the transmit, receive, and/or +//! timestamp control register. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | + ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS | + ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN | + ETH_CFG_TS_TSEN)) == 0); + + // + // Setup the Transmit Control Register. + // + ulTemp = HWREG(ulBase + MAC_O_TCTL); + ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN); + ulTemp |= ulConfig & 0x0FF; + HWREG(ulBase + MAC_O_TCTL) = ulTemp; + + // + // Setup the Receive Control Register. + // + ulTemp = HWREG(ulBase + MAC_O_RCTL); + ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL); + ulTemp |= (ulConfig >> 8) & 0x0FF; + HWREG(ulBase + MAC_O_RCTL) = ulTemp; + + // + // Setup the Time Stamp Configuration register. + // + ulTemp = HWREG(ulBase + MAC_O_TS); + ulTemp &= ~(MAC_TS_TSEN); + ulTemp |= (ulConfig >> 16) & 0x0FF; + HWREG(ulBase + MAC_O_TS) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the current configuration of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function queries the control registers of the Ethernet controller +//! and returns a bit-mapped configuration value. +//! +//! \sa The description of the EthernetConfigSet() function provides detailed +//! information for the bit-mapped configuration values that are returned. +//! +//! \return Returns the bit-mapped Ethernet controller configuration value. +// +//***************************************************************************** +unsigned long +EthernetConfigGet(unsigned long ulBase) +{ + unsigned long ulConfig; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Read and return the Ethernet controller configuration parameters, + // properly shifted into the appropriate bit field positions. + // + ulConfig = HWREG(ulBase + MAC_O_TS) << 16; + ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8; + ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN); + return(ulConfig); +} + +//***************************************************************************** +// +//! Sets the MAC address of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucMACAddr is the pointer to the array of MAC-48 address octets. +//! +//! This function programs the IEEE-defined MAC-48 address specified in +//! \e pucMACAddr into the Ethernet controller. This address is used by the +//! Ethernet controller for hardware-level filtering of incoming Ethernet +//! packets (when promiscuous mode is not enabled). +//! +//! The MAC-48 address is defined as 6 octets, illustrated by the following +//! example address. The numbers are shown in hexadecimal format. +//! +//! AC-DE-48-00-00-80 +//! +//! In this representation, the first three octets (AC-DE-48) are the +//! Organizationally Unique Identifier (OUI). This is a number assigned by +//! the IEEE to an organization that requests a block of MAC addresses. The +//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner +//! to uniquely identify a piece of hardware within that organization that is +//! to be connected to the Ethernet. +//! +//! In this representation, the octets are transmitted from left to right, +//! with the ``AC'' octet being transmitted first and the ``80'' octet being +//! transmitted last. Within an octet, the bits are transmitted LSB to MSB. +//! For this address, the first bit to be transmitted would be ``0'', the LSB +//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of +//! ``80''. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr) +{ + unsigned long ulTemp; + unsigned char *pucTemp = (unsigned char *)&ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucMACAddr != 0); + + // + // Program the MAC Address into the device. The first four bytes of the + // MAC Address are placed into the IA0 register. The remaining two bytes + // of the MAC address are placed into the IA1 register. + // + pucTemp[0] = pucMACAddr[0]; + pucTemp[1] = pucMACAddr[1]; + pucTemp[2] = pucMACAddr[2]; + pucTemp[3] = pucMACAddr[3]; + HWREG(ulBase + MAC_O_IA0) = ulTemp; + ulTemp = 0; + pucTemp[0] = pucMACAddr[4]; + pucTemp[1] = pucMACAddr[5]; + HWREG(ulBase + MAC_O_IA1) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the MAC address of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucMACAddr is the pointer to the location in which to store the +//! array of MAC-48 address octets. +//! +//! This function reads the currently programmed MAC address into the +//! \e pucMACAddr buffer. +//! +//! \sa Refer to EthernetMACAddrSet() API description for more details about +//! the MAC address format. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr) +{ + unsigned long ulTemp; + unsigned char *pucTemp = (unsigned char *)&ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucMACAddr != 0); + + // + // Read the MAC address from the device. The first four bytes of the + // MAC address are read from the IA0 register. The remaining two bytes + // of the MAC addres + // + ulTemp = HWREG(ulBase + MAC_O_IA0); + pucMACAddr[0] = pucTemp[0]; + pucMACAddr[1] = pucTemp[1]; + pucMACAddr[2] = pucTemp[2]; + pucMACAddr[3] = pucTemp[3]; + ulTemp = HWREG(ulBase + MAC_O_IA1); + pucMACAddr[4] = pucTemp[0]; + pucMACAddr[5] = pucTemp[1]; +} + +//***************************************************************************** +// +//! Enables the Ethernet controller for normal operation. +//! +//! \param ulBase is the base address of the controller. +//! +//! Once the Ethernet controller has been configured using the +//! EthernetConfigSet() function and the MAC address has been programmed using +//! the EthernetMACAddrSet() function, this API function can be called to +//! enable the controller for normal operation. +//! +//! This function enables the controller's transmitter and receiver, and +//! resets the receive FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Reset the receive FIFO. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; + + // + // Enable the Ethernet receiver. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN; + + // + // Enable Ethernet transmitter. + // + HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN; + + // + // Reset the receive FIFO again, after the receiver has been enabled. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; +} + +//***************************************************************************** +// +//! Disables the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! When terminating operations on the Ethernet interface, this function should +//! be called. This function disables the transmitter and receiver, and +//! clears out the receive FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Reset the receive FIFO. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; + + // + // Disable the Ethernet transmitter. + // + HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN); + + // + // Disable the Ethernet receiver. + // + HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN); + + // + // Reset the receive FIFO again, after the receiver has been disabled. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; +} + +//***************************************************************************** +// +//! Check for packet available from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! The Ethernet controller provides a register that contains the number of +//! packets available in the receive FIFO. When the last bytes of a packet are +//! successfully received (that is, the frame check sequence bytes), the packet +//! count is incremented. Once the packet has been fully read (including the +//! frame check sequence bytes) from the FIFO, the packet count is decremented. +//! +//! \return Returns \b true if there are one or more packets available in the +//! receive FIFO, including the current packet being read, and \b false +//! otherwise. +// +//***************************************************************************** +tBoolean +EthernetPacketAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Return the availability of packets. + // + return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false); +} + +//***************************************************************************** +// +//! Checks for packet space available in the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! The Ethernet controller's transmit FIFO is designed to support a single +//! packet at a time. After the packet has been written into the FIFO, the +//! transmit request bit must be set to enable the transmission of the packet. +//! Only after the packet has been transmitted can a new packet be written +//! into the FIFO. This function simply checks to see if a packet is +//! in progress. If so, there is no space available in the transmit FIFO. +//! +//! \return Returns \b true if a space is available in the transmit FIFO, and +//! \b false otherwise. +// +//***************************************************************************** +tBoolean +EthernetSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Return the availability of space. + // + return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true); +} + +//***************************************************************************** +// +//! \internal +//! +//! Internal function for reading a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is the maximum number of bytes to be read into the buffer. +//! +//! Based on the following table of how the receive frame is stored in the +//! receive FIFO, this function will extract a packet from the FIFO and store +//! it in the packet buffer that was passed in. +//! +//! Format of the data in the RX FIFO is as follows: +//! +//! \verbatim +//! +---------+----------+----------+----------+----------+ +//! | | 31:24 | 23:16 | 15:8 | 7:0 | +//! +---------+----------+----------+----------+----------+ +//! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB | +//! +---------+----------+----------+----------+----------+ +//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 | +//! +---------+----------+----------+----------+----------+ +//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 | +//! +---------+----------+----------+----------+----------+ +//! | ... | | | | | +//! +---------+----------+----------+----------+----------+ +//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 | +//! +---------+----------+----------+----------+----------+ +//! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 | +//! +---------+----------+----------+----------+----------+ +//! \endverbatim +//! +//! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes. +//! Where DA is Destination (MAC) Address. +//! Where SA is Source (MAC) Address. +//! Where FT is Frame Type (or Frame Length for Ethernet). +//! Where DATA is Payload Data for the Ethernet Frame. +//! Where FCS is the Frame Check Sequence. +//! +//! \return Returns the negated packet length \b -n if the packet is too large +//! for \e pucBuf, and returns the packet length \b n otherwise. +// +//***************************************************************************** +static long +EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + unsigned long ulTemp; + long lFrameLen, lTempLen; + long i = 0; + + // + // Read WORD 0 (see format above) from the FIFO, set the receive + // Frame Length and store the first two bytes of the destination + // address in the receive buffer. + // + ulTemp = HWREG(ulBase + MAC_O_DATA); + lFrameLen = (long)(ulTemp & 0xFFFF); + pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff); + pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff); + + // + // Read all but the last WORD into the receive buffer. + // + lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6); + while(i <= (lTempLen - 4)) + { + *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA); + i += 4; + } + + // + // Read the last 1, 2, or 3 BYTES into the buffer + // + if(i < lTempLen) + { + ulTemp = HWREG(ulBase + MAC_O_DATA); + if(i == lTempLen - 3) + { + pucBuf[i++] = ((ulTemp >> 0) & 0xff); + pucBuf[i++] = ((ulTemp >> 8) & 0xff); + pucBuf[i++] = ((ulTemp >> 16) & 0xff); + i += 1; + } + else if(i == lTempLen - 2) + { + pucBuf[i++] = ((ulTemp >> 0) & 0xff); + pucBuf[i++] = ((ulTemp >> 8) & 0xff); + i += 2; + } + else if(i == lTempLen - 1) + { + pucBuf[i++] = ((ulTemp >> 0) & 0xff); + i += 3; + } + } + + // + // Read any remaining WORDS (that did not fit into the buffer). + // + while(i < (lFrameLen - 2)) + { + ulTemp = HWREG(ulBase + MAC_O_DATA); + i += 4; + } + + // + // If frame was larger than the buffer, return the "negative" frame length + // + lFrameLen -= 6; + if(lFrameLen > lBufLen) + { + return(-lFrameLen); + } + + // + // Return the Frame Length + // + return(lFrameLen); +} + +//***************************************************************************** +// +//! Receives a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is the maximum number of bytes to be read into the buffer. +//! +//! This function reads a packet from the receive FIFO of the controller and +//! places it into \e pucBuf. If no packet is available the function +//! returns immediately. Otherwise, the function reads the entire packet +//! from the receive FIFO. If there are more bytes in the packet than can fit +//! into \e pucBuf (as specified by \e lBufLen), the function returns the +//! negated length of the packet and the buffer contains \e lBufLen bytes +//! of the packet. Otherwise, the function returns the length of the +//! packet that was read and \e pucBuf contains the entire packet +//! (excluding the frame check sequence bytes). +//! +//! This function replaces the original EthernetPacketNonBlockingGet() API and +//! performs the same actions. A macro is provided in ethernet.h to +//! map the original API to this API. +//! +//! \note This function returns immediately if no packet is available. +//! +//! \return Returns \b 0 if no packet is available, the negated packet length +//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n +//! otherwise. +// +//***************************************************************************** +long +EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Check to see if any packets are available. + // + if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0) + { + return(0); + } + + // + // Read the packet, and return. + // + return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! Waits for a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is the maximum number of bytes to be read into the buffer. +//! +//! This function reads a packet from the receive FIFO of the controller and +//! places it into \e pucBuf. The function waits until a packet is +//! available in the FIFO. Then the function reads the entire packet +//! from the receive FIFO. If there are more bytes in the packet than can +//! fit into \e pucBuf (as specified by \e lBufLen), the function returns +//! the negated length of the packet and the buffer contains \e lBufLen +//! bytes of the packet. Otherwise, the function returns the length of +//! the packet that was read and \e pucBuf contains the entire packet +//! (excluding the frame check sequence bytes). +//! +//! \note This function is blocking and does not return until a packet arrives. +//! +//! \return Returns the negated packet length \b -n if the packet is too large +//! for \e pucBuf, and returns the packet length \b n otherwise. +// +//***************************************************************************** +long +EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Wait for a packet to become available + // + while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0) + { + } + + // + // Read the packet + // + return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! \internal +//! +//! Internal function for sending a packet to the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is number of bytes in the packet to be transmitted. +//! +//! Puts a packet into the transmit FIFO of the controller. +//! +//! Format of the data in the TX FIFO is as follows: +//! +//! \verbatim +//! +---------+----------+----------+----------+----------+ +//! | | 31:24 | 23:16 | 15:8 | 7:0 | +//! +---------+----------+----------+----------+----------+ +//! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB | +//! +---------+----------+----------+----------+----------+ +//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 | +//! +---------+----------+----------+----------+----------+ +//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 | +//! +---------+----------+----------+----------+----------+ +//! | ... | | | | | +//! +---------+----------+----------+----------+----------+ +//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 | +//! +---------+----------+----------+----------+----------+ +//! \endverbatim +//! +//! Where PL is Payload Length, (DATA) only +//! Where DA is Destination (MAC) Address +//! Where SA is Source (MAC) Address +//! Where FT is Frame Type (or Frame Length for Ethernet) +//! Where DATA is Payload Data for the Ethernet Frame +//! +//! \return Returns the negated packet length \b -lBufLen if the packet is too +//! large for FIFO, and the packet length \b lBufLen otherwise. +// +//***************************************************************************** +static long +EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + unsigned long ulTemp; + long i = 0; + + // + // If the packet is too large, return the negative packet length as + // an error code. + // + if(lBufLen > (2048 - 2)) + { + return(-lBufLen); + } + + // + // Build and write WORD 0 (see format above) to the transmit FIFO. + // + ulTemp = (unsigned long)(lBufLen - 14); + ulTemp |= (pucBuf[i++] << 16); + ulTemp |= (pucBuf[i++] << 24); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + + // + // Write each subsequent WORD n to the transmit FIFO, except for the last + // WORD (if the word does not contain 4 bytes). + // + while(i <= (lBufLen - 4)) + { + HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i]; + i += 4; + } + + // + // Build the last word of the remaining 1, 2, or 3 bytes, and store + // the WORD into the transmit FIFO. + // + if(i != lBufLen) + { + if(i == (lBufLen - 3)) + { + ulTemp = (pucBuf[i++] << 0); + ulTemp |= (pucBuf[i++] << 8); + ulTemp |= (pucBuf[i++] << 16); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + } + else if(i == (lBufLen - 2)) + { + ulTemp = (pucBuf[i++] << 0); + ulTemp |= (pucBuf[i++] << 8); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + } + else if(i == (lBufLen - 1)) + { + ulTemp = (pucBuf[i++] << 0); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + } + } + + // + // Activate the transmitter + // + HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX; + + // + // Return the Buffer Length transmitted. + // + return(lBufLen); +} + +//***************************************************************************** +// +//! Sends a packet to the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is number of bytes in the packet to be transmitted. +//! +//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf +//! into the transmit FIFO of the controller and then activates the +//! transmitter for this packet. If no space is available in the FIFO, the +//! function returns immediately. If space is available, the +//! function returns once \e lBufLen bytes of the packet have been placed +//! into the FIFO and the transmitter has been started. The function does not +//! wait for the transmission to complete. The function returns the +//! negated \e lBufLen if the length is larger than the space available in +//! the transmit FIFO. +//! +//! This function replaces the original EthernetPacketNonBlockingPut() API and +//! performs the same actions. A macro is provided in ethernet.h to +//! map the original API to this API. +//! +//! \note This function does not block and returns immediately if no space +//! is available for the transmit packet. +//! +//! \return Returns \b 0 if no space is available in the transmit FIFO, the +//! negated packet length \b -lBufLen if the packet is too large for FIFO, and +//! the packet length \b lBufLen otherwise. +// +//***************************************************************************** +long +EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Check if the transmit FIFO is in use and return the appropriate code. + // + if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) + { + return(0); + } + + // + // Send the packet and return. + // + return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! Waits to send a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is number of bytes in the packet to be transmitted. +//! +//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf +//! into the transmit FIFO of the controller and then activates the transmitter +//! for this packet. This function waits until the transmit FIFO is empty. +//! Once space is available, the function returns once \e lBufLen bytes of +//! the packet have been placed into the FIFO and the transmitter has been +//! started. The function does not wait for the transmission to complete. The +//! function returns the negated \e lBufLen if the length is larger than +//! the space available in the transmit FIFO. +//! +//! \note This function blocks and waits until space is available for the +//! transmit packet before returning. +//! +//! \return Returns the negated packet length \b -lBufLen if the packet is too +//! large for FIFO, and the packet length \b lBufLen otherwise. +// +//***************************************************************************** +long +EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Wait for current packet (if any) to complete. + // + while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) + { + } + + // + // Send the packet and return. + // + return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for an Ethernet interrupt. +//! +//! \param ulBase is the base address of the controller. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled Ethernet interrupts occur. +//! +//! This function sets the handler to be called when the Ethernet interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific Ethernet interrupts must be enabled via +//! EthernetIntEnable(). It is the interrupt handler's responsibility to clear +//! the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_ETH, pfnHandler); + + // + // Enable the Ethernet interrupt. + // + IntEnable(INT_ETH); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for an Ethernet interrupt. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller so that the interrupt +//! handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_ETH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_ETH); +} + +//***************************************************************************** +// +//! Enables individual Ethernet interrupt sources. +//! +//! \param ulBase is the base address of the controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated Ethernet interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated +//! PHY supports a number of interrupt conditions. The appropriate PHY +//! register, PHY_MR17 or PHY_MR29 depending on the device class, must be read +//! to determine which PHY interrupt has occurred. This register can be read +//! using the EthernetPHYRead() API function. +//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the +//! management interface has completed successfully. +//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred +//! during reception of a frame. This error can indicate a length mismatch, a +//! CRC failure, or an error indication from the PHY. +//! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received +//! that exceeds the available space in the RX FIFO. +//! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX +//! FIFO has been successfully transmitted. +//! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred +//! during the transmission of a packet. This error can be either a retry +//! failure during the back-off process, or an invalid length stored in the TX +//! FIFO. +//! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are +//! available in the RX FIFO for processing. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX))); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + MAC_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual Ethernet interrupt sources. +//! +//! \param ulBase is the base address of the controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated Ethernet interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to EthernetIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX))); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current Ethernet interrupt status. +//! +//! \param ulBase is the base address of the controller. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the Ethernet controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in EthernetIntEnable(). +// +//***************************************************************************** +unsigned long +EthernetIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Read the unmasked status. + // + ulStatus = HWREG(ulBase + MAC_O_RIS); + + // + // If masked status is requested, mask it off. + // + if(bMasked) + { + ulStatus &= HWREG(ulBase + MAC_O_IM); + } + + // + // Return the interrupt status value. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Clears Ethernet interrupt sources. +//! +//! \param ulBase is the base address of the controller. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified Ethernet interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to EthernetIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX))); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + MAC_O_IACK) = ulIntFlags; +} + +//***************************************************************************** +// +//! Sets the PHY address. +//! +//! \param ulBase is the base address of the controller. +//! \param ucAddr is the address of the PHY. +//! +//! This function sets the address of the PHY that is accessed via +//! EthernetPHYRead() and EthernePHYWrite(). This configuration is only needed +//! when connecting to an external PHY via MII, and should not be used on +//! devices that have integrated PHYs. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Wait for any pending transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Set the PHY address. + // + HWREG(ulBase + MAC_O_MADD) = ucAddr; +} + +//***************************************************************************** +// +//! Writes to the PHY register. +//! +//! \param ulBase is the base address of the controller. +//! \param ucRegAddr is the address of the PHY register to be accessed. +//! \param ulData is the data to be written to the PHY register. +//! +//! This function writes the \e ulData to the PHY register specified by +//! \e ucRegAddr. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, + unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Wait for any pending transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Program the DATA to be written. + // + HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M; + + // + // Program the PHY register address and initiate the transaction. + // + HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) | + MAC_MCTL_WRITE | MAC_MCTL_START); + + // + // Wait for the write transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } +} + +//***************************************************************************** +// +//! Reads from a PHY register. +//! +//! \param ulBase is the base address of the controller. +//! \param ucRegAddr is the address of the PHY register to be accessed. +//! +//! This function returns the contents of the PHY register specified by +//! \e ucRegAddr. +//! +//! \return Returns the 16-bit value read from the PHY. +// +//***************************************************************************** +unsigned long +EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Wait for any pending transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Program the PHY register address and initiate the transaction. + // + HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) | + MAC_MCTL_START); + + // + // Wait for the transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Return the PHY data that was read. + // + return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M); +} + +//***************************************************************************** +// +//! Powers off the Ethernet PHY. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function powers off the Ethernet PHY, reducing the current +//! consumption of the device. While in the powered off state, the Ethernet +//! controller is unable to connect to the Ethernet. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYPowerOff(unsigned long ulBase) +{ + // + // Set the PWRDN bit and clear the ANEGEN bit in the PHY, putting it into + // its low power mode. + // + EthernetPHYWrite(ulBase, PHY_MR0, + (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_ANEGEN) | + PHY_MR0_PWRDN); +} + +//***************************************************************************** +// +//! Powers on the Ethernet PHY. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function powers on the Ethernet PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function is only +//! called if EthernetPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYPowerOn(unsigned long ulBase) +{ + // + // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into + // normal operating mode. + // + EthernetPHYWrite(ulBase, PHY_MR0, + (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_PWRDN) | + PHY_MR0_ANEGEN); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/ethernet.h b/driverlib/ethernet.h new file mode 100644 index 0000000..e60752b --- /dev/null +++ b/driverlib/ethernet.h @@ -0,0 +1,187 @@ +//***************************************************************************** +// +// ethernet.h - Defines and Macros for the ethernet module. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ETHERNET_H__ +#define __ETHERNET_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EthernetConfigSet as the ulConfig value, and +// returned from EthernetConfigGet. +// +//***************************************************************************** +#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP) +#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets +#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous +#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast +#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode +#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation +#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding + +//***************************************************************************** +// +// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and +// EthernetIntClear as the ulIntFlags parameter, and returned from +// EthernetIntStatus. +// +//***************************************************************************** +#define ETH_INT_PHY 0x040 // PHY Event/Interrupt +#define ETH_INT_MDIO 0x020 // Management Transaction +#define ETH_INT_RXER 0x010 // RX Error +#define ETH_INT_RXOF 0x008 // RX FIFO Overrun +#define ETH_INT_TX 0x004 // TX Complete +#define ETH_INT_TXER 0x002 // TX Error +#define ETH_INT_RX 0x001 // RX Complete + +//***************************************************************************** +// +// Helper Macros for Ethernet Processing +// +//***************************************************************************** +// +// htonl/ntohl - big endian/little endian byte swapping macros for +// 32-bit (long) values +// +//***************************************************************************** +#ifndef htonl + #define htonl(a) \ + ((((a) >> 24) & 0x000000ff) | \ + (((a) >> 8) & 0x0000ff00) | \ + (((a) << 8) & 0x00ff0000) | \ + (((a) << 24) & 0xff000000)) +#endif + +#ifndef ntohl + #define ntohl(a) htonl((a)) +#endif + +//***************************************************************************** +// +// htons/ntohs - big endian/little endian byte swapping macros for +// 16-bit (short) values +// +//***************************************************************************** +#ifndef htons + #define htons(a) \ + ((((a) >> 8) & 0x00ff) | \ + (((a) << 8) & 0xff00)) +#endif + +#ifndef ntohs + #define ntohs(a) htons((a)) +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk); +extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long EthernetConfigGet(unsigned long ulBase); +extern void EthernetMACAddrSet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetMACAddrGet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetEnable(unsigned long ulBase); +extern void EthernetDisable(unsigned long ulBase); +extern tBoolean EthernetPacketAvail(unsigned long ulBase); +extern tBoolean EthernetSpaceAvail(unsigned long ulBase); +extern long EthernetPacketGetNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPutNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern void EthernetIntRegister(unsigned long ulBase, + void (*pfnHandler)(void)); +extern void EthernetIntUnregister(unsigned long ulBase); +extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr); +extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, + unsigned long ulData); +extern unsigned long EthernetPHYRead(unsigned long ulBase, + unsigned char ucRegAddr); +extern void EthernetPHYPowerOff(unsigned long ulBase); +extern void EthernetPHYPowerOn(unsigned long ulBase); + +//***************************************************************************** +// +// Several Ethernet APIs have been renamed, with the original function name +// being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define EthernetInit(a) \ + EthernetInitExpClk(a, SysCtlClockGet()) +#define EthernetPacketNonBlockingGet(a, b, c) \ + EthernetPacketGetNonBlocking(a, b, c) +#define EthernetPacketNonBlockingPut(a, b, c) \ + EthernetPacketPutNonBlocking(a, b, c) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ETHERNET_H__ diff --git a/driverlib/ewarm-cm3/Exe/driverlib-cm3.a b/driverlib/ewarm-cm3/Exe/driverlib-cm3.a new file mode 100644 index 0000000..260024f Binary files /dev/null and b/driverlib/ewarm-cm3/Exe/driverlib-cm3.a differ diff --git a/driverlib/ewarm-cm4f/Exe/driverlib-cm4f.a b/driverlib/ewarm-cm4f/Exe/driverlib-cm4f.a new file mode 100644 index 0000000..ac42bbd Binary files /dev/null and b/driverlib/ewarm-cm4f/Exe/driverlib-cm4f.a differ diff --git a/driverlib/fan.c b/driverlib/fan.c new file mode 100644 index 0000000..c25a0fd --- /dev/null +++ b/driverlib/fan.c @@ -0,0 +1,649 @@ +//***************************************************************************** +// +// fan.c - Driver for the FAN controller. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_fan.h" +#include "inc/hw_ints.h" +#include "driverlib/fan.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! \addtogroup fan_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enables a FAN channel for operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to enable. +//! +//! This function enables the specified FAN channel for operation. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + // + // Enable the requested channel + // + HWREG(ulBase + FAN_O_CTL) |= 1 << ulChannel; +} + +//***************************************************************************** +// +//! Disables a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to disable. +//! +//! This function disables the specified FAN channel for operation. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + // + // Disable the requested channel + // + HWREG(ulBase + FAN_O_CTL) &= ~(1 << ulChannel); +} + +//***************************************************************************** +// +//! Gets the status of a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to query for status. +//! +//! This function queries and returns the status of the specified channel. +//! The returned value is one of: +//! +//! - \b FAN_STATUS_STALLED if the cooling fan is stalled +//! - \b FAN_STATUS_CHANGING if the fan is changing to the commanded speed +//! - \b FAN_STATUS_LOCKED if the fan is locked at the commanded speed +//! - \b FAN_STATUS_NOATTAIN if the fan cannot achieve the commanded speed +//! +//! \return Returns the status of the specified FAN channel. +// +//***************************************************************************** +unsigned long +FanChannelStatus(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + // + // Read and return the status for the specified fan channel + // + return((HWREG(ulBase + FAN_O_STS) >> (ulChannel * 2)) & FAN_STS_ST0_M); +} + +//***************************************************************************** +// +//! Configures a FAN channel for manual operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to configure. +//! \param ulConfig is the logical OR of manual configuration flags. +//! +//! This function configures a specific FAN channel to operate in manual +//! mode. The \e ulConfig parameter is the logical OR of several choices of +//! configuration flags as follows: +//! +//! One of the following to select the number of tachometer pulses used for +//! speed averaging: +//! +//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging +//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging +//! +//! One of the following to select the tachometer pulses per revolution: +//! +//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution +//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution +//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution +//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + // + // Program the fan channel for manual mode with parameters. + // + HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = FAN_CH0_MAN | ulConfig; +} + +//***************************************************************************** +// +//! Configures a FAN channel for automatic operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to configure. +//! \param ulConfig is the logical OR of configuration flags. +//! +//! This function configures a specific FAN channel to operate in automatic +//! mode. The \e ulConfig parameter is the logical OR of several choices of +//! configuration flags as follows: +//! +//! One of the following to select the automatic restart mode: +//! +//! - \b FAN_CONFIG_RESTART to enable automatic restart after stall +//! - \b FAN_CONFIG_NORESTART to disable automatic restart after stall +//! +//! One of the following to select the acceleration rate when changing speed: +//! +//! - \b FAN_CONFIG_ACCEL_FAST to select fast acceleration +//! - \b FAN_CONFIG_ACCEL_SLOW to select slow acceleration +//! +//! One of the following to select the number of tachometer pulses to use +//! for the hysteresis count: +//! \b FAN_CONFIG_HYST_1, \b FAN_CONFIG_HYST_2, \b FAN_CONFIG_HYST_4, +//! \b FAN_CONFIG_HYST_8, \b FAN_CONFIG_HYST_16, \b FAN_CONFIG_HYST_32, +//! \b FAN_CONFIG_HYST_64, or \b FAN_CONFIG_HYST_128 +//! +//! One of the following to select the start period as the number of tachometer +//! pulses. The start period is the amount of time that a starting PWM duty +//! cycle is used after the FAN channel is commended to a certain speed: +//! \b FAN_CONFIG_START_2, \b FAN_CONFIG_START_4, \b FAN_CONFIG_START_8, +//! \b FAN_CONFIG_START_16, \b FAN_CONFIG_START_32, \b FAN_CONFIG_START_64, +//! \b FAN_CONFIG_START_128, or \b FAN_CONFIG_START_256 +//! +//! One of the following to specify the duty cycle that is used when the FAN +//! channel is starting, during the starting period (above): +//! +//! - \b FAN_CONFIG_START_DUTY_OFF to disable the use of startup duty cycle +//! - \b FAN_CONFIG_START_DUTY_50 to select 50% startup duty cycle +//! - \b FAN_CONFIG_START_DUTY_75 to select 75% startup duty cycle +//! - \b FAN_CONFIG_START_DUTY_100 to select 100% startup duty cycle +//! +//! One of the following to select the number of tachometer pulses used for +//! speed averaging: +//! +//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging +//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging +//! +//! One of the following to select the tachometer pulses per revolution: +//! +//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution +//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution +//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution +//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + // + // Program the fan channel for automatic mode with parameters. + // + HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = ~FAN_CH0_MAN & ulConfig; +} + +//***************************************************************************** +// +//! Sets the duty cycle of a FAN channel when in manual mode. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to program the duty cycle. +//! \param ulDuty is the duty cycle in clocks from 0-511. +//! +//! This function sets the duty cycle of a FAN channel if the channel is +//! configured for manual mode. The duty cycle is specified in clocks from +//! 0-511 out of a 512-clock PWM period. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDuty) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + ASSERT(ulDuty < 512); + + // + // Program the specified duty cycle for the specified channel + // + HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) = + (ulDuty << FAN_CMD0_DC_S) & FAN_CMD0_DC_M; +} + +//***************************************************************************** +// +//! Reads the duty cycle of a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to query for duty cycle. +//! +//! This function reads the duty cycle of a FAN channel. If the channel is in +//! manual mode, then this is the value that was programmed. If the FAN +//! channel is configured for automatic mode, then this is the value that is +//! calculated by the Fan Control peripheral. +//! +//! \return Returns the FAN channel duty cycle as a number of clocks from +//! 0-511, out of a 512-clock PWM period. +// +//***************************************************************************** +unsigned long +FanChannelDutyGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulDuty; + + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + // + // Read the duty cycle field from the command register and shift to + // lower bits for return value. + // + ulDuty = HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) & FAN_CMD0_DC_M; + ulDuty >>= FAN_CMD0_DC_S; + + // + // Return the duty cycle for the specified channel. + // + return(ulDuty); +} + +//***************************************************************************** +// +//! Sets the RPM of a FAN channel when in automatic mode. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to program the RPM. +//! \param ulRPM is the RPM as a value from 0-8191. +//! +//! This function sets the RPM of the fan channel if the fan channel is +//! configured for automatic mode. If configured for manual mode, then this +//! function has no effect. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulRPM) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + ASSERT(ulRPM < 8192); + + // + // Program the specified RPM for the specified channel + // + HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) = ulRPM; +} + +//***************************************************************************** +// +//! Reads the RPM of a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to query for RPM. +//! +//! This function reads the RPM of a FAN channel. +//! +//! \return Returns the FAN channel RPM as a number from 0-4095. +// +//***************************************************************************** +unsigned long +FanChannelRPMGet(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel < 6); + + + // + // Read and return the RPM for the specified channel. + // + return(HWREG(ulBase + FAN_O_CST0 + (ulChannel * 0x10)) & FAN_CST0_RPM_M); +} + +//***************************************************************************** +// +//! Enables FAN module interrupts. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulFlags is the logical OR of all the interrupts to be enabled. +//! +//! This function enables one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be enabled. For each channel, the following interrupt flags are +//! available: +//! +//! - \b FAN_CHn_INT_STALL means that a stall was detected (in either mode). +//! - \b FAN_CHn_INT_AUTO_SPEED_ERROR means that in automatic mode, the cooling +//! fan cannot attain the commanded speed. +//! - \b FAN_CHn_INT_AUTO_SPEED_OK means that in automatic mode, the cooling +//! fan has attained the commanded speed. +//! +//! The interrupt flags have a different meaning if the FAN channel is +//! configured for manual mode. The following alternate set of flag names is +//! available for convenience to use in manual mode: +//! +//! - \b FAN_CHn_INT_MANUAL_SPEED_UPDATE means that in manual mode, the speed +//! was calculated. +//! - \b FAN_CHn_INT_MANUAL_SPEED_CHANGE means that in manual mode, the speed +//! changed. +//! +//! In the above flag names, the \b CHn placeholder should be replaced with +//! the actual channel number, 0-5 (for example, CH1). +//! +//! Note that even though the names are different for manual mode, the values +//! are the same. For example \b _AUTO_SPEED_ERROR is the same value as +//! \b _MANUAL_SPEED_UPDATE. The different names are provided just to make it +//! easier to associate a meaning with each interrupt flag. +//! +//! \return None. +// +//***************************************************************************** +void +FanIntEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Enable the requested interrupt sources. + // + HWREG(ulBase + FAN_O_IM) |= ulFlags; +} + +//***************************************************************************** +// +//! Disables FAN module interrupts. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulFlags is the logical OR of all the interrupts to be disabled. +//! +//! This function disables one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be enabled. For a list of possible interrupt flags, refer to the +//! documentation for the function FanIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +FanIntDisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Disable the requested interrupt sources. + // + HWREG(ulBase + FAN_O_IM) &= ~ulFlags; +} + +//***************************************************************************** +// +//! Gets the FAN module interrupt status. +//! +//! \param ulBase is the base address of the FAN module. +//! \param bMasked is \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the interrupt status of the FAN module. It can +//! return either the raw or masked interrupt status. +//! +//! \return Returns the masked or raw FAN interrupt status, as a bit field +//! of multiple FAN interrupt flags. For a list of all the possible interrupt +//! flags, refer to the documentation for the function FanIntEnable(). +// +//***************************************************************************** +unsigned long +FanIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + FAN_O_MIS)); + } + else + { + return(HWREG(ulBase + FAN_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears pending FAN module interrupts. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulFlags is the logical OR of all the interrupts to be cleared. +//! +//! This function clears one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be cleared. For a list of possible interrupt flags, refer to the +//! documentation for the function FanIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +FanIntClear(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Clear the requested pending interrupts + // + HWREG(ulBase + FAN_O_IC) = ulFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the FAN module. +//! +//! \param ulBase is the base address of the FAN module. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function registers and enables the handler to be called when the FAN +//! module generates an interrupt. Specific FAN interrupts must still be +//! enabled with the FanIntEnable() function. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_FAN0, pfnHandler); + + // + // Enable the FAN peripheral interrupt. + // + IntEnable(INT_FAN0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the FAN module. +//! +//! \param ulBase is the base address of the FAN module. +//! +//! This function unregisters and clears the handler to be called when the +//! FAN module interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FanIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Disable the FAN peripheral interrupt. + // + IntDisable(INT_FAN0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FAN0); +} + +//***************************************************************************** +// +//! Gets the number of supported FAN channels. +//! +//! \param ulBase is the base address of the FAN module. +//! +//! This function gets the number of FAN channels that are supported by the +//! Fan Control peripheral. +//! +//! \return Returns the number of FAN channels. +// +//***************************************************************************** +unsigned long +FanChannelsGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Read and return the fan channel count + // + return(HWREG(ulBase + FAN_O_PP) & FAN_PP_CHAN_M); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/fan.h b/driverlib/fan.h new file mode 100644 index 0000000..08fc1f5 --- /dev/null +++ b/driverlib/fan.h @@ -0,0 +1,216 @@ +//***************************************************************************** +// +// fan.h - Prototypes and macros for the Fan controller. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FAN_H__ +#define __FAN_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Fan status values that can be returned from the FanChannelStatus() function. +// +//***************************************************************************** +#define FAN_STATUS_STALLED 0 +#define FAN_STATUS_CHANGING 1 +#define FAN_STATUS_LOCKED 2 +#define FAN_STATUS_NOATTAIN 3 + +//***************************************************************************** +// +// Configuration flags to be used with FanChannelConfigManual() and +// FanChannelConfigAuto(). +// +//***************************************************************************** +#define FAN_CONFIG_RESTART (1 << 15) +#define FAN_CONFIG_NORESTART (0 << 15) +#define FAN_CONFIG_ACCEL_FAST (1 << 14) +#define FAN_CONFIG_ACCEL_SLOW (0 << 14) +#define FAN_CONFIG_HYST_1 (0 << 11) +#define FAN_CONFIG_HYST_2 (1 << 11) +#define FAN_CONFIG_HYST_4 (2 << 11) +#define FAN_CONFIG_HYST_8 (3 << 11) +#define FAN_CONFIG_HYST_16 (4 << 11) +#define FAN_CONFIG_HYST_32 (5 << 11) +#define FAN_CONFIG_HYST_64 (6 << 11) +#define FAN_CONFIG_HYST_128 (7 << 11) +#define FAN_CONFIG_START_2 (0 << 8) +#define FAN_CONFIG_START_4 (1 << 8) +#define FAN_CONFIG_START_8 (2 << 8) +#define FAN_CONFIG_START_16 (3 << 8) +#define FAN_CONFIG_START_32 (4 << 8) +#define FAN_CONFIG_START_64 (5 << 8) +#define FAN_CONFIG_START_128 (6 << 8) +#define FAN_CONFIG_START_256 (7 << 8) +#define FAN_CONFIG_START_DUTY_OFF \ + (0 << 6) +#define FAN_CONFIG_START_DUTY_50 \ + (1 << 6) +#define FAN_CONFIG_START_DUTY_75 \ + (2 << 6) +#define FAN_CONFIG_START_DUTY_100 \ + (3 << 6) +#define FAN_CONFIG_AVG_NONE (0 << 4) +#define FAN_CONFIG_AVG_2 (1 << 4) +#define FAN_CONFIG_AVG_4 (2 << 4) +#define FAN_CONFIG_AVG_8 (3 << 4) +#define FAN_CONFIG_TACH_1 (0 << 2) +#define FAN_CONFIG_TACH_2 (1 << 2) +#define FAN_CONFIG_TACH_4 (2 << 2) +#define FAN_CONFIG_TACH_8 (3 << 2) + +//***************************************************************************** +// +// Interrupt configuration/status flags to be used with the following +// functions: FanIntEnable(), FanIntDisable(), FanIntStatus(), FanIntClear(). +// +//***************************************************************************** +#define FAN_CH5_INT_AUTO_SPEED_OK \ + (1 << 22) +#define FAN_CH5_INT_MANUAL_SPEED_CHANGE \ + (1 << 22) +#define FAN_CH5_INT_AUTO_SPEED_ERROR \ + (1 << 21) +#define FAN_CH5_INT_MANUAL_SPEED_UPDATE \ + (1 << 21) +#define FAN_CH5_INT_STALL (1 << 20) +#define FAN_CH4_INT_AUTO_SPEED_OK \ + (1 << 18) +#define FAN_CH4_INT_MANUAL_SPEED_CHANGE \ + (1 << 18) +#define FAN_CH4_INT_AUTO_SPEED_ERROR \ + (1 << 17) +#define FAN_CH4_INT_MANUAL_SPEED_UPDATE \ + (1 << 17) +#define FAN_CH4_INT_STALL (1 << 16) +#define FAN_CH3_INT_AUTO_SPEED_OK \ + (1 << 14) +#define FAN_CH3_INT_MANUAL_SPEED_CHANGE \ + (1 << 14) +#define FAN_CH3_INT_AUTO_SPEED_ERROR \ + (1 << 13) +#define FAN_CH3_INT_MANUAL_SPEED_UPDATE \ + (1 << 13) +#define FAN_CH3_INT_STALL (1 << 12) +#define FAN_CH2_INT_AUTO_SPEED_OK \ + (1 << 10) +#define FAN_CH2_INT_MANUAL_SPEED_CHANGE \ + (1 << 10) +#define FAN_CH2_INT_AUTO_SPEED_ERROR \ + (1 << 9) +#define FAN_CH2_INT_MANUAL_SPEED_UPDATE \ + (1 << 9) +#define FAN_CH2_INT_STALL (1 << 8) +#define FAN_CH1_INT_AUTO_SPEED_OK \ + (1 << 6) +#define FAN_CH1_INT_MANUAL_SPEED_CHANGE \ + (1 << 6) +#define FAN_CH1_INT_AUTO_SPEED_ERROR \ + (1 << 5) +#define FAN_CH1_INT_MANUAL_SPEED_UPDATE \ + (1 << 5) +#define FAN_CH1_INT_STALL (1 << 4) +#define FAN_CH0_INT_AUTO_SPEED_OK \ + (1 << 2) +#define FAN_CH0_INT_MANUAL_SPEED_CHANGE \ + (1 << 2) +#define FAN_CH0_INT_AUTO_SPEED_ERROR \ + (1 << 1) +#define FAN_CH0_INT_MANUAL_SPEED_UPDATE \ + (1 << 1) +#define FAN_CH0_INT_STALL (1 << 0) +#define FAN_CHx_INT_AUTO_SPEED_OK(x) \ + (1 << (((x) * 4) + 2)) +#define FAN_CHx_INT_MANUAL_SPEED_CHANGE(x) \ + (1 << (((x) * 4) + 2)) +#define FAN_CHx_INT_AUTO_SPEED_ERROR(x) \ + (1 << (((x) * 4) + 1)) +#define FAN_CHx_INT_MANUAL_SPEED_UPDATE(x) \ + (1 << (((x) * 4) + 1)) +#define FAN_CHx_INT_STALL(x) (1 << ((x) * 4)) + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void FanChannelEnable(unsigned long ulBase, unsigned long ulChannel); +extern void FanChannelDisable(unsigned long ulBase, unsigned long ulChannel); +extern unsigned long FanChannelStatus(unsigned long ulBase, + unsigned long ulChannel); +extern void FanChannelConfigManual(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig); +extern void FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig); +extern void FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDuty); +extern unsigned long FanChannelDutyGet(unsigned long ulBase, + unsigned long ulChannel); +extern void FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulRPM); +extern unsigned long FanChannelRPMGet(unsigned long ulBase, + unsigned long ulChannel); +extern void FanIntEnable(unsigned long ulBase, unsigned long ulFlags); +extern void FanIntDisable(unsigned long ulBase, unsigned long ulFlags); +extern unsigned long FanIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void FanIntClear(unsigned long ulBase, unsigned long ulFlags); +extern void FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void FanIntUnregister(unsigned long ulBase); +extern unsigned long FanChannelsGet(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FAN_H__ diff --git a/driverlib/flash.c b/driverlib/flash.c new file mode 100644 index 0000000..9832890 --- /dev/null +++ b/driverlib/flash.c @@ -0,0 +1,929 @@ +//***************************************************************************** +// +// flash.c - Driver for programming the on-chip flash. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_flash.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Program Enable (FMPPE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPPERegs[] = +{ + FLASH_FMPPE, + FLASH_FMPPE1, + FLASH_FMPPE2, + FLASH_FMPPE3 +}; + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Read Enable (FMPRE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPRERegs[] = +{ + FLASH_FMPRE, + FLASH_FMPRE1, + FLASH_FMPRE2, + FLASH_FMPRE3 +}; + +//***************************************************************************** +// +//! Gets the number of processor clocks per micro-second. +//! +//! This function returns the number of clocks per micro-second, as presently +//! known by the flash controller. This function is only valid on Sandstorm- +//! and Fury-class devices. +//! +//! \return Returns the number of processor clocks per micro-second. +// +//***************************************************************************** +unsigned long +FlashUsecGet(void) +{ + // + // Return the number of clocks per micro-second. + // + return(HWREG(FLASH_USECRL) + 1); +} + +//***************************************************************************** +// +//! Sets the number of processor clocks per micro-second. +//! +//! \param ulClocks is the number of processor clocks per micro-second. +//! +//! This function is used to tell the flash controller the number of processor +//! clocks per micro-second. This value must be programmed correctly or the +//! flash most likely will not program correctly; it has no affect on reading +//! flash. This function is only valid on Sandstorm- and Fury-class devices. +//! +//! \return None. +// +//***************************************************************************** +void +FlashUsecSet(unsigned long ulClocks) +{ + // + // Set the number of clocks per micro-second. + // + HWREG(FLASH_USECRL) = ulClocks - 1; +} + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function erases a 1-kB block of the on-chip flash. After erasing, +//! the block is filled with 0xFF bytes. Read-only and execute-only blocks +//! cannot be erased. +//! +//! This function does not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +long +FlashErase(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_ERMISC); + + // + // Erase the block. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; + + // + // Wait until the block has been erased. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) + { + } + + // + // Return an error if an access violation or erase error occurred. + // + if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_ERRIS)) + { + return(-1); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function programs a sequence of words into the on-chip flash. +//! Each word in a page of flash can only be programmed one time between an +//! erase of that page; programming a word multiple times results in an +//! unpredictable value in that word of flash. +//! +//! Because the flash is programmed one word at a time, the starting address +//! and byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function does not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +long +FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC); + + // + // See if this device has a write buffer. + // + if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB) + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Set the address of this block of words. + // + HWREG(FLASH_FMA) = ulAddress & ~(0x7f); + + // + // Loop over the words in this 32-word block. + // + while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) && + (ulCount != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF; + + // + // Wait until the write buffer has been programmed. + // + while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF) + { + } + } + } + else + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Program the next word. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMD) = *pulData; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE) + { + } + + // + // Increment to the next word. + // + pulData++; + ulAddress += 4; + ulCount -= 4; + } + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)) + { + return(-1); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be queried. +//! +//! This function gets the current protection for the specified 2-kB block +//! of flash. Each block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +tFlashProtection +FlashProtectGet(unsigned long ulAddress) +{ + unsigned long ulFMPRE, ulFMPPE; + unsigned long ulBank; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + + // + // Calculate the Flash Bank from Base Address, and mask off the Bank + // from ulAddress for subsequent reference. + // + ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4); + ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1); + + // + // Read the appropriate flash protection registers for the specified + // flash bank. + // + ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]); + ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]); + + // + // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper + // bits of the FMPPE register are used for JTAG protect options, and are + // not available for the FLASH protection scheme. When Querying Block + // Protection, assume these bits are 1. + // + if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2)) + { + ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30); + } + + // + // Check the appropriate protection bits for the block of memory that + // is specified by the address. + // + switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (that is, it can not be erased + // or programmed, and the only reads allowed are via the instruction + // fetch interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (that is, it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function sets the protection for the specified 2-kB block of +//! flash. Blocks that are read/write can be made read-only or execute-only. +//! Blocks that are read-only can be made execute-only. Blocks that are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (that is, read-only to read/write) +//! result in a failure (and are prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This protocol allows the application to be executed in the desired flash +//! protection environment to check for inappropriate flash access (via the +//! flash interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +long +FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) +{ + unsigned long ulProtectRE, ulProtectPE; + unsigned long ulBank; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ulAddress /= FLASH_PROTECT_SIZE; + + // + // ulAddress contains a "raw" block number. Derive the Flash Bank from + // the "raw" block number, and convert ulAddress to a "relative" + // block number. + // + ulBank = ((ulAddress / 32) % 4); + ulAddress %= 32; + + // + // Get the current protection for the specified flash bank. + // + ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]); + ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]); + + // + // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper + // bits of the FMPPE register are used for JTAG protect options, and are + // not available for the FLASH protection scheme. When setting protection, + // check to see if block 30 or 31 and protection is FlashExecuteOnly. If + // so, return an error condition. + // + if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2)) + { + if((ulAddress >= 30) && (eProtect == FlashExecuteOnly)) + { + return(-1); + } + } + + // + // Set the protection based on the requested proection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) + { + return(-1); + } + + // + // Make this block read only. + // + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) || + (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper + // bits of the FMPPE register are used for JTAG options, and are not + // available for the FLASH protection scheme. When setting block + // protection, ensure that these bits are not altered. + // + if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2)) + { + ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30); + ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) & + (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30)); + } + + // + // Set the new protection for the specified flash bank. + // + HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE; + HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function makes the currently programmed flash protection settings +//! permanent. On some devices, this operation is non-reversible; a chip reset +//! or power cycle does not change the flash protection. +//! +//! This function does not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashProtectSave(void) +{ + unsigned long ulTemp, ulLimit; + + // + // If running on a Sandstorm-class device, only trigger a save of the first + // two protection registers (FMPRE and FMPPE). Otherwise, save the + // entire bank of flash protection registers. + // + ulLimit = CLASS_IS_SANDSTORM ? 2 : 8; + for(ulTemp = 0; ulTemp < ulLimit; ulTemp++) + { + // + // Tell the flash controller to write the flash protection register. + // + HWREG(FLASH_FMA) = ulTemp; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets the user registers. +//! +//! \param pulUser0 is a pointer to the location to store USER Register 0. +//! \param pulUser1 is a pointer to the location to store USER Register 1. +//! +//! This function reads the contents of user registers (0 and 1), and +//! stores them in the specified locations. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1) +{ + // + // Verify that the pointers are valid. + // + ASSERT(pulUser0 != 0); + ASSERT(pulUser1 != 0); + + // + // Verify that hardware supports user registers. + // + if(CLASS_IS_SANDSTORM) + { + return(-1); + } + + // + // Get and store the current value of the user registers. + // + *pulUser0 = HWREG(FLASH_USERREG0); + *pulUser1 = HWREG(FLASH_USERREG1); + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the user registers. +//! +//! \param ulUser0 is the value to store in USER Register 0. +//! \param ulUser1 is the value to store in USER Register 1. +//! +//! This function sets the contents of the user registers (0 and 1) to +//! the specified values. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashUserSet(unsigned long ulUser0, unsigned long ulUser1) +{ + // + // Verify that hardware supports user registers. + // + if(CLASS_IS_SANDSTORM) + { + return(-1); + } + + // + // Save the new values into the user registers. + // + HWREG(FLASH_USERREG0) = ulUser0; + HWREG(FLASH_USERREG1) = ulUser1; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the user registers. +//! +//! This function makes the currently programmed user register settings +//! permanent. On some devices, this operation is non-reversible; a chip reset +//! or power cycle does not change this setting. +//! +//! This function does not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashUserSave(void) +{ + // + // Verify that hardware supports user registers. + // + if(CLASS_IS_SANDSTORM) + { + return(-1); + } + + // + // Setting the MSB of FMA will trigger a permanent save of a USER + // register. Bit 0 will indicate User 0 (0) or User 1 (1). + // + HWREG(FLASH_FMA) = 0x80000000; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the USER1 Register. + // + HWREG(FLASH_FMA) = 0x80000001; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This function sets the handler to be called when the flash interrupt +//! occurs. The flash controller can generate an interrupt when an invalid +//! flash access occurs, such as trying to program or erase a read-only block, +//! or trying to read from an execute-only block. It can also generate an +//! interrupt when a program or erase operation has completed. The interrupt +//! is automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function clears the handler to be called when the flash interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values. +//! +//! This function enables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values. +//! +//! This function disables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the flash controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS. +// +//***************************************************************************** +unsigned long +FlashIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This function must be called in the interrupt handler +//! to keep the interrupt from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/flash.h b/driverlib/flash.h new file mode 100644 index 0000000..cd9cc34 --- /dev/null +++ b/driverlib/flash.h @@ -0,0 +1,126 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask +#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask +#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask +#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask +#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask +#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); +extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); +extern long FlashUserSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Deprecated function names. These definitions ensure backwards compatibility +// but new code should avoid using deprecated function names since these will +// be removed at some point in the future. +// +//***************************************************************************** +#ifndef DEPRECATED +#define FlashIntGetStatus FlashIntStatus +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/driverlib/fpu.c b/driverlib/fpu.c new file mode 100644 index 0000000..761829b --- /dev/null +++ b/driverlib/fpu.c @@ -0,0 +1,299 @@ +//***************************************************************************** +// +// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M +// processor. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup fpu_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/fpu.h" + +//***************************************************************************** +// +//! Enables the floating-point unit. +//! +//! This function enables the floating-point unit, allowing the floating-point +//! instructions to be executed. This function must be called prior to +//! performing any hardware floating-point operations; failure to do so results +//! in a NOCP usage fault. +//! +//! \return None. +// +//***************************************************************************** +void +FPUEnable(void) +{ + // + // Enable the coprocessors used by the floating-point unit. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); +} + +//***************************************************************************** +// +//! Disables the floating-point unit. +//! +//! This function disables the floating-point unit, preventing floating-point +//! instructions from executing (generating a NOCP usage fault instead). +//! +//! \return None. +// +//***************************************************************************** +void +FPUDisable(void) +{ + // + // Disable the coprocessors used by the floating-point unit. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS); +} + +//***************************************************************************** +// +//! Enables the stacking of floating-point registers. +//! +//! This function enables the stacking of floating-point registers s0-s15 when +//! an interrupt is handled. When enabled, space is reserved on the stack for +//! the floating-point context and the floating-point state is saved into this +//! stack space. Upon return from the interrupt, the floating-point context is +//! restored. +//! +//! If the floating-point registers are not stacked, floating-point +//! instructions cannot be safely executed in an interrupt handler because the +//! values of s0-s15 are not likely to be preserved for the interrupted code. +//! On the other hand, stacking the floating-point registers increases the +//! stacking operation from 8 words to 26 words, also increasing the interrupt +//! response latency. +//! +//! \return None. +// +//***************************************************************************** +void +FPUStackingEnable(void) +{ + // + // Enable automatic state preservation for the floating-point unit, and + // disable lazy state preservation (meaning that the floating-point state + // is always stacked when floating-point instructions are used). + // + HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN; +} + +//***************************************************************************** +// +//! Enables the lazy stacking of floating-point registers. +//! +//! This function enables the lazy stacking of floating-point registers s0-s15 +//! when an interrupt is handled. When lazy stacking is enabled, space is +//! reserved on the stack for the floating-point context, but the +//! floating-point state is not saved. If a floating-point instruction is +//! executed from within the interrupt context, the floating-point context is +//! first saved into the space reserved on the stack. On completion of the +//! interrupt handler, the floating-point context is only restored if it was +//! saved (as the result of executing a floating-point instruction). +//! +//! This method provides a compromise between fast interrupt response (because +//! the floating-point state is not saved on interrupt entry) and the ability +//! to use floating-point in interrupt handlers (because the floating-point +//! state is saved if floating-point instructions are used). +//! +//! \return None. +// +//***************************************************************************** +void +FPULazyStackingEnable(void) +{ + // + // Enable automatic and lazy state preservation for the floating-point + // unit. + // + HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN; +} + +//***************************************************************************** +// +//! Disables the stacking of floating-point registers. +//! +//! This function disables the stacking of floating-point registers s0-s15 when +//! an interrupt is handled. When floating-point context stacking is disabled, +//! floating-point operations performed in an interrupt handler destroy the +//! floating-point context of the main thread of execution. +//! +//! \return None. +// +//***************************************************************************** +void +FPUStackingDisable(void) +{ + // + // Disable automatic and lazy state preservation for the floating-point + // unit. + // + HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN); +} + +//***************************************************************************** +// +//! Selects the format of half-precision floating-point values. +//! +//! \param ulMode is the format for half-precision floating-point value, which +//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. +//! +//! This function selects between the IEEE half-precision floating-point +//! representation and the Cortex-M processor alternative representation. The +//! alternative representation has a larger range but does not have a way to +//! encode infinity (positive or negative) or NaN (quiet or signaling). The +//! default setting is the IEEE format. +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUHalfPrecisionModeSet(unsigned long ulMode) +{ + // + // Set the half-precision floating-point format. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ulMode; +} + +//***************************************************************************** +// +//! Selects the NaN mode. +//! +//! \param ulMode is the mode for NaN results; which is either +//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT. +//! +//! This function selects the handling of NaN results during floating-point +//! computations. NaNs can either propagate (the default), or they can return +//! the default NaN. +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUNaNModeSet(unsigned long ulMode) +{ + // + // Set the NaN mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ulMode; +} + +//***************************************************************************** +// +//! Selects the flush-to-zero mode. +//! +//! \param ulMode is the flush-to-zero mode; which is either +//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN. +//! +//! This function enables or disables the flush-to-zero mode of the +//! floating-point unit. When disabled (the default), the floating-point unit +//! is fully IEEE compliant. When enabled, values close to zero are treated as +//! zero, greatly improving the execution speed at the expense of some accuracy +//! (as well as IEEE compliance). +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUFlushToZeroModeSet(unsigned long ulMode) +{ + // + // Set the flush-to-zero mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ulMode; +} + +//***************************************************************************** +// +//! Selects the rounding mode for floating-point results. +//! +//! \param ulMode is the rounding mode. +//! +//! This function selects the rounding mode for floating-point results. After +//! a floating-point operation, the result is rounded toward the specified +//! value. The default mode is \b FPU_ROUND_NEAREST. +//! +//! The following rounding modes are available (as specified by \e ulMode): +//! +//! - \b FPU_ROUND_NEAREST - round toward the nearest value +//! - \b FPU_ROUND_POS_INF - round toward positive infinity +//! - \b FPU_ROUND_NEG_INF - round toward negative infinity +//! - \b FPU_ROUND_ZERO - round toward zero +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPURoundingModeSet(unsigned long ulMode) +{ + // + // Set the rounding mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ulMode; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/fpu.h b/driverlib/fpu.h new file mode 100644 index 0000000..3cf105a --- /dev/null +++ b/driverlib/fpu.h @@ -0,0 +1,112 @@ +//***************************************************************************** +// +// fpu.h - Prototypes for the floatint point manipulation routines. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FPU_H__ +#define __FPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_HALF_IEEE 0x00000000 +#define FPU_HALF_ALTERNATE 0x04000000 + +//***************************************************************************** +// +// Values that can be passed to FPUNaNModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_NAN_PROPAGATE 0x00000000 +#define FPU_NAN_DEFAULT 0x02000000 + +//***************************************************************************** +// +// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 +#define FPU_FLUSH_TO_ZERO_EN 0x01000000 + +//***************************************************************************** +// +// Values that can be passed to FPURoundingModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_ROUND_NEAREST 0x00000000 +#define FPU_ROUND_POS_INF 0x00400000 +#define FPU_ROUND_NEG_INF 0x00800000 +#define FPU_ROUND_ZERO 0x00c00000 + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void FPUEnable(void); +extern void FPUDisable(void); +extern void FPUStackingEnable(void); +extern void FPULazyStackingEnable(void); +extern void FPUStackingDisable(void); +extern void FPUHalfPrecisionModeSet(unsigned long ulMode); +extern void FPUNaNModeSet(unsigned long ulMode); +extern void FPUFlushToZeroModeSet(unsigned long ulMode); +extern void FPURoundingModeSet(unsigned long ulMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FPU_H__ diff --git a/driverlib/gcc-cm3/libdriver-cm3.a b/driverlib/gcc-cm3/libdriver-cm3.a new file mode 100644 index 0000000..377dd5d Binary files /dev/null and b/driverlib/gcc-cm3/libdriver-cm3.a differ diff --git a/driverlib/gcc-cm4f/libdriver-cm4f.a b/driverlib/gcc-cm4f/libdriver-cm4f.a new file mode 100644 index 0000000..7be29d1 Binary files /dev/null and b/driverlib/gcc-cm4f/libdriver-cm4f.a differ diff --git a/driverlib/gpio.c b/driverlib/gpio.c new file mode 100644 index 0000000..f4de010 --- /dev/null +++ b/driverlib/gpio.c @@ -0,0 +1,2076 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_gpio.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// The base addresses of all the GPIO modules. Both the APB and AHB apertures +// are provided. +// +//***************************************************************************** +static const unsigned long g_pulGPIOBaseAddrs[] = +{ + GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE, + GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE, + GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE, + GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE, + GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE, + GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE, + GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE, + GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE, + GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE, + GPIO_PORTK_BASE, GPIO_PORTK_BASE, + GPIO_PORTL_BASE, GPIO_PORTL_BASE, + GPIO_PORTM_BASE, GPIO_PORTM_BASE, + GPIO_PORTN_BASE, GPIO_PORTN_BASE, + GPIO_PORTP_BASE, GPIO_PORTP_BASE, + GPIO_PORTQ_BASE, GPIO_PORTQ_BASE, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a GPIO base address. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function determines if a GPIO port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +GPIOBaseValid(unsigned long ulPort) +{ + return((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTA_AHB_BASE) || + (ulPort == GPIO_PORTB_BASE) || (ulPort == GPIO_PORTB_AHB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTC_AHB_BASE) || + (ulPort == GPIO_PORTD_BASE) || (ulPort == GPIO_PORTD_AHB_BASE) || + (ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) || + (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) || + (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) || + (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) || + (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE) || + (ulPort == GPIO_PORTK_BASE) || (ulPort == GPIO_PORTL_BASE) || + (ulPort == GPIO_PORTM_BASE) || (ulPort == GPIO_PORTN_BASE) || + (ulPort == GPIO_PORTP_BASE) || (ulPort == GPIO_PORTQ_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the GPIO interrupt number. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! Given a GPIO base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +static long +GPIOGetIntNumber(unsigned long ulPort) +{ + long lInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIO_PORTA_BASE: + case GPIO_PORTA_AHB_BASE: + { + lInt = INT_GPIOA; + break; + } + + case GPIO_PORTB_BASE: + case GPIO_PORTB_AHB_BASE: + { + lInt = INT_GPIOB; + break; + } + + case GPIO_PORTC_BASE: + case GPIO_PORTC_AHB_BASE: + { + lInt = INT_GPIOC; + break; + } + + case GPIO_PORTD_BASE: + case GPIO_PORTD_AHB_BASE: + { + lInt = INT_GPIOD; + break; + } + + case GPIO_PORTE_BASE: + case GPIO_PORTE_AHB_BASE: + { + lInt = INT_GPIOE; + break; + } + + case GPIO_PORTF_BASE: + case GPIO_PORTF_AHB_BASE: + { + lInt = INT_GPIOF; + break; + } + + case GPIO_PORTG_BASE: + case GPIO_PORTG_AHB_BASE: + { + lInt = INT_GPIOG; + break; + } + + case GPIO_PORTH_BASE: + case GPIO_PORTH_AHB_BASE: + { + lInt = INT_GPIOH; + break; + } + + case GPIO_PORTJ_BASE: + case GPIO_PORTJ_AHB_BASE: + { + lInt = INT_GPIOJ; + break; + } + + case GPIO_PORTK_BASE: + { + lInt = INT_GPIOK; + break; + } + + case GPIO_PORTL_BASE: + { + lInt = INT_GPIOL; + break; + } + + case GPIO_PORTM_BASE: + { + lInt = INT_GPIOM; + break; + } + + case GPIO_PORTN_BASE: + { + lInt = INT_GPION; + break; + } + + case GPIO_PORTP_BASE: + { + lInt = INT_GPIOP0; + break; + } + + case GPIO_PORTQ_BASE: + { + lInt = INT_GPIOQ0; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(lInt); +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulPinIO is the pin direction and/or mode. +//! +//! This function configures the specified pin(s) on the selected GPIO port +//! as either input or output under software control, or it configures the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a +//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is +//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW +//! specifies that the pin is placed under hardware control. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note GPIOPadConfigSet() must also be used to configure the corresponding +//! pad(s) in order for them to propagate the signal to/from the GPIO. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || + (ulPinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? + (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AFSEL) & + ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the direction and mode of a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir, ulAFSEL; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_DIR); + ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); + return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); +} + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulIntType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin(s) on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! - \b GPIO_DISCRETE_INT +//! +//! where the different values describe the interrupt detection mechanism +//! (edge or level) and the particular triggering event (falling, rising, +//! or both edges for edge detect, low or high for level detect). +//! +//! Some devices also support discrete interrupts for each pin on a GPIO port, +//! giving each pin a separate interrupt vector. To use this feature, the +//! \b GPIO_DISCRETE_INT can be included to enable an interrupt per pin. The +//! \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports, +//! consult the data sheet to ensure that the device and the GPIO port supports +//! discrete interrupts. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or +//! both-edges detected interrupt, or it can be configured as a low-level or +//! high-level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_IBE); + ulIS = HWREG(ulPort + GPIO_O_IS); + ulIEV = HWREG(ulPort + GPIO_O_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulStrength specifies the output drive strength. +//! \param ulPinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pin(s) +//! on the selected GPIO port. For pin(s) configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ulStrength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! Some Stellaris devices also support output drive strengths of 6, 10, and 12 +//! mA. +//! +//! The parameter \e ulPinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_OD_WPU +//! - \b GPIO_PIN_TYPE_OD_WPD +//! - \b GPIO_PIN_TYPE_ANALOG +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an analog +//! input. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, unsigned long ulPinType) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulStrength == GPIO_STRENGTH_2MA) || + (ulStrength == GPIO_STRENGTH_4MA) || + (ulStrength == GPIO_STRENGTH_8MA) || + (ulStrength == GPIO_STRENGTH_8MA_SC)); + ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || + (ulPinType == GPIO_PIN_TYPE_STD_WPU) || + (ulPinType == GPIO_PIN_TYPE_STD_WPD) || + (ulPinType == GPIO_PIN_TYPE_OD) || + (ulPinType == GPIO_PIN_TYPE_OD_WPU) || + (ulPinType == GPIO_PIN_TYPE_OD_WPD) || + (ulPinType == GPIO_PIN_TYPE_ANALOG)); + + // + // Set the output drive strength. + // + HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? + (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? + (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? + (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? + (HWREG(ulPort + GPIO_O_SLR) | ucPins) : + (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); + + // + // Set the pin type. + // + HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? + (HWREG(ulPort + GPIO_O_ODR) | ucPins) : + (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? + (HWREG(ulPort + GPIO_O_PUR) | ucPins) : + (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? + (HWREG(ulPort + GPIO_O_PDR) | ucPins) : + (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? + (HWREG(ulPort + GPIO_O_DEN) | ucPins) : + (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); + + // + // Set the analog mode select register. This register only appears in + // DustDevil-class (and later) devices, but is a harmless write on + // Sandstorm- and Fury-class devices. + // + HWREG(ulPort + GPIO_O_AMSEL) = + ((ulPinType == GPIO_PIN_TYPE_ANALOG) ? + (HWREG(ulPort + GPIO_O_AMSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AMSEL) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! \param pulStrength is a pointer to storage for the output drive strength. +//! \param pulPinType is a pointer to storage for the output drive type. +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e pulStrength and +//! \e pulPinType correspond to the values used in GPIOPadConfigSet(). This +//! function also works for pin(s) configured as input pin(s); however, the +//! only meaningful data returned is whether the pin is terminated with a +//! pull-up or down resistor. +//! +//! \return None +// +//***************************************************************************** +void +GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, unsigned long *pulPinType) +{ + unsigned long ulPinType, ulStrength; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = (1 << ucPin); + + // + // Get the drive strength for this pin. + // + ulStrength = ((HWREG(ulPort + GPIO_O_DR2R) & ucPin) ? 1 : 0); + ulStrength |= ((HWREG(ulPort + GPIO_O_DR4R) & ucPin) ? 2 : 0); + ulStrength |= ((HWREG(ulPort + GPIO_O_DR8R) & ucPin) ? 4 : 0); + ulStrength |= ((HWREG(ulPort + GPIO_O_SLR) & ucPin) ? 8 : 0); + *pulStrength = ulStrength; + + // + // Get the pin type. + // + ulPinType = ((HWREG(ulPort + GPIO_O_ODR) & ucPin) ? 1 : 0); + ulPinType |= ((HWREG(ulPort + GPIO_O_PUR) & ucPin) ? 2 : 0); + ulPinType |= ((HWREG(ulPort + GPIO_O_PDR) & ucPin) ? 4 : 0); + ulPinType |= ((HWREG(ulPort + GPIO_O_DEN) & ucPin) ? 8 : 0); + *pulPinType = ulPinType; +} + +//***************************************************************************** +// +//! Enables interrupts for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Unmasks the interrupt for the specified pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) |= ucPins; +} + +//***************************************************************************** +// +//! Disables interrupts for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Masks the interrupt for the specified pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return Returns a bit-packed byte, where each bit that is set identifies +//! an active masked or raw interrupt, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! Bits 31:8 should be ignored. +// +//***************************************************************************** +long +GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the interrupt for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Clears the interrupt for the specified pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_ICR) = ucPins; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function also enables the corresponding GPIO interrupt +//! in the interrupt controller; individual pin interrupts and interrupt +//! sources must be enabled with GPIOPinIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfnIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function unregisters the interrupt handler for the specified +//! GPIO port. This function also disables the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOPinIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPortIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} + +//***************************************************************************** +// +//! Reads the values present of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The values at the specified pin(s) are read, as specified by \e ucPins. +//! Values are returned for both input and output pin(s), and the value +//! for pin(s) that are not specified by \e ucPins are set to 0. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); +} + +//***************************************************************************** +// +//! Writes a value to the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ucVal is the value to write to the pin(s). +//! +//! Writes the corresponding bit values to the output pin(s) specified by +//! \e ucPins. Writing to a pin configured as an input pin has no effect. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; +} + +//***************************************************************************** +// +//! Configures pin(s) for use as analog-to-digital converter inputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The analog-to-digital converter input pins must be properly configured +//! to function correctly on devices that are not Sandstorm- or Fury-class. +//! This function provides the proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an ADC input; it +//! only configures an ADC input pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as a CAN device. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The CAN pins must be properly configured for the CAN peripherals to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a CAN pin; it only +//! configures a CAN pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an analog comparator +//! input; it only configures an analog comparator pin for proper operation. +//! Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the external peripheral interface. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The external peripheral interface pins must be properly configured for the +//! external peripheral interface to function correctly. This function +//! provides a typical configuration for those pin(s); other configurations may +//! work as well depending upon the board setup (for example, using the on-chip +//! pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an external +//! peripheral interface pin; it only configures an external peripheral +//! interface pin for proper operation. Devices with flexible pin muxing also +//! require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Ethernet peripheral as LED signals. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The Ethernet peripheral provides two signals that can be used to drive +//! an LED (e.g. for link status/activity). This function provides a typical +//! configuration for the pins. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an Ethernet LED +//! pin; it only configures an Ethernet LED pin for proper operation. Devices +//! with flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Ethernet peripheral as MII signals. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The Ethernet peripheral on some parts provides a set of MII signals that +//! are used to connect to an external PHY. This function provides a typical +//! configuration for the pins. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an Ethernet MII +//! pin; it only configures an Ethernet MII pin for proper operation. Devices +//! with flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the fan module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The fan pins must be properly configured for the fan controller to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a fan pin; it only +//! configures a fan pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO inputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO inputs; this is especially true of Fury-class devices where the +//! digital input enable is turned off by default. This function provides the +//! proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO outputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO outputs; this is especially true of Fury-class devices where the +//! digital input enable is turned off by default. This function provides the +//! proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO open drain outputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO outputs; this is especially true of Fury-class devices where the +//! digital input enable is turned off by default. This function provides the +//! proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2C peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for those +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an I2C pin; it +//! only configures an I2C pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as SCL by the I2C peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for the SCL +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function should only be used for Blizzard-class devices. It +//! cannot be used to turn any pin into an I2C SCL pin; it only configures an +//! I2C SCL pin for proper operation. Devices with flexible pin muxing also +//! require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + if(CLASS_IS_SANDSTORM || CLASS_IS_FURY || CLASS_IS_DUSTDEVIL || + CLASS_IS_TEMPEST || CLASS_IS_FIRESTORM) + { + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); + } + else + { + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + } +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2S peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some I2S pins must be properly configured for the I2S peripheral to +//! function correctly. This function provides a typical configuration for +//! the digital I2S pin(s); other configurations may work as well depending +//! upon the board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a I2S pin; it only +//! configures a I2S pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the LPC module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The LPC pins must be properly configured for the LPC module to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an LPC pin; it only +//! configures an LPC pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures a pin for receive use by the PECI module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The PECI receive pin must be properly configured for the PECI module to +//! function correctly. This function provides a typical configuration for +//! that pin. +//! +//! The pin is specified using a bit-packed byte, where each bit that is set +//! identifies the pin to be accessed, and where bit 0 of the byte represents +//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a PECI receive pin; +//! it only configures a PECI receive pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures a pin for transmit use by the PECI module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The PECI transmit pin must be properly configured for the PECI module to +//! function correctly. This function provides a typical configuration for +//! that pin. +//! +//! The pin is specified using a bit-packed byte, where each bit that is set +//! identifies the pin to be accessed, and where bit 0 of the byte represents +//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a PECI transmit +//! pin; it only configures a PECI transmit pin for proper operation. Devices +//! with flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. Devices wtih flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, not using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a timer pin; it +//! only configures a timer pin for proper operation. Devices with flexible +//! pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a UART pin; it +//! only configures a UART pin for proper operation. Devices with flexible +//! pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the USB peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some USB analog pins must be properly configured for the USB peripheral to +//! function correctly. This function provides the proper configuration for +//! any USB pin(s). This can also be used to configure the EPEN and PFAULT pins +//! so that they are no longer used by the USB controller. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the USB peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some USB digital pins must be properly configured for the USB peripheral to +//! function correctly. This function provides a typical configuration for +//! the digital USB pin(s); other configurations may work as well depending +//! upon the board setup (for example, using the on-chip pull-ups). +//! +//! This function should only be used with EPEN and PFAULT pins as all other +//! USB pins are analog in nature or are not used in devices without OTG +//! functionality. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param ulPinConfig is the pin configuration value, specified as only one of +//! the \b GPIO_P??_??? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). To fully +//! configure a pin, a GPIOPinType*() function should also be called. +//! +//! The available mappings are supplied on a per-device basis in +//! pin_map.h. The \b PART_IS_ define enables the +//! appropriate set of defines for the device that is being used. +//! +//! \note This function is not valid on Sandstorm, Fury, and Dustdevil-class +//! devices. Also, if the same signal is assigned to two different GPIO port +//! pins, the signal is assigned to the port with the lowest letter and the +//! assignment to the higher letter port is ignored. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinConfigure(unsigned long ulPinConfig) +{ + unsigned long ulBase, ulShift; + + // + // Check the argument. + // + ASSERT(((ulPinConfig >> 16) & 0xff) < 15); + ASSERT(((ulPinConfig >> 8) & 0xe3) == 0); + + // + // Extract the base address index from the input value. + // + ulBase = (ulPinConfig >> 16) & 0xff; + + // + // Get the base address of the GPIO module, selecting either the APB or the + // AHB aperture as appropriate. + // + if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ulBase)) + { + ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1]; + } + else + { + ulBase = g_pulGPIOBaseAddrs[ulBase << 1]; + } + + // + // Extract the shift from the input value. + // + ulShift = (ulPinConfig >> 8) & 0xff; + + // + // Write the requested pin muxing value for this GPIO pin. + // + HWREG(ulBase + GPIO_O_PCTL) = ((HWREG(ulBase + GPIO_O_PCTL) & + ~(0xf << ulShift)) | + ((ulPinConfig & 0xf) << ulShift)); +} + +//***************************************************************************** +// +//! Enables a GPIO pin as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function enables a GPIO pin to be used as a trigger to start a uDMA +//! transaction. Any GPIO pin can be configured to be an external trigger for +//! the uDMA. The GPIO pin still generates interrupts if the interrupt is +//! enabled for the selected pin. +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO DMA Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_DMACTL) |= ucPins; +} + +//***************************************************************************** +// +//! Disables a GPIO pin as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function disables a GPIO pin from being used as a trigger to start a +//! uDMA transaction. This function can be used to disable this feature if it +//! was enabled via a call to GPIODMATriggerEnable(). +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO DMA Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_DMACTL) &= (~ucPins); +} + +//***************************************************************************** +// +//! Enables a GPIO pin as a trigger to start an ADC capture. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function enables a GPIO pin to be used as a trigger to start an ADC +//! sequence. Any GPIO pin can be configured to be an external trigger for +//! an ADC sequence. The GPIO pin still generates interrupts if the +//! interrupt is enabled for the selected pin. To enable the use of a GPIO pin +//! to trigger the ADC module, the ADCSequenceConfigure() function must be called +//! with the ADC_TRIGGER_EXTERNAL parameter. +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO ADC Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_ADCCTL) |= ucPins; +} + +//***************************************************************************** +// +//! Disable a GPIO pin as a trigger to start an ADC capture. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function disables a GPIO pin to be used as a trigger to start an ADC +//! sequence. This function can be used to disable this feature if it was +//! enabled via a call to GPIOADCTriggerEnable(). +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO ADC Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_ADCCTL) &= (~ucPins); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/gpio.h b/driverlib/gpio.h new file mode 100644 index 0000000..acf3c93 --- /dev/null +++ b/driverlib/gpio.h @@ -0,0 +1,199 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfnIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinConfigure(unsigned long ulPinConfig); +extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort, + unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins); +extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins); + +//**************************************************************************** +// +// The definitions for GPIOPinConfigure previously resided in this file but +// have been moved to pin_map.h and made part-specific (in other words, only +// those definitions that are valid based on the selected part, as defined by +// PART_, will be made available). For backwards compatibility, +// pin_map.h is included here so that the expected definitions will still be +// available (though part-specific now, so some that were previously available +// but inappropriate for the given part will not be available). +// +//***************************************************************************** +#ifndef DEPRECATED +#include "pin_map.h" +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/driverlib/hibernate.c b/driverlib/hibernate.c new file mode 100644 index 0000000..2a2fe34 --- /dev/null +++ b/driverlib/hibernate.c @@ -0,0 +1,1354 @@ +//***************************************************************************** +// +// hibernate.c - Driver for the Hibernation module +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup hibernate_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_hibernate.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/hibernate.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +// The delay in microseconds for writing to the Hibernation module registers. +// +//***************************************************************************** +#define DELAY_USECS 95 + +//***************************************************************************** +// +// The number of processor cycles to execute one pass of the delay loop. +// +//***************************************************************************** +#define LOOP_CYCLES 3 + +//***************************************************************************** +// +// The calculated number of delay loops to achieve the write delay. +// +//***************************************************************************** +static unsigned long g_ulWriteDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Polls until the write complete (WRC) bit in the hibernate control register +//! is set. +//! +//! \param None. +//! +//! On non-Fury-class devices, the Hibernation module provides an indication +//! when any write is completed. This mechanism is used to pace writes to the +//! module. This function merely polls this bit and returns as soon as it is +//! set. At this point, it is safe to perform another write to the module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateWriteComplete(void) +{ + // + // Add a delay here to enforce the required delay between write accesses to + // certain Hibernation module registers. + // + if(CLASS_IS_FURY) + { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Spin until the write complete bit is set, for later devices. + // + while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) + { + } + } +} + +//***************************************************************************** +// +//! Enables the Hibernation module for operation. +//! +//! \param ulHibClk is the rate of the clock supplied to the Hibernation +//! module. +//! +//! This function enables the Hibernation module for operation. This function +//! should be called before any of the Hibernation module features are used. +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! This function replaces the original HibernateEnable() API and performs the +//! same actions. A macro is provided in hibernate.h to map the +//! original API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateEnableExpClk(unsigned long ulHibClk) +{ + // + // Turn on the clock enable bit. + // + HWREG(HIB_CTL) |= HIB_CTL_CLK32EN; + + // + // For Fury-class devices, compute the number of delay loops that must be + // used to achieve the desired delay for writes to the hibernation + // registers. This value is used in calls to SysCtlDelay(). + // + if(CLASS_IS_FURY) + { + g_ulWriteDelay = (((ulHibClk / 1000) * DELAY_USECS) / + (1000L * LOOP_CYCLES)); + g_ulWriteDelay++; + } + else + { + // + // Non-fury parts must wait for write complete following register + // load (above). + // + HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Disables the Hibernation module for operation. +//! +//! This function disables the Hibernation module. After this function is +//! called, none of the Hibernation module features are available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDisable(void) +{ + // + // Turn off the clock enable bit. + // + HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Selects the clock input for the Hibernation module. +//! +//! \param ulClockInput specifies the clock input. +//! +//! This function configures the clock input for the Hibernation module. The +//! configuration option chosen depends entirely on hardware design. The clock +//! input for the module is either a 32.768-kHz oscillator/crystal or a +//! 4.194304-MHz crystal. +//! The \e ulClockFlags parameter must be one of the following: +//! +//! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz +//! oscillator. +//! - \b HIBERNATE_CLOCK_SEL_DIV128 - use the 4.194304-MHz crystal input, +//! divided by 128. +//! +//! \note The \b HIBERNATE_CLOCK_SEL_DIV128 setting is not available on all +//! Stellaris devices. Please consult the data sheet to determine if the +//! device that you are using supports the 4.194304 crystal as a source for the +//! Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateClockSelect(unsigned long ulClockInput) +{ + // + // Check the arguments. + // + ASSERT((ulClockInput == HIBERNATE_CLOCK_SEL_RAW) || + (ulClockInput == HIBERNATE_CLOCK_SEL_DIV128)); + + // + // Set the clock selection bit according to the parameter. + // + HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL); + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Configures the clock input for the Hibernation module. +//! +//! \param ulConfig is one of the possible configuration options for the clock +//! input listed below. +//! +//! This function is used to configure the clock input for the Hibernation +//! module. The \e ulConfig parameter can be one of the following values: +//! +//! - \b HIBERNATE_OSC_DISABLE specifies that the internal oscillator +//! is powered off and either an externally supplied clock source or no clock +//! source is being used. +//! - \b HIBERNATE_OSC_HIGHDRIVE specifies a higher drive strength when a 24pF +//! filter capacitor is used with a crystal. +//! - \b HIBERNATE_OSC_LOWDRIVE specifies a lower drive strength when a 12pF +//! filter capacitor is used with a crystal. +//! +//! +//! The \b HIBERNATE_OSC_DISABLE option is used to disable and power down the +//! internal oscillator if an external clock source or no clock source is used +//! instead of a 32.768 kHz crystal. In the case where an external crystal is +//! used, either the \b HIBERNATE_OSC_HIGHDRIVE or \b HIBERNATE_OSC_LOWDRIVE is +//! used. This optimizes the oscillator drive strength to match the size of +//! the filter capacitor that is used with the external crystal circuit. +//! +//! \note The ability to configure the clock input in the Hibernation +//! module is not available on all Stellaris devices. Please consult the data +//! sheet for the Stellaris device that you are using to determine if this +//! feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateClockConfig(unsigned long ulConfig) +{ + unsigned long ulHIBCtl; + + ASSERT((ulConfig & (HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE)) == 0); + + ulHIBCtl = HWREG(HIB_CTL); + + // + // Clear the current configuration bits. + // + ulHIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE); + + // + // Set the new configuration bits. + // + ulHIBCtl |= ulConfig & (HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE); + + // + // Set the hibernation clocking configuration. + // + HWREG(HIB_CTL) = ulHIBCtl; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Enables the RTC feature of the Hibernation module. +//! +//! This function enables the RTC in the Hibernation module. The RTC can be +//! used to wake the processor from hibernation at a certain time, or to +//! generate interrupts at certain times. This function must be called before +//! using any of the RTC features of the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCEnable(void) +{ + // + // Turn on the RTC enable bit. + // + HWREG(HIB_CTL) |= HIB_CTL_RTCEN; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables the RTC feature of the Hibernation module. +//! +//! This function disables the RTC in the Hibernation module. After calling +//! this function, the RTC features of the Hibernation module are not +//! available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCDisable(void) +{ + // + // Turn off the RTC enable bit. + // + HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Forces the Hibernation module to initiate a check of the battery voltage. +//! +//! This function forces the Hibernation module to initiate a check of the +//! battery voltage immediately rather than waiting for the next check interval +//! to pass. After calling this function, the application should call the +//! () function and wait for the function to return a zero +//! value before calling the HibernateIntStatus() to check if the return code +//! has the \b HIBERNATE_INT_LOW_BAT set. If \b HIBERNATE_INT_LOW_BAT is set, +//! the battery level is low. The application can also enable the +//! \b HIBERNATE_INT_LOW_BAT interrupt and wait for an interrupt to indicate +//! that the battery level is low. +//! +//! \note A hibernation request is held off if a battery check is in progress. +//! This function is only available on some Stellaris devices. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateBatCheckStart(void) +{ + // + // Initiated a forced battery check. + // + HWREG(HIB_CTL) |= HIB_CTL_BATCHK; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns if a forced battery check has completed. +//! +//! This function returns if the forced battery check initiated by a call to +//! the HibernateBatCheckStart() function has completed. This function +//! returns a non-zero value until the battery level check has completed. Once +//! this function returns a value of zero, the hibernation module has completed +//! the battery check and the HibernateIntStatus() function can be used to +//! check if the battery was low by checking if the value returned has the +//! \b HIBERNATE_INT_LOW_BAT set. +//! +//! \note This function is only available on some Stellaris devices. +//! +//! \return The value is zero when the battery level check has completed or +//! non-zero if the check is still in process. +// +//***************************************************************************** +unsigned long +HibernateBatCheckDone(void) +{ + // + // Read the current state of the batter check. + // + return(HWREG(HIB_CTL) & HIB_CTL_BATCHK); +} + +//***************************************************************************** +// +//! Configures the wake conditions for the Hibernation module. +//! +//! \param ulWakeFlags specifies which conditions should be used for waking. +//! +//! This function enables the conditions under which the Hibernation module +//! wakes. The \e ulWakeFlags parameter is the logical OR of any combination +//! of the following: +//! +//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. +//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. +//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low-battery +//! level being detected. +//! +//! \note The \b HIBERNATE_WAKE_LOW_BAT parameter is only available on some +//! Stellaris devices. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateWakeSet(unsigned long ulWakeFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT))); + + // + // Set the specified wake flags in the control register. + // + HWREG(HIB_CTL) = (ulWakeFlags | + (HWREG(HIB_CTL) & ~(HIBERNATE_WAKE_PIN | + HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT))); + + // + // Wait for write completion + // + HibernateWriteComplete(); + +} + +//***************************************************************************** +// +//! Gets the currently configured wake conditions for the Hibernation module. +//! +//! This function returns the flags representing the wake configuration for the +//! Hibernation module. The return value is a combination of the following +//! flags: +//! +//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. +//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. +//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low-battery +//! level being detected. +//! +//! \note The \b HIBERNATE_WAKE_LOW_BAT parameter is only available on some +//! Stellaris devices. +//! +//! \return Returns flags indicating the configured wake conditions. +// +//***************************************************************************** +unsigned long +HibernateWakeGet(void) +{ + // + // Read the wake bits from the control register and return those bits to + // the caller. + // + return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT)); +} + +//***************************************************************************** +// +//! Configures the low-battery detection. +//! +//! \param ulLowBatFlags specifies behavior of low-battery detection. +//! +//! This function enables the low-battery detection and whether hibernation is +//! allowed if a low-battery is detected. If low-battery detection is enabled, +//! then a low-battery condition is indicated in the raw interrupt status +//! register, which can also trigger an interrupt. Optionally, hibernation can +//! be aborted if a low-battery is detected. +//! +//! The \e ulLowBatFlags parameter is one of the following values: +//! +//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low-battery condition. +//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low-battery condition, and abort +//! hibernation if low-battery is detected. +//! +//! The other setting in the \e ulLowBatFlags allows the caller to set one of +//! the following voltage level trigger values : +//! +//! - \b HIBERNATE_LOW_BAT_1_9V - voltage low level is 1.9V +//! - \b HIBERNATE_LOW_BAT_2_1V - voltage low level is 2.1V +//! - \b HIBERNATE_LOW_BAT_2_3V - voltage low level is 2.3V +//! - \b HIBERNATE_LOW_BAT_2_5V - voltage low level is 2.5V +//! +//! \b Example: Abort hibernate if the voltage level is below 2.1V. +//! +//! \verbatim +//! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V); +//! \endverbatim +//! +//! \note The parameters with the specific voltage levels are only available on +//! some Stellaris devices. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateLowBatSet(unsigned long ulLowBatFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulLowBatFlags & ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT))); + + // + // Set the low-battery detect and abort bits in the control register, + // according to the parameter. + // + HWREG(HIB_CTL) = (ulLowBatFlags | + (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M + | HIBERNATE_LOW_BAT_ABORT))); + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the currently configured low-battery detection behavior. +//! +//! This function returns a value representing the currently configured low +//! battery detection behavior. +//! +//! The return value is a combination of the values described in the +//! HibernateLowBatSet() function. +//! +//! \return Returns a value indicating the configured low-battery detection. +// +//***************************************************************************** +unsigned long +HibernateLowBatGet(void) +{ + // + // Read the supported low bat bits from the control register and return + // those bits to the caller. + // + return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)); +} + +//***************************************************************************** +// +//! Sets the value of the real time clock (RTC) counter. +//! +//! \param ulRTCValue is the new value for the RTC. +//! +//! This function sets the value of the RTC. The RTC count seconds if the +//! hardware is configured correctly. The RTC must be enabled by calling +//! HibernateRTCEnable() before calling this function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCSet(unsigned long ulRTCValue) +{ + // + // Write the new RTC value to the RTC load register. + // + HWREG(HIB_RTCLD) = ulRTCValue; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the real time clock (RTC) counter. +//! +//! This function gets the value of the RTC and returns it to the caller. +//! +//! \return Returns the value of the RTC counter in seconds. +// +//***************************************************************************** +unsigned long +HibernateRTCGet(void) +{ + // + // Return the value of the RTC counter register to the caller. + // + return(HWREG(HIB_RTCC)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC match 0 register. +//! +//! \param ulMatch is the value for the match register. +//! +//! This function sets the match 0 register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCMatch0Set(unsigned long ulMatch) +{ + // + // Write the new match value to the match register. + // + HWREG(HIB_RTCM0) = ulMatch; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the RTC match 0 register. +//! +//! This function gets the value of the match 0 register for the RTC. +//! +//! \return Returns the value of the match register. +// +//***************************************************************************** +unsigned long +HibernateRTCMatch0Get(void) +{ + // + // Return the value of the match register to the caller. + // + return(HWREG(HIB_RTCM0)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC match 1 register. +//! +//! \param ulMatch is the value for the match register. +//! +//! This function sets the match 1 register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. +//! +//! \note The Hibernation RTC Match 1 feature is not available on all Stellaris +//! devices. Please consult the data sheet for the Stellaris device that you +//! are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCMatch1Set(unsigned long ulMatch) +{ + // + // Write the new match value to the match register. + // + HWREG(HIB_RTCM1) = ulMatch; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the RTC match 1 register. +//! +//! This function gets the value of the match 1 register for the RTC. +//! +//! \note The Hibernation RTC Match 1 feature is not available on all Stellaris +//! devices. Please consult the data sheet for the Stellaris device that you +//! are using to determine if this feature is available. +//! +//! \return Returns the value of the match register. +// +//***************************************************************************** +unsigned long +HibernateRTCMatch1Get(void) +{ + // + // Return the value of the match register to the caller. + // + return(HWREG(HIB_RTCM1)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC sub second match 0 register. +//! +//! \param ulMatch is the value for the sub second match register. +//! +//! This function sets the sub second match 0 register for the RTC in 1/32768 +//! of a second increments. The Hibernation module can be configured to wake +//! from hibernation, and/or generate an interrupt when the value of the RTC +//! counter is the same as the match combined with the sub second match +//! register. +//! +//! \note The Hibernation sub second RTC Match 0 feature is not available on +//! all Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCSSMatch0Set(unsigned long ulMatch) +{ + // + // Write the new sub second match value to the sub second match register. + // + HWREG(HIB_RTCSS) = ulMatch << HIB_RTCSS_RTCSSM_S; + + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the value of the RTC sub second match 0 register. +//! +//! This function returns the current value of the sub second match 0 register +//! for the RTC. The value returned is in 1/32768 second increments. +//! +//! \note The Hibernation sub second RTC Match 0 feature is not available on +//! all Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine if this feature is available. +//! +//! \return Returns the value of the sub section match register. +// +//***************************************************************************** +unsigned long +HibernateRTCSSMatch0Get(void) +{ + // + // Read the current second RTC count. + // + return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S); +} + +//***************************************************************************** +// +//! Returns the current value of the RTC sub second count. +//! +//! This function returns the current value of the sub second count for the +//! for the RTC in 1/32768 of a second increments. +//! +//! \note The Hibernation sub second RTC Match 0 feature is not available on +//! all Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine if this feature is available. +//! +//! \return The current RTC sub second count in 1/32768 seconds. +// +//***************************************************************************** +unsigned long +HibernateRTCSSGet(void) +{ + // + // Read the current second RTC count. + // + return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M); +} + +//***************************************************************************** +// +//! Sets the value of the RTC pre-divider trim register. +//! +//! \param ulTrim is the new value for the pre-divider trim register. +//! +//! This function sets the value of the pre-divider trim register. The input +//! time source is divided by the pre-divider to achieve a one-second clock +//! rate. Once every 64 seconds, the value of the pre-divider trim register is +//! applied to the pre-divider to allow fine-tuning of the RTC rate, in order +//! to make corrections to the rate. The software application can make +//! adjustments to the pre-divider trim register to account for variations in +//! the accuracy of the input time source. The nominal value is 0x7FFF, and it +//! can be adjusted up or down in order to fine-tune the RTC rate. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCTrimSet(unsigned long ulTrim) +{ + // + // Check the arguments. + // + ASSERT(ulTrim < 0x10000); + + // + // Write the new trim value to the trim register. + // + HWREG(HIB_RTCT) = ulTrim; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Gets the value of the RTC pre-divider trim register. +//! +//! This function gets the value of the pre-divider trim register. This +//! function can be used to get the current value of the trim register prior +//! to making an adjustment by using the HibernateRTCTrimSet() function. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +HibernateRTCTrimGet(void) +{ + // + // Return the value of the trim register to the caller. + // + return(HWREG(HIB_RTCT)); +} + +//***************************************************************************** +// +//! Stores data in the battery-backed memory of the Hibernation module. +//! +//! \param pulData points to the data that the caller wants to store in the +//! memory of the Hibernation module. +//! \param ulCount is the count of 32-bit words to store. +//! +//! Stores a set of data in the Hibernation module battery-backed memory. +//! This memory is preserved when the power to the processor is turned off, +//! and can be used to store application state information which is available +//! when the processor wakes. Up to 16 32-bit words can be stored in the +//! battery-backed memory. The data can be restored by calling the +//! HibernateDataGet() function. +//! +//! \note The amount of memory available in the Hibernation module varies +//! across Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine the amount of memory available in +//! the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDataSet(unsigned long *pulData, unsigned long ulCount) +{ + unsigned long ulIdx; + + // + // Check the arguments. + // + ASSERT(ulCount <= 64); + ASSERT(pulData != 0); + + // + // Loop through all the words to be stored, storing one at a time. + // + for(ulIdx = 0; ulIdx < ulCount; ulIdx++) + { + // + // Write a word to the battery-backed storage area. + // + HWREG(HIB_DATA + (ulIdx * 4)) = pulData[ulIdx]; + + // + // Wait for write completion + // + HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Reads a set of data from the battery-backed memory of the Hibernation +//! module. +//! +//! \param pulData points to a location where the data that is read from the +//! Hibernation module is stored. +//! \param ulCount is the count of 32-bit words to read. +//! +//! This function retrieves a set of data from the Hibernation module +//! battery-backed memory that was previously stored with the HibernateDataSet() +//! function. The caller must ensure that \e pulData points to a large enough +//! memory block to hold all the data that is read from the battery-backed +//! memory. +//! +//! \note The amount of memory available in the Hibernation module varies +//! across Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine the amount of memory available in +//! the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDataGet(unsigned long *pulData, unsigned long ulCount) +{ + unsigned long ulIdx; + + // + // Check the arguments. + // + ASSERT(ulCount <= 64); + ASSERT(pulData != 0); + + // + // Loop through all the words to be restored, reading one at a time. + // + for(ulIdx = 0; ulIdx < ulCount; ulIdx++) + { + // + // Read a word from the battery-backed storage area. No delay is + // required between reads. + // + pulData[ulIdx] = HWREG(HIB_DATA + (ulIdx * 4)); + } +} + +//***************************************************************************** +// +//! Requests hibernation mode. +//! +//! This function requests the Hibernation module to disable the external +//! regulator, thus removing power from the processor and all peripherals. The +//! Hibernation module remains powered from the battery or auxiliary power +//! supply. +//! +//! The Hibernation module re-enables the external regulator when one of +//! the configured wake conditions occurs (such as RTC match or external +//! \b WAKE pin). When the power is restored the processor goes through a +//! power-on reset although the Hibernation module is not reset. The processor +//! can retrieve saved state information with the HibernateDataGet() function. +//! Prior to calling the function to request hibernation mode, the conditions +//! for waking must have already been set by using the HibernateWakeSet() +//! function. +//! +//! Note that this function may return because some time may elapse before the +//! power is actually removed, or it may not be removed at all. For this +//! reason, the processor continues to execute instructions for some time +//! and the caller should be prepared for this function to return. There are +//! various reasons why the power may not be removed. For example, if the +//! HibernateLowBatSet() function was used to configure an abort if low +//! battery is detected, then the power is not removed if the battery +//! voltage is too low. There may be other reasons, related to the external +//! circuit design, that a request for hibernation may not actually occur. +//! +//! For all these reasons, the caller must be prepared for this function to +//! return. The simplest way to handle it is to just enter an infinite loop +//! and wait for the power to be removed. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRequest(void) +{ + // + // Set the bit in the control register to cut main power to the processor. + // + HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Enables interrupts for the Hibernation module. +//! +//! \param ulIntFlags is the bit mask of the interrupts to be enabled. +//! +//! This function enables the specified interrupt sources from the Hibernation +//! module. +//! +//! The \e ulIntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b HIBERNATE_INT_WR_COMPLETE - write complete interrupt +//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt +//! - \b HIBERNATE_INT_LOW_BAT - low-battery interrupt +//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt +//! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt +//! +//! \note The \b HIBERNATE_INT_WR_COMPLETE and \b HIBERNATE_INT_RTC_MATCH_1 +//! settings are not available on all Stellaris devices. Please consult the +//! data sheet for the Stellaris device that you are using to determine if +//! these interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntEnable(unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_RTC_MATCH_1 | + HIBERNATE_INT_WR_COMPLETE))); + + // + // Set the specified interrupt mask bits. + // + HWREG(HIB_IM) |= ulIntFlags; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables interrupts for the Hibernation module. +//! +//! \param ulIntFlags is the bit mask of the interrupts to be disabled. +//! +//! This function disables the specified interrupt sources from the +//! Hibernation module. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to the HibernateIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntDisable(unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_RTC_MATCH_1 | + HIBERNATE_INT_WR_COMPLETE))); + + // + // Clear the specified interrupt mask bits. + // + HWREG(HIB_IM) &= ~ulIntFlags; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the Hibernation module interrupt. +//! +//! \param pfnHandler points to the function to be called when a hibernation +//! interrupt occurs. +//! +//! This function registers the interrupt handler in the system interrupt +//! controller. The interrupt is enabled at the global level, but individual +//! interrupt sources must still be enabled with a call to +//! HibernateIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_HIBERNATE, pfnHandler); + + // + // Enable the hibernate module interrupt. + // + IntEnable(INT_HIBERNATE); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the Hibernation module interrupt. +//! +//! This function unregisters the interrupt handler in the system interrupt +//! controller. The interrupt is disabled at the global level, and the +//! interrupt handler is longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntUnregister(void) +{ + // + // Disable the hibernate interrupt. + // + IntDisable(INT_HIBERNATE); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_HIBERNATE); +} + +//***************************************************************************** +// +//! Gets the current interrupt status of the Hibernation module. +//! +//! \param bMasked is false to retrieve the raw interrupt status, and true to +//! retrieve the masked interrupt status. +//! +//! This function returns the interrupt status of the Hibernation module. The +//! caller can use this function to determine the cause of a hibernation +//! interrupt. Either the masked or raw interrupt status can be returned. +//! +//! \return Returns the interrupt status as a bit field with the values as +//! described in the HibernateIntEnable() function. +// +//***************************************************************************** +unsigned long +HibernateIntStatus(tBoolean bMasked) +{ + // + // Read and return the Hibernation module raw or masked interrupt status. + // + if(bMasked == true) + { + return(HWREG(HIB_MIS) & 0x1f); + } + else + { + return(HWREG(HIB_RIS) & 0x1f); + } +} + +//***************************************************************************** +// +//! Clears pending interrupts from the Hibernation module. +//! +//! \param ulIntFlags is the bit mask of the interrupts to be cleared. +//! +//! This function clears the specified interrupt sources. This function must +//! be called within the interrupt handler or else the handler is called again +//! upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to the HibernateIntEnable() function. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntClear(unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_RTC_MATCH_1 | + HIBERNATE_INT_WR_COMPLETE))); + + // + // Write the specified interrupt bits into the interrupt clear register. + // + HWREG(HIB_IC) |= ulIntFlags; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Checks to see if the Hibernation module is already powered up. +//! +//! This function queries the control register to determine if the module is +//! already active. This function can be called at a power-on reset to help +//! determine if the reset is due to a wake from hibernation or a cold start. +//! If the Hibernation module is already active, then it does not need to be +//! re-enabled and its status can be queried immediately. +//! +//! The software application should also use the HibernateIntStatus() function +//! to read the raw interrupt status to determine the cause of the wake. The +//! HibernateDataGet() function can be used to restore state. These +//! combinations of functions can be used by the software to determine if the +//! processor is waking from hibernation and the appropriate action to take as +//! a result. +//! +//! \return Returns \b true if the module is already active, and \b false if +//! not. +// +//***************************************************************************** +unsigned long +HibernateIsActive(void) +{ + // + // Read the control register, and return true if the module is enabled. + // + return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0); +} + +//***************************************************************************** +// +//! Enables GPIO retention after wake from hibernate. +//! +//! Calling this function enables the GPIO pin state to be maintained during +//! hibernation and remain active even when waking from hibernation. +//! The GPIO module itself is reset upon entering hibernation and no longer +//! controls the output pin. To maintain the current output level after waking +//! from hibernation, the GPIO module must be reconfigured and then the +//! HibernateGPIORetentionDisable() function must be called to return control +//! of the GPIO pin to the GPIO module. +//! +//! \note The hibernation GPIO retention setting is not available on all +//! Stellaris devices. Please consult the data sheet to determine if the +//! device you are using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateGPIORetentionEnable(void) +{ + // + // Enable power to the pads so that pin state can be retained. + // + HWREG(HIB_CTL) |= HIB_CTL_VDD3ON; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Disables GPIO retention after wake from hibernate. +//! +//! Calling this function disables the retention of the the GPIO pin state +//! during hibernation and allows the GPIO pins to be controlled by the system. +//! If the HibernateGPIORetentionEnable() function is called before entering +//! the hibernate, this function must be called after returning from the +//! hibernate state to allow the GPIO pins to be controlled by GPIO module. +//! +//! \note The hibernate GPIO retention setting is not available on all +//! Stellaris devices. Please consult the data sheet to determine if the +//! device you are using supports this feature in the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateGPIORetentionDisable(void) +{ + // + // Disable the hibernate power to the pads. + // + HWREG(HIB_CTL) &= ~HIB_CTL_VDD3ON; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the current setting for GPIO retention. +//! +//! This function returns the current setting for GPIO retention in the +//! hibernate module. +//! +//! \note The hibernation GPIO retention setting is not available on all +//! Stellaris devices. Please consult the data sheet to determine if the +//! device you are using supports this feature in the Hibernation module. +//! +//! \return Returns true if GPIO retention is enabled and false if GPIO +//! retention is disabled. +// +//***************************************************************************** +tBoolean +HibernateGPIORetentionGet(void) +{ + // + // Read the current GPIO retention configuration. + // + if(HWREG(HIB_CTL) & HIB_CTL_VDD3ON) + { + return(true); + } + return(false); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/hibernate.h b/driverlib/hibernate.h new file mode 100644 index 0000000..bd6c237 --- /dev/null +++ b/driverlib/hibernate.h @@ -0,0 +1,167 @@ +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HIBERNATE_H__ +#define __HIBERNATE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros needed for selecting the clock source for HibernateClockSelect() +// +//***************************************************************************** +#define HIBERNATE_CLOCK_SEL_RAW 0x00000004 +#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000 + +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +#define HIBERNATE_WAKE_PIN 0x00000010 +#define HIBERNATE_WAKE_RTC 0x00000008 +#define HIBERNATE_WAKE_LOW_BAT 0x00000200 + +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +#define HIBERNATE_LOW_BAT_DETECT 0x00000020 +#define HIBERNATE_LOW_BAT_ABORT 0x000000A0 +#define HIBERNATE_LOW_BAT_1_9V 0x00000000 +#define HIBERNATE_LOW_BAT_2_1V 0x00002000 +#define HIBERNATE_LOW_BAT_2_3V 0x00004000 +#define HIBERNATE_LOW_BAT_2_5V 0x00006000 + +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +#define HIBERNATE_INT_WR_COMPLETE 0x00000010 +#define HIBERNATE_INT_PIN_WAKE 0x00000008 +#define HIBERNATE_INT_LOW_BAT 0x00000004 +#define HIBERNATE_INT_RTC_MATCH_0 0x00000001 +#define HIBERNATE_INT_RTC_MATCH_1 0x00000002 + +//***************************************************************************** +// +// Macros defining oscillator configuration options for the +// HibernateClockConfig() function. +// +//***************************************************************************** +#define HIBERNATE_OSC_LOWDRIVE 0x00040000 +#define HIBERNATE_OSC_HIGHDRIVE 0x00060000 +#define HIBERNATE_OSC_DISABLE 0x00010000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HibernateGPIORetentionEnable(void); +extern void HibernateGPIORetentionDisable(void); +extern tBoolean HibernateGPIORetentionGet(void); +extern void HibernateEnableExpClk(unsigned long ulHibClk); +extern void HibernateDisable(void); +extern void HibernateClockSelect(unsigned long ulClockInput); +extern void HibernateRTCEnable(void); +extern void HibernateRTCDisable(void); +extern void HibernateWakeSet(unsigned long ulWakeFlags); +extern unsigned long HibernateWakeGet(void); +extern void HibernateLowBatSet(unsigned long ulLowBatFlags); +extern unsigned long HibernateLowBatGet(void); +extern void HibernateRTCSet(unsigned long ulRTCValue); +extern unsigned long HibernateRTCGet(void); +extern void HibernateRTCMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch0Get(void); +extern void HibernateRTCMatch1Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch1Get(void); +extern void HibernateRTCTrimSet(unsigned long ulTrim); +extern unsigned long HibernateRTCTrimGet(void); +extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateRequest(void); +extern void HibernateIntEnable(unsigned long ulIntFlags); +extern void HibernateIntDisable(unsigned long ulIntFlags); +extern void HibernateIntRegister(void (*pfnHandler)(void)); +extern void HibernateIntUnregister(void); +extern unsigned long HibernateIntStatus(tBoolean bMasked); +extern void HibernateIntClear(unsigned long ulIntFlags); +extern unsigned long HibernateIsActive(void); +extern void HibernateRTCSSMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCSSMatch0Get(void); +extern unsigned long HibernateRTCSSGet(void); +extern void HibernateClockConfig(unsigned long ulConfig); +extern void HibernateBatCheckStart(void); +extern unsigned long HibernateBatCheckDone(void); + +//***************************************************************************** +// +// Several Hibernate module APIs have been renamed, with the original function +// name being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define HibernateEnable(a) \ + HibernateEnableExpClk(a, SysCtlClockGet()) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HIBERNATE_H__ diff --git a/driverlib/i2c.c b/driverlib/i2c.c new file mode 100644 index 0000000..5ea5d7a --- /dev/null +++ b/driverlib/i2c.c @@ -0,0 +1,1590 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2c.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/i2c.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// A mapping of I2C base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulI2CIntMap[][2] = +{ + { I2C0_MASTER_BASE, INT_I2C0 }, + { I2C1_MASTER_BASE, INT_I2C1 }, + { I2C2_MASTER_BASE, INT_I2C2 }, + { I2C3_MASTER_BASE, INT_I2C3 }, + { I2C4_MASTER_BASE, INT_I2C4 }, + { I2C5_MASTER_BASE, INT_I2C5 }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a I2C master base address. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function determines if a I2C master module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +I2CMasterBaseValid(unsigned long ulBase) +{ + return((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE) || + (ulBase == I2C2_MASTER_BASE) || (ulBase == I2C3_MASTER_BASE) || + (ulBase == I2C4_MASTER_BASE) || (ulBase == I2C5_MASTER_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a I2C slave base address. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function determines if a I2C slave module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +I2CSlaveBaseValid(unsigned long ulBase) +{ + return((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE) || + (ulBase == I2C2_SLAVE_BASE) || (ulBase == I2C3_SLAVE_BASE) || + (ulBase == I2C4_SLAVE_BASE) || (ulBase == I2C5_SLAVE_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the I2C interrupt number. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! Given a I2C base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns an I2C interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +I2CIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps I2C base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulI2CIntMap) / + sizeof(g_ppulI2CIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulI2CIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulI2CIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulI2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! This function initializes operation of the I2C Master block by configuring +//! the bus speed for the master and enabling the I2C Master block. +//! +//! If the parameter \e bFast is \b true, then the master block is set up to +//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at +//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually +//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) +//! mode, a specific command is used to switch to the faster clocks after the +//! initial communication with the slave is done at either 100 Kbps or +//! 400 Kbps. +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! This function replaces the original I2CMasterInit() API and performs the +//! same actions. A macro is provided in i2c.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast) +{ + unsigned long ulSCLFreq; + unsigned long ulTPR; + + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ulBase); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ulSCLFreq = 400000; + } + else + { + ulSCLFreq = 100000; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ulTPR = ((ulI2CClk + (2 * 10 * ulSCLFreq) - 1) / (2 * 10 * ulSCLFreq)) - 1; + HWREG(ulBase + I2C_O_MTPR) = ulTPR; + + // + // Check to see if this I2C peripheral is High-Speed enabled. If yes, also + // choose the fastest speed that is less than or equal to 3.4 Mbps. + // + if(HWREG(ulBase + I2C_O_PP) & I2C_PP_HS) + { + ulTPR = ((ulI2CClk + (2 * 3 * 3400000) - 1) / + (2 * 3 * 3400000)) - 1; + HWREG(ulBase + I2C_O_MTPR) = I2C_MTPR_HS | ulTPR; + } +} + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block by configuring +//! the slave address and enabling the I2C Slave block. +//! +//! The parameter \e ucSlaveAddr is the value that is compared against the +//! slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ulBase); + + // + // Set up the slave address. + // + HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; +} + +//***************************************************************************** +// +//! Sets the I2C slave address. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ucAddrNum determines which slave address is set. +//! \param ucSlaveAddr is the 7-bit slave address +//! +//! This function writes the specified slave address. The \e ulAddrNum field +//! dictates which slave address is configured. For example, a value of 0 +//! configures the primary address and a value of 1 configures the secondary. +//! +//! \note Not all Stellaris devices support a secondary address. Please +//! consult the device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum, + unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + ASSERT(!(ucAddrNum > 1)); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Determine which slave address is being set. + // + switch(ucAddrNum) + { + // + // Set up the primary slave address. + // + case 0: + { + HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; + break; + } + + // + // Set up and enable the secondary slave address. + // + case 1: + { + HWREG(ulBase + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ucSlaveAddr; + break; + } + } +} + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function enables operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Enable the master block. + // + HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE; +} + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This fucntion enables operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Enable the clock to the slave block. + // + HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |= + I2C_MCR_SFE; + + // + // Enable the slave. + // + HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function disables operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Disable the master block. + // + HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE); +} + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function disables operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Disable the slave. + // + HWREG(ulBase + I2C_O_SCSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &= + ~(I2C_MCR_SFE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! This function sets the handler to be called when an I2C interrupt occurs. +//! This function enables the global interrupt in the interrupt controller; +//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Determine the interrupt number based on the I2C port. + // + ulInt = I2CIntNumberGet(ulBase); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function clears the handler to be called when an I2C interrupt +//! occurs. This function also masks off the interrupt in the interrupt r +//! controlle so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Determine the interrupt number based on the I2C port. + // + ulInt = I2CIntNumberGet(ulBase); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) = 1; +} + +//***************************************************************************** +// +//! Enables individual I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Master interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt +//! - \b I2C_MASTER_INT_DATA - Data interrupt +//! +//! \note Not all Stellaris devices support all of the listed interrupt +//! sources. Please consult the device data sheet to determine if these +//! features are supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Enables individual I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Slave interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt +//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt +//! - \b I2C_SLAVE_INT_DATA - Data interrupt +//! +//! \note Not all Stellaris devices support the all of the listed interrupts. +//! Please consult the device data sheet to determine if these features are +//! supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! Disables individual I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Master interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CMasterIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Disables individual I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Slave interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CSlaveIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +tBoolean +I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CMasterIntEnableEx(). +// +//***************************************************************************** +unsigned long +I2CMasterIntStatusEx(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + I2C_O_MMIS)); + } + else + { + return(HWREG(ulBase + I2C_O_MRIS)); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +tBoolean +I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_O_SMIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_O_SRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CSlaveIntEnableEx(). +// +//***************************************************************************** +unsigned long +I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + // + // Workaround for I2C slave masked interrupt status register errata + // (7.1) for Dustdevil Rev A0 devices. + // + if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0) + { + ulValue = HWREG(ulBase + I2C_O_SRIS); + return(ulValue & HWREG(ulBase + I2C_O_SIMR)); + } + else + { + return(HWREG(ulBase + I2C_O_SMIS)); + } + } + else + { + return(HWREG(ulBase + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Stellaris + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Master interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CMasterIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_O_MICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CSlaveIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_O_SICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Sets the address that the I2C Master places on the bus. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function configures the address that the I2C Master places on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address indicates that the I2C Master is initiating a +//! read from the slave; otherwise the address indicates that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, + tBoolean bReceive) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! Reads the state of the SDA and SCL pins. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function returns the state of the I2C bus by providing the real time +//! values of the SDA and SCL pins. +//! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return Returns the state of the bus with SDA in bit position 1 and SCL in +//! bit position 0. +// +//***************************************************************************** +unsigned long +I2CMasterLineStateGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return the line state. + // + return(HWREG(ulBase + I2C_O_MBMON)); +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +tBoolean +I2CMasterBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return the busy status. + // + if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +tBoolean +I2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return the bus busy status. + // + if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulCmd command to be issued to the I2C Master module. +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The \e ucCmd parameter can be one of the following +//! values: +//! +//! - \b I2C_MASTER_CMD_SINGLE_SEND +//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \b I2C_MASTER_CMD_BURST_SEND_START +//! - \b I2C_MASTER_CMD_BURST_SEND_CONT +//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! - \b I2C_MASTER_CMD_QUICK_COMMAND +//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_QUICK_COMMAND) || + (ulCmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); + + // + // Send the command. + // + HWREG(ulBase + I2C_O_MCS) = ulCmd; +} + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, +//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or +//! \b I2C_MASTER_ERR_ARB_LOST. +// +//***************************************************************************** +unsigned long +I2CMasterErr(unsigned long ulBase) +{ + unsigned long ulErr; + + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Get the raw error state + // + ulErr = HWREG(ulBase + I2C_O_MCS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ulErr & I2C_MCS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ulErr & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) + { + return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucData data to be transmitted from the I2C Master. +//! +//! This function places the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Write the byte. + // + HWREG(ulBase + I2C_O_MDR) = ucData; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +unsigned long +I2CMasterDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! Sets the Master clock timeout value. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulValue is the number of I2C clocks before the timeout is asserted. +//! +//! This function enables and configures the clock low timeout feature in the +//! I2C peripheral. This feature is implemented as a 12-bit counter, with the +//! upper 8-bits being programmable. For example, to program a timeout of 20ms +//! with a 100kHz SCL frequency, \e ulValue would be 0x7d. +//! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Write the timeout value. + // + HWREG(ulBase + I2C_O_MCLKOCNT) = ulValue; +} + +//***************************************************************************** +// +//! Configures ACK override behavior of the I2C Slave. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bEnable enables or disables ACK override. +//! +//! This function enables or disables ACK override, allowing the user +//! application to drive the value on SDA during the ACK cycle. +//! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to determine if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Enable or disable based on bEnable. + // + if(bEnable) + { + HWREG(ulBase + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; + } + else + { + HWREG(ulBase + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; + } +} + +//***************************************************************************** +// +//! Writes the ACK value. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. +//! +//! This function puts the desired ACK value on SDA during the ACK cycle. The +//! value written is only valid when ACK override is enabled using +//! I2CSlaveACKOverride(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // ACK or NACK based on the value of bACK. + // + if(bACK) + { + HWREG(ulBase + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; + } + else + { + HWREG(ulBase + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; + } +} + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function returns the action requested from a master, if any. +//! Possible values are: +//! +//! - \b I2C_SLAVE_ACT_NONE +//! - \b I2C_SLAVE_ACT_RREQ +//! - \b I2C_SLAVE_ACT_TREQ +//! - \b I2C_SLAVE_ACT_RREQ_FBR +//! - \b I2C_SLAVE_ACT_OWN2SEL +//! - \b I2C_SLAVE_ACT_QCMD +//! - \b I2C_SLAVE_ACT_QCMD_DATA +//! +//! \note Not all Stellaris devices support the second I2C slave's own address +//! or the quick command function. Please consult the device data sheet to +//! determine if these features are supported. +//! +//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been +//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that +//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ +//! to indicate that an I2C master has requested that the I2C Slave module send +//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent +//! data to the I2C slave and the first byte following the slave's own address +//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C +//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick +//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the +//! data bit was set when the quick command was received. +// +//***************************************************************************** +unsigned long +I2CSlaveStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Return the slave status. + // + return(HWREG(ulBase + I2C_O_SCSR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ucData is the data to be transmitted from the I2C Slave +//! +//! This function places the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Write the byte. + // + HWREG(ulBase + I2C_O_SDR) = ucData; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! unsigned long. +// +//***************************************************************************** +unsigned long +I2CSlaveDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_O_SDR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/i2c.h b/driverlib/i2c.h new file mode 100644 index 0000000..f4775dc --- /dev/null +++ b/driverlib/i2c.h @@ -0,0 +1,224 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000011 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt. +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterIntEnableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CMasterIntDisableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase, + tBoolean bMasked); +extern void I2CMasterIntClearEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue); +extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable); +extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK); +extern unsigned long I2CMasterLineStateGet(unsigned long ulBase); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum, + unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2CSlaveIntDisableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase, + tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +//***************************************************************************** +// +// Several I2C APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define I2CMasterInit(a, b) \ + I2CMasterInitExpClk(a, SysCtlClockGet(), b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/driverlib/i2s.c b/driverlib/i2s.c new file mode 100644 index 0000000..ea1bff6 --- /dev/null +++ b/driverlib/i2s.c @@ -0,0 +1,1149 @@ +//***************************************************************************** +// +// i2s.c - Driver for the I2S controller. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2s_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2s.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/i2s.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Enables the I2S transmit module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function enables the transmit module for operation. The module +//! should be enabled after configuration. When the module is disabled, +//! no data or clocks are generated on the I2S signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Enable the tx FIFO service request. + // + HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN; +} + +//***************************************************************************** +// +//! Disables the I2S transmit module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function disables the transmit module for operation. The module +//! should be disabled before configuration. When the module is disabled, +//! no data or clocks are generated on the I2S signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN; +} + +//***************************************************************************** +// +//! Writes data samples to the I2S transmit FIFO with blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param ulData is the single- or dual-channel I2S data. +//! +//! This function writes a single-channel sample or combined left-right +//! samples to the I2S transmit FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2STxConfigSet(). +//! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData +//! parameter contains either the left or right sample. The left and right +//! sample alternate with each write to the FIFO, left sample first. If the +//! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or +//! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both +//! the left and right samples. If the transmit mode is +//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single +//! channel sample. +//! +//! For the compact modes, both the left and right samples are written at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no room in the transmit FIFO, then this function waits +//! in a polling loop until the data can be written. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Wait until there is space. + // + while(HWREG(ulBase + I2S_O_TXLEV) >= 16) + { + } + + // + // Write the data to the I2S. + // + HWREG(ulBase + I2S_O_TXFIFO) = ulData; +} + +//***************************************************************************** +// +//! Writes data samples to the I2S transmit FIFO without blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param ulData is the single- or dual-channel I2S data. +//! +//! This function writes a single-channel sample or combined left-right +//! samples to the I2S transmit FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2STxConfigSet(). +//! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData +//! parameter contains either the left or right sample. The left and right +//! sample alternate with each write to the FIFO, left sample first. If the +//! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or +//! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both +//! the left and right samples. If the transmit mode is +//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single- +//! channel sample. +//! +//! For the compact modes, both the left and right samples are written at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no room in the transmit FIFO, then this function returns +//! immediately without writing any data to the FIFO. +//! +//! \return The number of elements written to the I2S transmit FIFO (1 or 0). +// +//***************************************************************************** +long +I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Check for space to write. + // + if(HWREG(ulBase + I2S_O_TXLEV) < 16) + { + HWREG(ulBase + I2S_O_TXFIFO) = ulData; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Configures the I2S transmit module. +//! +//! \param ulBase is the I2S module base address. +//! \param ulConfig is the logical OR of the configuration options. +//! +//! This function is used to configure the options for the I2S transmit +//! channel. The parameter \e ulConfig is the logical OR of the following +//! options: +//! +//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. +//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether +//! the I2S transmitter is the clock master or slave. +//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per sample. +//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per word that are transferred on the data +//! line. +//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether +//! the module transmits zeroes or repeats the last sample when the FIFO is +//! empty. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK | + I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK | + I2S_CONFIG_SAMPLE_SIZE_MASK | + I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig); + + // + // Check to see if a compact mode is used. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8) + { + // + // If compact 8 mode is used, then need to adjust some bits + // before writing the config register. Also set the FIFO + // config register for 8-bit compact samples. + // + ulConfig &= ~I2S_CONFIG_MODE_MONO; + HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; + } + else + { + // + // If compact 8 mode is not used, then set the FIFO config + // register for 16 bit. This setting is okay if a compact + // mode is not used. + // + HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; + } + + // + // Write the configuration register. Because all the fields are + // specified by the configuration parameter, it is not necessary + // to do a read-modify-write. + // + HWREG(ulBase + I2S_O_TXCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which a service request is generated. +//! +//! \param ulBase is the I2S module base address. +//! \param ulLevel is the FIFO service request limit. +//! +//! This function is used to set the transmit FIFO fullness level at which a +//! service request occurs. The service request is used to generate an +//! interrupt or a DMA transfer request. The transmit FIFO generates a +//! service request when the number of items in the FIFO is less than the level +//! specified in the \e ulLevel parameter. For example, if \e ulLevel is 8, +//! then a service request is generated when there are less than 8 samples +//! remaining in the transmit FIFO. +//! +//! For the purposes of counting the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, the level must be an even number from 0 to 16. The maximum value is +//! 16, which causes a service request when there is any room in the FIFO. +//! The minimum value is 0, which disables the service request. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT(ulLevel <= 16); + + // + // Write the FIFO limit + // + HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel; +} + +//***************************************************************************** +// +//! Gets the current setting of the FIFO service request level. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the value of the transmit FIFO service +//! request level. This value is set using the I2STxFIFOLimitSet() +//! function. +//! +//! \return Returns the current value of the FIFO service request limit. +// +//***************************************************************************** +unsigned long +I2STxFIFOLimitGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the FIFO limit + // + return(HWREG(ulBase + I2S_O_TXLIMIT)); +} + +//***************************************************************************** +// +//! Gets the number of samples in the transmit FIFO. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the number of samples in the transmit FIFO. +//! For the purposes of measuring the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, normally the level is an even number from 0 to 16. If dual stereo +//! mode is used and only the left sample has been written without the matching +//! right sample, then the FIFO level is an odd value. If the FIFO level is +//! odd, it indicates a left-right sample mismatch. +//! +//! \return Returns the number of samples in the transmit FIFO, which is +//! normally an even number. +// +//***************************************************************************** +unsigned long +I2STxFIFOLevelGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the transmit FIFO level. + // + return(HWREG(ulBase + I2S_O_TXLEV)); +} + +//***************************************************************************** +// +//! Enables the I2S receive module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function enables the receive module for operation. The module should +//! be enabled after configuration. When the module is disabled, no data is +//! clocked in regardless of the signals on the I2S interface. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Enable the tx FIFO service request. + // + HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN; +} + +//***************************************************************************** +// +//! Disables the I2S receive module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function disables the receive module for operation. The module should +//! be disabled before configuration. When the module is disabled, no data is +//! clocked in regardless of the signals on the I2S interface. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN; +} + +//***************************************************************************** +// +//! Reads data samples from the I2S receive FIFO with blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param pulData points to storage for the returned I2S sample data. +//! +//! This function reads a single channel sample or combined left-right +//! samples from the I2S receive FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2SRxConfigSet(). +//! If the receive mode is \b I2S_MODE_DUAL_STEREO then the returned value +//! contains either the left or right sample. The left and right sample +//! alternate with each read from the FIFO, left sample first. If the receive +//! mode is \b I2S_MODE_COMPACT_STEREO_16 or \b I2S_MODE_COMPACT_STEREO_8, then +//! the returned data contains both the left and right samples. If the +//! receive mode is \b I2S_MODE_SINGLE_MONO then the returned data +//! contains the single channel sample. +//! +//! For the compact modes, both the left and right samples are read at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no data in the receive FIFO, then this function waits +//! in a polling loop until data is available. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Wait until there is data available. + // + while(HWREG(ulBase + I2S_O_RXLEV) == 0) + { + } + + // + // Read data from the I2S receive FIFO. + // + *pulData = HWREG(ulBase + I2S_O_RXFIFO); +} + +//***************************************************************************** +// +//! Reads data samples from the I2S receive FIFO without blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param pulData points to storage for the returned I2S sample data. +//! +//! This function reads a single channel sample or combined left-right +//! samples from the I2S receive FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2SRxConfigSet(). +//! If the receive mode is \b I2S_MODE_DUAL_STEREO then the received data +//! contains either the left or right sample. The left and right sample +//! alternate with each read from the FIFO, left sample first. If the receive +//! mode is \b I2S_MODE_COMPACT_STEREO_16 or \b I2S_MODE_COMPACT_STEREO_8, then +//! the received data contains both the left and right samples. If the +//! receive mode is \b I2S_MODE_SINGLE_MONO then the received data +//! contains the single channel sample. +//! +//! For the compact modes, both the left and right samples are read at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no data in the receive FIFO, then this function returns +//! immediately without reading any data from the FIFO. +//! +//! \return The number of elements read from the I2S receive FIFO (1 or 0). +// +//***************************************************************************** +long +I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Check for available samples. + // + if(HWREG(ulBase + I2S_O_RXLEV) != 0) + { + *pulData = HWREG(ulBase + I2S_O_RXFIFO); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Configures the I2S receive module. +//! +//! \param ulBase is the I2S module base address. +//! \param ulConfig is the logical OR of the configuration options. +//! +//! This function is used to configure the options for the I2S receive +//! channel. The parameter \e ulConfig is the logical OR of the following +//! options: +//! +//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. +//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether +//! the I2S receiver is the clock master or slave. +//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per sample. +//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per word that are transferred on the data +//! line. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK | + I2S_CONFIG_CLK_MASK | I2S_CONFIG_SAMPLE_SIZE_MASK | + I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig); + + // + // Clear out any prior config of the RX FIFO config register. + // + HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; + + // + // If mono mode is used, then the FMM bit needs to be set. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO) + { + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; + } + + // + // If a compact mode is used, then the CSS bit needs to be set. + // + else if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8) + { + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; + } + + // + // The "mono" bits must be removed from the configuration word + // prior to writing to hardware, because the RX configuration register + // does not actually use these bits. + // + ulConfig &= ~I2S_CONFIG_MODE_MONO; + + // + // Write the configuration register. Because all the fields are + // specified by the configuration parameter, it is not necessary + // to do a read-modify-write. + // + HWREG(ulBase + I2S_O_RXCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which a service request is generated. +//! +//! \param ulBase is the I2S module base address. +//! \param ulLevel is the FIFO service request limit. +//! +//! This function is used to set the receive FIFO fullness level at which a +//! service request occurs. The service request is used to generate an +//! interrupt or a DMA transfer request. The receive FIFO generates a +//! service request when the number of items in the FIFO is greater than the +//! level specified in the \e ulLevel parameter. For example, if \e ulLevel is +//! 4, then a service request is generated when there are more than 4 samples +//! available in the receive FIFO. +//! +//! For the purposes of counting the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, the level must be an even number from 0 to 16. The minimum value is +//! 0, which causes a service request when there is any data available in +//! the FIFO. The maximum value is 16, which disables the service request +//! (because there cannot be more than 16 items in the FIFO). +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT(ulLevel <= 16); + + // + // Write the FIFO limit + // + HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel; +} + +//***************************************************************************** +// +//! Gets the current setting of the FIFO service request level. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the value of the receive FIFO service +//! request level. This value is set using the I2SRxFIFOLimitSet() +//! function. +//! +//! \return Returns the current value of the FIFO service request limit. +// +//***************************************************************************** +unsigned long +I2SRxFIFOLimitGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the FIFO limit. The lower bit is masked + // because it always reads as 1 and has no meaning. + // + return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); +} + +//***************************************************************************** +// +//! Gets the number of samples in the receive FIFO. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the number of samples in the receive FIFO. +//! For the purposes of measuring the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, normally the level is an even number from 0 to 16. If dual stereo +//! mode is used and only the left sample has been read without reading the +//! matching right sample, then the FIFO level is an odd value. If the FIFO +//! level is odd, it indicates a left-right sample mismatch. +//! +//! \return Returns the number of samples in the transmit FIFO, which is +//! normally an even number. +// +//***************************************************************************** +unsigned long +I2SRxFIFOLevelGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the receive FIFO level. + // + return(HWREG(ulBase + I2S_O_RXLEV)); +} + +//***************************************************************************** +// +//! Enables the I2S transmit and receive modules for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function simultaneously enables the transmit and receive modules for +//! operation, providing a synchronized SCLK and LRCLK. The module should be +//! enabled after configuration. When the module is disabled, no data or +//! clocks are generated on the I2S signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxRxEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Enable the Tx FIFO service request. + // + HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; + + // + // Enable the Rx FIFO service request. + // + HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; + + // + // Enable the transmit and receive modules. + // + HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN; +} + +//***************************************************************************** +// +//! Disables the I2S transmit and receive modules. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function simultaneously disables the transmit and receive modules. +//! When the module is disabled, no data or clocks are generated on the I2S +//! signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxRxDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Disable the transmit and receive modules. + // + HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN); +} + +//***************************************************************************** +// +//! Configures the I2S transmit and receive modules. +//! +//! \param ulBase is the I2S module base address. +//! \param ulConfig is the logical OR of the configuration options. +//! +//! This function is used to configure the options for the I2S transmit and +//! receive channels with identical parameters. The parameter \e ulConfig is +//! the logical OR of the following options: +//! +//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. +//! - \b I2S_CONFIG_MODE_DUAL for dual-channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single-channel mono format. +//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether +//! the I2S transmitter is the clock master or slave. +//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per sample. +//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per word that are transferred on the data +//! line. +//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether +//! the module transmits zeroes or repeats the last sample when the FIFO is +//! empty. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK | + I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK | + I2S_CONFIG_SAMPLE_SIZE_MASK | + I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig); + + // + // Clear out any prior configuration of the FIFO config registers. + // + HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; + HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; + + // + // If mono mode is used, then the FMM bit needs to be set. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO) + { + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; + ulConfig &= ~(I2S_CONFIG_MODE_MONO); + } + + // + // If a compact mode is used, then the CSS bit needs to be set. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8) + { + HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS; + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; + } + + // + // Write the configuration register. Because all the fields are specified + // by the configuration parameter, it is not necessary to do a + // read-modify-write. + // + HWREG(ulBase + I2S_O_TXCFG) = ulConfig; + HWREG(ulBase + I2S_O_RXCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Selects the source of the master clock, internal or external. +//! +//! \param ulBase is the I2S module base address. +//! \param ulMClock is the logical OR of the master clock configuration +//! choices. +//! +//! This function selects whether the master clock is sourced from the device +//! internal PLL or comes from an external pin. The I2S serial bit clock +//! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master +//! clock. The transmit and receive modules can be configured independently. +//! The \e ulMClock parameter is chosen from the following: +//! +//! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT +//! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT +//! +//! \return None. +// +//***************************************************************************** +void +I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock) +{ + unsigned long ulConfig; + + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulMClock & (I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT)) == ulMClock); + + // + // Set the clock selection bits in the configuation word. + // + ulConfig = HWREG(ulBase + I2S_O_CFG) & + ~(I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT); + HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock; +} + +//***************************************************************************** +// +//! Enables I2S interrupt sources. +//! +//! \param ulBase is the I2S module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the specified I2S sources to generate interrupts. +//! The \e ulIntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b I2S_INT_RXERR for receive errors +//! - \b I2S_INT_RXREQ for receive FIFO service requests +//! - \b I2S_INT_TXERR for transmit errors +//! - \b I2S_INT_TXREQ for transmit FIFO service requests +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ | + I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + I2S_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables I2S interrupt sources. +//! +//! \param ulBase is the I2S module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the specified I2S sources for interrupt +//! generation. The \e ulIntFlags parameter can be the logical OR +//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ, +//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ | + I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the I2S interrupt status. +//! +//! \param ulBase is the I2S module base address. +//! \param bMasked is set \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the I2S interrupt status. It can return either +//! the raw or masked interrupt status. +//! +//! \return Returns the masked or raw I2S interrupt status, as a bit field +//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ, +//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ +// +//***************************************************************************** +unsigned long +I2SIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + I2S_O_MIS)); + } + else + { + return(HWREG(ulBase + I2S_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears pending I2S interrupt sources. +//! +//! \param ulBase is the I2S module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified pending I2S interrupts. This function +//! must be called in the interrupt handler to keep the interrupt from being +//! triggered again immediately upon exit. The \e ulIntFlags parameter can be +//! the logical OR of any of the following values: \b I2S_INT_RXERR, +//! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ | + I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + I2S_O_IC) = ulIntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2S controller. +//! +//! \param ulBase is the I2S module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function sets and enables the handler to be called when the I2S +//! controller generates an interrupt. Specific I2S interrupts must still be +//! enabled with the I2SIntEnable() function. It is the responsibility of the +//! interrupt handler to clear any pending interrupts with I2SIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_I2S0, pfnHandler); + + // + // Enable the I2S interface interrupt. + // + IntEnable(INT_I2S0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2S controller. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function disables and clears the handler to be called when the +//! I2S interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Disable the I2S interface interrupt. + // + IntDisable(INT_I2S0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_I2S0); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/i2s.h b/driverlib/i2s.h new file mode 100644 index 0000000..0510f49 --- /dev/null +++ b/driverlib/i2s.h @@ -0,0 +1,169 @@ +//***************************************************************************** +// +// i2s.h - Prototypes and macros for the I2S controller. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to I2STxConfigSet() and I2SRxConfigSet() +// +//***************************************************************************** +#define I2S_CONFIG_FORMAT_MASK 0x3C000000 // JST, DLY, SCP, LRP +#define I2S_CONFIG_FORMAT_I2S 0x14000000 // !JST, DLY, !SCP, LRP +#define I2S_CONFIG_FORMAT_LEFT_JUST \ + 0x00000000 // !JST, !DLY, !SCP, !LRP +#define I2S_CONFIG_FORMAT_RIGHT_JUST \ + 0x20000000 // JST, !DLY, !SCP, !LRP + +#define I2S_CONFIG_SCLK_INVERT 0x08000000 + +#define I2S_CONFIG_MODE_MASK 0x03000000 +#define I2S_CONFIG_MODE_DUAL 0x00000000 +#define I2S_CONFIG_MODE_COMPACT_16 \ + 0x01000000 +#define I2S_CONFIG_MODE_COMPACT_8 \ + 0x03000000 +#define I2S_CONFIG_MODE_MONO 0x02000000 + +#define I2S_CONFIG_EMPTY_MASK 0x00800000 +#define I2S_CONFIG_EMPTY_ZERO 0x00000000 +#define I2S_CONFIG_EMPTY_REPEAT 0x00800000 + +#define I2S_CONFIG_CLK_MASK 0x00400000 +#define I2S_CONFIG_CLK_MASTER 0x00400000 +#define I2S_CONFIG_CLK_SLAVE 0x00000000 + +#define I2S_CONFIG_SAMPLE_SIZE_MASK \ + 0x0000FC00 +#define I2S_CONFIG_SAMPLE_SIZE_32 \ + 0x00007C00 +#define I2S_CONFIG_SAMPLE_SIZE_24 \ + 0x00005C00 +#define I2S_CONFIG_SAMPLE_SIZE_20 \ + 0x00004C00 +#define I2S_CONFIG_SAMPLE_SIZE_16 \ + 0x00003C00 +#define I2S_CONFIG_SAMPLE_SIZE_8 \ + 0x00001C00 + +#define I2S_CONFIG_WIRE_SIZE_MASK \ + 0x000003F0 +#define I2S_CONFIG_WIRE_SIZE_32 0x000001F0 +#define I2S_CONFIG_WIRE_SIZE_24 0x00000170 +#define I2S_CONFIG_WIRE_SIZE_20 0x00000130 +#define I2S_CONFIG_WIRE_SIZE_16 0x000000F0 +#define I2S_CONFIG_WIRE_SIZE_8 0x00000070 + +//***************************************************************************** +// +// Values that can be passed to I2SMasterClockSelect() +// +//***************************************************************************** +#define I2S_TX_MCLK_EXT 0x00000010 +#define I2S_TX_MCLK_INT 0x00000000 +#define I2S_RX_MCLK_EXT 0x00000020 +#define I2S_RX_MCLK_INT 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to I2SIntEnable(), I2SIntDisable(), and +// I2SIntClear() +// +//***************************************************************************** +#define I2S_INT_RXERR 0x00000020 +#define I2S_INT_RXREQ 0x00000010 +#define I2S_INT_TXERR 0x00000002 +#define I2S_INT_TXREQ 0x00000001 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void I2STxEnable(unsigned long ulBase); +extern void I2STxDisable(unsigned long ulBase); +extern void I2STxDataPut(unsigned long ulBase, unsigned long ulData); +extern long I2STxDataPutNonBlocking(unsigned long ulBase, + unsigned long ulData); +extern void I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern void I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel); +extern unsigned long I2STxFIFOLimitGet(unsigned long ulBase); +extern unsigned long I2STxFIFOLevelGet(unsigned long ulBase); +extern void I2SRxEnable(unsigned long ulBase); +extern void I2SRxDisable(unsigned long ulBase); +extern void I2SRxDataGet(unsigned long ulBase, unsigned long *pulData); +extern long I2SRxDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern void I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel); +extern unsigned long I2SRxFIFOLimitGet(unsigned long ulBase); +extern unsigned long I2SRxFIFOLevelGet(unsigned long ulBase); +extern void I2STxRxEnable(unsigned long ulBase); +extern void I2STxRxDisable(unsigned long ulBase); +extern void I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern void I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock); +extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long I2SIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void I2SIntUnregister(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2S_H__ diff --git a/driverlib/interrupt.c b/driverlib/interrupt.c new file mode 100644 index 0000000..11df0b4 --- /dev/null +++ b/driverlib/interrupt.c @@ -0,0 +1,837 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/cpu.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +static const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulRegs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, + NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, + NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, + NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, + NVIC_PRI32, NVIC_PRI33, NVIC_PRI34 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulEnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt disable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulDisRegs[] = +{ + NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt pend for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulPendRegs[] = +{ + NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt unpend for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulUnpendRegs[] = +{ + NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4 +}; + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +#if defined(ewarm) +#pragma data_alignment=1024 +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#elif defined(sourcerygxx) +static __attribute__((section(".cs3.region-head.ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); +#elif defined(ccs) || defined(DOXYGEN) +#pragma DATA_ALIGN(g_pfnRAMVectors, 1024) +#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable") +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#else +static __attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! This function allows the processor to respond to interrupts. This function +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error occurs in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! This function prevents the processor from receiving interrupts. This +//! function does not affect the set of interrupts enabled in the interrupt +//! controller; it just gates the single interrupt from the controller to the +//! processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error occurs in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function is called in +//! interrupt context. Because the handler function can preempt other code, +//! care must be taken to protect memory or peripherals that are accessed by +//! the handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise the NVIC does not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts. +//! See the discussion of compile-time versus run-time interrupt handler +//! registration in the introduction to this chapter. +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long ulIdx, ulValue; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + ulValue = HWREG(NVIC_VTABLE); + for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) + { + g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) + + ulValue); + } + + // + // Point the NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = pfnHandler; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source is +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; +} + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! sub-priority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Stellaris family, three bits are available for hardware interrupt +//! prioritization and therefore priority grouping values of three through +//! seven have the same effect. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! sub-priority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism only looks at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. The remaining bits can be +//! used to sub-prioritize the interrupt sources, and may be used by the +//! hardware priority mechanism on a future part. This arrangement allows +//! priorities to migrate to different NVIC implementations without changing +//! the gross prioritization of the interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if(ulInterrupt >= 16) + { + // + // Enable the general interrupt. + // + HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if(ulInterrupt >= 16) + { + // + // Disable the general interrupt. + // + HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Returns if a peripheral interrupt is enabled. +//! +//! \param ulInterrupt specifies the interrupt to check. +//! +//! This function checks if the specified interrupt is enabled in the interrupt +//! controller. +//! +//! \return A non-zero value if the interrupt is enabled. +// +//***************************************************************************** +unsigned long +IntIsEnabled(unsigned long ulInterrupt) +{ + unsigned long ulRet; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Initialize the return value. + // + ulRet = 0; + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Check the MemManage interrupt. + // + ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Check the bus fault interrupt. + // + ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Check the usage fault interrupt. + // + ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Check the System Tick interrupt. + // + ulRet = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN; + } + else if(ulInterrupt >= 16) + { + // + // Check the general interrupt. + // + ulRet = HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) & + (1 << ((ulInterrupt - 16) & 31)); + } + return(ulRet); +} + +//***************************************************************************** +// +//! Pends an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be pended. +//! +//! The specified interrupt is pended in the interrupt controller. Pending an +//! interrupt causes the interrupt controller to execute the corresponding +//! interrupt handler at the next available time, based on the current +//! interrupt state priorities. For example, if called by a higher priority +//! interrupt handler, the specified interrupt handler is not called until +//! after the current interrupt handler has completed execution. The interrupt +//! must have been enabled for it to be called. +//! +//! \return None. +// +//***************************************************************************** +void +IntPendSet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to pend. + // + if(ulInterrupt == FAULT_NMI) + { + // + // Pend the NMI interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ulInterrupt == FAULT_PENDSV) + { + // + // Pend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Pend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if(ulInterrupt >= 16) + { + // + // Pend the general interrupt. + // + HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Un-pends an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be un-pended. +//! +//! The specified interrupt is un-pended in the interrupt controller. This +//! will cause any previously generated interrupts that have not been handled +//! yet (due to higher priority interrupts or the interrupt no having been +//! enabled yet) to be discarded. +//! +//! \return None. +// +//***************************************************************************** +void +IntPendClear(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to unpend. + // + if(ulInterrupt == FAULT_PENDSV) + { + // + // Unpend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Unpend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if(ulInterrupt >= 16) + { + // + // Unpend the general interrupt. + // + HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Sets the priority masking level +//! +//! \param ulPriorityMask is the priority level that is masked. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level are masked. Masking +//! interrupts can be used to globally disable a set of interrupts with +//! priority below a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. +//! +//! The hardware priority mechanism only looks at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityMaskSet(unsigned long ulPriorityMask) +{ + CPUbasepriSet(ulPriorityMask); +} + +//***************************************************************************** +// +//! Gets the priority masking level +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. +//! +//! The hardware priority mechanism only looks at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +unsigned long +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/interrupt.h b/driverlib/interrupt.h new file mode 100644 index 0000000..c3cabb8 --- /dev/null +++ b/driverlib/interrupt.h @@ -0,0 +1,93 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean IntMasterEnable(void); +extern tBoolean IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); +extern unsigned long IntIsEnabled(unsigned long ulInterrupt); +extern void IntPendSet(unsigned long ulInterrupt); +extern void IntPendClear(unsigned long ulInterrupt); +extern void IntPriorityMaskSet(unsigned long ulPriorityMask); +extern unsigned long IntPriorityMaskGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/driverlib/lpc.c b/driverlib/lpc.c new file mode 100644 index 0000000..aa50a98 --- /dev/null +++ b/driverlib/lpc.c @@ -0,0 +1,1548 @@ +//***************************************************************************** +// +// lpc.c - Driver for the Low Pin Count (LPC) module. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup lpc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_lpc.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/lpc.h" + +//***************************************************************************** +// +//! \internal +//! Checks an LPC Channel. +//! +//! \param ulChannel is the LPC channel identifier. +//! +//! This function determines if a channel identifier is valid. This function +//! does not check for Channel 7 (COMx). +//! +//! \return Returns \b true if the channel identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +LPCChannelValid(unsigned long ulChannel) +{ + return((ulChannel == LPC_CHAN_CH0) || + (ulChannel == LPC_CHAN_CH1) || + (ulChannel == LPC_CHAN_CH2) || + (ulChannel == LPC_CHAN_CH3) || + (ulChannel == LPC_CHAN_CH4) || + (ulChannel == LPC_CHAN_CH5) || + (ulChannel == LPC_CHAN_CH6) || + (ulChannel == LPC_CHAN_CH7)); +} +#endif // #ifdef DEBUG + +//***************************************************************************** +// +//! Sets the configuration of the LPC module. +//! +//! \param ulBase is the base address of the LPC module. +//! \param ulConfig specifies the configuration of the LPC module. +//! +//! This function configures the LPC module for basic operation. The +//! configuration of individual channels is handled in a separate function. +//! +//! The \e ulConfig parameter is the logical OR of the following values: +//! - \b LPC_CFG_WAKE - Force assertion of the LPC0CLKRUN signal when the +//! LPC bus is powered down (LPC0PD is asserted). +//! +//! \return None. +// +//***************************************************************************** +void +LPCConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulConfig & ~(LPC_CFG_WAKE)) == 0); + + // + // Configure the appropriate LPC Control Register fields. + // + ulTemp = HWREG(ulBase + LPC_O_CTL); + ulTemp &= ~LPC_CTL_WAKE; + ulTemp |= (ulConfig & LPC_CTL_WAKE); + HWREG(ulBase + LPC_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the current configuration of the LPC module. +//! +//! \param ulBase is the base address of the LPC module. +//! +//! This function queries the control register of the LPC module and returns +//! a bit-mapped value. +//! +//! \sa The description of the LPCConfigSet() function provides detailed +//! information for the bit-mapped configuration values that are returned. +//! +//! \return Returns the bit-mapped LPC module configuration value. +// +//***************************************************************************** +unsigned long +LPCConfigGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return the configuration value + // + return((HWREG(ulBase + LPC_O_CTL) & LPC_CTL_WAKE)); +} + +//***************************************************************************** +// +//! Sets the Status Block Address for the LPC peripheral. +//! +//! \param ulBase is the base address of the LPC module. +//! \param ulAddress is the host address to use for the block status. +//! \param bEnabled indicates whether the block address feature should +//! be enabled. +//! +//! This function sets the LPC block address register and optionally enables +//! it. +//! +//! \return None. +// +//***************************************************************************** +void +LPCStatusBlockAddressSet(unsigned long ulBase, unsigned long ulAddress, + tBoolean bEnabled) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulAddress & ~0xFFFFFFFE) == 0); + + // + // Set (and optionally enable) the Status Block Address + // + HWREG(ulBase + LPC_O_STSADDR) = (ulAddress | (bEnabled ? 1 : 0)); +} + +//***************************************************************************** +// +//! Gets the Status Block Address for the LPC peripheral. +//! +//! \param ulBase is the base address of the LPC module. +//! +//! This function returns the LPC block address register. The LSB is used +//! to indicate whether this feature has been enabled or not. +//! +//! \return None. +// +//***************************************************************************** +unsigned +LPCStatusBlockAddressGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return the Status Block Address, including the enable bit. + // + return(HWREG(ulBase + LPC_O_STSADDR)); +} + +//***************************************************************************** +// +//! Returns the status of the LPC module. +//! +//! \param ulBase is the base address of the LPC module. +//! \param pulCount is a pointer to storage for the channel count. +//! \param pulPoolSize is a pointer to storage for the register pool size. +//! +//! This function reads the value of the LPC Status register, calculates the +//! number of channels and buffer pool size, and then returns the raw status +//! value. +//! +//! \return Returns the contents of the LPC Status register. +// +//***************************************************************************** +unsigned long +LPCStatusGet(unsigned long ulBase, unsigned long *pulCount, + unsigned long *pulPoolSize) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get a snapshot of the status register. + // + ulStatus = HWREG(ulBase + LPC_O_STS); + + // + // Extract the channel count from the status, including COMx channel. + // + if(pulCount) + { + *pulCount = (((ulStatus & LPC_STS_CHCNT_M) >> LPC_STS_CHCNT_S) + 1); + } + + // + // Extract/Calculate the register pool size. + // + if(pulPoolSize) + { + *pulPoolSize = (((ulStatus & LPC_STS_POOLSZ_M) >> 16) * 256); + } + + // + // Return the raw status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Generates a pulse on the SCIn signal. +//! +//! \param ulBase is the base address of the LPC module. +//! \param ulCount is the number used to generate the pulse width value. +//! +//! This function generates a pulse on the SCIn interrupt pin. The width of +//! the pulse is (2 << \e ulCount) LPC Clock Periods, where \e ulCount can take +//! on the value of 0, 1, 2, or 3. So, the pulse width is 2, 4, 8, or 16 clock +//! periods. +//! +//! \return None. +// +//***************************************************************************** +void +LPCSCIAssert(unsigned long ulBase, unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(ulCount <= 3); + + // + // Wait for any previous pulse to be completed, by checking the SCI bit + // (which is a self-clearing bit that is used to generate the pulse). + // + while(HWREG(ulBase + LPC_O_CTL) & LPC_CTL_SCI) + { + } + + // + // Set the count value first, prior to enabling the pulse. + // + HWREG(ulBase + LPC_O_CTL) &= ~LPC_CTL_SCICNT_M; + HWREG(ulBase + LPC_O_CTL) |= (ulCount << 10); + + // + // Now, generate the pulse by setting the SCI bit. + // + HWREG(ulBase + LPC_O_CTL) |= LPC_CTL_SCI; +} + +//***************************************************************************** +// +//! Configure the LPC IRQ operation. +//! +//! \param ulBase is the base address of the LPC module. +//! \param bIRQPulse is a flag to indicate the manual IRQ bits should be +//! cleared after they have been sent (in an SIRQ frame). +//! \param bIRQOnChange is a flag to indicate that an SIRQ frame should be +//! sent whenever any IRQ bits (manual/auto) change status. +//! +//! This function configures the LPC IRQs. If the \e bIRQPulse parameter is +//! \b true, then manual IRQ values are cleared after they are sent. If the +//! \e bIRQOnChange parameter is true, then IRQ values (manual and/or +//! automatic) are sent when a change is detected. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse, tBoolean bIRQOnChange) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Setup IRQ pulse configuration. + // + if(bIRQPulse) + { + HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_PULSE; + } + else + { + HWREG(ulBase + LPC_O_IRQCTL) &= ~LPC_IRQCTL_PULSE; + } + + // + // Setup IRQ on-change configuration. + // + if(bIRQOnChange) + { + HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_ONCHG; + } + else + { + HWREG(ulBase + LPC_O_IRQCTL) &= ~LPC_IRQCTL_ONCHG; + } +} + +//***************************************************************************** +// +//! Set the manual LPC IRQ bits. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIRQ specifies the IRQ bits that should be set. +//! +//! This function sets the IRQ bits that are sent in the SERIRQ frame. The +//! value in the \e ulIRQ register is OR-ed into the existing manual IRQ +//! setting. The value for the \e ulIRQ parameter can be any combination of +//! the following values: \b LPC_IRQ15, \b LPC_IRQ14, \b LPC_IRQ13, +//! \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, \b LPC_IRQ8, +//! \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, \b LPC_IRQ3, +//! \b LPC_IRQ2, \b LPC_IRQ1, or \b LPC_IRQ0. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current IRQ configuration, mask off the bits that we are to + // be operating on, set/clear them as appropriate, then rewrite the + // register. + // + ulTemp = HWREG(ulBase + LPC_O_IRQCTL); + ulTemp |= (ulIRQ & 0xFFFF0000); + HWREG(ulBase + LPC_O_IRQCTL) = ulTemp; +} + +//***************************************************************************** +// +//! Clear the manual LPC IRQ bits. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIRQ specifies the IRQ bits that should be cleared. +//! +//! This function clears the IRQ bits that are sent in the SERIRQ frame. The +//! value in the \e ulIRQ register is OR-ed into the existing manual IRQ +//! setting. The value for the \e ulIRQ parameter can be any combination of +//! the following values: \b LPC_IRQ15, \b LPC_IRQ14, \b LPC_IRQ13, +//! \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, \b LPC_IRQ8, +//! \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, \b LPC_IRQ3, +//! \b LPC_IRQ2, \b LPC_IRQ1, or \b LPC_IRQ0. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current IRQ configuration, mask off the bits that we are to + // be operating on, set/clear them as appropriate, then rewrite the + // register. + // + ulTemp = HWREG(ulBase + LPC_O_IRQCTL); + ulTemp &= ~(ulIRQ & 0xFFFF0000); + HWREG(ulBase + LPC_O_IRQCTL) = ulTemp; +} + +//***************************************************************************** +// +//! Get the configuration and status of the IRQ signals +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function returns the LPC module's SERIRQ status. The value returned +//! is a combination of the following values: \b LPC_IRQ15, \b LPC_IRQ14, +//! \b LPC_IRQ13, \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, +//! \b LPC_IRQ8, \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, +//! \b LPC_IRQ3, \b LPC_IRQ2, \b LPC_IRQ1, \b LPC_IRQ0, \b LPC_IRQ_BUSY, or +//! \b LPC_IRQ_CONT. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +LPCIRQGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Simply read the registers and return the values. + // + return(HWREG(ulBase + LPC_O_IRQST)); +} + +//***************************************************************************** +// +//! Trigger a manual SIRQ frame. +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function forces the sending of an SIRQ frame using whatever values are +//! currently set (auto and/or manual). +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQSend(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Set the bit to force the sending of an SIRQ frame. + // + HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_SND; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the LPC module. +//! +//! \param ulBase specifies the LPC module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! LPC interrupt occurs. +//! +//! This function registers the handler to be called when an LPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific LPC interrupts must be enabled via LPCIntEnable(). +//! If necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via LPCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_LPC0, pfnHandler); + + // + // Enable the LPC interrupt. + // + IntEnable(INT_LPC0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the LPC module. +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function unregisters the handler to be called when an LPC interrupt +//! occurs. This fucntion also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Disable the LPC interrupt. + // + IntDisable(INT_LPC0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_LPC0); +} + +//***************************************************************************** +// +//! Enables individual LPC interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated LPC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter can be any of the following values: +//! \b LPC_INT_RST, \b LPC_INT_SLEEP, \b LPC_INT_COMx, \b LPC_INT_SIRQ, +//! \b LPC_INT_CHn_EP_TO_HOST, \b LPC_INT_CHn_EP_FROM_DATA, +//! \b LPC_INT_CHn_EP_FROM_CMD, \b LPC_INT_CHn_MB_HOST_WON, +//! \b LPC_INT_CHn_MB_HOST_WRITE, \b LPC_INT_CHn_MB_HOST_READ, or +//! \b LPC_INT_CHn_MB_MCU_LOST, where \b CHn can be \b CH6, \b CH5, \b CH4, +//! \b CH3, \b CH2, \b CH1, or \b CH0. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current mask value. + // + HWREG(ulBase + LPC_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual LPC interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated LPC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \sa The description of the LPCIntEnable() function provides detailed +//! information for the bit-mapped values in \e ulIntFlags. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + LPC_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the LPC module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the LPC module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! The interpretation of the LPC_INT_CHn fields varies based on the type +//! value programed for the specific Channel. +//! +//! \sa The description of the LPCIntEnable() function provides detailed +//! information for the bit-mapped values returned by this function. +//! +//! \return The current interrupt status. +// +//***************************************************************************** +unsigned long +LPCIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + LPC_O_MIS)); + } + else + { + return(HWREG(ulBase + LPC_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears LPC interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified LPC interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \sa The description of the LPCIntEnable() function provides detailed +//! information for the bit-mapped values in \e ulIntFlags. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + LPC_O_IC) = ulIntFlags; +} + +//***************************************************************************** +// +//! Enables an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to enable. +//! +//! The specified LPC Channel is enabled. +//! +//! The value for the \e ulChannel parameter can be any one of the following +//! values: \b LPC_CHAN_CH0, \b LPC_CHAN_CH1, \b LPC_CHAN_CH2, +//! \b LPC_CHAN_CH3, \b LPC_CHAN_CH4, \b LPC_CHAN_CH5, \b LPC_CHAN_CH6 or +//! \b LPC_CHAN_CH7. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Enable the specified channel. + // + HWREG(ulBase + LPC_O_CTL) |= (1 << ulChannel); +} + +//***************************************************************************** +// +//! Disables an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to disable. +//! +//! This function disables the specified LPC Channel. +//! +//! \sa The description of the LPCChannelEnable() function provides detailed +//! information for the values that can be used for the \e ulChannel parameter. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Disable the specified channel. + // + HWREG(ulBase + LPC_O_CTL) &= ~(1 << ulChannel); +} + +//***************************************************************************** +// +//! Sets the configuration of an LPC Channel as an endpoint. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param ulConfig specifies configuration options required for the endpoint. +//! \param ulOffset specifies the offset from the beginning of the buffer pool +//! for this endpoint's data. +//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this +//! channel. +//! +//! This function enables the specified LPC Channel as an endpoint. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelConfigEPSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig, unsigned long ulAddress, + unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulConfig & ~(LPC_CH0CTL_IRQSEL1_M | LPC_CH0CTL_IRQSEL0_M | + LPC_CH0CTL_IRQEN1 | LPC_CH0CTL_IRQEN0_M)) == 0); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256) - 4)); + + // + // Convert the byte offset address into a half-word + // offset address and add into the control word. + // + ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) & + LPC_CH0CTL_OFFSET_M); + + // + // Write the final control value into the control word for + // the channel. + // + HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig; + + // + // Setup the IO and/or MEM address to match for this channel. + // + HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress; +} + +//***************************************************************************** +// +//! Sets the configuration of an LPC Channel as a mailbox. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param ulConfig specifies configuration options required for the endpoint. +//! \param ulOffset specifies the offset from the beginning of the buffer pool +//! for this endpoint's data. +//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this +//! channel. +//! +//! This function enables the specified LPC Channel as a mailbox. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelConfigMBSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig, unsigned long ulAddress, + unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulConfig & ~(LPC_CH0CTL_IRQSEL1_M | LPC_CH0CTL_IRQSEL1_M | + LPC_CH0CTL_IRQSEL0_M | + LPC_CH0CTL_IRQEN2 | LPC_CH0CTL_IRQEN1 | + LPC_CH0CTL_IRQEN0_M | + LPC_CH0CTL_ARBDIS | LPC_CH0CTL_AMASK_M)) == 0); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256) - 4)); + + // + // Convert the byte offset address into a half-word + // offset address and add into the control word. + // + ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) & + LPC_CH0CTL_OFFSET_M); + + // + // Set the configuration bit that enables Mailbox mode. + // + ulConfig |= LPC_CH0CTL_TYPE; + + // + // Write the final control value into the control word for + // the channel. + // + HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig; + + // + // Setup the IO and/or MEM address to match for this channel. + // + HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress; +} + +//***************************************************************************** +// +//! Sets the configuration of an LPC Channel as a COMx. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param ulConfig specifies configuration options required for the endpoint. +//! \param ulOffset specifies the offset from the beginning of the buffer pool +//! for this endpoint's data. +//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this +//! channel. +//! \param ulCOMxMode specifies the COMx mode to be used. +//! +//! The specified LPC Channel is enabled as a COMx. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelConfigCOMxSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig, unsigned long ulAddress, + unsigned long ulOffset, unsigned long ulCOMxMode) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT(ulChannel == LPC_CHAN_COMx); + ASSERT((ulConfig & ~(LPC_CH7CTL_IRQSEL1_M | LPC_CH7CTL_IRQSEL0_M | + LPC_CH7CTL_CX | LPC_CH7CTL_IRQEN1 | + LPC_CH7CTL_IRQEN0_M)) == 0); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256) - 4)); + ASSERT((ulCOMxMode & ~LPC_DMACX_CXACT_M) == 0); + + // + // Convert the byte offset address into a half-word + // offset address and add into the control word. + // + ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) & + LPC_CH0CTL_OFFSET_M); + + // + // Write the final control value into the control word for + // the channel. + // + HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig; + + // + // Setup the IO and/or MEM address to match for this channel. + // + HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress; + + // + // Configure the COMx Mode for this channel. + // + ulTemp = HWREG(ulBase + LPC_O_DMACX); + ulTemp &= ~LPC_DMACX_CXACT_M; + ulTemp |= ulCOMxMode; + ulTemp |= LPC_DMACX_COMX; + HWREG(ulBase + LPC_O_DMACX) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the configuration of an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param pulOffset is a pointer to storage for the channel pool offset. +//! \param pulAddress is a pointer to storage for the channel bus address. +//! \param pulCOMxMode is a pointer to storage for the channel COMx mode. +//! +//! This function determines and returns the configuration for the specified +//! channel. +//! +//! \return Returns the bit-mapped channel control register value. +// +//***************************************************************************** +unsigned long +LPCChannelConfigGet(unsigned long ulBase, unsigned long ulChannel, + unsigned long *pulAddress, unsigned long *pulOffset, + unsigned long *pulCOMxMode) +{ + unsigned long ulConfig; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Read the channel control register. + // + ulConfig = HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)); + + // + // Get the buffer pool offset value. + // + if(pulOffset) + { + *pulOffset = ((ulConfig & LPC_CH0CTL_OFFSET_M) >> + (LPC_CH0CTL_OFFSET_S - 1)); + } + + // + // Get the IO/Memory address that this endpoint responds to. + // + if(pulAddress) + { + *pulAddress = HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)); + } + + // + // Configure the COMx Mode for this channel. + // + if(pulCOMxMode && (ulChannel == LPC_CHAN_COMx)) + { + *pulCOMxMode = (HWREG(ulBase + LPC_O_DMACX) & 0x00070000); + } + + // + // Return the raw config value. + // + return(ulConfig); +} + +//***************************************************************************** +// +//! Gets the absolute base address of the channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! +//! Thos function calculates the absolute address of the channel pool from the +//! channel configuration setting and returns it. +//! +//! \return Returns the absolute base address of the channel pool. +// +//***************************************************************************** +unsigned long +LPCChannelPoolAddressGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulAddress; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Read the channel control register. + // + ulAddress = HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)); + + // + // Mask off the channel offset portion and shift it into a byte + // offset (stored as half-word offset). + // + ulAddress = ((ulAddress & LPC_CH0CTL_OFFSET_M) >> + (LPC_CH0CTL_OFFSET_S - 1)); + + // + // Add the LPC and Buffer Pool base address to get the final + // address to return. + // + ulAddress += (ulBase + LPC_O_POOL); + + // + // Return the address to the calling routine. + // + return(ulAddress); +} + +//***************************************************************************** +// +//! Reads the status word from an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC Channel. +//! +//! This function reads the status word from an LPC channel and returns it to +//! the caller. +//! +//! \return content of the channel status register. +// +//***************************************************************************** +unsigned long +LPCChannelStatusGet(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Read the half-word status from the LPC Channel + // + return (HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10))); +} + +//***************************************************************************** +// +//! Sets the user bits in the status word (16-bits) of an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC Channel. +//! \param ulStatus is the user bit values to set. +//! +//! This function sets the selected user bits of the status word for an LPC +//! channel. +//! +//! \return None +// +//***************************************************************************** +void +LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulStatus) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0); + + // + // Read the status from the LPC Channel, and set new values for + // the user bits. + // + ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)); + ulTemp |= ulStatus; + HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)) = ulTemp; +} + +//***************************************************************************** +// +//! Clears the user bits in the status word (16-bits) of an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC Channel. +//! \param ulStatus is the user bit values to clear. +//! +//! This function sets the selected user bits of the status word for an LPC +//! channel. +//! +//! \return None +// +//***************************************************************************** +void +LPCChannelStatusClear(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulStatus) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0); + + // + // Read the status from the LPC Channel, and set new values for + // the user bits. + // + ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)); + ulTemp &= ~ulStatus; + HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)) = ulTemp; +} + +//***************************************************************************** +// +//! Sets the configuration of DMA for LPC channels. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulConfig specifies the DMA channel configuration. +//! \param ulMask specifies the configuration mask to be used. +//! +//! This function sets the specified DMA channel operation based on the +//! \e ulConfig parameter. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelDMAConfigSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMask) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulConfig & ~0x000000FF) == 0); + ASSERT((ulConfig & 0x00000003) != 0x00000003); + ASSERT((ulConfig & 0x0000000C) != 0x0000000C); + ASSERT((ulConfig & 0x00000030) != 0x00000030); + ASSERT((ulConfig & 0x000000C0) != 0x000000C0); + ASSERT((ulMask & ~0x000000FF) == 0); + + // + // Get the current mask value. + // + ulTemp = HWREG(ulBase + LPC_O_DMACX); + ulTemp &= ~ulMask; + ulTemp |= (ulConfig & ulMask); + HWREG(ulBase + LPC_O_DMACX) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the configuration of DMA for LPC channels. +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function returns the configuration of the LPC DMA channels. +//! +//! \return Returns the bit-mapped DMA channel configuration. +// +//***************************************************************************** +unsigned long +LPCChannelDMAConfigGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current mask value. + // + return(HWREG(ulBase + LPC_O_DMACX) & 0x000000FF); +} + +//***************************************************************************** +// +//! Reads a byte from the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! +//! This function reads a byte from the channel pool. +//! +//! \return Returns the byte read from the pool memory. +// +//***************************************************************************** +unsigned char +LPCByteRead(unsigned long ulBase, unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Return the byte from the LPC Buffer Pool. + // + return(HWREGB(ulBase + LPC_O_POOL + ulOffset)); +} + +//***************************************************************************** +// +//! Writes a byte to the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! \param ucData specifies the byte to write. +//! +//! This function writes a byte to the channel pool. +//! +//! \return None +// +//***************************************************************************** +void +LPCByteWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Write the byte to the LPC Buffer Pool. + // + HWREGB(ulBase + LPC_O_POOL + ulOffset) = ucData; +} + +//***************************************************************************** +// +//! Reads a half-word from the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! +//! This function reads a half-word from the channel pool. The \e ulOffset +//! specified must be half-word aligned. +//! +//! \return Returns the half-word read from the pool memory. +// +//***************************************************************************** +unsigned short +LPCHalfWordRead(unsigned long ulBase, unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 1) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Return the half-word from the LPC Buffer Pool. + // + return(HWREGH(ulBase + LPC_O_POOL + ulOffset)); +} + +//***************************************************************************** +// +//! Writes a half-word to the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! \param usData specifies the byte to write. +//! +//! This function writes a half-word to the channel pool. The \e ulOffset +//! specified must be half-word aligned. +//! +//! \return None +// +//***************************************************************************** +void +LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned short usData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 1) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Write the half-word to the LPC Buffer Pool. + // + HWREGH(ulBase + LPC_O_POOL + ulOffset) = usData; +} + +//***************************************************************************** +// +//! Reads a word from the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! +//! This function reads a word from the channel pool. The \e ulOffset +//! specified must be word aligned. +//! +//! \return Returns the word read from the pool memory. +// +//***************************************************************************** +unsigned long +LPCWordRead(unsigned long ulBase, unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Return the word from the LPC Buffer Pool. + // + return(HWREG(ulBase + LPC_O_POOL + ulOffset)); +} + +//***************************************************************************** +// +//! Writes a word to the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! \param ulData specifies the word to write. +//! +//! This function writes a word to the channel pool. The \e ulOffset +//! specified must be word aligned. +//! +//! \return None +// +//***************************************************************************** +void +LPCWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 1) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Write the word to the LPC Buffer Pool. + // + HWREG(ulBase + LPC_O_POOL + ulOffset) = ulData; +} + +//***************************************************************************** +// +//! Enables individual COMx interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated COMx interrupt sources to trigger the +//! COMx interrupt in the primary LPC interrupt registers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulIntFlags & ~(LPC_DMACX_CXEM | LPC_DMACX_CXTXEM | + LPC_DMACX_CXRXEM)) == 0); + + // + // Get the current mask value. + // + HWREG(ulBase + LPC_O_DMACX) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual COMx interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated COMx interrupt sources from triggering +//! the COMx interrupt in the primary LPC interrupt registers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulIntFlags & ~(LPC_DMACX_CXEM | LPC_DMACX_CXTXEM | + LPC_DMACX_CXRXEM)) == 0); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + LPC_O_DMACX) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current COMx interrupt status. +//! +//! \param ulBase specifies the LPC module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the COMx module. +//! +//! \return The current interrupt status. +// +//***************************************************************************** +unsigned long +LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + ulStatus = HWREG(ulBase + LPC_O_DMACX); + if(bMasked) + { + ulStatus = ulStatus & (ulStatus << 4); + } + return(ulStatus & (LPC_DMACX_CXRES | LPC_DMACX_CXTXRES | + LPC_DMACX_CXRXRES)); +} + +//***************************************************************************** +// +//! Clears COMx interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified COMx interrupt sources so that they no +//! longer assert. +//! +//! \return None. +// +//***************************************************************************** +void +LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulIntFlags & ~(LPC_DMACX_CXRES | LPC_DMACX_CXTXRES | + LPC_DMACX_CXRXRES)) == 0); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + LPC_O_DMACX) |= ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/lpc.h b/driverlib/lpc.h new file mode 100644 index 0000000..97a92e0 --- /dev/null +++ b/driverlib/lpc.h @@ -0,0 +1,485 @@ +//***************************************************************************** +// +// lpc.h - Prototypes for the Low Pin Count (LPC) driver. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __LPC_H__ +#define __LPC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to LPCConfigSet as the ulConfig value, and +// returned from LPCConfigGet. +// +//***************************************************************************** +#define LPC_CFG_WAKE 0x00000100 // Restart the LPC Bus + +//***************************************************************************** +// +// Values that can be returned from LPCStatus. +// +//***************************************************************************** +#define LPC_STATUS_RST 0x00000400 // LPC is in Reset +#define LPC_STATUS_BUSY 0x00000200 // LPC is Busy +#define LPC_STATUS_SLEEP 0x00000100 // LPC is in Sleep Mode +#define LPC_STATUS_CA7 0x00000080 // Channel 7 Active +#define LPC_STATUS_CA6 0x00000040 // Channel 6 Active +#define LPC_STATUS_CA5 0x00000020 // Channel 5 Active +#define LPC_STATUS_CA4 0x00000010 // Channel 4 Active +#define LPC_STATUS_CA3 0x00000008 // Channel 3 Active +#define LPC_STATUS_CA2 0x00000004 // Channel 2 Active +#define LPC_STATUS_CA1 0x00000002 // Channel 1 Active +#define LPC_STATUS_CA0 0x00000001 // Channel 0 Active + +//***************************************************************************** +// +// Values that can be passed to LPCIRQSet and LPCIRQClear in the ulIRQ +// parameter and returned from LPCIRQGet. +// +//***************************************************************************** +#define LPC_IRQ15 0x80000000 // Serial IRQ15 +#define LPC_IRQ14 0x40000000 // Serial IRQ14 +#define LPC_IRQ13 0x20000000 // Serial IRQ13 +#define LPC_IRQ12 0x10000000 // Serial IRQ12 +#define LPC_IRQ11 0x08000000 // Serial IRQ11 +#define LPC_IRQ10 0x04000000 // Serial IRQ10 +#define LPC_IRQ9 0x02000000 // Serial IRQ9 +#define LPC_IRQ8 0x01000000 // Serial IRQ8 +#define LPC_IRQ7 0x00800000 // Serial IRQ7 +#define LPC_IRQ6 0x00400000 // Serial IRQ6 +#define LPC_IRQ5 0x00200000 // Serial IRQ5 +#define LPC_IRQ4 0x00100000 // Serial IRQ4 +#define LPC_IRQ3 0x00080000 // Serial IRQ3 +#define LPC_IRQ2 0x00040000 // Serial IRQ2 +#define LPC_IRQ1 0x00020000 // Serial IRQ1 +#define LPC_IRQ0 0x00010000 // Serial IRQ0 + +//***************************************************************************** +// +// Addition values that can be returned from LPCIRQGet. +// +//***************************************************************************** +#define LPC_IRQ_BUSY 0x00000004 // SERIRQ frame in progress +#define LPC_IRQ_CONT 0x00000001 // SERIRQ in Continuous Mode + +//***************************************************************************** +// +// Values that can be passed as the ulChannel parameter in LPCChannel... +// API calls. +// +//***************************************************************************** +#define LPC_CHAN_CH0 0 // LPC Channel 0 +#define LPC_CHAN_CH1 1 // LPC Channel 1 +#define LPC_CHAN_CH2 2 // LPC Channel 2 +#define LPC_CHAN_CH3 3 // LPC Channel 3 +#define LPC_CHAN_CH4 4 // LPC Channel 4 +#define LPC_CHAN_CH5 5 // LPC Channel 5 +#define LPC_CHAN_CH6 6 // LPC Channel 6 +#define LPC_CHAN_CH7 7 // LPC Channel 7 (COMx) +#define LPC_CHAN_COMx 7 // LPC Channel 7 (COMx) + +//***************************************************************************** +// +// Values that can be passed as part of the ulConfig parameter in the +// LPCChannelConfig... functions. +// +//***************************************************************************** +#define LPC_CHAN_IRQSEL2_NONE 0x00000000 // LPC Channel IRQSEL2 Disabled +#define LPC_CHAN_IRQSEL2_IRQ0 0x00080000 // LPC Channel IRQSEL2 IRQ0 +#define LPC_CHAN_IRQSEL2_IRQ1 0x10080000 // LPC Channel IRQSEL2 IRQ1 +#define LPC_CHAN_IRQSEL2_IRQ2 0x20080000 // LPC Channel IRQSEL2 IRQ2 +#define LPC_CHAN_IRQSEL2_IRQ3 0x30080000 // LPC Channel IRQSEL2 IRQ3 +#define LPC_CHAN_IRQSEL2_IRQ4 0x40080000 // LPC Channel IRQSEL2 IRQ4 +#define LPC_CHAN_IRQSEL2_IRQ5 0x50080000 // LPC Channel IRQSEL2 IRQ5 +#define LPC_CHAN_IRQSEL2_IRQ6 0x60080000 // LPC Channel IRQSEL2 IRQ6 +#define LPC_CHAN_IRQSEL2_IRQ7 0x70080000 // LPC Channel IRQSEL2 IRQ7 +#define LPC_CHAN_IRQSEL2_IRQ8 0x80080000 // LPC Channel IRQSEL2 IRQ8 +#define LPC_CHAN_IRQSEL2_IRQ9 0x90080000 // LPC Channel IRQSEL2 IRQ9 +#define LPC_CHAN_IRQSEL2_IRQ10 0xA0080000 // LPC Channel IRQSEL2 IRQ10 +#define LPC_CHAN_IRQSEL2_IRQ11 0xB0080000 // LPC Channel IRQSEL2 IRQ11 +#define LPC_CHAN_IRQSEL2_IRQ12 0xC0080000 // LPC Channel IRQSEL2 IRQ12 +#define LPC_CHAN_IRQSEL2_IRQ13 0xD0080000 // LPC Channel IRQSEL2 IRQ13 +#define LPC_CHAN_IRQSEL2_IRQ14 0xE0080000 // LPC Channel IRQSEL2 IRQ14 +#define LPC_CHAN_IRQSEL2_IRQ15 0xF0080000 // LPC Channel IRQSEL2 IRQ15 + +#define LPC_CHAN_COMxIRQ_DISABLE \ + 0x00000000 // LCP Channel COMx IRQ Disabled +#define LPC_CHAN_COMxIRQ_ENABLE 0x00080000 // LCP Channel COMx IRQ Enabled + +#define LPC_CHAN_IRQSEL1_NONE 0x00000000 // LPC Channel IRQSEL1 Disabled +#define LPC_CHAN_IRQSEL1_IRQ0 0x00040000 // LPC Channel IRQSEL1 IRQ0 +#define LPC_CHAN_IRQSEL1_IRQ1 0x01040000 // LPC Channel IRQSEL1 IRQ1 +#define LPC_CHAN_IRQSEL1_IRQ2 0x02040000 // LPC Channel IRQSEL1 IRQ2 +#define LPC_CHAN_IRQSEL1_IRQ3 0x03040000 // LPC Channel IRQSEL1 IRQ3 +#define LPC_CHAN_IRQSEL1_IRQ4 0x04040000 // LPC Channel IRQSEL1 IRQ4 +#define LPC_CHAN_IRQSEL1_IRQ5 0x05040000 // LPC Channel IRQSEL1 IRQ5 +#define LPC_CHAN_IRQSEL1_IRQ6 0x06040000 // LPC Channel IRQSEL1 IRQ6 +#define LPC_CHAN_IRQSEL1_IRQ7 0x07040000 // LPC Channel IRQSEL1 IRQ7 +#define LPC_CHAN_IRQSEL1_IRQ8 0x08040000 // LPC Channel IRQSEL1 IRQ8 +#define LPC_CHAN_IRQSEL1_IRQ9 0x09040000 // LPC Channel IRQSEL1 IRQ9 +#define LPC_CHAN_IRQSEL1_IRQ10 0x0A040000 // LPC Channel IRQSEL1 IRQ10 +#define LPC_CHAN_IRQSEL1_IRQ11 0x0B040000 // LPC Channel IRQSEL1 IRQ11 +#define LPC_CHAN_IRQSEL1_IRQ12 0x0C040000 // LPC Channel IRQSEL1 IRQ12 +#define LPC_CHAN_IRQSEL1_IRQ13 0x0D040000 // LPC Channel IRQSEL1 IRQ13 +#define LPC_CHAN_IRQSEL1_IRQ14 0x0E040000 // LPC Channel IRQSEL1 IRQ14 +#define LPC_CHAN_IRQSEL1_IRQ15 0x0F040000 // LPC Channel IRQSEL1 IRQ15 + +#define LPC_CHAN_IRQSEL0_NONE 0x00000000 // LPC Channel IRQSEL0 Disabled +#define LPC_CHAN_IRQSEL0_IRQ0 0x00000000 // LPC Channel IRQSEL0 IRQ0 +#define LPC_CHAN_IRQSEL0_IRQ1 0x00100000 // LPC Channel IRQSEL0 IRQ1 +#define LPC_CHAN_IRQSEL0_IRQ2 0x00200000 // LPC Channel IRQSEL0 IRQ2 +#define LPC_CHAN_IRQSEL0_IRQ3 0x00300000 // LPC Channel IRQSEL0 IRQ3 +#define LPC_CHAN_IRQSEL0_IRQ4 0x00400000 // LPC Channel IRQSEL0 IRQ4 +#define LPC_CHAN_IRQSEL0_IRQ5 0x00500000 // LPC Channel IRQSEL0 IRQ5 +#define LPC_CHAN_IRQSEL0_IRQ6 0x00600000 // LPC Channel IRQSEL0 IRQ6 +#define LPC_CHAN_IRQSEL0_IRQ7 0x00700000 // LPC Channel IRQSEL0 IRQ7 +#define LPC_CHAN_IRQSEL0_IRQ8 0x00800000 // LPC Channel IRQSEL0 IRQ8 +#define LPC_CHAN_IRQSEL0_IRQ9 0x00900000 // LPC Channel IRQSEL0 IRQ9 +#define LPC_CHAN_IRQSEL0_IRQ10 0x00A00000 // LPC Channel IRQSEL0 IRQ10 +#define LPC_CHAN_IRQSEL0_IRQ11 0x00B00000 // LPC Channel IRQSEL0 IRQ11 +#define LPC_CHAN_IRQSEL0_IRQ12 0x00C00000 // LPC Channel IRQSEL0 IRQ12 +#define LPC_CHAN_IRQSEL0_IRQ13 0x00D00000 // LPC Channel IRQSEL0 IRQ13 +#define LPC_CHAN_IRQSEL0_IRQ14 0x00E00000 // LPC Channel IRQSEL0 IRQ14 +#define LPC_CHAN_IRQSEL0_IRQ15 0x00F00000 // LPC Channel IRQSEL0 IRQ15 +#define LPC_CHAN_IRQEN0_OFF 0x00000000 // LPC Channel IRQEN0 Disabled +#define LPC_CHAN_IRQEN0_TRG1 0x00010000 // LPC Channel IRQEN0 Trigger 1 +#define LPC_CHAN_IRQEN0_TRG2 0x00020000 // LPC Channel IRQEN0 Trigger 2 +#define LPC_CHAN_IRQEN0_TRG3 0x00030000 // LPC Channel IRQEN0 Trigger 3 + +#define LPC_CHAN_MBARB_ENABLED 0x00000000 // LPC Channel Mailbox Arbritration + // enabled. +#define LPC_CHAN_MBARB_DISABLED 0x00008000 // LPC Channel Mailbox Arbritration + // disabled. + +#define LPC_CHAN_SIZE_4 0x00000000 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_8 0x00000004 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_16 0x00000008 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_32 0x0000000C // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_64 0x00000010 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_128 0x00000014 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_256 0x00000018 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_512 0x0000001C // Mailbox IO/Memory Window size + // is 4 Bytes. + +//***************************************************************************** +// +// Values that can be passed to LCPChannelConfigCOMxSet as the ulCOMxMode +// parameter or returned from LPCChannelConfigGet in the pulCOMxMode +// parameter. +// +//***************************************************************************** +#define LPC_COMx_MODE_FRMHNML 0x00000000 // Normal From Host model. +#define LPC_COMx_MODE_FRMHIGN 0x00020000 // Ignore From Host data. +#define LPC_COMx_MODE_FRMHDMA 0x00040000 // COMx DMA on From Host data to + // memory +#define LPC_COMx_MODE_UARTDMA 0x00060000 // COMx DMA on From Host data to + // UART1 + +//***************************************************************************** +// +// Additinal values that can be returned from LPCChannelConfigGet in the +// pulCOMxMode parameter. +// +//***************************************************************************** +#define LPC_COMx_ENABLED 0x00010000 // COMx mode enabled. + +//***************************************************************************** +// +// Values that can be passed to LPCIntEnable, LPCIntDisable, and LPCIntClear +// as the ulIntFlags parameter and returned by LPCIntStatus. +// +//***************************************************************************** +#define LPC_INT_RST 0x80000000 // LPC Bus Enters or Exits + // Reset State. +#define LPC_INT_SLEEP 0x40000000 // LPC Bus Enters or Exits + // Sleep State. +#define LPC_INT_COMx 0x20000000 // COMx has read/written + // data. +#define LPC_INT_SIRQ 0x10000000 // SERIRQ frame has completed +#define LPC_INT_CH6_EP_TO_HOST (1 << 24) // To-Host has been read. +#define LPC_INT_CH6_EP_FROM_DATA \ + (2 << 24) // From-Host has been written as + // data. +#define LPC_INT_CH6_EP_FROM_CMD (4 << 24) // From-Host has been written as + // command. +#define LPC_INT_CH6_MB_HOST_WON (1 << 24) // Host Won (HW1ST) +#define LPC_INT_CH6_MB_HOST_WRITE \ + (2 << 24) // Host Wrote Last Byte. +#define LPC_INT_CH6_MB_HOST_READ \ + (4 << 24) // Host Read Last Byte +#define LPC_INT_CH6_MB_MCU_LOST (8 << 24) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH5_EP_TO_HOST (1 << 20) // To-Host has been read. +#define LPC_INT_CH5_EP_FROM_DATA \ + (2 << 20) // From-Host has been written as + // data. +#define LPC_INT_CH5_EP_FROM_CMD (4 << 20) // From-Host has been written as + // command. +#define LPC_INT_CH5_MB_HOST_WON (1 << 20) // Host Won (HW1ST) +#define LPC_INT_CH5_MB_HOST_WRITE \ + (2 << 20) // Host Wrote Last Byte. +#define LPC_INT_CH5_MB_HOST_READ \ + (4 << 20) // Host Read Last Byte +#define LPC_INT_CH5_MB_MCU_LOST (8 << 20) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH4_EP_TO_HOST (1 << 16) // To-Host has been read. +#define LPC_INT_CH4_EP_FROM_DATA \ + (2 << 16) // From-Host has been written as + // data. +#define LPC_INT_CH4_EP_FROM_CMD (4 << 16) // From-Host has been written as + // command. +#define LPC_INT_CH4_MB_HOST_WON (1 << 16) // Host Won (HW1ST) +#define LPC_INT_CH4_MB_HOST_WRITE \ + (2 << 16) // Host Wrote Last Byte. +#define LPC_INT_CH4_MB_HOST_READ \ + (4 << 16) // Host Read Last Byte +#define LPC_INT_CH4_MB_MCU_LOST (8 << 16) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH3_EP_TO_HOST (1 << 12) // To-Host has been read. +#define LPC_INT_CH3_EP_FROM_DATA \ + (2 << 12) // From-Host has been written as + // data. +#define LPC_INT_CH3_EP_FROM_CMD (4 << 12) // From-Host has been written as + // command. +#define LPC_INT_CH3_MB_HOST_WON (1 << 12) // Host Won (HW1ST) +#define LPC_INT_CH3_MB_HOST_WRITE \ + (2 << 12) // Host Wrote Last Byte. +#define LPC_INT_CH3_MB_HOST_READ \ + (4 << 12) // Host Read Last Byte +#define LPC_INT_CH3_MB_MCU_LOST (8 << 12) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH2_EP_TO_HOST (1 << 8) // To-Host has been read. +#define LPC_INT_CH2_EP_FROM_DATA \ + (2 << 8) // From-Host has been written as + // data. +#define LPC_INT_CH2_EP_FROM_CMD (4 << 8) // From-Host has been written as + // command. +#define LPC_INT_CH2_MB_HOST_WON (1 << 8) // Host Won (HW1ST) +#define LPC_INT_CH2_MB_HOST_WRITE \ + (2 << 8) // Host Wrote Last Byte. +#define LPC_INT_CH2_MB_HOST_READ \ + (4 << 8) // Host Read Last Byte +#define LPC_INT_CH2_MB_MCU_LOST (8 << 8) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH1_EP_TO_HOST (1 << 4) // To-Host has been read. +#define LPC_INT_CH1_EP_FROM_DATA \ + (2 << 4) // From-Host has been written as + // data. +#define LPC_INT_CH1_EP_FROM_CMD (4 << 4) // From-Host has been written as + // command. +#define LPC_INT_CH1_MB_HOST_WON (1 << 4) // Host Won (HW1ST) +#define LPC_INT_CH1_MB_HOST_WRITE \ + (2 << 4) // Host Wrote Last Byte. +#define LPC_INT_CH1_MB_HOST_READ \ + (4 << 4) // Host Read Last Byte +#define LPC_INT_CH1_MB_MCU_LOST (8 << 4) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH0_EP_TO_HOST (1 << 0) // To-Host has been read. +#define LPC_INT_CH0_EP_FROM_DATA \ + (2 << 0) // From-Host has been written as + // data. +#define LPC_INT_CH0_EP_FROM_CMD (4 << 0) // From-Host has been written as + // command. +#define LPC_INT_CH0_MB_HOST_WON (1 << 0) // Host Won (HW1ST) +#define LPC_INT_CH0_MB_HOST_WRITE \ + (2 << 0) // Host Wrote Last Byte. +#define LPC_INT_CH0_MB_HOST_READ \ + (4 << 0) // Host Read Last Byte +#define LPC_INT_CH0_MB_MCU_LOST (8 << 0) // MCU Lost (when host had HW1ST). + +//***************************************************************************** +// +// Values that can be passed to LPCCOMxInt... functions as the ulIntFlags +// parameter and returned by LPCIntStatus. +// +//***************************************************************************** +#define LPC_COMx_INT_CX 0x02000000 // Raw Event State for COMx +#define LPC_COMx_INT_CXTX 0x01000000 // Raw Event State for COMx TX +#define LPC_COMx_INT_CXRX 0x00800000 // Raw Event State for COMx RX +#define LPC_COMx_MASK_CX 0x00200000 // Event Mask for COMx +#define LPC_COMx_MASK_CXTX 0x00100000 // Event Mask for COMx TX +#define LPC_COMx_MASK_CXRX 0x00080000 // Event Mask for COMx RX + +//***************************************************************************** +// +// Values that can be passed to the LPCChannelDMAConfigSet function as part +// of the ulConfig or ulMask parameter, or can be returned from the +// LPCChannelConfigGet function. +// +//***************************************************************************** +#define LPC_DMA_CH3_WEN 0x00000080 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH3_REN 0x00000040 // Trigger DMA when "From Host" + // data buffer is full. +#define LPC_DMA_CH2_WEN 0x00000020 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH2_REN 0x00000010 // Trigger DMA when "From Host" + // data buffer is full. +#define LPC_DMA_CH1_WEN 0x00000008 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH1_REN 0x00000004 // Trigger DMA when "From Host" + // data buffer is full. +#define LPC_DMA_CH0_WEN 0x00000002 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH0_REN 0x00000001 // Trigger DMA when "From Host" + // data buffer is full. +//***************************************************************************** +// +// Values that can be passed to the LPCChannelStatusSet and +// LPCChannelStatusClear function, and returned by the LPCChannelStatusGet +// function. +// +//***************************************************************************** +#define LPC_CH_ST_USER0 0x00000100 // User Status Bit 0 +#define LPC_CH_ST_USER1 0x00000200 // User Status Bit 1 +#define LPC_CH_ST_USER2 0x00000400 // User Status Bit 2 +#define LPC_CH_ST_USER3 0x00000800 // User Status Bit 3 +#define LPC_CH_ST_USER4 0x00001000 // User Status Bit 4 + +//***************************************************************************** +// +// Additinoal values that can be returned by the LPCChannelStatusGet function. +// +//***************************************************************************** +#define LPC_CH_ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH_ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH_ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH_ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH_ST_CMD 0x00000008 // Command or Data +#define LPC_CH_ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH_ST_TOH 0x00000001 // To-Host Transaction + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void LPCConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long LPCConfigGet(unsigned long ulBase); +extern unsigned long LPCStatusGet(unsigned long ulBase, + unsigned long *pulCount, + unsigned long *pulPoolSize); +extern void LPCStatusBlockAddressSet(unsigned long ulBase, + unsigned long ulAddress, + tBoolean bEnabled); +extern unsigned LPCStatusBlockAddressGet(unsigned long ulBase); +extern void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount); +extern void LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse, + tBoolean bIRQOnChange); +extern void LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ); +extern void LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ); +extern unsigned long LPCIRQGet(unsigned long ulBase); +extern void LPCIRQSend(unsigned long ulBase); +extern void LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void LPCIntUnregister(unsigned long ulBase); +extern void LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long LPCIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel); +extern void LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel); +extern void LPCChannelConfigEPSet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig, + unsigned long ulAddress, + unsigned long ulOffset); +extern void LPCChannelConfigMBSet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig, + unsigned long ulAddress, + unsigned long ulOffset); +extern void LPCChannelConfigCOMxSet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig, + unsigned long ulAddress, + unsigned long ulOffset, + unsigned long ulCOMxMode); +extern unsigned long LPCChannelConfigGet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long *pulAddress, + unsigned long *pulOffset, + unsigned long *pulCOMxMode); +extern unsigned long LPCChannelPoolAddressGet(unsigned long ulBase, + unsigned long ulChannel); +extern unsigned long LPCChannelStatusGet(unsigned long ulBase, + unsigned long ulChannel); +extern void LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulStatus); +extern void LPCChannelStatusClear(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulStatus); +extern void LPCChannelDMAConfigSet(unsigned long ulBase, + unsigned long ulConfig, + unsigned long ulMask); +extern unsigned long LPCChannelDMAConfigGet(unsigned long ulBase); +extern unsigned char LPCByteRead(unsigned long ulBase, unsigned long ulOffset); +extern void LPCByteWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned char ucData); +extern unsigned short LPCHalfWordRead(unsigned long ulBase, + unsigned long ulOffset); +extern void LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned short usData); +extern unsigned long LPCWordRead(unsigned long ulBase, unsigned long ulOffset); +extern void LPCWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned long ulData); +extern void LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __LPC_H__ diff --git a/driverlib/mpu.c b/driverlib/mpu.c new file mode 100644 index 0000000..a9cd1a0 --- /dev/null +++ b/driverlib/mpu.c @@ -0,0 +1,460 @@ +//***************************************************************************** +// +// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpu_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/mpu.h" + +//***************************************************************************** +// +//! Enables and configures the MPU for use. +//! +//! \param ulMPUConfig is the logical OR of the possible configurations. +//! +//! This function enables the Cortex-M memory protection unit. It also +//! configures the default behavior when in privileged mode and while handling +//! a hard fault or NMI. Prior to enabling the MPU, at least one region must +//! be set by calling MPURegionSet() or else by enabling the default region for +//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to +//! MPUEnable(). Once the MPU is enabled, a memory management fault is +//! generated for memory access violations. +//! +//! The \e ulMPUConfig parameter should be the logical OR of any of the +//! following: +//! +//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in +//! privileged mode and when no other regions are defined. If this option +//! is not enabled, then there must be at least one valid region already +//! defined when the MPU is enabled. +//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI +//! exception handler. If this option is not enabled, then the MPU is +//! disabled while in one of these exception handlers and the default +//! memory map is applied. +//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, +//! no default memory map is provided in privileged mode, and the MPU isl +//! not enabled in the fault handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUEnable(unsigned long ulMPUConfig) +{ + // + // Check the arguments. + // + ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT | + MPU_CONFIG_HARDFLT_NMI))); + + // + // Set the MPU control bits according to the flags passed by the user, + // and also set the enable bit. + // + HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the MPU for use. +//! +//! This function disables the Cortex-M memory protection unit. When the +//! MPU is disabled, the default memory map is used and memory management +//! faults are not generated. +//! +//! \return None. +// +//***************************************************************************** +void +MPUDisable(void) +{ + // + // Turn off the MPU enable bit. + // + HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Gets the count of regions supported by the MPU. +//! +//! This function is used to get the total number of regions that are supported +//! by the MPU, including regions that are already programmed. +//! +//! \return The number of memory protection regions that are available +//! for programming using MPURegionSet(). +// +//***************************************************************************** +unsigned long +MPURegionCountGet(void) +{ + // + // Read the DREGION field of the MPU type register and mask off + // the bits of interest to get the count of regions. + // + return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) + >> NVIC_MPU_TYPE_DREGION_S); +} + +//***************************************************************************** +// +//! Enables a specific region. +//! +//! \param ulRegion is the region number to enable. +//! +//! This function is used to enable a memory protection region. The region +//! should already be configured with the MPURegionSet() function. Once +//! enabled, the memory protection rules of the region are applied and access +//! violations cause a memory management fault. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionEnable(unsigned long ulRegion) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + + // + // Select the region to modify. + // + HWREG(NVIC_MPU_NUMBER) = ulRegion; + + // + // Modify the enable bit in the region attributes. + // + HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE; +} + +//***************************************************************************** +// +//! Disables a specific region. +//! +//! \param ulRegion is the region number to disable. +//! +//! This function is used to disable a previously enabled memory protection +//! region. The region remains configured if it is not overwritten with +//! another call to MPURegionSet(), and can be enabled again by calling +//! MPURegionEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionDisable(unsigned long ulRegion) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + + // + // Select the region to modify. + // + HWREG(NVIC_MPU_NUMBER) = ulRegion; + + // + // Modify the enable bit in the region attributes. + // + HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE; +} + +//***************************************************************************** +// +//! Sets up the access rules for a specific region. +//! +//! \param ulRegion is the region number to set up. +//! \param ulAddr is the base address of the region. It must be aligned +//! according to the size of the region specified in ulFlags. +//! \param ulFlags is a set of flags to define the attributes of the region. +//! +//! This function sets up the protection rules for a region. The region has +//! a base address and a set of attributes including the size. The base +//! address parameter, \e ulAddr, must be aligned according to the size, and +//! the size must be a power of 2. +//! +//! The \e ulFlags parameter is the logical OR of all of the attributes +//! of the region. It is a combination of choices for region size, +//! execute permission, read/write permissions, disabled sub-regions, +//! and a flag to determine if the region is enabled. +//! +//! The size flag determines the size of a region and must be one of the +//! following: +//! +//! - \b MPU_RGN_SIZE_32B +//! - \b MPU_RGN_SIZE_64B +//! - \b MPU_RGN_SIZE_128B +//! - \b MPU_RGN_SIZE_256B +//! - \b MPU_RGN_SIZE_512B +//! - \b MPU_RGN_SIZE_1K +//! - \b MPU_RGN_SIZE_2K +//! - \b MPU_RGN_SIZE_4K +//! - \b MPU_RGN_SIZE_8K +//! - \b MPU_RGN_SIZE_16K +//! - \b MPU_RGN_SIZE_32K +//! - \b MPU_RGN_SIZE_64K +//! - \b MPU_RGN_SIZE_128K +//! - \b MPU_RGN_SIZE_256K +//! - \b MPU_RGN_SIZE_512K +//! - \b MPU_RGN_SIZE_1M +//! - \b MPU_RGN_SIZE_2M +//! - \b MPU_RGN_SIZE_4M +//! - \b MPU_RGN_SIZE_8M +//! - \b MPU_RGN_SIZE_16M +//! - \b MPU_RGN_SIZE_32M +//! - \b MPU_RGN_SIZE_64M +//! - \b MPU_RGN_SIZE_128M +//! - \b MPU_RGN_SIZE_256M +//! - \b MPU_RGN_SIZE_512M +//! - \b MPU_RGN_SIZE_1G +//! - \b MPU_RGN_SIZE_2G +//! - \b MPU_RGN_SIZE_4G +//! +//! The execute permission flag must be one of the following: +//! +//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code +//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code +//! +//! The read/write access permissions are applied separately for the +//! privileged and user modes. The read/write access flags must be one +//! of the following: +//! +//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode +//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access +//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only +//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write +//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access +//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only +//! +//! The region is automatically divided into 8 equally-sized sub-regions by +//! the MPU. Sub-regions can only be used in regions of size 256 bytes +//! or larger. Any of these 8 sub-regions can be disabled, allowing for +//! creation of ``holes'' in a region which can be left open, or overlaid +//! by another region with different attributes. Any of the 8 sub-regions +//! can be disabled with a logical OR of any of the following flags: +//! +//! - \b MPU_SUB_RGN_DISABLE_0 +//! - \b MPU_SUB_RGN_DISABLE_1 +//! - \b MPU_SUB_RGN_DISABLE_2 +//! - \b MPU_SUB_RGN_DISABLE_3 +//! - \b MPU_SUB_RGN_DISABLE_4 +//! - \b MPU_SUB_RGN_DISABLE_5 +//! - \b MPU_SUB_RGN_DISABLE_6 +//! - \b MPU_SUB_RGN_DISABLE_7 +//! +//! Finally, the region can be initially enabled or disabled with one of +//! the following flags: +//! +//! - \b MPU_RGN_ENABLE +//! - \b MPU_RGN_DISABLE +//! +//! As an example, to set a region with the following attributes: size of +//! 32 KB, execution enabled, read-only for both privileged and user, one +//! sub-region disabled, and initially enabled; the \e ulFlags parameter would +//! have the following value: +//! +//! +//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO | +//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) +//! +//! +//! \note This function writes to multiple registers and is not protected +//! from interrupts. It is possible that an interrupt which accesses a +//! region may occur while that region is in the process of being changed. +//! The safest way to handle this is to disable a region before changing it. +//! Refer to the discussion of this in the API Detailed Description section. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1)) + == ulAddr); + + // + // Program the base address, use the region field to select the + // region at the same time. + // + HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID; + + // + // Program the region attributes. Set the TEX field and the S, C, + // and B bits to fixed values that are suitable for all Stellaris + // memory. + // + HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M | + NVIC_MPU_ATTR_CACHEABLE)) | + NVIC_MPU_ATTR_SHAREABLE | + NVIC_MPU_ATTR_BUFFRABLE; +} + +//***************************************************************************** +// +//! Gets the current settings for a specific region. +//! +//! \param ulRegion is the region number to get. +//! \param pulAddr points to storage for the base address of the region. +//! \param pulFlags points to the attribute flags for the region. +//! +//! This function retrieves the configuration of a specific region. The +//! meanings and format of the parameters is the same as that of the +//! MPURegionSet() function. +//! +//! This function can be used to save the configuration of a region for later +//! use with the MPURegionSet() function. The region's enable state is +//! preserved in the attributes that are saved. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, + unsigned long *pulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + ASSERT(pulAddr); + ASSERT(pulFlags); + + // + // Select the region to get. + // + HWREG(NVIC_MPU_NUMBER) = ulRegion; + + // + // Read and store the base address for the region. + // + *pulAddr = HWREG(NVIC_MPU_BASE); + + // + // Read and store the region attributes. + // + *pulFlags = HWREG(NVIC_MPU_ATTR); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the memory management fault. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! memory management fault occurs. +//! +//! This function sets and enables the handler to be called when the MPU +//! generates a memory management fault due to a protection region access +//! violation. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUIntRegister(void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(FAULT_MPU, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(FAULT_MPU); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the memory management fault. +//! +//! This function disables and clears the handler to be called when a +//! memory management fault occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(FAULT_MPU); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_MPU); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/mpu.h b/driverlib/mpu.h new file mode 100644 index 0000000..c604018 --- /dev/null +++ b/driverlib/mpu.h @@ -0,0 +1,162 @@ +//***************************************************************************** +// +// mpu.h - Defines and Macros for the memory protection unit. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __MPU_H__ +#define __MPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Flags that can be passed to MPUEnable. +// +//***************************************************************************** +#define MPU_CONFIG_PRIV_DEFAULT 4 +#define MPU_CONFIG_HARDFLT_NMI 2 +#define MPU_CONFIG_NONE 0 + +//***************************************************************************** +// +// Flags for the region size to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_SIZE_32B (4 << 1) +#define MPU_RGN_SIZE_64B (5 << 1) +#define MPU_RGN_SIZE_128B (6 << 1) +#define MPU_RGN_SIZE_256B (7 << 1) +#define MPU_RGN_SIZE_512B (8 << 1) + +#define MPU_RGN_SIZE_1K (9 << 1) +#define MPU_RGN_SIZE_2K (10 << 1) +#define MPU_RGN_SIZE_4K (11 << 1) +#define MPU_RGN_SIZE_8K (12 << 1) +#define MPU_RGN_SIZE_16K (13 << 1) +#define MPU_RGN_SIZE_32K (14 << 1) +#define MPU_RGN_SIZE_64K (15 << 1) +#define MPU_RGN_SIZE_128K (16 << 1) +#define MPU_RGN_SIZE_256K (17 << 1) +#define MPU_RGN_SIZE_512K (18 << 1) + +#define MPU_RGN_SIZE_1M (19 << 1) +#define MPU_RGN_SIZE_2M (20 << 1) +#define MPU_RGN_SIZE_4M (21 << 1) +#define MPU_RGN_SIZE_8M (22 << 1) +#define MPU_RGN_SIZE_16M (23 << 1) +#define MPU_RGN_SIZE_32M (24 << 1) +#define MPU_RGN_SIZE_64M (25 << 1) +#define MPU_RGN_SIZE_128M (26 << 1) +#define MPU_RGN_SIZE_256M (27 << 1) +#define MPU_RGN_SIZE_512M (28 << 1) + +#define MPU_RGN_SIZE_1G (29 << 1) +#define MPU_RGN_SIZE_2G (30 << 1) +#define MPU_RGN_SIZE_4G (31 << 1) + +//***************************************************************************** +// +// Flags for the permissions to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_PERM_EXEC 0x00000000 +#define MPU_RGN_PERM_NOEXEC 0x10000000 +#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 +#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 +#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 +#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 +#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 +#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 + +//***************************************************************************** +// +// Flags for the sub-region to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_SUB_RGN_DISABLE_0 0x00000100 +#define MPU_SUB_RGN_DISABLE_1 0x00000200 +#define MPU_SUB_RGN_DISABLE_2 0x00000400 +#define MPU_SUB_RGN_DISABLE_3 0x00000800 +#define MPU_SUB_RGN_DISABLE_4 0x00001000 +#define MPU_SUB_RGN_DISABLE_5 0x00002000 +#define MPU_SUB_RGN_DISABLE_6 0x00004000 +#define MPU_SUB_RGN_DISABLE_7 0x00008000 + +//***************************************************************************** +// +// Flags to enable or disable a region, to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_ENABLE 1 +#define MPU_RGN_DISABLE 0 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void MPUEnable(unsigned long ulMPUConfig); +extern void MPUDisable(void); +extern unsigned long MPURegionCountGet(void); +extern void MPURegionEnable(unsigned long ulRegion); +extern void MPURegionDisable(unsigned long ulRegion); +extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, + unsigned long ulFlags); +extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, + unsigned long *pulFlags); +extern void MPUIntRegister(void (*pfnHandler)(void)); +extern void MPUIntUnregister(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __MPU_H__ diff --git a/driverlib/peci.c b/driverlib/peci.c new file mode 100644 index 0000000..177474b --- /dev/null +++ b/driverlib/peci.c @@ -0,0 +1,1000 @@ +//***************************************************************************** +// +// peci.c - Driver for the Platform Environment Control Interface (PECI) +// module. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup peci_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_peci.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/peci.h" + +//***************************************************************************** +// +// The following defines provide characteristics of the PECI module that are +// important to the driver but which can not be gleaned from the register +// definitions. Note that the maximum baud rate here is set higher than +// specified to allow callers to achieve 1Mbps on a slow part. +// +//***************************************************************************** +#define PECI_MAX_BAUD 4000000 // Max baud rate +#define PECI_MIN_BAUD 2000 // Min baud rate +#define PECI_MIN_RATIO (CLASS_IS_BLIZZARD ? 10 : 1) // Min baud rate divider +#define PECI_MAX_RATIO 65535 // Max baud rate divider +#define PECI_POLL_PRESCALE 4096 // Polling timer prescaler +#define PECI_MIN_POLL 2 // Min polling interval (ms) +#define PECI_MAX_POLL 1000 // Max polling interval (ms) + +//***************************************************************************** +// +//! \internal +//! Checks a PECI domain. +//! +//! \param ulDomain is the PECI domain identifier. +//! +//! This function determines if a domain identifier is valid. +//! +//! \return Returns \b true if the domain identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +PECIDomainValid(unsigned long ulDomain) +{ + return((ulDomain == PECI_DOMAIN_M0D0) || + (ulDomain == PECI_DOMAIN_M0D1) || + (ulDomain == PECI_DOMAIN_M1D0) || + (ulDomain == PECI_DOMAIN_M1D1)); +} +#endif + +//***************************************************************************** +// +//! Sets the configuration of the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulPECIClk is the rate of the clock supplied to the PECI module. +//! \param ulBaud is the bit rate that should be used for the PECI transfers. +//! \param ulPoll is the polling rate, in ms, that should be used for the +//! time between PECI polls. +//! \param ulOffset is the offset to be applied to all temperature values to +//! convert from relative to absolute. +//! \param ulRetry is the number of retry attempts for a PECI transaction. +//! +//! This function initializes operation of the PECI block. It programs the bit +//! rate, polling rate and retry counts for PECI transactions. It also +//! programs the offset value to be used to translate relative temperature +//! values from PECI transactions to absolute values. At the end of this +//! function, no host/domain combinations are enabled. Each desired +//! host/domain combination can be configured/enabled with a call to +//! PECIDomainEnable(). +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! The \e ulBaud parameter defines the starting bit rate for the PECI +//! transactions. This value is used to calculate a divisor value based on +//! the specified \e ulPECIClk. If the exact baud rate cannot be achieved +//! (due to rounding), the baud rate is programmed to the nearest value that +//! is less than the specified value. Note that, due to client clock +//! stretching and delays through external components, the actual baud rate +//! observed on the PECI bus will always be lower than the value specified in +//! this parameter. +//! +//! The \e ulPoll parameter defines the polling rate, in milliseconds, used +//! for PECI transactions. For generation of the polling rate, the \e +//! ulPECIClk is pre-divided by \b 4096. A value of 0 disables the polling +//! feature. If the exact polling rate cannot be achieved (due to rounding), +//! the polling rate is programmed to the nearest value that is greater than +//! the specified value. +//! +//! The \e ulRetry parameter defines the number of PECI transactions that are +//! attempted before indicating an error condition. +//! +//! \return None. +// +//***************************************************************************** +void +PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long ulBaud, unsigned long ulPoll, + unsigned long ulOffset, unsigned long ulRetry) +{ + unsigned long ulTemp, ulDiv; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(ulPECIClk != 0); + ASSERT((ulBaud != 0) && (ulBaud <= PECI_MAX_BAUD) && + (ulBaud >= PECI_MIN_BAUD) && + ((ulBaud * 4 * PECI_MIN_RATIO) < ulPECIClk)); + ASSERT((ulPoll == 0) || + ((ulPoll >= PECI_MIN_POLL) && (ulPoll <= PECI_MAX_POLL))); + + // + // Generate value for the PECI Control Register. + // + ulTemp = ((ulOffset << PECI_CTL_OFFSET_S) & PECI_CTL_OFFSET_M); + ulTemp |= ((ulRetry << PECI_CTL_CRETRY_S) & PECI_CTL_CRETRY_M); + HWREG(ulBase + PECI_O_CTL) = ulTemp; + + // + // Compute the divisor for the PECI baud rate clock. + // Round up, to ensure programmed baud rate is <= specified rate. + // Ensure that proper ratio is maintained for clock:baud. + // + ulDiv = (ulPECIClk + (4 * ulBaud) - 1) / (4 * ulBaud); + ulDiv = (ulDiv < PECI_MIN_RATIO) ? PECI_MIN_RATIO : ulDiv; + ulDiv = (ulDiv > PECI_MAX_RATIO) ? PECI_MAX_RATIO : ulDiv; + ulTemp = ((ulDiv << PECI_DIV_BAUD_S) & PECI_DIV_BAUD_M); + + // + // Compute the divisor for the PECI polling rate. + // Round up, to ensure programmed polling rate is >= specified rate. + // Note that the order of calculation is important here since ulPECIClk is + // in the 10s of MHz range and ulPoll can be several thousand for slow + // polling rates. If we change the order, the calculation can overflow + // resulting in incorrect polling rates. + // + ulDiv = ((ulPoll == 0) ? 0 : ((((ulPECIClk / 1000) * ulPoll) + + (PECI_POLL_PRESCALE - 1)) / + PECI_POLL_PRESCALE)); + ulTemp |= ((ulDiv << PECI_DIV_POLL_S) & PECI_DIV_POLL_M);; + HWREG(ulBase + PECI_O_DIV) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the current configuration of the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulPECIClk is the rate of the clock supplied to the PECI module. +//! \param pulBaud is a pointer to storage for the bit rate. +//! \param pulPoll is a pointer to storage for the polling rate. +//! \param pulOffset is a pointer to storage for the offset. +//! \param pulRetry is a pointer to storage for the retry count. +//! +//! The baud rate and poll rate for the PECI module are determined, given an +//! explicitly provided peripheral clock. The returned rates are the actual +//! rates being used; they may not be the same as the requested rates, due to +//! rounding in the calculations. +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! The baud rate returned in \e *pulBaud represents the rate at which the +//! peripheral starts PECI transactions. Due to client clock stretching and +//! delays associated with external components, the actual baud rate observed +//! will always be lower than this value. +//! +//! \return None. +// +//***************************************************************************** +void +PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long *pulBaud, unsigned long *pulPoll, + unsigned long *pulOffset, unsigned long *pulRetry) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(ulPECIClk != 0); + ASSERT(pulBaud != 0); + ASSERT(pulPoll != 0); + ASSERT(pulOffset != 0); + ASSERT(pulRetry != 0); + + // + // Retrieve the Offset and Retry values + // + ulTemp = HWREG(ulBase + PECI_O_CTL); + *pulOffset = ((ulTemp & PECI_CTL_OFFSET_M) >> PECI_CTL_OFFSET_S); + *pulRetry = ((ulTemp & PECI_CTL_CRETRY_M) >> PECI_CTL_CRETRY_S); + + // + // Calculate the baud rate. + // + ulTemp = HWREG(ulBase + PECI_O_DIV); + *pulBaud = (ulPECIClk / (4 * ((ulTemp & PECI_DIV_BAUD_M) >> + PECI_DIV_BAUD_S))); + + // + // Compute the divisor for the PECI polling rate. + // Round up, to ensure programmed polling rate is >= specified rate. + // + *pulPoll = ((((ulTemp & PECI_DIV_POLL_M) >> PECI_DIV_POLL_S) * 1000) / + (ulPECIClk / PECI_POLL_PRESCALE)); +} + +//***************************************************************************** +// +//! Enables bypassing of negotiation errors. +//! +//! \param ulBase is the base address of the PECI module. +//! +//! This function enables bypassing of negotiation errors that might occur +//! during a PECI transaction. When enabled, negotiation errors are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +PECIBypassEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Enable bypass. + // + HWREG(ulBase + PECI_O_CTL) |= PECI_CTL_BYERR; +} + +//***************************************************************************** +// +//! Disables bypassing of negotiation errors. +//! +//! \param ulBase is the base address of the PECI module. +//! +//! This function disables bypassing of negotiation errors that might occur +//! during a PECI transaction. When disabled, negotiation errors are reported +//! and the remainder of the transaction is aborted. +//! +//! \return None. +// +//***************************************************************************** +void +PECIBypassDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Disable bypass. + // + HWREG(ulBase + PECI_O_CTL) &= ~PECI_CTL_BYERR; +} + +//***************************************************************************** +// +//! Sets the configuration of the specified PECI domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be configured. +//! \param ulHigh is the high temperature threshold value. +//! \param ulLow is the low temperature threshold value. +//! +//! This function configures the specified PECI domain for temperature +//! monitoring operations. The values for \e ulHigh and \e ulLow can be +//! specified as values relative to the maximum temperature allowed, or they +//! can be specified as absolute temperatures if an offset was programmed +//! in the PECIConfigSet() function. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain, + unsigned long ulHigh, unsigned long ulLow) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + ASSERT(ulHigh <= 0xFFFF); + ASSERT(ulLow <= 0xFFFF); + ASSERT(ulHigh > ulLow); + + // + // Set the HTHRESH and LTHRESH fields in the domain control/status + // register. + // + HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4)) = + (((ulHigh << PECI_M0D0C_HITHR_S) & PECI_M0D0C_HITHR_M) | + ((ulLow << PECI_M0D0C_LOTHR_S) & PECI_M0D0C_LOTHR_M)); +} + +//***************************************************************************** +// +//! Gets the configuration of the specified PECI domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be configured. +//! \param pulHigh is a pointer to storage for the high threshold. +//! \param pulLow is a pointer to storage for the low threshold. +//! +//! This function configures the specified PECI domain for temperature +//! monitoring operations. The values for \e ulHigh and \e ulLow can be +//! specified as values relative to the maximum temperature allowed, or they +//! can be specified as absolute temperatures if an offset was programmed +//! in the PECIConfigSet() function. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain, + unsigned long *pulHigh, unsigned long *pulLow) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + ASSERT(pulHigh != 0); + ASSERT(pulLow != 0); + + // + // Get the HTHRESH and LTHRESH fields in the domain control/status + // register. + // + ulTemp = HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4)); + *pulHigh = ((ulTemp && PECI_M0D0C_HITHR_M) >> PECI_M0D0C_HITHR_S); + *pulLow = ((ulTemp && PECI_M0D0C_LOTHR_M) >> PECI_M0D0C_LOTHR_S); +} + +//***************************************************************************** +// +//! Enables a domain within the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be enabled. +//! +//! This function enables the specified PECI domain for temperature monitoring +//! operations. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Enable the specified domain. + // + HWREG(ulBase + PECI_O_CTL) |= (1 << ulDomain); +} + +//***************************************************************************** +// +//! Disables a domain within the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function disables the specified PECI domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Disable the specified domain. + // + HWREG(ulBase + PECI_O_CTL) &= ~(1 << ulDomain); +} + +//***************************************************************************** +// +//! Reads the current temperature value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function returns the most recently read temperature value from the +//! specified domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +PECIDomainValueGet(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Return the most recently polled temperature value + // + return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) & + PECI_M0D0_VALUE_M))); +} + +//***************************************************************************** +// +//! Reads the maximum/error value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function returns the maximum temperature value for the specified +//! domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +PECIDomainMaxReadGet(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Return the most recently polled temperature value + // + return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) & + PECI_M0D0_MAXREAD_M) >> PECI_M0D0_MAXREAD_S)); +} + +//***************************************************************************** +// +//! Clears the current temperature value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function clears the current temperature value for the specified +//! domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Clear the temperature value. + // + HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_VALUE_M; +} + +//***************************************************************************** +// +//! Clears the maximum/error value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function clears the maximum temperature measurement value for the +//! specified domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainMaxReadClear(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Clear the maximum/error value. + // + HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_MAXREAD_M; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the PECI module. +//! +//! \param ulBase specifies the PECI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! PECI interrupt occurs. +//! +//! This function registers the handler to be called when an PECI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific PECI interrupts must be enabled via PECIIntEnable(). +//! If necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via PECIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_PECI0, pfnHandler); + + // + // Enable the PECI interrupt. + // + IntEnable(INT_PECI0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the PECI module. +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function unregisters the handler to be called when a PECI interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Disable the PECI interrupt. + // + IntDisable(INT_PECI0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_PECI0); +} + +//***************************************************************************** +// +//! Enables individual PECI interrupt sources. +//! +//! \param ulBase specifies the PECI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! \param ulIntMode is the mode for the PECI domain interrupts. +//! +//! This function enables the indicated PECI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter can be any of the following values: +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1. +//! +//! The \e ulIntMode parameter is used to configure the interrupt mode for +//! the corresponding \b PECI_DOMAIN_MnDm field, and can be any of the +//! following values: \b PECI_M0D0_MODE1, \b PECI_M0D0_MODE2, +//! \b PECI_M0D0_MODE3, \b PECI_M0D1_MODE1, \b PECI_M0D1_MODE2, +//! \b PECI_M0D1_MODE3. \b PECI_M1D0_MODE1, \b PECI_M1D0_MODE2, +//! \b PECI_M1D0_MODE3, \b PECI_M1D1_MODE1, \b PECI_M1D1_MODE2, or +//! \b PECI_M1D1_MODE3. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags, + unsigned long ulIntMode) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Get the current mask value. + // + ulTemp = HWREG(ulBase + PECI_O_IM); + + // + // Clear the bit/bit-fields that are configured, based on the value + // in the flags parameter. + // + ulTemp &= ~ulIntFlags; + + // + // Set/Enable the bit/bit-fields based on the value in the flags and mode + // parameter. The flags parameter alters the bits in the lower half + // of the mask, while the mode alters the bit fields in the upper + // half of the mask. + // + ulTemp |= (0x0000FFFF & ulIntFlags); + ulTemp |= (0xFFFF0000 & ulIntMode); + HWREG(ulBase + PECI_O_IM) = ulTemp; +} + +//***************************************************************************** +// +//! Disables individual PECI interrupt sources. +//! +//! \param ulBase specifies the PECI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated PECI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter can be any of the following values: +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + PECI_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the PECI module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the PECI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! The interpretation of the PECI_DOMAIN_MnDm fields vary based on the mode +//! value programed using the PECIIntEnable() function for the field. Each +//! field may take on one of the following values: +//! \b PECI_MnDm_MODE1_HIGH, \b PECI_MnDm_MODE2_MID, \b PECI_MnDm_MODE2_HIGH, +//! \b PECI_MnDm_MODE3_LOW, \b PECI_MnDm_MODE3_MID, or \b PECI_MnDm_MODE3_HIGH. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1. +// +//***************************************************************************** +unsigned long +PECIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + PECI_O_MIS)); + } + else + { + return(HWREG(ulBase + PECI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears PECI interrupt sources. +//! +//! \param ulBase specifies the PECI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified PECI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being recognized again immediately upon exit. +//! The \e ulIntFlags parameter can consist of any combination of the +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1 values. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + PECI_O_IC) = ulIntFlags; +} + +//***************************************************************************** +// +//! Sends a PECI Advanced Command. +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function sends a PECI Advanced Command. If the interface is not IDLE, +//! it waits for the interface to become IDLE then sends the command. The +//! function parameters are used to populate the message control fields before +//! activating the command. +//! +//! \return None. +// +//***************************************************************************** +void +PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd, + unsigned char ucHidRe, unsigned char ucDomain, + unsigned char ucProcAdd, unsigned long ulArg, + unsigned char ucSize, unsigned long ulData0, + unsigned long ulData1) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Wait for the interface to be idle. + // + while(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF) + { + } + + // + // Fill in the registers for the advanced command. + // + HWREG(ulBase + PECI_O_ACARG) = ulArg; + HWREG(ulBase + PECI_O_ACRDWR0) = ulData0; + HWREG(ulBase + PECI_O_ACRDWR1) = ulData1; + HWREG(ulBase + PECI_O_ACADDR) = (ucHidRe << 24) | + (ucSize << 16) | + (ucDomain << 8) | + (ucProcAdd << 0); + + // + // Now, issue the command. + // + HWREG(ulBase + PECI_O_ACCMD) = ucCmd; +} + +//***************************************************************************** +// +//! Sends a PECI Advanced Command (non blocking). +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function sends a PECI Advanced Command. If the interface is not IDLE, +//! it returns immediately. Otherwise, it sends the the command. The function +//! parameters are used to populate the message control fields before +//! activating the command. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +PECIAdvCmdSendNonBlocking(unsigned long ulBase, unsigned char ucCmd, + unsigned char ucHidRe, unsigned char ucDomain, + unsigned char ucProcAdd, unsigned long ulArg, + unsigned char ucSize, unsigned long ulData0, + unsigned long ulData1) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Check for the interface to be idle. + // If not, return immediately. + // + if(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF) + { + return(0); + } + + // + // Send the command. + // + PECIAdvCmdSend(ulBase, ucCmd, ucHidRe, ucDomain, ucProcAdd, ulArg, + ucSize, ulData0, ulData1); + + // + // Return, indicating that the command has been issued. + // + return(1); +} + +//***************************************************************************** +// +//! Obtains status of previous PECI Advanced Command. +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function gets the status of a previously issued PECI Advanced Command. +//! If the command has completed, and the data pointers are non-zero, the data +//! registers are read and saved. +//! +//! \return -1 if command has not yet been completed, otherwise, the return +//! code associated with the Advanced Command. +// +//***************************************************************************** +unsigned long +PECIAdvCmdStatusGet(unsigned long ulBase, unsigned long *pulData0, + unsigned long *pulData1) +{ + unsigned long ulCode; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // If the command has completed, optionally read and save the data + // registers. + // + ulCode = HWREG(ulBase + PECI_O_ACCODE); + if(ulCode != 0xFFFFFFFF) + { + if(pulData0 != (void *)0) + { + *pulData0 = HWREG(ulBase + PECI_O_ACRDWR0); + } + if(pulData1 != (void *)0) + { + *pulData1 = HWREG(ulBase + PECI_O_ACRDWR1); + } + } + + // + // Return the command code from the most recently completed command. + // + return(ulCode); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/peci.h b/driverlib/peci.h new file mode 100644 index 0000000..a3e6e92 --- /dev/null +++ b/driverlib/peci.h @@ -0,0 +1,241 @@ +//***************************************************************************** +// +// peci.h - Prototypes for Platform Environment Control Interface (PECI) +// driver. +// +// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PECI_H__ +#define __PECI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to PECIConfigDomain, PECIEnableDomain, +// PECIDisableDomain, PECIReadDomainValue, PECIReadDomainMax, and +// PECIClearDomain as the ulDomain parameter. +// +//***************************************************************************** +#define PECI_DOMAIN_M0D0 0 // Microprocessor 0 / Domain 0 +#define PECI_DOMAIN_M0D1 1 // Microprocessor 0 / Domain 1 +#define PECI_DOMAIN_M1D0 2 // Microprocessor 1 / Domain 0 +#define PECI_DOMAIN_M1D1 3 // Microprocessor 1 / Domain 1 + +//***************************************************************************** +// +// Values that can be passed to PECIIntEnable, PECIIntDisable, and PECIIntClear +// as the ulIntFlags parameter and returned by PECIIntStatus. +// +//***************************************************************************** +#define PECI_READ 0x00000001 // End of PECI Poll +#define PECI_ERR 0x00000002 // Error on PECI Poll +#define PECI_AC 0x00000004 // Advanced Command Complete +#define PECI_M0D0 0x00030000 // Microprocessor 0 / Domain 0 +#define PECI_M0D1 0x000C0000 // Microprocessor 0 / Domain 1 +#define PECI_M1D0 0x00300000 // Microprocessor 1 / Domain 0 +#define PECI_M1D1 0x00C00000 // Microprocessor 1 / Domain 1 + +//***************************************************************************** +// +// Additional values that can be returned by PECIIntStatus. +// +//***************************************************************************** +#define PECI_M0D0_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 0 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M0D0_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 0 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M0D0_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 0 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M0D0_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 0 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M0D0_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 0 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M0D0_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 0 + // Mode 3 + // Temperature CROSSED above HIGH +#define PECI_M0D1_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 1 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M0D1_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 1 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M0D1_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 1 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M0D1_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 1 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M0D1_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 1 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M0D1_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 1 + // Mode 3 + // Temperature CROSSED above HIGH +#define PECI_M1D0_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 0 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M1D0_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 0 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M1D0_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 0 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M1D0_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 0 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M1D0_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 0 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M1D0_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 0 + // Mode 3 + // Temperature CROSSED above HIGH +#define PECI_M1D1_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 1 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M1D1_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 1 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M1D1_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 1 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M1D1_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 1 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M1D1_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 1 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M1D1_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 1 + // Mode 3 + // Temperature CROSSED above HIGH + +//***************************************************************************** +// +// Values that can be passed to PECIIntEnable as the ulIntMode parameter. +// +//***************************************************************************** +#define PECI_M0D0_MODE1 0x00010000 // Domain Interrupt Mode 1 +#define PECI_M0D0_MODE2 0x00020000 // Domain Interrupt Mode 2 +#define PECI_M0D0_MODE3 0x00030000 // Domain Interrupt Mode 3 +#define PECI_M0D1_MODE1 0x00040000 // Domain Interrupt Mode 1 +#define PECI_M0D1_MODE2 0x00080000 // Domain Interrupt Mode 2 +#define PECI_M0D1_MODE3 0x000C0000 // Domain Interrupt Mode 3 +#define PECI_M1D0_MODE1 0x00100000 // Domain Interrupt Mode 1 +#define PECI_M1D0_MODE2 0x00200000 // Domain Interrupt Mode 2 +#define PECI_M1D0_MODE3 0x00300000 // Domain Interrupt Mode 3 +#define PECI_M1D1_MODE1 0x00400000 // Domain Interrupt Mode 1 +#define PECI_M1D1_MODE2 0x00800000 // Domain Interrupt Mode 2 +#define PECI_M1D1_MODE3 0x00C00000 // Domain Interrupt Mode 3 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long ulBaud, unsigned long ulPoll, + unsigned long ulOffset, unsigned long ulRetry); +extern void PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long *pulBaud, unsigned long *pulPoll, + unsigned long *pulOffset, unsigned long *pulRetry); +extern void PECIBypassEnable(unsigned long ulBase); +extern void PECIBypassDisable(unsigned long ulBase); +extern void PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain, + unsigned long ulHigh, unsigned long ulLow); +extern void PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain, + unsigned long *pulHigh, unsigned long *pulLow); +extern void PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain); +extern void PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain); +extern unsigned long PECIDomainValueGet(unsigned long ulBase, + unsigned long ulDomain); +extern unsigned long PECIDomainMaxReadGet(unsigned long ulBase, + unsigned long ulDomain); +extern void PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain); +extern void PECIDomainMaxReadClear(unsigned long ulBase, + unsigned long ulDomain); +extern void PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void PECIIntUnregister(unsigned long ulBase); +extern void PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags, + unsigned long ulIntMode); +extern void PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long PECIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd, + unsigned char ucHidRe, unsigned char ucDomain, + unsigned char ucProcAdd, unsigned long ulArg, + unsigned char ucSize, unsigned long ulData0, + unsigned long ulData1); +extern unsigned long PECIAdvCmdSendNonBlocking(unsigned long ulBase, + unsigned char ucCmd, + unsigned char ucHidRe, + unsigned char ucDomain, + unsigned char ucProcAdd, + unsigned long ulArg, + unsigned char ucSize, + unsigned long ulData0, + unsigned long ulData1); +extern unsigned long PECIAdvCmdStatusGet(unsigned long ulBase, + unsigned long *pulData0, + unsigned long *pulData1); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PECI_H__ diff --git a/driverlib/pin_map.h b/driverlib/pin_map.h new file mode 100644 index 0000000..f666f41 --- /dev/null +++ b/driverlib/pin_map.h @@ -0,0 +1,61811 @@ +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// +// LM3S101 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S101 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define 32KHZ_PERIPH SYSCTL_PERIPH_GPIOB +#define 32KHZ_PORT GPIO_PORTB_BASE +#define 32KHZ_PIN GPIO_PIN_1 + +#endif // PART_LM3S101 + +//***************************************************************************** +// +// LM3S102 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S102 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define 32KHZ_PERIPH SYSCTL_PERIPH_GPIOB +#define 32KHZ_PORT GPIO_PORTB_BASE +#define 32KHZ_PIN GPIO_PIN_1 + +#endif // PART_LM3S102 + +//***************************************************************************** +// +// LM3S300 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S300 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S300 + +//***************************************************************************** +// +// LM3S301 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S301 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S301 + +//***************************************************************************** +// +// LM3S308 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S308 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S308 + +//***************************************************************************** +// +// LM3S310 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S310 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S310 + +//***************************************************************************** +// +// LM3S315 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S315 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S315 + +//***************************************************************************** +// +// LM3S316 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S316 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S316 + +//***************************************************************************** +// +// LM3S317 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S317 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S317 + +//***************************************************************************** +// +// LM3S328 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S328 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S328 + +//***************************************************************************** +// +// LM3S600 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S600 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S600 + +//***************************************************************************** +// +// LM3S601 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S601 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define IDX_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX_PORT GPIO_PORTD_BASE +#define IDX_PIN GPIO_PIN_7 + +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 + +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S601 + +//***************************************************************************** +// +// LM3S608 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S608 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S608 + +//***************************************************************************** +// +// LM3S610 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S610 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S610 + +//***************************************************************************** +// +// LM3S611 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S611 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S611 + +//***************************************************************************** +// +// LM3S612 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S612 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S612 + +//***************************************************************************** +// +// LM3S613 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S613 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S613 + +//***************************************************************************** +// +// LM3S615 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S615 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S615 + +//***************************************************************************** +// +// LM3S617 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S617 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S617 + +//***************************************************************************** +// +// LM3S618 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S618 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define IDX_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX_PORT GPIO_PORTB_BASE +#define IDX_PIN GPIO_PIN_2 + +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 + +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S618 + +//***************************************************************************** +// +// LM3S628 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S628 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S628 + +//***************************************************************************** +// +// LM3S800 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S800 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S800 + +//***************************************************************************** +// +// LM3S801 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S801 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define IDX_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX_PORT GPIO_PORTD_BASE +#define IDX_PIN GPIO_PIN_7 + +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 + +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S801 + +//***************************************************************************** +// +// LM3S808 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S808 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S808 + +//***************************************************************************** +// +// LM3S811 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S811 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S811 + +//***************************************************************************** +// +// LM3S812 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S812 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S812 + +//***************************************************************************** +// +// LM3S815 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S815 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S815 + +//***************************************************************************** +// +// LM3S817 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S817 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S817 + +//***************************************************************************** +// +// LM3S818 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S818 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define IDX_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX_PORT GPIO_PORTB_BASE +#define IDX_PIN GPIO_PIN_2 + +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 + +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S818 + +//***************************************************************************** +// +// LM3S828 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S828 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 + +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 + +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 + +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 + +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 + +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S828 + +//***************************************************************************** +// +// LM3S1110 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1110 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1110 + +//***************************************************************************** +// +// LM3S1133 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1133 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1133 + +//***************************************************************************** +// +// LM3S1138 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1138 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP4_PORT GPIO_PORTF_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1138 + +//***************************************************************************** +// +// LM3S1150 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1150 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1150 + +//***************************************************************************** +// +// LM3S1162 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1162 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1162 + +//***************************************************************************** +// +// LM3S1165 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1165 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP6_PORT GPIO_PORTB_BASE +#define CCP6_PIN GPIO_PIN_5 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1165 + +//***************************************************************************** +// +// LM3S1332 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1332 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1332 + +//***************************************************************************** +// +// LM3S1435 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1435 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1435 + +//***************************************************************************** +// +// LM3S1439 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1439 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1439 + +//***************************************************************************** +// +// LM3S1512 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1512 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOF +#define C2O_PORT GPIO_PORTF_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP4_PORT GPIO_PORTD_BASE +#define CCP4_PIN GPIO_PIN_5 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1512 + +//***************************************************************************** +// +// LM3S1538 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1538 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1538 + +//***************************************************************************** +// +// LM3S1601 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1601 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1601 + +//***************************************************************************** +// +// LM3S1607 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1607 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_1 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_0 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U2RX_PORT GPIO_PORTB_BASE +#define U2RX_PIN GPIO_PIN_4 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOE +#define U2TX_PORT GPIO_PORTE_BASE +#define U2TX_PIN GPIO_PIN_4 + +#endif // PART_LM3S1607 + +//***************************************************************************** +// +// LM3S1608 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1608 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1608 + +//***************************************************************************** +// +// LM3S1620 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1620 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1620 + +//***************************************************************************** +// +// LM3S1621 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1621 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1621 + +//***************************************************************************** +// +// LM3S1625 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1625 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1625 + +//***************************************************************************** +// +// LM3S1626 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1626 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_5 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_4 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_5 + +#endif // PART_LM3S1626 + +//***************************************************************************** +// +// LM3S1627 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1627 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_5 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX0_PORT GPIO_PORTB_BASE +#define IDX0_PIN GPIO_PIN_4 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1627 + +//***************************************************************************** +// +// LM3S1635 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1635 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1635 + +//***************************************************************************** +// +// LM3S1637 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1637 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1637 + +//***************************************************************************** +// +// LM3S1651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1651 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S1651 + +//***************************************************************************** +// +// LM3S1751 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1751 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1751 + +//***************************************************************************** +// +// LM3S1776 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1776 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 + +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOC +#define FAULT2_PORT GPIO_PORTC_BASE +#define FAULT2_PIN GPIO_PIN_5 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM6_PORT GPIO_PORTC_BASE +#define PWM6_PIN GPIO_PIN_4 + +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM7_PORT GPIO_PORTC_BASE +#define PWM7_PIN GPIO_PIN_6 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1776 + +//***************************************************************************** +// +// LM3S1811 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1811 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1811 + +//***************************************************************************** +// +// LM3S1816 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1816 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1816 + +//***************************************************************************** +// +// LM3S1850 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1850 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1850 + +//***************************************************************************** +// +// LM3S1911 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1911 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1911 + +//***************************************************************************** +// +// LM3S1918 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1918 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1918 + +//***************************************************************************** +// +// LM3S1937 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1937 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S1937 + +//***************************************************************************** +// +// LM3S1958 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1958 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1958 + +//***************************************************************************** +// +// LM3S1960 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1960 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOF +#define C2O_PORT GPIO_PORTF_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP4_PORT GPIO_PORTF_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOH +#define IDX1_PORT GPIO_PORTH_BASE +#define IDX1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHA1_PORT GPIO_PORTG_BASE +#define PHA1_PIN GPIO_PIN_6 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 + +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHB1_PORT GPIO_PORTG_BASE +#define PHB1_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1960 + +//***************************************************************************** +// +// LM3S1968 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1968 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT_PORT GPIO_PORTH_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOF +#define IDX1_PORT GPIO_PORTF_BASE +#define IDX1_PIN GPIO_PIN_1 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHA1_PORT GPIO_PORTG_BASE +#define PHA1_PIN GPIO_PIN_6 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHB1_PORT GPIO_PORTG_BASE +#define PHB1_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_2 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S1968 + +//***************************************************************************** +// +// LM3S1B21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1B21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1B21 + +//***************************************************************************** +// +// LM3S1C21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1C21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1C21 + +//***************************************************************************** +// +// LM3S1C26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1C26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1C26 + +//***************************************************************************** +// +// LM3S1C58 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1C58 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 + +#define GPIO_PG5_CCP5 0x00061401 + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 + +#define GPIO_PH1_CCP7 0x00070401 + +#endif // PART_LM3S1C58 + +//***************************************************************************** +// +// LM3S1D21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1D21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1D21 + +//***************************************************************************** +// +// LM3S1D26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1D26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1D26 + +//***************************************************************************** +// +// LM3S1F11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1F11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1F11 + +//***************************************************************************** +// +// LM3S1F16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1F16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1F16 + +//***************************************************************************** +// +// LM3S1G21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1G21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1G21 + +//***************************************************************************** +// +// LM3S1G58 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1G58 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 + +#define GPIO_PG5_CCP5 0x00061401 + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 + +#define GPIO_PH1_CCP7 0x00070401 + +#endif // PART_LM3S1G58 + +//***************************************************************************** +// +// LM3S1H11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1H11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1H11 + +//***************************************************************************** +// +// LM3S1H16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1H16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1H16 + +//***************************************************************************** +// +// LM3S1J11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1J11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH2_C1O 0x00070802 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1J11 + +//***************************************************************************** +// +// LM3S1J16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1J16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1J16 + +//***************************************************************************** +// +// LM3S1N11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1N11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH2_C1O 0x00070802 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1N11 + +//***************************************************************************** +// +// LM3S1N16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1N16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1N16 + +//***************************************************************************** +// +// LM3S1P51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1P51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S1P51 + +//***************************************************************************** +// +// LM3S1R21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1R21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1R21 + +//***************************************************************************** +// +// LM3S1R26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1R26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1R26 + +//***************************************************************************** +// +// LM3S1W16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1W16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1W16 + +//***************************************************************************** +// +// LM3S1Z16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1Z16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1Z16 + +//***************************************************************************** +// +// LM3S2016 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2016 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2016 + +//***************************************************************************** +// +// LM3S2110 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2110 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2110 + +//***************************************************************************** +// +// LM3S2139 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2139 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2139 + +//***************************************************************************** +// +// LM3S2276 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2276 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 + +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOC +#define FAULT2_PORT GPIO_PORTC_BASE +#define FAULT2_PIN GPIO_PIN_5 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM6_PORT GPIO_PORTC_BASE +#define PWM6_PIN GPIO_PIN_4 + +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM7_PORT GPIO_PORTC_BASE +#define PWM7_PIN GPIO_PIN_6 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2276 + +//***************************************************************************** +// +// LM3S2410 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2410 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2410 + +//***************************************************************************** +// +// LM3S2412 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2412 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2412 + +//***************************************************************************** +// +// LM3S2432 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2432 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2432 + +//***************************************************************************** +// +// LM3S2533 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2533 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2533 + +//***************************************************************************** +// +// LM3S2601 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2601 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2601 + +//***************************************************************************** +// +// LM3S2608 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2608 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2608 + +//***************************************************************************** +// +// LM3S2616 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2616 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_7 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_7 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0RX_PORT GPIO_PORTA_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0TX_PORT GPIO_PORTA_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2616 + +//***************************************************************************** +// +// LM3S2620 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2620 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOE +#define C2O_PORT GPIO_PORTE_BASE +#define C2O_PIN GPIO_PIN_7 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2620 + +//***************************************************************************** +// +// LM3S2637 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2637 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2637 + +//***************************************************************************** +// +// LM3S2651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2651 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2651 + +//***************************************************************************** +// +// LM3S2671 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2671 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_7 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_7 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_5 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_1 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2671 + +//***************************************************************************** +// +// LM3S2678 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2678 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_1 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_0 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT0_PORT GPIO_PORTB_BASE +#define FAULT0_PIN GPIO_PIN_3 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX0_PORT GPIO_PORTB_BASE +#define IDX0_PIN GPIO_PIN_2 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2678 + +//***************************************************************************** +// +// LM3S2730 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2730 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2730 + +//***************************************************************************** +// +// LM3S2739 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2739 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2739 + +//***************************************************************************** +// +// LM3S2776 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2776 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 + +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOC +#define FAULT2_PORT GPIO_PORTC_BASE +#define FAULT2_PIN GPIO_PIN_5 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM6_PORT GPIO_PORTC_BASE +#define PWM6_PIN GPIO_PIN_4 + +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM7_PORT GPIO_PORTC_BASE +#define PWM7_PIN GPIO_PIN_6 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2776 + +//***************************************************************************** +// +// LM3S2793 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2793 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2793 + +//***************************************************************************** +// +// LM3S2911 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2911 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2911 + +//***************************************************************************** +// +// LM3S2918 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2918 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S2918 + +//***************************************************************************** +// +// LM3S2939 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2939 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2939 + +//***************************************************************************** +// +// LM3S2948 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2948 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2948 + +//***************************************************************************** +// +// LM3S2950 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2950 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOF +#define C2O_PORT GPIO_PORTF_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_2 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_3 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2950 + +//***************************************************************************** +// +// LM3S2965 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2965 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP4_PORT GPIO_PORTD_BASE +#define CCP4_PIN GPIO_PIN_5 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP5_PORT GPIO_PORTG_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOH +#define IDX1_PORT GPIO_PORTH_BASE +#define IDX1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHA1_PORT GPIO_PORTG_BASE +#define PHA1_PIN GPIO_PIN_6 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 + +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHB1_PORT GPIO_PORTG_BASE +#define PHB1_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_2 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_3 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S2965 + +//***************************************************************************** +// +// LM3S2B93 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2B93 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2B93 + +//***************************************************************************** +// +// LM3S2D93 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2D93 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2D93 + +//***************************************************************************** +// +// LM3S2U93 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2U93 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2U93 + +//***************************************************************************** +// +// LM3S3634 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3634 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_1 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_0 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#endif // PART_LM3S3634 + +//***************************************************************************** +// +// LM3S3651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3651 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_7 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_3 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP6_PORT GPIO_PORTD_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP7_PORT GPIO_PORTD_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 + +#endif // PART_LM3S3651 + +//***************************************************************************** +// +// LM3S3654 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3654 + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3654 + +//***************************************************************************** +// +// LM3S3739 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3739 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP7_PORT GPIO_PORTD_BASE +#define CCP7_PIN GPIO_PIN_3 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2RX_PORT GPIO_PORTD_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2TX_PORT GPIO_PORTD_BASE +#define U2TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 + +#endif // PART_LM3S3739 + +//***************************************************************************** +// +// LM3S3748 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3748 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_3 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP2_PORT GPIO_PORTF_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_4 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOF +#define FAULT0_PORT GPIO_PORTF_BASE +#define FAULT0_PIN GPIO_PIN_4 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT1_PORT GPIO_PORTG_BASE +#define FAULT1_PIN GPIO_PIN_5 + +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT2_PORT GPIO_PORTG_BASE +#define FAULT2_PIN GPIO_PIN_3 + +#define FAULT3_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT3_PORT GPIO_PORTH_BASE +#define FAULT3_PIN GPIO_PIN_2 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM2_PORT GPIO_PORTF_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM3_PORT GPIO_PORTF_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM4_PORT GPIO_PORTG_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM5_PORT GPIO_PORTG_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM6_PORT GPIO_PORTG_BASE +#define PWM6_PIN GPIO_PIN_6 + +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM7_PORT GPIO_PORTG_BASE +#define PWM7_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOC +#define U1RX_PORT GPIO_PORTC_BASE +#define U1RX_PIN GPIO_PIN_6 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOC +#define U1TX_PORT GPIO_PORTC_BASE +#define U1TX_PIN GPIO_PIN_7 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 + +#endif // PART_LM3S3748 + +//***************************************************************************** +// +// LM3S3749 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3749 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_7 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_3 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP2_PORT GPIO_PORTF_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP3_PORT GPIO_PORTA_BASE +#define CCP3_PIN GPIO_PIN_7 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP4_PORT GPIO_PORTF_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP6_PORT GPIO_PORTD_BASE +#define CCP6_PIN GPIO_PIN_2 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT0_PORT GPIO_PORTG_BASE +#define FAULT0_PIN GPIO_PIN_2 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT1_PORT GPIO_PORTG_BASE +#define FAULT1_PIN GPIO_PIN_4 + +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT2_PORT GPIO_PORTG_BASE +#define FAULT2_PIN GPIO_PIN_3 + +#define FAULT3_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT3_PORT GPIO_PORTH_BASE +#define FAULT3_PIN GPIO_PIN_2 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SDA_PORT GPIO_PORTG_BASE +#define I2C1SDA_PIN GPIO_PIN_1 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOG +#define IDX0_PORT GPIO_PORTG_BASE +#define IDX0_PIN GPIO_PIN_5 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHA0_PORT GPIO_PORTF_BASE +#define PHA0_PIN GPIO_PIN_6 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_6 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM6_PORT GPIO_PORTG_BASE +#define PWM6_PIN GPIO_PIN_6 + +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM7_PORT GPIO_PORTG_BASE +#define PWM7_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2RX_PORT GPIO_PORTD_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2TX_PORT GPIO_PORTD_BASE +#define U2TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 + +#endif // PART_LM3S3749 + +//***************************************************************************** +// +// LM3S3826 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3826 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3826 + +//***************************************************************************** +// +// LM3S3J26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3J26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3J26 + +//***************************************************************************** +// +// LM3S3N26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3N26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3N26 + +//***************************************************************************** +// +// LM3S3W26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3W26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3W26 + +//***************************************************************************** +// +// LM3S3Z26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3Z26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3Z26 + +//***************************************************************************** +// +// LM3S5632 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5632 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#endif // PART_LM3S5632 + +//***************************************************************************** +// +// LM3S5651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5651 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5651 + +//***************************************************************************** +// +// LM3S5652 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5652 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP2_PORT GPIO_PORTE_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP3_PORT GPIO_PORTA_BASE +#define CCP3_PIN GPIO_PIN_7 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 + +#endif // PART_LM3S5652 + +//***************************************************************************** +// +// LM3S5656 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5656 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5656 + +//***************************************************************************** +// +// LM3S5662 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5662 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_2 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT0_PORT GPIO_PORTB_BASE +#define FAULT0_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 + +#endif // PART_LM3S5662 + +//***************************************************************************** +// +// LM3S5732 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5732 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#endif // PART_LM3S5732 + +//***************************************************************************** +// +// LM3S5737 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5737 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_1 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#endif // PART_LM3S5737 + +//***************************************************************************** +// +// LM3S5739 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5739 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0RX_PORT GPIO_PORTA_BASE +#define CAN0RX_PIN GPIO_PIN_6 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0TX_PORT GPIO_PORTA_BASE +#define CAN0TX_PIN GPIO_PIN_7 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 + +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 + +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP7_PORT GPIO_PORTD_BASE +#define CCP7_PIN GPIO_PIN_3 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SDA_PORT GPIO_PORTG_BASE +#define I2C1SDA_PIN GPIO_PIN_1 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2RX_PORT GPIO_PORTD_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2TX_PORT GPIO_PORTD_BASE +#define U2TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 + +#endif // PART_LM3S5739 + +//***************************************************************************** +// +// LM3S5747 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5747 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#endif // PART_LM3S5747 + +//***************************************************************************** +// +// LM3S5749 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5749 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_1 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT0_PORT GPIO_PORTG_BASE +#define FAULT0_PIN GPIO_PIN_2 + +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT1_PORT GPIO_PORTG_BASE +#define FAULT1_PIN GPIO_PIN_4 + +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT2_PORT GPIO_PORTG_BASE +#define FAULT2_PIN GPIO_PIN_3 + +#define FAULT3_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT3_PORT GPIO_PORTH_BASE +#define FAULT3_PIN GPIO_PIN_2 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOG +#define IDX0_PORT GPIO_PORTG_BASE +#define IDX0_PIN GPIO_PIN_5 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHA0_PORT GPIO_PORTF_BASE +#define PHA0_PIN GPIO_PIN_6 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 + +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM6_PORT GPIO_PORTG_BASE +#define PWM6_PIN GPIO_PIN_6 + +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM7_PORT GPIO_PORTG_BASE +#define PWM7_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 + +#endif // PART_LM3S5749 + +//***************************************************************************** +// +// LM3S5752 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5752 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP2_PORT GPIO_PORTE_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP3_PORT GPIO_PORTA_BASE +#define CCP3_PIN GPIO_PIN_7 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 + +#endif // PART_LM3S5752 + +//***************************************************************************** +// +// LM3S5762 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5762 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_2 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT0_PORT GPIO_PORTB_BASE +#define FAULT0_PIN GPIO_PIN_3 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 + +#endif // PART_LM3S5762 + +//***************************************************************************** +// +// LM3S5791 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5791 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5791 + +//***************************************************************************** +// +// LM3S5951 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5951 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5951 + +//***************************************************************************** +// +// LM3S5956 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5956 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5956 + +//***************************************************************************** +// +// LM3S5B91 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5B91 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5B91 + +//***************************************************************************** +// +// LM3S5C31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5C31 + +//***************************************************************************** +// +// LM3S5C36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5C36 + +//***************************************************************************** +// +// LM3S5C51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5C51 + +//***************************************************************************** +// +// LM3S5C56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5C56 + +//***************************************************************************** +// +// LM3S5D51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5D51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5D51 + +//***************************************************************************** +// +// LM3S5D56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5D56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5D56 + +//***************************************************************************** +// +// LM3S5D91 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5D91 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5D91 + +//***************************************************************************** +// +// LM3S5G31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5G31 + +//***************************************************************************** +// +// LM3S5G36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5G36 + +//***************************************************************************** +// +// LM3S5G51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5G51 + +//***************************************************************************** +// +// LM3S5G56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5G56 + +//***************************************************************************** +// +// LM3S5K31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5K31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5K31 + +//***************************************************************************** +// +// LM3S5K36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5K36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5K36 + +//***************************************************************************** +// +// LM3S5P31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5P31 + +//***************************************************************************** +// +// LM3S5P36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5P36 + +//***************************************************************************** +// +// LM3S5P3B Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P3B + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5P3B + +//***************************************************************************** +// +// LM3S5P51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5P51 + +//***************************************************************************** +// +// LM3S5P56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5P56 + +//***************************************************************************** +// +// LM3S5R31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5R31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5R31 + +//***************************************************************************** +// +// LM3S5R36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5R36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5R36 + +//***************************************************************************** +// +// LM3S5T36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5T36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5T36 + +//***************************************************************************** +// +// LM3S5U91 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5U91 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5U91 + +//***************************************************************************** +// +// LM3S5Y36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5Y36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5Y36 + +//***************************************************************************** +// +// LM3S6100 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6100 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6100 + +//***************************************************************************** +// +// LM3S6110 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6110 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6110 + +//***************************************************************************** +// +// LM3S6420 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6420 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6420 + +//***************************************************************************** +// +// LM3S6422 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6422 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6422 + +//***************************************************************************** +// +// LM3S6432 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6432 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6432 + +//***************************************************************************** +// +// LM3S6537 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6537 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6537 + +//***************************************************************************** +// +// LM3S6610 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6610 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOE +#define C2O_PORT GPIO_PORTE_BASE +#define C2O_PIN GPIO_PIN_7 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6610 + +//***************************************************************************** +// +// LM3S6611 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6611 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6611 + +//***************************************************************************** +// +// LM3S6618 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6618 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6618 + +//***************************************************************************** +// +// LM3S6633 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6633 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6633 + +//***************************************************************************** +// +// LM3S6637 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6637 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6637 + +//***************************************************************************** +// +// LM3S6730 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6730 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6730 + +//***************************************************************************** +// +// LM3S6753 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6753 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6753 + +//***************************************************************************** +// +// LM3S6816 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6816 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT_PORT GPIO_PORTE_BASE +#define FAULT_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6816 + +//***************************************************************************** +// +// LM3S6911 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6911 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6911 + +//***************************************************************************** +// +// LM3S6916 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6916 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT_PORT GPIO_PORTE_BASE +#define FAULT_PIN GPIO_PIN_1 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6916 + +//***************************************************************************** +// +// LM3S6918 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6918 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S6918 + +//***************************************************************************** +// +// LM3S6938 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6938 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6938 + +//***************************************************************************** +// +// LM3S6950 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6950 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6950 + +//***************************************************************************** +// +// LM3S6952 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6952 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6952 + +//***************************************************************************** +// +// LM3S6965 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6965 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 + +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOF +#define IDX1_PORT GPIO_PORTF_BASE +#define IDX1_PIN GPIO_PIN_1 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHA1_PORT GPIO_PORTE_BASE +#define PHA1_PIN GPIO_PIN_3 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHB1_PORT GPIO_PORTE_BASE +#define PHB1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S6965 + +//***************************************************************************** +// +// LM3S6C11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6C11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#endif // PART_LM3S6C11 + +//***************************************************************************** +// +// LM3S6C65 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6C65 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S6C65 + +//***************************************************************************** +// +// LM3S6G11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6G11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#endif // PART_LM3S6G11 + +//***************************************************************************** +// +// LM3S6G65 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6G65 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S6G65 + +//***************************************************************************** +// +// LM3S8530 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8530 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CAN2RX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2RX_PORT GPIO_PORTE_BASE +#define CAN2RX_PIN GPIO_PIN_4 + +#define CAN2TX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2TX_PORT GPIO_PORTE_BASE +#define CAN2TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S8530 + +//***************************************************************************** +// +// LM3S8538 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8538 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8538 + +//***************************************************************************** +// +// LM3S8630 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8630 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8630 + +//***************************************************************************** +// +// LM3S8730 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8730 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8730 + +//***************************************************************************** +// +// LM3S8733 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8733 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8733 + +//***************************************************************************** +// +// LM3S8738 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8738 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S8738 + +//***************************************************************************** +// +// LM3S8930 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8930 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S8930 + +//***************************************************************************** +// +// LM3S8933 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8933 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8933 + +//***************************************************************************** +// +// LM3S8938 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8938 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 + +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 + +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 + +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 + +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 + +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 + +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S8938 + +//***************************************************************************** +// +// LM3S8962 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8962 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 + +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOF +#define IDX1_PORT GPIO_PORTF_BASE +#define IDX1_PIN GPIO_PIN_1 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHA1_PORT GPIO_PORTE_BASE +#define PHA1_PIN GPIO_PIN_3 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_6 + +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHB1_PORT GPIO_PORTE_BASE +#define PHB1_PIN GPIO_PIN_2 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8962 + +//***************************************************************************** +// +// LM3S8970 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8970 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 + +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 + +#define CAN2RX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2RX_PORT GPIO_PORTE_BASE +#define CAN2RX_PIN GPIO_PIN_4 + +#define CAN2TX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2TX_PORT GPIO_PORTE_BASE +#define CAN2TX_PIN GPIO_PIN_5 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 + +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 + +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 + +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 + +#endif // PART_LM3S8970 + +//***************************************************************************** +// +// LM3S8971 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8971 + +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 + +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 + +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 + +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 + +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 + +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 + +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX0_PORT GPIO_PORTB_BASE +#define IDX0_PIN GPIO_PIN_2 + +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 + +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 + +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 + +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 + +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 + +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 + +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 + +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 + +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 + +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#endif // PART_LM3S8971 + +//***************************************************************************** +// +// LM3S8C62 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8C62 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 + +#define GPIO_PD6_FAULT0 0x00031801 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S8C62 + +//***************************************************************************** +// +// LM3S8G62 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8G62 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 + +#define GPIO_PD6_FAULT0 0x00031801 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S8G62 + +//***************************************************************************** +// +// LM3S9781 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9781 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9781 + +//***************************************************************************** +// +// LM3S9790 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9790 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9790 + +//***************************************************************************** +// +// LM3S9792 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9792 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9792 + +//***************************************************************************** +// +// LM3S9971 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9971 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9971 + +//***************************************************************************** +// +// LM3S9997 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9997 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9997 + +//***************************************************************************** +// +// LM3S9B81 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B81 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B81 + +//***************************************************************************** +// +// LM3S9B90 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B90 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9B90 + +//***************************************************************************** +// +// LM3S9B92 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B92 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B92 + +//***************************************************************************** +// +// LM3S9B95 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B95 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B95 + +//***************************************************************************** +// +// LM3S9B96 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B96 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B96 + +//***************************************************************************** +// +// LM3S9BN2 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9BN2 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9BN2 + +//***************************************************************************** +// +// LM3S9BN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9BN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9BN5 + +//***************************************************************************** +// +// LM3S9BN6 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9BN6 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9BN6 + +//***************************************************************************** +// +// LM3S9C97 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9C97 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9C97 + +//***************************************************************************** +// +// LM3S9CN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9CN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9CN5 + +//***************************************************************************** +// +// LM3S9D81 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D81 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D81 + +//***************************************************************************** +// +// LM3S9D90 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D90 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9D90 + +//***************************************************************************** +// +// LM3S9D92 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D92 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D92 + +//***************************************************************************** +// +// LM3S9D95 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D95 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D95 + +//***************************************************************************** +// +// LM3S9D96 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D96 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D96 + +//***************************************************************************** +// +// LM3S9DN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9DN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9DN5 + +//***************************************************************************** +// +// LM3S9DN6 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9DN6 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9DN6 + +//***************************************************************************** +// +// LM3S9G97 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9G97 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9G97 + +//***************************************************************************** +// +// LM3S9GN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9GN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9GN5 + +//***************************************************************************** +// +// LM3S9L71 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9L71 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9L71 + +//***************************************************************************** +// +// LM3S9L97 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9L97 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9L97 + +//***************************************************************************** +// +// LM3S9U81 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U81 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U81 + +//***************************************************************************** +// +// LM3S9U90 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U90 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9U90 + +//***************************************************************************** +// +// LM3S9U92 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U92 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U92 + +//***************************************************************************** +// +// LM3S9U95 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U95 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U95 + +//***************************************************************************** +// +// LM3S9U96 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U96 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U96 + +//***************************************************************************** +// +// LM4F110B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110B2QR + +//***************************************************************************** +// +// LM4F110C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110C4QR + +//***************************************************************************** +// +// LM4F110E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110E5QR + +//***************************************************************************** +// +// LM4F110H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110H5QR + +//***************************************************************************** +// +// LM4F111B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111B2QR + +//***************************************************************************** +// +// LM4F111C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111C4QR + +//***************************************************************************** +// +// LM4F111E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111E5QR + +//***************************************************************************** +// +// LM4F111H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111H5QR + +//***************************************************************************** +// +// LM4F112C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112C4QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F112C4QC + +//***************************************************************************** +// +// LM4F112E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112E5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F112E5QC + +//***************************************************************************** +// +// LM4F112H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112H5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F112H5QC + +//***************************************************************************** +// +// LM4F112H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112H5QD + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F112H5QD + +//***************************************************************************** +// +// LM4F120B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120B2QR + +//***************************************************************************** +// +// LM4F120C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120C4QR + +//***************************************************************************** +// +// LM4F120E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120E5QR + +//***************************************************************************** +// +// LM4F120H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120H5QR + +//***************************************************************************** +// +// LM4F121B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121B2QR + +//***************************************************************************** +// +// LM4F121C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121C4QR + +//***************************************************************************** +// +// LM4F121E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121E5QR + +//***************************************************************************** +// +// LM4F121H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121H5QR + +//***************************************************************************** +// +// LM4F122C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122C4QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F122C4QC + +//***************************************************************************** +// +// LM4F122E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122E5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F122E5QC + +//***************************************************************************** +// +// LM4F122H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122H5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F122H5QC + +//***************************************************************************** +// +// LM4F122H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122H5QD + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F122H5QD + +//***************************************************************************** +// +// LM4F130C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F130C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F130C4QR + +//***************************************************************************** +// +// LM4F130E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F130E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F130E5QR + +//***************************************************************************** +// +// LM4F130H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F130H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F130H5QR + +//***************************************************************************** +// +// LM4F131C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F131C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F131C4QR + +//***************************************************************************** +// +// LM4F131E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F131E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F131E5QR + +//***************************************************************************** +// +// LM4F131H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F131H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F131H5QR + +//***************************************************************************** +// +// LM4F132C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132C4QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F132C4QC + +//***************************************************************************** +// +// LM4F132E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132E5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F132E5QC + +//***************************************************************************** +// +// LM4F132H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132H5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F132H5QC + +//***************************************************************************** +// +// LM4F132H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132H5QD + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F132H5QD + +//***************************************************************************** +// +// LM4F210B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F210B2QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F210B2QR + +//***************************************************************************** +// +// LM4F210C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F210C4QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F210C4QR + +//***************************************************************************** +// +// LM4F210E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F210E5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F210E5QR + +//***************************************************************************** +// +// LM4F210H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F210H5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F210H5QR + +//***************************************************************************** +// +// LM4F211B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F211B2QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F211B2QR + +//***************************************************************************** +// +// LM4F211C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F211C4QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F211C4QR + +//***************************************************************************** +// +// LM4F211E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F211E5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F211E5QR + +//***************************************************************************** +// +// LM4F211H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F211H5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F211H5QR + +//***************************************************************************** +// +// LM4F212C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F212C4QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F212C4QC + +//***************************************************************************** +// +// LM4F212E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F212E5QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F212E5QC + +//***************************************************************************** +// +// LM4F212H5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F212H5BB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4F212H5BB + +//***************************************************************************** +// +// LM4F212H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F212H5QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F212H5QC + +//***************************************************************************** +// +// LM4F212H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F212H5QD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F212H5QD + +//***************************************************************************** +// +// LM4F230E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F230E5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F230E5QR + +//***************************************************************************** +// +// LM4F230H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F230H5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F230H5QR + +//***************************************************************************** +// +// LM4F231E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F231E5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F231E5QR + +//***************************************************************************** +// +// LM4F231H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F231H5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F231H5QR + +//***************************************************************************** +// +// LM4F232E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232E5QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F232E5QC + +//***************************************************************************** +// +// LM4F232H5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232H5BB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4F232H5BB + +//***************************************************************************** +// +// LM4F232H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232H5QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F232H5QC + +//***************************************************************************** +// +// LM4F232H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232H5QD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F232H5QD + +//***************************************************************************** +// +// LM4FS1AH5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FS1AH5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FS1AH5BB + +//***************************************************************************** +// +// LM4FS1GE5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FS1GE5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK5_U7TX 0x00091401 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FS1GE5BB + +//***************************************************************************** +// +// LM4FS1GH5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FS1GH5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK5_U7TX 0x00091401 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FS1GH5BB + +//***************************************************************************** +// +// LM4FS99H5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FS99H5BB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_FAN0PWM7 0x00080802 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_FAN0TACH7 0x00080C02 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_FAN0PWM6 0x00091002 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_FAN0TACH6 0x00091402 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FS99H5BB + +//***************************************************************************** +// +// LM4FSXAH5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FSXAH5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FSXAH5BB + +//***************************************************************************** +// +// LM4FSXLH5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FSXLH5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FSXLH5BB + +//***************************************************************************** +// +// Pin Mapping Functions +// +// This section describes the code that is responsible for handling the +// mapping of peripheral functions to their physical location on the pins of +// a device. +// +//***************************************************************************** + +//***************************************************************************** +// +// Definitions to support mapping GPIO Ports and Pins to their function. +// +//***************************************************************************** + +//***************************************************************************** +// +// Configures the specified ADC pin to function as an ADC pin. +// +// \param ulName is one of the valid names for the ADC pins. +// +// This function takes on of the valid names for an ADC pin and configures +// the pin for its ADC functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2, +// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7. +// +// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeADC(ulName) GPIOPinTypeADC(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified CAN pin to function as a CAN pin. +// +// \param ulName is one of the valid names for the CAN pins. +// +// This function takes one of the valid names for a CAN pin and configures +// the pin for its CAN functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX, +// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX. +// +// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeCAN(ulName) GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified comparator pin to function as a comparator pin. +// +// \param ulName is one of the valid names for the Comparator pins. +// +// This function takes one of the valid names for a comparator pin and +// configures the pin for its comparator functionality depending on the part +// that is defined. +// +// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS, +// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS. +// +// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins +// at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeComparator(ulName) \ + GPIOPinTypeComparator(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified I2C pin to function as an I2C pin. +// +// \param ulName is one of the valid names for the I2C pins. +// +// This function takes one of the valid names for an I2C pin and configures +// the pin for its I2C functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA, +// \b I2C1SCL, or \b I2C1SDA. +// +// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified Ethernet LED to function as an Ethernet LED pin. +// +// \param ulName is one of the valid names for the Ethernet LED pins. +// +// This function takes one of the valid names for an Ethernet LED pin and +// configures the pin for its Ethernet LED functionality depending on the part +// that is defined. +// +// The valid names for the pins are as follows: \b LED0 or \b LED1. +// +// sa GPIOPinTypeEthernetLED() in order to configure multiple Ethernet LED +// pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeEthernetLED(ulName) \ + GPIOPinTypeEthernetLED(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified PWM pin to function as a PWM pin. +// +// \param ulName is one of the valid names for the PWM pins. +// +// This function takes one of the valid names for a PWM pin and configures +// the pin for its PWM functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2, +// \b PWM3, \b PWM4, \b PWM5, or \b FAULT. +// +// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypePWM(ulName) GPIOPinTypePWM(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified QEI pin to function as a QEI pin. +// +// \param ulName is one of the valid names for the QEI pins. +// +// This function takes one of the valid names for a QEI pin and configures +// the pin for its QEI functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0, +// \b PHA1, \b PHB1, or \b IDX1. +// +// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeQEI(ulName) GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified SSI pin to function as an SSI pin. +// +// \param ulName is one of the valid names for the SSI pins. +// +// This function takes one of the valid names for an SSI pin and configures +// the pin for its SSI functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS, +// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX. +// +// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeSSI(ulName) GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified Timer pin to function as a Timer pin. +// +// \param ulName is one of the valid names for the Timer pins. +// +// This function takes one of the valid names for a Timer pin and configures +// the pin for its Timer functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2, +// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7. +// +// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeTimer(ulName) GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified UART pin to function as a UART pin. +// +// \param ulName is one of the valid names for the UART pins. +// +// This function takes one of the valid names for a UART pin and configures +// the pin for its UART functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX, +// \b U1TX, \b U2RX, or \b U2TX. +// +// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeUART(ulName) GPIOPinTypeUART(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +//! Configures the specified USB digital pin to function as a USB pin. +//! +//! \param ulName is one of the valid names for a USB digital pin. +//! +//! This function takes one of the valid names for a USB digital pin and +//! configures the pin for its USB functionality depending on the part that is +//! defined. +//! +//! The valid names for the pins are as follows: \b EPEN or \b PFAULT. +//! +//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at +//! once. +//! +//! \return None. +// +//***************************************************************************** +#define PinTypeUSBDigital(ulName) \ + GPIOPinTypeUSBDigital(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +//! Enables the peripheral port used by the given pin. +//! +//! \param ulName is one of the valid names for a pin. +//! +//! This function takes one of the valid names for a pin function and +//! enables the peripheral port for that pin depending on the part that is +//! defined. +//! +//! Any valid pin name can be used. +//! +//! \sa SysCtlPeripheralEnable() in order to enable a single port when +//! multiple pins are on the same port. +//! +//! \return None. +// +//***************************************************************************** +#define PeripheralEnable(ulName) \ + SysCtlPeripheralEnable(ulName##_PERIPH) + +#endif // __PIN_MAP_H__ diff --git a/driverlib/pwm.c b/driverlib/pwm.c new file mode 100644 index 0000000..25dfe87 --- /dev/null +++ b/driverlib/pwm.c @@ -0,0 +1,1880 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pwm.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \ + ((_mod_) + PWM_GEN_EXT_0 + \ + ((_gen_) - PWM_GEN_0) * 2) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! \internal +//! Checks a PWM generator number. +//! +//! \param ulGen is the generator number. +//! +//! This function determines if a PWM generator number is valid. +//! +//! \return Returnes \b true if the generator number is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +PWMGenValid(unsigned long ulGen) +{ + return((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2) || (ulGen == PWM_GEN_3)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a PWM output number. +//! +//! \param ulPWMOut is the output number. +//! +//! This function determines if a PWM output number is valid. +//! +//! \return Returns \b true if the output number is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +PWMOutValid(unsigned long ulPWMOut) +{ + return((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5) || + (ulPWMOut == PWM_OUT_6) || (ulPWMOut == PWM_OUT_7)); +} +#endif + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to configure. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulConfig is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it counts from a value down to zero, +//! and then resets to the preset value, producing left-aligned PWM +//! signals (that is, the rising edge of the two PWM signals produced by the +//! generator occur at the same time). In count up/down mode, it counts up +//! from zero to the preset value, counts back down to zero, and then repeats +//! the process, producing center-aligned PWM signals (that is, +//! the middle of the high/low period of the PWM signals produced by the +//! generator occurs at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their effect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This mode allows multiple parameters to be modified and take +//! effect simultaneously, instead of one at a time. Additionally, parameters +//! to multiple PWM generators in synchronous mode can be updated +//! simultaneously, allowing them to be treated as if they were a unified +//! generator. In non-synchronous mode, the parameter updates are not delayed +//! until a synchronization event. In either mode, the parameter updates only +//! occur when the counter is at zero to help prevent oddly formed PWM signals +//! during the update (that is, a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it continues to +//! count until it reaches zero, at which point it pauses until the +//! processor is restarted. If configured to continue running, it keeps +//! counting as if nothing had happened. +//! +//! The \e ulConfig parameter contains the desired configuration. It is the +//! logical OR of the following: +//! +//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting +//! mode +//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter +//! load and comparator update synchronization mode +//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior +//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or +//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization +//! mode for generator counting mode changes +//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or +//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter +//! synchronization mode +//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to +//! specify whether fault conditions are latched or not +//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to +//! specify whether minimum fault period support is required +//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify +//! whether extended fault source selection support is enabled or not +//! +//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the +//! minimum duration of a PWM fault signal. Faults are signaled for at +//! least this time even if the external fault pin deasserts earlier. Care +//! should be taken when using this mode because during the fault signal +//! period, the fault interrupt from the PWM generator remains asserted. The +//! fault interrupt handler may, therefore, reenter immediately if it exits +//! prior to expiration of the fault timer. +//! +//! \note Changes to the counter mode affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Change the global configuration of the generator. + // + HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER | + PWM_X_CTL_FLTSRC | PWM_X_CTL_DBFALLUPD_M | + PWM_X_CTL_DBRISEUPD_M | + PWM_X_CTL_DBCTLUPD_M | + PWM_X_CTL_GENBUPD_M | + PWM_X_CTL_GENAUPD_M | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ulConfig); + + // + // Set the individual PWM generator controls. + // + if(ulConfig & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (that is, center align the + // signals). + // + HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE | + PWM_X_GENA_ACTCMPAD_ZERO); + HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE | + PWM_X_GENB_ACTCMPBD_ZERO); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (that is, left align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE | + PWM_X_GENA_ACTCMPAD_ZERO); + HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE | + PWM_X_GENB_ACTCMPBD_ZERO); + } +} + +//***************************************************************************** +// +//! Sets the period of a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be modified. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulPeriod specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of PWM clock +//! ticks between pulses on the generator block zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ulPeriod / 2) < 65536); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; + } +} + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of PWM clock ticks +//! between pulses on the generator block zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in PWM clock ticks. +// +//***************************************************************************** +unsigned long +PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Figure out the counter mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ulGen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ulGen + PWM_O_X_LOAD) + 1); + } +} + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be enabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function allows the PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenEnable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be disabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function blocks the PWM clock from driving the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); +} + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to modify. This parameter must be one +//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ulWidth specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth) +{ + unsigned long ulGenBase, ulReg; + + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMOutValid(ulPWMOut)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulWidth /= 2; + } + + // + // Get the period. + // + ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ulWidth < ulReg); + + // + // Compute the compare value. + // + ulReg = ulReg - ulWidth; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; + } + else + { + HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; + } +} + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to query. This parameter must be one of +//! \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. +//! +//! This function gets the currently programmed pulse width for the specified +//! PWM output. If the update of the comparator for the specified output has +//! yet to be completed, the value returned may not be the active pulse width. +//! The value returned is the programmed pulse width, measured in PWM clock +//! ticks. +//! +//! \return Returns the width of the pulse in PWM clock ticks. +// +//***************************************************************************** +unsigned long +PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) +{ + unsigned long ulGenBase, ulReg, ulLoad; + + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMOutValid(ulPWMOut)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load - compare) * 2. Otherwise, set width = load - compare. + // + ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); + } + else + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); + } + ulReg = ulLoad - ulReg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulReg = ulReg * 2; + } + + // + // Return the pulse width. + // + return(ulReg); +} + +//***************************************************************************** +// +//! Enables the PWM dead band output and sets the dead band delays. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param usRise specifies the width of delay from the rising edge. +//! \param usFall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, +//! where the dead bands are defined as the number of \b PWM clock ticks +//! from the rising or falling edge of the generator's \b OutA signal. +//! Note that this function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//**************************************************************************** +void +PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT(usRise < 4096); + ASSERT(usFall < 4096); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Write the dead band delay values. + // + HWREG(ulGen + PWM_O_X_DBRISE) = usRise; + HWREG(ulGen + PWM_O_X_DBFALL) = usFall; + + // + // Enable the deadband functionality. + // + HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +void +PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= + ~(PWM_X_DBCTL_ENABLE); +} + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be updated. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +void +PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | + PWM_GEN_3_BIT))); + + // + // Synchronize pending PWM register changes. + // + HWREG(ulBase + PWM_O_CTL) = ulGenBits; +} + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be synchronized. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base +//! of the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +void +PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | + PWM_GEN_3_BIT))); + + // + // Synchronize the counters in the specified generators by writing to the + // module's synchronization register. + // + HWREG(ulBase + PWM_O_SYNC) = ulGenBits; +} + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function enables or disables the selected PWM outputs. The +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's ENABLE output control register and set or clear the + // requested bits. + // + if(bEnable == true) + { + HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function causes the specified +//! PWM output signals to be inverted or made active low. If \e bInvert is +//! \b false, the specified outputs are passed through as is or made active +//! high. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's INVERT output control register and set or clear the + // requested bits. + // + if(bInvert == true) + { + HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Specifies the level of PWM outputs suppressed in response to a fault +//! condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bDriveHigh determines if the signal is driven high or low during an +//! active fault condition. +//! +//! This function determines whether a PWM output pin that is suppressed in +//! response to a fault condition is driven high or low. The affected outputs +//! are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bDriveHigh determines the output level for the pins identified by +//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs are +//! driven high when a fault is detected. If it is \e false, the pins are +//! driven low. +//! +//! In a fault condition, pins which have not been configured to be suppressed +//! via a call to PWMOutputFault() are unaffected by this function. +//! +//! \note This function is available only on devices which support extended +//! PWM fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bDriveHigh) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's FAULT output control register and set or clear the + // requested bits. + // + if(bDriveHigh == true) + { + HWREG(ulBase + PWM_O_FAULTVAL) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULTVAL) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. +//! \param bFaultSuppress determines if the signal is suppressed or passed +//! through during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bFaultSuppress determines the fault handling +//! characteristics for the selected outputs. If \e bFaultSuppress is \b true, +//! then the selected outputs are made inactive. If \e bFaultSuppress is +//! \b false, then the selected outputs are unaffected by the detected fault. +//! +//! On devices supporting extended PWM fault handling, the state the affected +//! output pins are driven to can be configured with PWMOutputFaultLevel(). If +//! not configured, or if the device does not support extended PWM fault +//! handling, affected outputs are driven low on a fault condition. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultSuppress) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's FAULT output control register and set or clear the + // requested bits. + // + if(bFaultSuppress == true) + { + HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Gets the PWM generator interrupt number. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function returns the interrupt number of the corresponding PWM +//! generator. +//! +//! \return Returns the interrupt number. +// +//***************************************************************************** +static unsigned long +PWMGenIntGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Determine the generator and PWM module in question. + // + switch(ulBase + ulGen) + { + // + // The first PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_0: + { + return(INT_PWM0_0); + } + + // + // The second PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_1: + { + return(INT_PWM0_1); + } + + // + // The third PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_2: + { + return(INT_PWM0_2); + } + + // + // The fourth PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_3: + { + return(INT_PWM0_3); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_0: + { + return(INT_PWM1_0); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_1: + { + return(INT_PWM1_1); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_2: + { + return(INT_PWM1_2); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_3: + { + return(INT_PWM1_3); + } + + // + // An unknown PWM module/generator was specified. + // + default: + { + return(0); + } + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function also enables the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = PWMGenIntGet(ulBase, ulGen); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function unregisters the interrupt handler for the specified +//! PWM generator block. This function also disables the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = PWMGenIntGet(ulBase, ulGen); + + // + // Disable the PWMx interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Gets the PWM fault interrupt number. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function returns the fault interrupt number of the corresponding +//! PWM module. +//! +//! \return Returns the interrupt number. +// +//***************************************************************************** +static unsigned long +PWMFaultIntGet(unsigned long ulBase) +{ + // + // Return the fault interrupt number. + // + return((ulBase == PWM0_BASE) ? INT_PWM0_FAULT : INT_PWM1_FAULT); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function also enables the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + + // + // Get the interrupt number associated with the specified module. + // + ulInt = PWMFaultIntGet(ulBase); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function removes the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function also disables the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + + // + // Get the interrupt number associated with the specified module. + // + ulInt = PWMFaultIntGet(ulBase); + + // + // Disable the PWM fault interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers enabled. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. +//! \param ulIntTrig specifies the interrupts and triggers to be enabled. +//! +//! This function unmasks the specified interrupt(s) and trigger(s) by setting +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ulIntTrig parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, +//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, +//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | + PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | + PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD | + PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU | + PWM_TR_CNT_BD)) == 0); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; +} + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers disabled. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. +//! \param ulIntTrig specifies the interrupts and triggers to be disabled. +//! +//! This function masks the specified interrupt(s) and trigger(s) by clearing +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ulIntTrig parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, +//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, +//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | + PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | + PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD | + PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU | + PWM_TR_CNT_BD)) == 0); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return Returns the contents of the interrupt status register or the +//! contents of the raw interrupt status register for the specified +//! PWM generator. +// +//***************************************************************************** +unsigned long +PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ulGen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ulGen + PWM_O_X_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulInts specifies the interrupts to be cleared. +//! +//! This funciton clears the specified interrupt(s) by writing a 1 to the +//! specified bits of the interrupt status register for the specified PWM +//! generator. The \e ulInts parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | + PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == + 0); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; +} + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be enabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! This function unmasks the specified interrupt(s) by setting the specified +//! bits of the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | + PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Read the module's interrupt enable register and enable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; +} + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be disabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! This function masks the specified interrupt(s) by clearing the specified +//! bits of the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | + PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Read the module's interrupt enable register and disable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); +} + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function clears the fault interrupt by writing to the appropriate bit +//! of the interrupt status register for the selected PWM module. +//! +//! This function clears only the FAULT0 interrupt and is retained for +//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be +//! used instead because it supports all fault interrupts supported on devices +//! with and without extended PWM fault handling support. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0; +} + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status is returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, +//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and +//! \b PWM_INT_FAULT3. +//! +//***************************************************************************** +unsigned long +PWMIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ulBase + PWM_O_ISC)); + } + else + { + return(HWREG(ulBase + PWM_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulFaultInts specifies the fault interrupts to clear. +//! +//! This function clears one or more fault interrupts by writing to the +//! appropriate bit of the PWM interrupt status register. The parameter +//! \e ulFaultInts must be the logical OR of any of \b PWM_INT_FAULT0, +//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! When running on a device supporting extended PWM fault handling, the fault +//! interrupts are derived by performing a logical OR of each of the configured +//! fault trigger signals for a given generator. Therefore, these interrupts +//! are not directly related to the four possible FAULTn inputs to the device +//! but indicate that a fault has been signaled to one of the four possible PWM +//! generators. On a device without extended PWM fault handling, the interrupt +//! is directly related to the state of the single FAULT pin. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Clear the supplied fault bits. + // + HWREG(ulBase + PWM_O_ISC) = ulFaultInts; +} + +//***************************************************************************** +// +//! Configures the minimum fault period and fault pin senses for a given +//! PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator for which fault configuration is being +//! set. This function must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, +//! or \b PWM_GEN_3. +//! \param ulMinFaultPeriod is the minimum fault active period expressed in +//! PWM clock cycles. +//! \param ulFaultSenses indicates which sense of each FAULT input should be +//! considered the ``asserted'' state. Valid values are logical OR +//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. +//! +//! This function configures the minimum fault period for a given generator +//! along with the sense of each of the 4 possible fault inputs. The minimum +//! fault period is expressed in PWM clock cycles and takes effect only if +//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the +//! \e ulConfig parameter. When a fault input is asserted, the minimum fault +//! period timer ensures that it remains asserted for at least the number of +//! clock cycles specified. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulMinFaultPeriod, + unsigned long ulFaultSenses) +{ + // + // Check the arguments. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M); + ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW | + PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW | + PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW | + PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) == + 0); + + // + // Write the minimum fault period. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod; + + // + // Write the fault senses. + // + HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses; +} + +//***************************************************************************** +// +//! Configures the set of fault triggers for a given PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator for which fault triggers are being set. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. +//! \param ulGroup indicates the subset of possible faults that are to be +//! configured. This parameter must be \b PWM_FAULT_GROUP_0 or +//! \b PWM_FAULT_GROUP_1. +//! \param ulFaultTriggers defines the set of inputs that are to contribute +//! towards generation of the fault signal to the given PWM generator. For +//! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0, +//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. For +//! \b PWM_FAULT_GROUP_1, this is the logical OR of \b PWM_FAULT_DCMP0, +//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, +//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or +//! \b PWM_FAULT_DCMP7. +//! +//! This function allows selection of the set of fault inputs that is combined +//! to generate a fault condition to a given PWM generator. By default, all +//! generators use only FAULT0 (for backwards compatibility) but if +//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the +//! \e ulConfig parameter, extended fault handling is enabled and this function +//! must be called to configure the fault triggers. +//! +//! The fault signal to the PWM generator is generated by ORing together each +//! of the signals specified in the \e ulFaultTriggers parameter after having +//! adjusted the sense of each FAULTn input based on the configuration +//! previously set using a call to PWMGenFaultConfigure(). +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, unsigned long ulFaultTriggers) +{ + // + // Check for valid parameters. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) && + ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | + PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0)); + ASSERT((ulGroup == PWM_FAULT_GROUP_1) && + ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | + PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | + PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | + PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); + + // + // Write the fault triggers to the appropriate register. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) = + ulFaultTriggers; + } + else + { + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1) = + ulFaultTriggers; + } +} + +//***************************************************************************** +// +//! Returns the set of fault triggers currently configured for a given PWM +//! generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator for which fault triggers are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGroup indicates the subset of faults that are being queried. This +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! +//! This function allows an application to query the current set of inputs that +//! contribute to the generation of a fault condition to a given PWM generator. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return Returns the current fault triggers configured for the fault group +//! provided. For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of +//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the +//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, +//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, +//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. +// +//***************************************************************************** +unsigned long +PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup) +{ + // + // Check for valid parameters. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + + // + // Return the current fault triggers. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0)); + } + else + { + return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1)); + } +} + +//***************************************************************************** +// +//! Returns the current state of the fault triggers for a given PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator for which fault trigger states are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGroup indicates the subset of faults that are being queried. This +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! +//! This function allows an application to query the current state of each of +//! the fault trigger inputs to a given PWM generator. The current state of +//! each fault trigger input is returned unless PWMGenConfigure() has +//! previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in the +//! \e ulConfig parameter, in which case the returned status is the latched +//! fault trigger status. +//! +//! If latched faults are configured, the application must call +//! PWMGenFaultClear() to clear each trigger. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return Returns the current state of the fault triggers for the given PWM +//! generator. A set bit indicates that the associated trigger is active. +//! For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of +//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the +//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, +//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, +//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. +// +//***************************************************************************** +unsigned long +PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup) +{ + // + // Check for valid parameters. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + + // + // Return the current fault status. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0)); + } + else + { + return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1)); + } +} + +//***************************************************************************** +// +//! Clears one or more latched fault triggers for a given PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator for which fault trigger states are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGroup indicates the subset of faults that are being queried. +//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! \param ulFaultTriggers is the set of fault triggers which are to be +//! cleared. +//! +//! This function allows an application to clear the fault triggers for a +//! given PWM generator. This function is only required if PWMGenConfigure() +//! has previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in +//! parameter \e ulConfig. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, unsigned long ulFaultTriggers) +{ + // + // Check for valid parameters. + // + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) && + ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | + PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0)); + ASSERT((ulGroup == PWM_FAULT_GROUP_1) && + ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | + PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | + PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | + PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); + + // + // Clear the given faults. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) = + ulFaultTriggers; + } + else + { + HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1) = + ulFaultTriggers; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/pwm.h b/driverlib/pwm.h new file mode 100644 index 0000000..73f1c22 --- /dev/null +++ b/driverlib/pwm.h @@ -0,0 +1,298 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#ifndef DEPRECATED +#define PWM_INT_FAULT 0x00010000 // Fault interrupt +#endif +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_1 1 + +#define PWM_FAULT_DCMP0 0x00000001 +#define PWM_FAULT_DCMP1 0x00000002 +#define PWM_FAULT_DCMP2 0x00000004 +#define PWM_FAULT_DCMP3 0x00000008 +#define PWM_FAULT_DCMP4 0x00000010 +#define PWM_FAULT_DCMP5 0x00000020 +#define PWM_FAULT_DCMP6 0x00000040 +#define PWM_FAULT_DCMP7 0x00000080 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFaultLevel(unsigned long ulBase, + unsigned long ulPWMOutBits, + tBoolean bDriveHigh); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultSuppress); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void PWMFaultIntClearExt(unsigned long ulBase, + unsigned long ulFaultInts); +extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulMinFaultPeriod, + unsigned long ulFaultSenses); +extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); +extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern unsigned long PWMGenFaultStatus(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/driverlib/qei.c b/driverlib/qei.c new file mode 100644 index 0000000..237f484 --- /dev/null +++ b/driverlib/qei.c @@ -0,0 +1,633 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_qei.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function enables operation of the quadrature encoder module. The +//! module must be configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +void +QEIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Enable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function disables operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Disable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulConfig is the configuration for the quadrature encoder. See below +//! for a description of this parameter. +//! \param ulMaxPosition specifies the maximum position value. +//! +//! This function configures the operation of the quadrature encoder. The +//! \e ulConfig parameter provides the configuration of the encoder and is the +//! logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ulMaxPosition is the maximum value of the position integrator and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +void +QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Write the new configuration to the hardware. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ulConfig); + + // + // Set the maximum position. + // + HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter is not yet aligned with the index pulse). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +unsigned long +QEIPositionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the current position counter. + // + return(HWREG(ulBase + QEI_O_POS)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPosition is the new position for the encoder. +//! +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +void +QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Set the position counter. + // + HWREG(ulBase + QEI_O_POS) = ulPosition; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +long +QEIDirectionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the direction of rotation. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function returns the error indicator for the quadrature encoder. It +//! is an error for both of the signals of the quadrature input to change at +//! the same time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +tBoolean +QEIErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the error indicator. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function enables operation of the velocity capture in the quadrature +//! encoder module. The module must be configured before velocity capture is +//! enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Enable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; +} + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function disables operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Disable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of \b QEI_VELDIV_1, +//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16, +//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128. +//! \param ulPeriod specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This function configures the operation of the velocity capture portion of +//! the quadrature encoder. The position increment signal is predivided as +//! specified by \e ulPreDiv before being accumulated by the velocity capture. +//! The divided signal is accumulated over \e ulPeriod system clock before +//! being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ulPeriod != 0); + + // + // Set the velocity predivider. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ulPreDiv); + + // + // Set the timer period. + // + HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; +} + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function returns the current speed of the encoder. The value returned +//! is the number of pulses detected in the specified time period; this number +//! can be multiplied by the number of time periods per second and divided by +//! the number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return Returns the number of pulses captured in the given time period. +// +//***************************************************************************** +unsigned long +QEIVelocityGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the speed capture value. + // + return(HWREG(ulBase + QEI_O_SPEED)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This function registers the handler to be called when a quadrature encoder +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific quadrature encoder interrupts must be +//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Determine the interrupt number based on the QEI module. + // + ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1; + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function unregisters the handler to be called when a quadrature +//! encoder interrupt occurs. This function also masks off the interrupt in +//! the interrupt controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Determine the interrupt number based on the QEI module. + // + ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or +//! \b QEI_INTINDEX values. +//! +//! This function enables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. +//! +//! This function disables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the quadrature encoder +//! module. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. +// +//***************************************************************************** +unsigned long +QEIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + QEI_O_ISC)); + } + else + { + return(HWREG(ulBase + QEI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being triggered again immediately upon +//! exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + QEI_O_ISC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/qei.h b/driverlib/qei.h new file mode 100644 index 0000000..84a629f --- /dev/null +++ b/driverlib/qei.h @@ -0,0 +1,127 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/driverlib/readme.txt b/driverlib/readme.txt new file mode 100644 index 0000000..e747a7e --- /dev/null +++ b/driverlib/readme.txt @@ -0,0 +1,36 @@ +This project will build the Stellaris Peripheral Driver Library. + +------------------------------------------------------------------------------- + +Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +This is part of revision 9453 of the Stellaris Peripheral Driver Library. diff --git a/driverlib/rom.h b/driverlib/rom.h new file mode 100644 index 0000000..ff78796 --- /dev/null +++ b/driverlib/rom.h @@ -0,0 +1,6744 @@ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((unsigned long *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14])) +#define ROM_ETHERNETTABLE ((unsigned long *)(ROM_APITABLE[15])) +#define ROM_USBTABLE ((unsigned long *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((unsigned long *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((unsigned long *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21])) +#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[22])) +#define ROM_EPITABLE ((unsigned long *)(ROM_APITABLE[23])) +#define ROM_EEPROMTABLE ((unsigned long *)(ROM_APITABLE[24])) +#define ROM_FANTABLE ((unsigned long *)(ROM_APITABLE[25])) +#define ROM_FPUTABLE ((unsigned long *)(ROM_APITABLE[26])) +#define ROM_LPCTABLE ((unsigned long *)(ROM_APITABLE[27])) +#define ROM_PECITABLE ((unsigned long *)(ROM_APITABLE[28])) +#define ROM_SMBUSTABLE ((unsigned long *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((unsigned long *)(ROM_APITABLE[30])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long *pulBuffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + tBoolean bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulTrigger, \ + unsigned long ulPriority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulStep, \ + unsigned long ulConfig))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceOverflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceUnderflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCProcessorTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFactor))ROM_ADCTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulConfig))ROM_ADCTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorRegionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulLowRef, \ + unsigned long ulHighRef))ROM_ADCTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorReset \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + tBoolean bTrigger, \ + tBoolean bInterrupt))ROM_ADCTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulStatus))ROM_ADCTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCReferenceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCReferenceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPhase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCPhaseDelayGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCResolutionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulResolution))ROM_ADCTABLE[26]) +#endif +#if defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCResolutionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAN API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANInit \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANEnable \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANDisable \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANBitTimingSet \ + ((void (*)(unsigned long ulBase, \ + tCANBitClkParms *pClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANBitTimingGet \ + ((void (*)(unsigned long ulBase, \ + tCANBitClkParms *pClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANMessageSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID, \ + tCANMsgObject *pMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANMessageGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID, \ + tCANMsgObject *pMsgObject, \ + tBoolean bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANMessageClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANRetryGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANRetrySet \ + ((void (*)(unsigned long ulBase, \ + tBoolean bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANErrCntrGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long *pulRxCount, \ + unsigned long *pulTxCount))ROM_CANTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANBitRateSet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulSourceClock, \ + unsigned long ulBitRate))ROM_CANTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulConfig))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorRefSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorValueGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + tBoolean bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EEPROM API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMRead \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_EEPROMTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockCountGet \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockHide \ + ((void (*)(unsigned long ulBlock))ROM_EEPROMTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockLock \ + ((unsigned long (*)(unsigned long ulBlock))ROM_EEPROMTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockPasswordSet \ + ((unsigned long (*)(unsigned long ulBlock, \ + unsigned long *pulPassword, \ + unsigned long ulCount))ROM_EEPROMTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockProtectGet \ + ((unsigned long (*)(unsigned long ulBlock))ROM_EEPROMTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockProtectSet \ + ((unsigned long (*)(unsigned long ulBlock, \ + unsigned long ulProtect))ROM_EEPROMTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockUnlock \ + ((unsigned long (*)(unsigned long ulBlock, \ + unsigned long *pulPassword, \ + unsigned long ulCount))ROM_EEPROMTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_EEPROMTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_EEPROMTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_EEPROMTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_EEPROMTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMMassErase \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMProgram \ + ((unsigned long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_EEPROMTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMProgramNonBlocking \ + ((unsigned long (*)(unsigned long ulData, \ + unsigned long ulAddress))ROM_EEPROMTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMSizeGet \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMStatusGet \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMInit \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EPI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_EPITABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_EPITABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIDividerSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDivider))ROM_EPITABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigSDRAMSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulRefresh))ROM_EPITABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigGPModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulFrameCount, \ + unsigned long ulMaxWait))ROM_EPITABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigHB8Set \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxWait))ROM_EPITABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigHB16Set \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxWait))ROM_EPITABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIAddressMapSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMap))ROM_EPITABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulDataSize, \ + unsigned long ulAddress))ROM_EPITABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadStart \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulCount))ROM_EPITABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadStop \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_EPITABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadCount \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_EPITABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadAvail \ + ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadGet32 \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulCount, \ + unsigned long *pulBuf))ROM_EPITABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadGet16 \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulCount, \ + unsigned short *pusBuf))ROM_EPITABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadGet8 \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulCount, \ + unsigned char *pucBuf))ROM_EPITABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIFIFOConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_EPITABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIWriteFIFOCountGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_EPITABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_EPITABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntErrorStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntErrorClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulErrFlags))ROM_EPITABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Ethernet API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEthClk))ROM_ETHERNETTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_ETHERNETTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetMACAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetMACAddrGet \ + ((void (*)(unsigned long ulBase, \ + unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetEnable \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetDisable \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketGet \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketPut \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_ETHERNETTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucRegAddr, \ + unsigned long ulData))ROM_ETHERNETTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYRead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned char ucRegAddr))ROM_ETHERNETTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_UpdateEthernet \ + ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr))ROM_ETHERNETTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYPowerOff \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYPowerOn \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Fan API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelConfigAuto \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig))ROM_FANTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelConfigManual \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig))ROM_FANTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelDutyGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelDutySet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulDuty))ROM_FANTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelRPMGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelRPMSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulRPM))ROM_FANTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelsGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_FANTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_FANTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProgram \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUsecGet \ + ((unsigned long (*)(void))ROM_FLASHTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUsecSet \ + ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashErase \ + ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProtectSet \ + ((long (*)(unsigned long ulAddress, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProtectSave \ + ((long (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUserGet \ + ((long (*)(unsigned long *pulUser0, \ + unsigned long *pulUser1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUserSet \ + ((long (*)(unsigned long ulUser0, \ + unsigned long ulUser1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUserSave \ + ((long (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUNaNModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPURoundingModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinWrite \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned char ucVal))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODirModeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulPinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODirModeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOIntTypeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulIntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOIntTypeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPadConfigSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulStrength, \ + unsigned long ulPadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPadConfigGet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPin, \ + unsigned long *pulStrength, \ + unsigned long *pulPadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntStatus \ + ((long (*)(unsigned long ulPort, \ + tBoolean bMasked))ROM_GPIOTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntClear \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinRead \ + ((long (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypePWM \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeUART \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeADC \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeI2S \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinConfigure \ + ((void (*)(unsigned long ulPinConfig))ROM_GPIOTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEthernetLED \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeUSBAnalog \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEPI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEthernetMII \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeFan \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeLPC \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypePECIRx \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypePECITx \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[38]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeI2CSCL \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[39]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Hibernate API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateEnableExpClk \ + ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateClockSelect \ + ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateWakeSet \ + ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateWakeGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateLowBatSet \ + ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateLowBatGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSet \ + ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCMatch0Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCMatch0Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_HibernateRTCMatch1Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_HibernateRTCMatch1Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCTrimGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateDataSet \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulCount))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateDataGet \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulCount))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIsActive \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSSMatch0Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSSMatch0Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSSGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateClockConfig \ + ((void (*)(unsigned long ulConfig))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateBatCheckDone \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[30]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulI2CClk, \ + tBoolean bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveInit \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr, \ + tBoolean bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterBusBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterErr \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntStatusEx \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntStatusEx \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulValue))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(unsigned long ulBase, \ + tBoolean bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(unsigned long ulBase, \ + tBoolean bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddrNum, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterLineStateGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[38]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2S API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2STABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxEnable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_I2STABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_I2STABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_I2STABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxFIFOLimitSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLevel))ROM_I2STABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxFIFOLimitGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxFIFOLevelGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxEnable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_I2STABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_I2STABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_I2STABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxFIFOLimitSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLevel))ROM_I2STABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxFIFOLimitGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxFIFOLevelGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxRxEnable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxRxDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxRxConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_I2STABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SMasterClockSelect \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMClock))ROM_I2STABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntEnable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntMasterEnable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntMasterDisable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntDisable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityGroupingGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPrioritySet \ + ((void (*)(unsigned long ulInterrupt, \ + unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityGet \ + ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPendSet \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPendClear \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityMaskSet \ + ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityMaskGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the LPC API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCByteRead \ + ((unsigned char (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCByteWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned char ucData))ROM_LPCTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigCOMxSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset, \ + unsigned long ulCOMxMode))ROM_LPCTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long *pulAddress, \ + unsigned long *pulOffset, \ + unsigned long *pulCOMxMode))ROM_LPCTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigEPSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset))ROM_LPCTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigMBSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset))ROM_LPCTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelDMAConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelDMAConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMask))ROM_LPCTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulStatus))ROM_LPCTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelStatusSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulStatus))ROM_LPCTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_LPCTABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_LPCTABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCHalfWordRead \ + ((unsigned short (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[20]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCHalfWordWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned short usData))ROM_LPCTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIRQ))ROM_LPCTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQConfig \ + ((void (*)(unsigned long ulBase, \ + tBoolean bIRQPulse, \ + tBoolean bIRQOnChange))ROM_LPCTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQSend \ + ((void (*)(unsigned long ulBase))ROM_LPCTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIRQ))ROM_LPCTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_LPCTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCSCIAssert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCount))ROM_LPCTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long *pulCount, \ + unsigned long *pulPoolSize))ROM_LPCTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCWordRead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCWordWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned long ulData))ROM_LPCTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelPoolAddressGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCStatusBlockAddressGet \ + ((unsigned (*)(unsigned long ulBase))ROM_LPCTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCStatusBlockAddressSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulAddress, \ + tBoolean bEnabled))ROM_LPCTABLE[36]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the MPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPUEnable \ + ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionCountGet \ + ((unsigned long (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionEnable \ + ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionDisable \ + ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionSet \ + ((void (*)(unsigned long ulRegion, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionGet \ + ((void (*)(unsigned long ulRegion, \ + unsigned long *pulAddr, \ + unsigned long *pulFlags))ROM_MPUTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PECI API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_PECITABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIAdvCmdSend \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucCmd, \ + unsigned char ucHidRe, \ + unsigned char ucDomain, \ + unsigned char ucProcAdd, \ + unsigned long ulArg, \ + unsigned char ucSize, \ + unsigned long ulData0, \ + unsigned long ulData1))ROM_PECITABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIAdvCmdSendNonBlocking \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned char ucCmd, \ + unsigned char ucHidRe, \ + unsigned char ucDomain, \ + unsigned char ucProcAdd, \ + unsigned long ulArg, \ + unsigned char ucSize, \ + unsigned long ulData0, \ + unsigned long ulData1))ROM_PECITABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIAdvCmdStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long *pulData0, \ + unsigned long *pulData1))ROM_PECITABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPECIClk, \ + unsigned long *pulBaud, \ + unsigned long *pulPoll, \ + unsigned long *pulOffset, \ + unsigned long *pulRetry))ROM_PECITABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPECIClk, \ + unsigned long ulBaud, \ + unsigned long ulPoll, \ + unsigned long ulOffset, \ + unsigned long ulRetry))ROM_PECITABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainMaxReadClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainValueClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain, \ + unsigned long *pulHigh, \ + unsigned long *pulLow))ROM_PECITABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain, \ + unsigned long ulHigh, \ + unsigned long ulLow))ROM_PECITABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainMaxReadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_PECITABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags, \ + unsigned long ulIntMode))ROM_PECITABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PECITABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIBypassEnable \ + ((void (*)(unsigned long ulBase))ROM_PECITABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIBypassDisable \ + ((void (*)(unsigned long ulBase))ROM_PECITABLE[18]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMPulseWidthSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOut, \ + unsigned long ulWidth))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulConfig))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenPeriodSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulPeriod))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenPeriodGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMPulseWidthGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulPWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMDeadBandEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned short usRise, \ + unsigned short usFall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMDeadBandDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMSyncUpdate \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMSyncTimeBase \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputState \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputInvert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputFault \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + tBoolean bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulInts))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMFaultIntClear \ + ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulMinFaultPeriod, \ + unsigned long ulFaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup, \ + unsigned long ulFaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultTriggerGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup, \ + unsigned long ulFaultTriggers))ROM_PWMTABLE[28]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIPositionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIPositionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPosition))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIDirectionGet \ + ((long (*)(unsigned long ulBase))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIErrorGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPreDiv, \ + unsigned long ulPeriod))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SMBus API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + unsigned char *pucAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + unsigned char ucAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucTxData, \ + unsigned char ucTxSize, \ + unsigned char *pucRxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterBlockRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData))ROM_SMBUSTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucData))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucOwnSlaveAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucTxData, \ + unsigned char ucTxSize, \ + unsigned char *pucRxData, \ + unsigned char ucRxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *pSMBus, \ + unsigned long ulI2CBase, \ + unsigned long ulSMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucTxData, \ + unsigned char *pucRxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + tBoolean bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusRxPacketSizeGet \ + ((unsigned char (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char ucAddressNum, \ + unsigned char ucSlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagARGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveCommandGet \ + ((unsigned char (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *pSMBus, \ + unsigned long ulI2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *pSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[54]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveDataSend \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[55]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSSIClk, \ + unsigned long ulProtocol, \ + unsigned long ulMode, \ + unsigned long ulBitRate, \ + unsigned long ulDataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIEnable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDisable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_SSITABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_SSITABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIClockSourceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIClockSourceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSource))ROM_SSITABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlSRAMSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlFlashSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPinPresent \ + ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralPresent \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntEnable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntDisable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntClear \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_SysCtlLDOSet \ + ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_SysCtlLDOGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlResetCauseGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPWMClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlADCSpeedSet \ + ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlADCSpeedGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[28]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlGPIOAHBEnable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlGPIOAHBDisable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_SysCtlI2SMClkSet \ + ((unsigned long (*)(unsigned long ulInputClock, \ + unsigned long ulMClk))ROM_SYSCTLTABLE[33]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlDelay \ + ((void (*)(unsigned long ulCount))ROM_SYSCTLTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralReady \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPIOSCCalibrate \ + ((unsigned long (*)(unsigned long ulType))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[46]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysExc API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickValueGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickPeriodSet \ + ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickPeriodGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlEvent \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulEvent))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerRTCEnable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerRTCDisable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_TIMERTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadSet64 \ + ((void (*)(unsigned long ulBase, \ + unsigned long long ullValue))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerValueGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchSet64 \ + ((void (*)(unsigned long ulBase, \ + unsigned long long ullValue))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTParityModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulParity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTParityModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long ulBaud, \ + unsigned long ulConfig))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long *pulBaud, \ + unsigned long *pulConfig))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTEnableSIR \ + ((void (*)(unsigned long ulBase, \ + tBoolean bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDisableSIR \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharsAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharGetNonBlocking \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharGet \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharPutNonBlocking \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTBreakCtl \ + ((void (*)(unsigned long ulBase, \ + tBoolean bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFOEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTTxIntModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_UARTTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTTxIntModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTRxErrorGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTRxErrorClear \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTClockSourceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSource))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTClockSourceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr, \ + unsigned char ucMask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitAddrSend \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr))ROM_UARTTABLE[36]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulMode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + unsigned long ulTransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAErrorStatusGet \ + ((unsigned long (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelEnable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelDisable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelIsEnabled \ + ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelRequest \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAttributeGet \ + ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelControlSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulControl))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelSizeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelModeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelSelectSecondary \ + ((void (*)(unsigned long ulSecPeriphs))ROM_UDMATABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelSelectDefault \ + ((void (*)(unsigned long ulDefPeriphs))ROM_UDMATABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAIntStatus \ + ((unsigned long (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAIntClear \ + ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned ulTaskCount, \ + void *pvTaskList, \ + unsigned long ulIsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAssign \ + ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the USB API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevAddrGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulAddress))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevConnect \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevDisconnect \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulMaxPacketSize, \ + unsigned long ulFlags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + tBoolean bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned char *pucData, \ + unsigned long *pulSize))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataPut \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned char *pucData, \ + unsigned long ulSize))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataSend \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulTransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long *pulFIFOAddress, \ + unsigned long *pulFIFOSize, \ + unsigned long ulFlags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFIFOAddress, \ + unsigned long ulFIFOSize, \ + unsigned long ulFlags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOFlush \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFrameNumberGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulMaxPacketSize, \ + unsigned long ulNAKPollInterval, \ + unsigned long ulTargetEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + tBoolean bDataToggle, \ + unsigned long ulFlags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostHubAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostHubAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrDisable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrEnable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostRequestIN \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostRequestStatus \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostReset \ + ((void (*)(unsigned long ulBase, \ + tBoolean bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostResume \ + ((void (*)(unsigned long ulBase, \ + tBoolean bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostSpeedGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostSuspend \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[39]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[40]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long *pulMaxPacketSize, \ + unsigned long *pulFlags))ROM_USBTABLE[41]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[42]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[43]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataAvail \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[44]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBOTGHostRequest \ + ((void (*)(unsigned long ulBase, \ + tBoolean bHNP))ROM_USBTABLE[45]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[46]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDMAChannel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulChannel))ROM_USBTABLE[47]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntDisableControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[48]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntEnableControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[49]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntStatusControl \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[50]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntDisableEndpoint \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[51]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntEnableEndpoint \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[52]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntStatusEndpoint \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[53]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[54]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBPHYPowerOff \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBPHYPowerOn \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateUSB \ + ((void (*)(unsigned char *pucDescriptorInfo))ROM_USBTABLE[58]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBOTGMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[59]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntClear \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogRunning \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogResetEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogResetDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogLock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogUnlock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogLockState \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogReloadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogReloadGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogStallEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogStallDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulType))ROM_WATCHDOGTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Software API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc16Array \ + ((unsigned short (*)(unsigned long ulWordLen, \ + const unsigned long *pulData))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc16Array3 \ + ((void (*)(unsigned long ulWordLen, \ + const unsigned long *pulData, \ + unsigned short *pusCrc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc16 \ + ((unsigned short (*)(unsigned short usCrc, \ + const unsigned char *pucData, \ + unsigned long ulCount))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc8CCITT \ + ((unsigned char (*)(unsigned char ucCrc, \ + const unsigned char *pucData, \ + unsigned long ulCount))ROM_SOFTWARETABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +//***************************************************************************** +// +// Deprecated ROM functions. +// +//***************************************************************************** +#ifndef DEPRECATED +#ifdef ROM_FlashIntStatus +#define ROM_FlashIntGetStatus \ + ROM_FlashIntStatus +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define ROM_USBDevEndpointConfig \ + ROM_USBDevEndpointConfigSet +#endif +#ifdef ROM_USBHostPwrConfig +#define ROM_USBHostPwrFaultConfig \ + ROM_USBHostPwrConfig +#endif +#endif + +#endif // __ROM_H__ diff --git a/driverlib/rom_map.h b/driverlib/rom_map.h new file mode 100644 index 0000000..9bcdb8b --- /dev/null +++ b/driverlib/rom_map.h @@ -0,0 +1,5075 @@ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available and in flash otherwise. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCSequenceDataGet +#define MAP_ADCSequenceDataGet \ + ROM_ADCSequenceDataGet +#else +#define MAP_ADCSequenceDataGet \ + ADCSequenceDataGet +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCSequenceEnable +#define MAP_ADCSequenceEnable \ + ROM_ADCSequenceEnable +#else +#define MAP_ADCSequenceEnable \ + ADCSequenceEnable +#endif +#ifdef ROM_ADCSequenceDisable +#define MAP_ADCSequenceDisable \ + ROM_ADCSequenceDisable +#else +#define MAP_ADCSequenceDisable \ + ADCSequenceDisable +#endif +#ifdef ROM_ADCSequenceConfigure +#define MAP_ADCSequenceConfigure \ + ROM_ADCSequenceConfigure +#else +#define MAP_ADCSequenceConfigure \ + ADCSequenceConfigure +#endif +#ifdef ROM_ADCSequenceStepConfigure +#define MAP_ADCSequenceStepConfigure \ + ROM_ADCSequenceStepConfigure +#else +#define MAP_ADCSequenceStepConfigure \ + ADCSequenceStepConfigure +#endif +#ifdef ROM_ADCSequenceOverflow +#define MAP_ADCSequenceOverflow \ + ROM_ADCSequenceOverflow +#else +#define MAP_ADCSequenceOverflow \ + ADCSequenceOverflow +#endif +#ifdef ROM_ADCSequenceOverflowClear +#define MAP_ADCSequenceOverflowClear \ + ROM_ADCSequenceOverflowClear +#else +#define MAP_ADCSequenceOverflowClear \ + ADCSequenceOverflowClear +#endif +#ifdef ROM_ADCSequenceUnderflow +#define MAP_ADCSequenceUnderflow \ + ROM_ADCSequenceUnderflow +#else +#define MAP_ADCSequenceUnderflow \ + ADCSequenceUnderflow +#endif +#ifdef ROM_ADCSequenceUnderflowClear +#define MAP_ADCSequenceUnderflowClear \ + ROM_ADCSequenceUnderflowClear +#else +#define MAP_ADCSequenceUnderflowClear \ + ADCSequenceUnderflowClear +#endif +#ifdef ROM_ADCProcessorTrigger +#define MAP_ADCProcessorTrigger \ + ROM_ADCProcessorTrigger +#else +#define MAP_ADCProcessorTrigger \ + ADCProcessorTrigger +#endif +#ifdef ROM_ADCHardwareOversampleConfigure +#define MAP_ADCHardwareOversampleConfigure \ + ROM_ADCHardwareOversampleConfigure +#else +#define MAP_ADCHardwareOversampleConfigure \ + ADCHardwareOversampleConfigure +#endif +#ifdef ROM_ADCComparatorConfigure +#define MAP_ADCComparatorConfigure \ + ROM_ADCComparatorConfigure +#else +#define MAP_ADCComparatorConfigure \ + ADCComparatorConfigure +#endif +#ifdef ROM_ADCComparatorRegionSet +#define MAP_ADCComparatorRegionSet \ + ROM_ADCComparatorRegionSet +#else +#define MAP_ADCComparatorRegionSet \ + ADCComparatorRegionSet +#endif +#ifdef ROM_ADCComparatorReset +#define MAP_ADCComparatorReset \ + ROM_ADCComparatorReset +#else +#define MAP_ADCComparatorReset \ + ADCComparatorReset +#endif +#ifdef ROM_ADCComparatorIntDisable +#define MAP_ADCComparatorIntDisable \ + ROM_ADCComparatorIntDisable +#else +#define MAP_ADCComparatorIntDisable \ + ADCComparatorIntDisable +#endif +#ifdef ROM_ADCComparatorIntEnable +#define MAP_ADCComparatorIntEnable \ + ROM_ADCComparatorIntEnable +#else +#define MAP_ADCComparatorIntEnable \ + ADCComparatorIntEnable +#endif +#ifdef ROM_ADCComparatorIntStatus +#define MAP_ADCComparatorIntStatus \ + ROM_ADCComparatorIntStatus +#else +#define MAP_ADCComparatorIntStatus \ + ADCComparatorIntStatus +#endif +#ifdef ROM_ADCComparatorIntClear +#define MAP_ADCComparatorIntClear \ + ROM_ADCComparatorIntClear +#else +#define MAP_ADCComparatorIntClear \ + ADCComparatorIntClear +#endif +#ifdef ROM_ADCReferenceSet +#define MAP_ADCReferenceSet \ + ROM_ADCReferenceSet +#else +#define MAP_ADCReferenceSet \ + ADCReferenceSet +#endif +#ifdef ROM_ADCReferenceGet +#define MAP_ADCReferenceGet \ + ROM_ADCReferenceGet +#else +#define MAP_ADCReferenceGet \ + ADCReferenceGet +#endif +#ifdef ROM_ADCPhaseDelaySet +#define MAP_ADCPhaseDelaySet \ + ROM_ADCPhaseDelaySet +#else +#define MAP_ADCPhaseDelaySet \ + ADCPhaseDelaySet +#endif +#ifdef ROM_ADCPhaseDelayGet +#define MAP_ADCPhaseDelayGet \ + ROM_ADCPhaseDelayGet +#else +#define MAP_ADCPhaseDelayGet \ + ADCPhaseDelayGet +#endif +#ifdef ROM_ADCResolutionSet +#define MAP_ADCResolutionSet \ + ROM_ADCResolutionSet +#else +#define MAP_ADCResolutionSet \ + ADCResolutionSet +#endif +#ifdef ROM_ADCResolutionGet +#define MAP_ADCResolutionGet \ + ROM_ADCResolutionGet +#else +#define MAP_ADCResolutionGet \ + ADCResolutionGet +#endif + +//***************************************************************************** +// +// Macros for the CAN API. +// +//***************************************************************************** +#ifdef ROM_CANIntClear +#define MAP_CANIntClear \ + ROM_CANIntClear +#else +#define MAP_CANIntClear \ + CANIntClear +#endif +#ifdef ROM_CANInit +#define MAP_CANInit \ + ROM_CANInit +#else +#define MAP_CANInit \ + CANInit +#endif +#ifdef ROM_CANEnable +#define MAP_CANEnable \ + ROM_CANEnable +#else +#define MAP_CANEnable \ + CANEnable +#endif +#ifdef ROM_CANDisable +#define MAP_CANDisable \ + ROM_CANDisable +#else +#define MAP_CANDisable \ + CANDisable +#endif +#ifdef ROM_CANBitTimingSet +#define MAP_CANBitTimingSet \ + ROM_CANBitTimingSet +#else +#define MAP_CANBitTimingSet \ + CANBitTimingSet +#endif +#ifdef ROM_CANBitTimingGet +#define MAP_CANBitTimingGet \ + ROM_CANBitTimingGet +#else +#define MAP_CANBitTimingGet \ + CANBitTimingGet +#endif +#ifdef ROM_CANMessageSet +#define MAP_CANMessageSet \ + ROM_CANMessageSet +#else +#define MAP_CANMessageSet \ + CANMessageSet +#endif +#ifdef ROM_CANMessageGet +#define MAP_CANMessageGet \ + ROM_CANMessageGet +#else +#define MAP_CANMessageGet \ + CANMessageGet +#endif +#ifdef ROM_CANStatusGet +#define MAP_CANStatusGet \ + ROM_CANStatusGet +#else +#define MAP_CANStatusGet \ + CANStatusGet +#endif +#ifdef ROM_CANMessageClear +#define MAP_CANMessageClear \ + ROM_CANMessageClear +#else +#define MAP_CANMessageClear \ + CANMessageClear +#endif +#ifdef ROM_CANIntEnable +#define MAP_CANIntEnable \ + ROM_CANIntEnable +#else +#define MAP_CANIntEnable \ + CANIntEnable +#endif +#ifdef ROM_CANIntDisable +#define MAP_CANIntDisable \ + ROM_CANIntDisable +#else +#define MAP_CANIntDisable \ + CANIntDisable +#endif +#ifdef ROM_CANIntStatus +#define MAP_CANIntStatus \ + ROM_CANIntStatus +#else +#define MAP_CANIntStatus \ + CANIntStatus +#endif +#ifdef ROM_CANRetryGet +#define MAP_CANRetryGet \ + ROM_CANRetryGet +#else +#define MAP_CANRetryGet \ + CANRetryGet +#endif +#ifdef ROM_CANRetrySet +#define MAP_CANRetrySet \ + ROM_CANRetrySet +#else +#define MAP_CANRetrySet \ + CANRetrySet +#endif +#ifdef ROM_CANErrCntrGet +#define MAP_CANErrCntrGet \ + ROM_CANErrCntrGet +#else +#define MAP_CANErrCntrGet \ + CANErrCntrGet +#endif +#ifdef ROM_CANBitRateSet +#define MAP_CANBitRateSet \ + ROM_CANBitRateSet +#else +#define MAP_CANBitRateSet \ + CANBitRateSet +#endif + +//***************************************************************************** +// +// Macros for the Comparator API. +// +//***************************************************************************** +#ifdef ROM_ComparatorIntClear +#define MAP_ComparatorIntClear \ + ROM_ComparatorIntClear +#else +#define MAP_ComparatorIntClear \ + ComparatorIntClear +#endif +#ifdef ROM_ComparatorConfigure +#define MAP_ComparatorConfigure \ + ROM_ComparatorConfigure +#else +#define MAP_ComparatorConfigure \ + ComparatorConfigure +#endif +#ifdef ROM_ComparatorRefSet +#define MAP_ComparatorRefSet \ + ROM_ComparatorRefSet +#else +#define MAP_ComparatorRefSet \ + ComparatorRefSet +#endif +#ifdef ROM_ComparatorValueGet +#define MAP_ComparatorValueGet \ + ROM_ComparatorValueGet +#else +#define MAP_ComparatorValueGet \ + ComparatorValueGet +#endif +#ifdef ROM_ComparatorIntEnable +#define MAP_ComparatorIntEnable \ + ROM_ComparatorIntEnable +#else +#define MAP_ComparatorIntEnable \ + ComparatorIntEnable +#endif +#ifdef ROM_ComparatorIntDisable +#define MAP_ComparatorIntDisable \ + ROM_ComparatorIntDisable +#else +#define MAP_ComparatorIntDisable \ + ComparatorIntDisable +#endif +#ifdef ROM_ComparatorIntStatus +#define MAP_ComparatorIntStatus \ + ROM_ComparatorIntStatus +#else +#define MAP_ComparatorIntStatus \ + ComparatorIntStatus +#endif + +//***************************************************************************** +// +// Macros for the EEPROM API. +// +//***************************************************************************** +#ifdef ROM_EEPROMRead +#define MAP_EEPROMRead \ + ROM_EEPROMRead +#else +#define MAP_EEPROMRead \ + EEPROMRead +#endif +#ifdef ROM_EEPROMBlockCountGet +#define MAP_EEPROMBlockCountGet \ + ROM_EEPROMBlockCountGet +#else +#define MAP_EEPROMBlockCountGet \ + EEPROMBlockCountGet +#endif +#ifdef ROM_EEPROMBlockHide +#define MAP_EEPROMBlockHide \ + ROM_EEPROMBlockHide +#else +#define MAP_EEPROMBlockHide \ + EEPROMBlockHide +#endif +#ifdef ROM_EEPROMBlockLock +#define MAP_EEPROMBlockLock \ + ROM_EEPROMBlockLock +#else +#define MAP_EEPROMBlockLock \ + EEPROMBlockLock +#endif +#ifdef ROM_EEPROMBlockPasswordSet +#define MAP_EEPROMBlockPasswordSet \ + ROM_EEPROMBlockPasswordSet +#else +#define MAP_EEPROMBlockPasswordSet \ + EEPROMBlockPasswordSet +#endif +#ifdef ROM_EEPROMBlockProtectGet +#define MAP_EEPROMBlockProtectGet \ + ROM_EEPROMBlockProtectGet +#else +#define MAP_EEPROMBlockProtectGet \ + EEPROMBlockProtectGet +#endif +#ifdef ROM_EEPROMBlockProtectSet +#define MAP_EEPROMBlockProtectSet \ + ROM_EEPROMBlockProtectSet +#else +#define MAP_EEPROMBlockProtectSet \ + EEPROMBlockProtectSet +#endif +#ifdef ROM_EEPROMBlockUnlock +#define MAP_EEPROMBlockUnlock \ + ROM_EEPROMBlockUnlock +#else +#define MAP_EEPROMBlockUnlock \ + EEPROMBlockUnlock +#endif +#ifdef ROM_EEPROMIntClear +#define MAP_EEPROMIntClear \ + ROM_EEPROMIntClear +#else +#define MAP_EEPROMIntClear \ + EEPROMIntClear +#endif +#ifdef ROM_EEPROMIntDisable +#define MAP_EEPROMIntDisable \ + ROM_EEPROMIntDisable +#else +#define MAP_EEPROMIntDisable \ + EEPROMIntDisable +#endif +#ifdef ROM_EEPROMIntEnable +#define MAP_EEPROMIntEnable \ + ROM_EEPROMIntEnable +#else +#define MAP_EEPROMIntEnable \ + EEPROMIntEnable +#endif +#ifdef ROM_EEPROMIntStatus +#define MAP_EEPROMIntStatus \ + ROM_EEPROMIntStatus +#else +#define MAP_EEPROMIntStatus \ + EEPROMIntStatus +#endif +#ifdef ROM_EEPROMMassErase +#define MAP_EEPROMMassErase \ + ROM_EEPROMMassErase +#else +#define MAP_EEPROMMassErase \ + EEPROMMassErase +#endif +#ifdef ROM_EEPROMProgram +#define MAP_EEPROMProgram \ + ROM_EEPROMProgram +#else +#define MAP_EEPROMProgram \ + EEPROMProgram +#endif +#ifdef ROM_EEPROMProgramNonBlocking +#define MAP_EEPROMProgramNonBlocking \ + ROM_EEPROMProgramNonBlocking +#else +#define MAP_EEPROMProgramNonBlocking \ + EEPROMProgramNonBlocking +#endif +#ifdef ROM_EEPROMSizeGet +#define MAP_EEPROMSizeGet \ + ROM_EEPROMSizeGet +#else +#define MAP_EEPROMSizeGet \ + EEPROMSizeGet +#endif +#ifdef ROM_EEPROMStatusGet +#define MAP_EEPROMStatusGet \ + ROM_EEPROMStatusGet +#else +#define MAP_EEPROMStatusGet \ + EEPROMStatusGet +#endif +#ifdef ROM_EEPROMInit +#define MAP_EEPROMInit \ + ROM_EEPROMInit +#else +#define MAP_EEPROMInit \ + EEPROMInit +#endif + +//***************************************************************************** +// +// Macros for the EPI API. +// +//***************************************************************************** +#ifdef ROM_EPIIntStatus +#define MAP_EPIIntStatus \ + ROM_EPIIntStatus +#else +#define MAP_EPIIntStatus \ + EPIIntStatus +#endif +#ifdef ROM_EPIModeSet +#define MAP_EPIModeSet \ + ROM_EPIModeSet +#else +#define MAP_EPIModeSet \ + EPIModeSet +#endif +#ifdef ROM_EPIDividerSet +#define MAP_EPIDividerSet \ + ROM_EPIDividerSet +#else +#define MAP_EPIDividerSet \ + EPIDividerSet +#endif +#ifdef ROM_EPIConfigSDRAMSet +#define MAP_EPIConfigSDRAMSet \ + ROM_EPIConfigSDRAMSet +#else +#define MAP_EPIConfigSDRAMSet \ + EPIConfigSDRAMSet +#endif +#ifdef ROM_EPIConfigGPModeSet +#define MAP_EPIConfigGPModeSet \ + ROM_EPIConfigGPModeSet +#else +#define MAP_EPIConfigGPModeSet \ + EPIConfigGPModeSet +#endif +#ifdef ROM_EPIConfigHB8Set +#define MAP_EPIConfigHB8Set \ + ROM_EPIConfigHB8Set +#else +#define MAP_EPIConfigHB8Set \ + EPIConfigHB8Set +#endif +#ifdef ROM_EPIConfigHB16Set +#define MAP_EPIConfigHB16Set \ + ROM_EPIConfigHB16Set +#else +#define MAP_EPIConfigHB16Set \ + EPIConfigHB16Set +#endif +#ifdef ROM_EPIAddressMapSet +#define MAP_EPIAddressMapSet \ + ROM_EPIAddressMapSet +#else +#define MAP_EPIAddressMapSet \ + EPIAddressMapSet +#endif +#ifdef ROM_EPINonBlockingReadConfigure +#define MAP_EPINonBlockingReadConfigure \ + ROM_EPINonBlockingReadConfigure +#else +#define MAP_EPINonBlockingReadConfigure \ + EPINonBlockingReadConfigure +#endif +#ifdef ROM_EPINonBlockingReadStart +#define MAP_EPINonBlockingReadStart \ + ROM_EPINonBlockingReadStart +#else +#define MAP_EPINonBlockingReadStart \ + EPINonBlockingReadStart +#endif +#ifdef ROM_EPINonBlockingReadStop +#define MAP_EPINonBlockingReadStop \ + ROM_EPINonBlockingReadStop +#else +#define MAP_EPINonBlockingReadStop \ + EPINonBlockingReadStop +#endif +#ifdef ROM_EPINonBlockingReadCount +#define MAP_EPINonBlockingReadCount \ + ROM_EPINonBlockingReadCount +#else +#define MAP_EPINonBlockingReadCount \ + EPINonBlockingReadCount +#endif +#ifdef ROM_EPINonBlockingReadAvail +#define MAP_EPINonBlockingReadAvail \ + ROM_EPINonBlockingReadAvail +#else +#define MAP_EPINonBlockingReadAvail \ + EPINonBlockingReadAvail +#endif +#ifdef ROM_EPINonBlockingReadGet32 +#define MAP_EPINonBlockingReadGet32 \ + ROM_EPINonBlockingReadGet32 +#else +#define MAP_EPINonBlockingReadGet32 \ + EPINonBlockingReadGet32 +#endif +#ifdef ROM_EPINonBlockingReadGet16 +#define MAP_EPINonBlockingReadGet16 \ + ROM_EPINonBlockingReadGet16 +#else +#define MAP_EPINonBlockingReadGet16 \ + EPINonBlockingReadGet16 +#endif +#ifdef ROM_EPINonBlockingReadGet8 +#define MAP_EPINonBlockingReadGet8 \ + ROM_EPINonBlockingReadGet8 +#else +#define MAP_EPINonBlockingReadGet8 \ + EPINonBlockingReadGet8 +#endif +#ifdef ROM_EPIFIFOConfig +#define MAP_EPIFIFOConfig \ + ROM_EPIFIFOConfig +#else +#define MAP_EPIFIFOConfig \ + EPIFIFOConfig +#endif +#ifdef ROM_EPIWriteFIFOCountGet +#define MAP_EPIWriteFIFOCountGet \ + ROM_EPIWriteFIFOCountGet +#else +#define MAP_EPIWriteFIFOCountGet \ + EPIWriteFIFOCountGet +#endif +#ifdef ROM_EPIIntEnable +#define MAP_EPIIntEnable \ + ROM_EPIIntEnable +#else +#define MAP_EPIIntEnable \ + EPIIntEnable +#endif +#ifdef ROM_EPIIntDisable +#define MAP_EPIIntDisable \ + ROM_EPIIntDisable +#else +#define MAP_EPIIntDisable \ + EPIIntDisable +#endif +#ifdef ROM_EPIIntErrorStatus +#define MAP_EPIIntErrorStatus \ + ROM_EPIIntErrorStatus +#else +#define MAP_EPIIntErrorStatus \ + EPIIntErrorStatus +#endif +#ifdef ROM_EPIIntErrorClear +#define MAP_EPIIntErrorClear \ + ROM_EPIIntErrorClear +#else +#define MAP_EPIIntErrorClear \ + EPIIntErrorClear +#endif + +//***************************************************************************** +// +// Macros for the Ethernet API. +// +//***************************************************************************** +#ifdef ROM_EthernetIntClear +#define MAP_EthernetIntClear \ + ROM_EthernetIntClear +#else +#define MAP_EthernetIntClear \ + EthernetIntClear +#endif +#ifdef ROM_EthernetInitExpClk +#define MAP_EthernetInitExpClk \ + ROM_EthernetInitExpClk +#else +#define MAP_EthernetInitExpClk \ + EthernetInitExpClk +#endif +#ifdef ROM_EthernetConfigSet +#define MAP_EthernetConfigSet \ + ROM_EthernetConfigSet +#else +#define MAP_EthernetConfigSet \ + EthernetConfigSet +#endif +#ifdef ROM_EthernetConfigGet +#define MAP_EthernetConfigGet \ + ROM_EthernetConfigGet +#else +#define MAP_EthernetConfigGet \ + EthernetConfigGet +#endif +#ifdef ROM_EthernetMACAddrSet +#define MAP_EthernetMACAddrSet \ + ROM_EthernetMACAddrSet +#else +#define MAP_EthernetMACAddrSet \ + EthernetMACAddrSet +#endif +#ifdef ROM_EthernetMACAddrGet +#define MAP_EthernetMACAddrGet \ + ROM_EthernetMACAddrGet +#else +#define MAP_EthernetMACAddrGet \ + EthernetMACAddrGet +#endif +#ifdef ROM_EthernetEnable +#define MAP_EthernetEnable \ + ROM_EthernetEnable +#else +#define MAP_EthernetEnable \ + EthernetEnable +#endif +#ifdef ROM_EthernetDisable +#define MAP_EthernetDisable \ + ROM_EthernetDisable +#else +#define MAP_EthernetDisable \ + EthernetDisable +#endif +#ifdef ROM_EthernetPacketAvail +#define MAP_EthernetPacketAvail \ + ROM_EthernetPacketAvail +#else +#define MAP_EthernetPacketAvail \ + EthernetPacketAvail +#endif +#ifdef ROM_EthernetSpaceAvail +#define MAP_EthernetSpaceAvail \ + ROM_EthernetSpaceAvail +#else +#define MAP_EthernetSpaceAvail \ + EthernetSpaceAvail +#endif +#ifdef ROM_EthernetPacketGetNonBlocking +#define MAP_EthernetPacketGetNonBlocking \ + ROM_EthernetPacketGetNonBlocking +#else +#define MAP_EthernetPacketGetNonBlocking \ + EthernetPacketGetNonBlocking +#endif +#ifdef ROM_EthernetPacketGet +#define MAP_EthernetPacketGet \ + ROM_EthernetPacketGet +#else +#define MAP_EthernetPacketGet \ + EthernetPacketGet +#endif +#ifdef ROM_EthernetPacketPutNonBlocking +#define MAP_EthernetPacketPutNonBlocking \ + ROM_EthernetPacketPutNonBlocking +#else +#define MAP_EthernetPacketPutNonBlocking \ + EthernetPacketPutNonBlocking +#endif +#ifdef ROM_EthernetPacketPut +#define MAP_EthernetPacketPut \ + ROM_EthernetPacketPut +#else +#define MAP_EthernetPacketPut \ + EthernetPacketPut +#endif +#ifdef ROM_EthernetIntEnable +#define MAP_EthernetIntEnable \ + ROM_EthernetIntEnable +#else +#define MAP_EthernetIntEnable \ + EthernetIntEnable +#endif +#ifdef ROM_EthernetIntDisable +#define MAP_EthernetIntDisable \ + ROM_EthernetIntDisable +#else +#define MAP_EthernetIntDisable \ + EthernetIntDisable +#endif +#ifdef ROM_EthernetIntStatus +#define MAP_EthernetIntStatus \ + ROM_EthernetIntStatus +#else +#define MAP_EthernetIntStatus \ + EthernetIntStatus +#endif +#ifdef ROM_EthernetPHYWrite +#define MAP_EthernetPHYWrite \ + ROM_EthernetPHYWrite +#else +#define MAP_EthernetPHYWrite \ + EthernetPHYWrite +#endif +#ifdef ROM_EthernetPHYRead +#define MAP_EthernetPHYRead \ + ROM_EthernetPHYRead +#else +#define MAP_EthernetPHYRead \ + EthernetPHYRead +#endif +#ifdef ROM_EthernetPHYAddrSet +#define MAP_EthernetPHYAddrSet \ + ROM_EthernetPHYAddrSet +#else +#define MAP_EthernetPHYAddrSet \ + EthernetPHYAddrSet +#endif +#ifdef ROM_EthernetPHYPowerOff +#define MAP_EthernetPHYPowerOff \ + ROM_EthernetPHYPowerOff +#else +#define MAP_EthernetPHYPowerOff \ + EthernetPHYPowerOff +#endif +#ifdef ROM_EthernetPHYPowerOn +#define MAP_EthernetPHYPowerOn \ + ROM_EthernetPHYPowerOn +#else +#define MAP_EthernetPHYPowerOn \ + EthernetPHYPowerOn +#endif + +//***************************************************************************** +// +// Macros for the Fan API. +// +//***************************************************************************** +#ifdef ROM_FanIntClear +#define MAP_FanIntClear \ + ROM_FanIntClear +#else +#define MAP_FanIntClear \ + FanIntClear +#endif +#ifdef ROM_FanChannelConfigAuto +#define MAP_FanChannelConfigAuto \ + ROM_FanChannelConfigAuto +#else +#define MAP_FanChannelConfigAuto \ + FanChannelConfigAuto +#endif +#ifdef ROM_FanChannelConfigManual +#define MAP_FanChannelConfigManual \ + ROM_FanChannelConfigManual +#else +#define MAP_FanChannelConfigManual \ + FanChannelConfigManual +#endif +#ifdef ROM_FanChannelDisable +#define MAP_FanChannelDisable \ + ROM_FanChannelDisable +#else +#define MAP_FanChannelDisable \ + FanChannelDisable +#endif +#ifdef ROM_FanChannelDutyGet +#define MAP_FanChannelDutyGet \ + ROM_FanChannelDutyGet +#else +#define MAP_FanChannelDutyGet \ + FanChannelDutyGet +#endif +#ifdef ROM_FanChannelDutySet +#define MAP_FanChannelDutySet \ + ROM_FanChannelDutySet +#else +#define MAP_FanChannelDutySet \ + FanChannelDutySet +#endif +#ifdef ROM_FanChannelEnable +#define MAP_FanChannelEnable \ + ROM_FanChannelEnable +#else +#define MAP_FanChannelEnable \ + FanChannelEnable +#endif +#ifdef ROM_FanChannelRPMGet +#define MAP_FanChannelRPMGet \ + ROM_FanChannelRPMGet +#else +#define MAP_FanChannelRPMGet \ + FanChannelRPMGet +#endif +#ifdef ROM_FanChannelRPMSet +#define MAP_FanChannelRPMSet \ + ROM_FanChannelRPMSet +#else +#define MAP_FanChannelRPMSet \ + FanChannelRPMSet +#endif +#ifdef ROM_FanChannelStatus +#define MAP_FanChannelStatus \ + ROM_FanChannelStatus +#else +#define MAP_FanChannelStatus \ + FanChannelStatus +#endif +#ifdef ROM_FanChannelsGet +#define MAP_FanChannelsGet \ + ROM_FanChannelsGet +#else +#define MAP_FanChannelsGet \ + FanChannelsGet +#endif +#ifdef ROM_FanIntDisable +#define MAP_FanIntDisable \ + ROM_FanIntDisable +#else +#define MAP_FanIntDisable \ + FanIntDisable +#endif +#ifdef ROM_FanIntEnable +#define MAP_FanIntEnable \ + ROM_FanIntEnable +#else +#define MAP_FanIntEnable \ + FanIntEnable +#endif +#ifdef ROM_FanIntStatus +#define MAP_FanIntStatus \ + ROM_FanIntStatus +#else +#define MAP_FanIntStatus \ + FanIntStatus +#endif + +//***************************************************************************** +// +// Macros for the Flash API. +// +//***************************************************************************** +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashUsecGet +#define MAP_FlashUsecGet \ + ROM_FlashUsecGet +#else +#define MAP_FlashUsecGet \ + FlashUsecGet +#endif +#ifdef ROM_FlashUsecSet +#define MAP_FlashUsecSet \ + ROM_FlashUsecSet +#else +#define MAP_FlashUsecSet \ + FlashUsecSet +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif +#ifdef ROM_FlashProtectSet +#define MAP_FlashProtectSet \ + ROM_FlashProtectSet +#else +#define MAP_FlashProtectSet \ + FlashProtectSet +#endif +#ifdef ROM_FlashProtectSave +#define MAP_FlashProtectSave \ + ROM_FlashProtectSave +#else +#define MAP_FlashProtectSave \ + FlashProtectSave +#endif +#ifdef ROM_FlashUserGet +#define MAP_FlashUserGet \ + ROM_FlashUserGet +#else +#define MAP_FlashUserGet \ + FlashUserGet +#endif +#ifdef ROM_FlashUserSet +#define MAP_FlashUserSet \ + ROM_FlashUserSet +#else +#define MAP_FlashUserSet \ + FlashUserSet +#endif +#ifdef ROM_FlashUserSave +#define MAP_FlashUserSave \ + ROM_FlashUserSave +#else +#define MAP_FlashUserSave \ + FlashUserSave +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif + +//***************************************************************************** +// +// Macros for the FPU API. +// +//***************************************************************************** +#ifdef ROM_FPUEnable +#define MAP_FPUEnable \ + ROM_FPUEnable +#else +#define MAP_FPUEnable \ + FPUEnable +#endif +#ifdef ROM_FPUDisable +#define MAP_FPUDisable \ + ROM_FPUDisable +#else +#define MAP_FPUDisable \ + FPUDisable +#endif +#ifdef ROM_FPUFlushToZeroModeSet +#define MAP_FPUFlushToZeroModeSet \ + ROM_FPUFlushToZeroModeSet +#else +#define MAP_FPUFlushToZeroModeSet \ + FPUFlushToZeroModeSet +#endif +#ifdef ROM_FPUHalfPrecisionModeSet +#define MAP_FPUHalfPrecisionModeSet \ + ROM_FPUHalfPrecisionModeSet +#else +#define MAP_FPUHalfPrecisionModeSet \ + FPUHalfPrecisionModeSet +#endif +#ifdef ROM_FPULazyStackingEnable +#define MAP_FPULazyStackingEnable \ + ROM_FPULazyStackingEnable +#else +#define MAP_FPULazyStackingEnable \ + FPULazyStackingEnable +#endif +#ifdef ROM_FPUNaNModeSet +#define MAP_FPUNaNModeSet \ + ROM_FPUNaNModeSet +#else +#define MAP_FPUNaNModeSet \ + FPUNaNModeSet +#endif +#ifdef ROM_FPURoundingModeSet +#define MAP_FPURoundingModeSet \ + ROM_FPURoundingModeSet +#else +#define MAP_FPURoundingModeSet \ + FPURoundingModeSet +#endif +#ifdef ROM_FPUStackingDisable +#define MAP_FPUStackingDisable \ + ROM_FPUStackingDisable +#else +#define MAP_FPUStackingDisable \ + FPUStackingDisable +#endif +#ifdef ROM_FPUStackingEnable +#define MAP_FPUStackingEnable \ + ROM_FPUStackingEnable +#else +#define MAP_FPUStackingEnable \ + FPUStackingEnable +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOPadConfigSet +#define MAP_GPIOPadConfigSet \ + ROM_GPIOPadConfigSet +#else +#define MAP_GPIOPadConfigSet \ + GPIOPadConfigSet +#endif +#ifdef ROM_GPIOPadConfigGet +#define MAP_GPIOPadConfigGet \ + ROM_GPIOPadConfigGet +#else +#define MAP_GPIOPadConfigGet \ + GPIOPadConfigGet +#endif +#ifdef ROM_GPIOPinIntEnable +#define MAP_GPIOPinIntEnable \ + ROM_GPIOPinIntEnable +#else +#define MAP_GPIOPinIntEnable \ + GPIOPinIntEnable +#endif +#ifdef ROM_GPIOPinIntDisable +#define MAP_GPIOPinIntDisable \ + ROM_GPIOPinIntDisable +#else +#define MAP_GPIOPinIntDisable \ + GPIOPinIntDisable +#endif +#ifdef ROM_GPIOPinIntStatus +#define MAP_GPIOPinIntStatus \ + ROM_GPIOPinIntStatus +#else +#define MAP_GPIOPinIntStatus \ + GPIOPinIntStatus +#endif +#ifdef ROM_GPIOPinIntClear +#define MAP_GPIOPinIntClear \ + ROM_GPIOPinIntClear +#else +#define MAP_GPIOPinIntClear \ + GPIOPinIntClear +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinTypeCAN +#define MAP_GPIOPinTypeCAN \ + ROM_GPIOPinTypeCAN +#else +#define MAP_GPIOPinTypeCAN \ + GPIOPinTypeCAN +#endif +#ifdef ROM_GPIOPinTypeComparator +#define MAP_GPIOPinTypeComparator \ + ROM_GPIOPinTypeComparator +#else +#define MAP_GPIOPinTypeComparator \ + GPIOPinTypeComparator +#endif +#ifdef ROM_GPIOPinTypeGPIOInput +#define MAP_GPIOPinTypeGPIOInput \ + ROM_GPIOPinTypeGPIOInput +#else +#define MAP_GPIOPinTypeGPIOInput \ + GPIOPinTypeGPIOInput +#endif +#ifdef ROM_GPIOPinTypeGPIOOutput +#define MAP_GPIOPinTypeGPIOOutput \ + ROM_GPIOPinTypeGPIOOutput +#else +#define MAP_GPIOPinTypeGPIOOutput \ + GPIOPinTypeGPIOOutput +#endif +#ifdef ROM_GPIOPinTypeI2C +#define MAP_GPIOPinTypeI2C \ + ROM_GPIOPinTypeI2C +#else +#define MAP_GPIOPinTypeI2C \ + GPIOPinTypeI2C +#endif +#ifdef ROM_GPIOPinTypePWM +#define MAP_GPIOPinTypePWM \ + ROM_GPIOPinTypePWM +#else +#define MAP_GPIOPinTypePWM \ + GPIOPinTypePWM +#endif +#ifdef ROM_GPIOPinTypeQEI +#define MAP_GPIOPinTypeQEI \ + ROM_GPIOPinTypeQEI +#else +#define MAP_GPIOPinTypeQEI \ + GPIOPinTypeQEI +#endif +#ifdef ROM_GPIOPinTypeSSI +#define MAP_GPIOPinTypeSSI \ + ROM_GPIOPinTypeSSI +#else +#define MAP_GPIOPinTypeSSI \ + GPIOPinTypeSSI +#endif +#ifdef ROM_GPIOPinTypeTimer +#define MAP_GPIOPinTypeTimer \ + ROM_GPIOPinTypeTimer +#else +#define MAP_GPIOPinTypeTimer \ + GPIOPinTypeTimer +#endif +#ifdef ROM_GPIOPinTypeUART +#define MAP_GPIOPinTypeUART \ + ROM_GPIOPinTypeUART +#else +#define MAP_GPIOPinTypeUART \ + GPIOPinTypeUART +#endif +#ifdef ROM_GPIOPinTypeGPIOOutputOD +#define MAP_GPIOPinTypeGPIOOutputOD \ + ROM_GPIOPinTypeGPIOOutputOD +#else +#define MAP_GPIOPinTypeGPIOOutputOD \ + GPIOPinTypeGPIOOutputOD +#endif +#ifdef ROM_GPIOPinTypeADC +#define MAP_GPIOPinTypeADC \ + ROM_GPIOPinTypeADC +#else +#define MAP_GPIOPinTypeADC \ + GPIOPinTypeADC +#endif +#ifdef ROM_GPIOPinTypeUSBDigital +#define MAP_GPIOPinTypeUSBDigital \ + ROM_GPIOPinTypeUSBDigital +#else +#define MAP_GPIOPinTypeUSBDigital \ + GPIOPinTypeUSBDigital +#endif +#ifdef ROM_GPIOPinTypeI2S +#define MAP_GPIOPinTypeI2S \ + ROM_GPIOPinTypeI2S +#else +#define MAP_GPIOPinTypeI2S \ + GPIOPinTypeI2S +#endif +#ifdef ROM_GPIOPinConfigure +#define MAP_GPIOPinConfigure \ + ROM_GPIOPinConfigure +#else +#define MAP_GPIOPinConfigure \ + GPIOPinConfigure +#endif +#ifdef ROM_GPIOPinTypeEthernetLED +#define MAP_GPIOPinTypeEthernetLED \ + ROM_GPIOPinTypeEthernetLED +#else +#define MAP_GPIOPinTypeEthernetLED \ + GPIOPinTypeEthernetLED +#endif +#ifdef ROM_GPIOPinTypeUSBAnalog +#define MAP_GPIOPinTypeUSBAnalog \ + ROM_GPIOPinTypeUSBAnalog +#else +#define MAP_GPIOPinTypeUSBAnalog \ + GPIOPinTypeUSBAnalog +#endif +#ifdef ROM_GPIOPinTypeEPI +#define MAP_GPIOPinTypeEPI \ + ROM_GPIOPinTypeEPI +#else +#define MAP_GPIOPinTypeEPI \ + GPIOPinTypeEPI +#endif +#ifdef ROM_GPIOPinTypeEthernetMII +#define MAP_GPIOPinTypeEthernetMII \ + ROM_GPIOPinTypeEthernetMII +#else +#define MAP_GPIOPinTypeEthernetMII \ + GPIOPinTypeEthernetMII +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOADCTriggerEnable +#define MAP_GPIOADCTriggerEnable \ + ROM_GPIOADCTriggerEnable +#else +#define MAP_GPIOADCTriggerEnable \ + GPIOADCTriggerEnable +#endif +#ifdef ROM_GPIOADCTriggerDisable +#define MAP_GPIOADCTriggerDisable \ + ROM_GPIOADCTriggerDisable +#else +#define MAP_GPIOADCTriggerDisable \ + GPIOADCTriggerDisable +#endif +#ifdef ROM_GPIOPinTypeFan +#define MAP_GPIOPinTypeFan \ + ROM_GPIOPinTypeFan +#else +#define MAP_GPIOPinTypeFan \ + GPIOPinTypeFan +#endif +#ifdef ROM_GPIOPinTypeLPC +#define MAP_GPIOPinTypeLPC \ + ROM_GPIOPinTypeLPC +#else +#define MAP_GPIOPinTypeLPC \ + GPIOPinTypeLPC +#endif +#ifdef ROM_GPIOPinTypePECIRx +#define MAP_GPIOPinTypePECIRx \ + ROM_GPIOPinTypePECIRx +#else +#define MAP_GPIOPinTypePECIRx \ + GPIOPinTypePECIRx +#endif +#ifdef ROM_GPIOPinTypePECITx +#define MAP_GPIOPinTypePECITx \ + ROM_GPIOPinTypePECITx +#else +#define MAP_GPIOPinTypePECITx \ + GPIOPinTypePECITx +#endif +#ifdef ROM_GPIOPinTypeI2CSCL +#define MAP_GPIOPinTypeI2CSCL \ + ROM_GPIOPinTypeI2CSCL +#else +#define MAP_GPIOPinTypeI2CSCL \ + GPIOPinTypeI2CSCL +#endif + +//***************************************************************************** +// +// Macros for the Hibernate API. +// +//***************************************************************************** +#ifdef ROM_HibernateIntClear +#define MAP_HibernateIntClear \ + ROM_HibernateIntClear +#else +#define MAP_HibernateIntClear \ + HibernateIntClear +#endif +#ifdef ROM_HibernateEnableExpClk +#define MAP_HibernateEnableExpClk \ + ROM_HibernateEnableExpClk +#else +#define MAP_HibernateEnableExpClk \ + HibernateEnableExpClk +#endif +#ifdef ROM_HibernateDisable +#define MAP_HibernateDisable \ + ROM_HibernateDisable +#else +#define MAP_HibernateDisable \ + HibernateDisable +#endif +#ifdef ROM_HibernateClockSelect +#define MAP_HibernateClockSelect \ + ROM_HibernateClockSelect +#else +#define MAP_HibernateClockSelect \ + HibernateClockSelect +#endif +#ifdef ROM_HibernateRTCEnable +#define MAP_HibernateRTCEnable \ + ROM_HibernateRTCEnable +#else +#define MAP_HibernateRTCEnable \ + HibernateRTCEnable +#endif +#ifdef ROM_HibernateRTCDisable +#define MAP_HibernateRTCDisable \ + ROM_HibernateRTCDisable +#else +#define MAP_HibernateRTCDisable \ + HibernateRTCDisable +#endif +#ifdef ROM_HibernateWakeSet +#define MAP_HibernateWakeSet \ + ROM_HibernateWakeSet +#else +#define MAP_HibernateWakeSet \ + HibernateWakeSet +#endif +#ifdef ROM_HibernateWakeGet +#define MAP_HibernateWakeGet \ + ROM_HibernateWakeGet +#else +#define MAP_HibernateWakeGet \ + HibernateWakeGet +#endif +#ifdef ROM_HibernateLowBatSet +#define MAP_HibernateLowBatSet \ + ROM_HibernateLowBatSet +#else +#define MAP_HibernateLowBatSet \ + HibernateLowBatSet +#endif +#ifdef ROM_HibernateLowBatGet +#define MAP_HibernateLowBatGet \ + ROM_HibernateLowBatGet +#else +#define MAP_HibernateLowBatGet \ + HibernateLowBatGet +#endif +#ifdef ROM_HibernateRTCSet +#define MAP_HibernateRTCSet \ + ROM_HibernateRTCSet +#else +#define MAP_HibernateRTCSet \ + HibernateRTCSet +#endif +#ifdef ROM_HibernateRTCGet +#define MAP_HibernateRTCGet \ + ROM_HibernateRTCGet +#else +#define MAP_HibernateRTCGet \ + HibernateRTCGet +#endif +#ifdef ROM_HibernateRTCMatch0Set +#define MAP_HibernateRTCMatch0Set \ + ROM_HibernateRTCMatch0Set +#else +#define MAP_HibernateRTCMatch0Set \ + HibernateRTCMatch0Set +#endif +#ifdef ROM_HibernateRTCMatch0Get +#define MAP_HibernateRTCMatch0Get \ + ROM_HibernateRTCMatch0Get +#else +#define MAP_HibernateRTCMatch0Get \ + HibernateRTCMatch0Get +#endif +#ifdef ROM_HibernateRTCMatch1Set +#define MAP_HibernateRTCMatch1Set \ + ROM_HibernateRTCMatch1Set +#else +#define MAP_HibernateRTCMatch1Set \ + HibernateRTCMatch1Set +#endif +#ifdef ROM_HibernateRTCMatch1Get +#define MAP_HibernateRTCMatch1Get \ + ROM_HibernateRTCMatch1Get +#else +#define MAP_HibernateRTCMatch1Get \ + HibernateRTCMatch1Get +#endif +#ifdef ROM_HibernateRTCTrimSet +#define MAP_HibernateRTCTrimSet \ + ROM_HibernateRTCTrimSet +#else +#define MAP_HibernateRTCTrimSet \ + HibernateRTCTrimSet +#endif +#ifdef ROM_HibernateRTCTrimGet +#define MAP_HibernateRTCTrimGet \ + ROM_HibernateRTCTrimGet +#else +#define MAP_HibernateRTCTrimGet \ + HibernateRTCTrimGet +#endif +#ifdef ROM_HibernateDataSet +#define MAP_HibernateDataSet \ + ROM_HibernateDataSet +#else +#define MAP_HibernateDataSet \ + HibernateDataSet +#endif +#ifdef ROM_HibernateDataGet +#define MAP_HibernateDataGet \ + ROM_HibernateDataGet +#else +#define MAP_HibernateDataGet \ + HibernateDataGet +#endif +#ifdef ROM_HibernateRequest +#define MAP_HibernateRequest \ + ROM_HibernateRequest +#else +#define MAP_HibernateRequest \ + HibernateRequest +#endif +#ifdef ROM_HibernateIntEnable +#define MAP_HibernateIntEnable \ + ROM_HibernateIntEnable +#else +#define MAP_HibernateIntEnable \ + HibernateIntEnable +#endif +#ifdef ROM_HibernateIntDisable +#define MAP_HibernateIntDisable \ + ROM_HibernateIntDisable +#else +#define MAP_HibernateIntDisable \ + HibernateIntDisable +#endif +#ifdef ROM_HibernateIntStatus +#define MAP_HibernateIntStatus \ + ROM_HibernateIntStatus +#else +#define MAP_HibernateIntStatus \ + HibernateIntStatus +#endif +#ifdef ROM_HibernateIsActive +#define MAP_HibernateIsActive \ + ROM_HibernateIsActive +#else +#define MAP_HibernateIsActive \ + HibernateIsActive +#endif +#ifdef ROM_HibernateRTCSSMatch0Set +#define MAP_HibernateRTCSSMatch0Set \ + ROM_HibernateRTCSSMatch0Set +#else +#define MAP_HibernateRTCSSMatch0Set \ + HibernateRTCSSMatch0Set +#endif +#ifdef ROM_HibernateRTCSSMatch0Get +#define MAP_HibernateRTCSSMatch0Get \ + ROM_HibernateRTCSSMatch0Get +#else +#define MAP_HibernateRTCSSMatch0Get \ + HibernateRTCSSMatch0Get +#endif +#ifdef ROM_HibernateRTCSSGet +#define MAP_HibernateRTCSSGet \ + ROM_HibernateRTCSSGet +#else +#define MAP_HibernateRTCSSGet \ + HibernateRTCSSGet +#endif +#ifdef ROM_HibernateClockConfig +#define MAP_HibernateClockConfig \ + ROM_HibernateClockConfig +#else +#define MAP_HibernateClockConfig \ + HibernateClockConfig +#endif +#ifdef ROM_HibernateBatCheckStart +#define MAP_HibernateBatCheckStart \ + ROM_HibernateBatCheckStart +#else +#define MAP_HibernateBatCheckStart \ + HibernateBatCheckStart +#endif +#ifdef ROM_HibernateBatCheckDone +#define MAP_HibernateBatCheckDone \ + ROM_HibernateBatCheckDone +#else +#define MAP_HibernateBatCheckDone \ + HibernateBatCheckDone +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif + +//***************************************************************************** +// +// Macros for the I2S API. +// +//***************************************************************************** +#ifdef ROM_I2SIntStatus +#define MAP_I2SIntStatus \ + ROM_I2SIntStatus +#else +#define MAP_I2SIntStatus \ + I2SIntStatus +#endif +#ifdef ROM_I2STxEnable +#define MAP_I2STxEnable \ + ROM_I2STxEnable +#else +#define MAP_I2STxEnable \ + I2STxEnable +#endif +#ifdef ROM_I2STxDisable +#define MAP_I2STxDisable \ + ROM_I2STxDisable +#else +#define MAP_I2STxDisable \ + I2STxDisable +#endif +#ifdef ROM_I2STxDataPut +#define MAP_I2STxDataPut \ + ROM_I2STxDataPut +#else +#define MAP_I2STxDataPut \ + I2STxDataPut +#endif +#ifdef ROM_I2STxDataPutNonBlocking +#define MAP_I2STxDataPutNonBlocking \ + ROM_I2STxDataPutNonBlocking +#else +#define MAP_I2STxDataPutNonBlocking \ + I2STxDataPutNonBlocking +#endif +#ifdef ROM_I2STxConfigSet +#define MAP_I2STxConfigSet \ + ROM_I2STxConfigSet +#else +#define MAP_I2STxConfigSet \ + I2STxConfigSet +#endif +#ifdef ROM_I2STxFIFOLimitSet +#define MAP_I2STxFIFOLimitSet \ + ROM_I2STxFIFOLimitSet +#else +#define MAP_I2STxFIFOLimitSet \ + I2STxFIFOLimitSet +#endif +#ifdef ROM_I2STxFIFOLimitGet +#define MAP_I2STxFIFOLimitGet \ + ROM_I2STxFIFOLimitGet +#else +#define MAP_I2STxFIFOLimitGet \ + I2STxFIFOLimitGet +#endif +#ifdef ROM_I2STxFIFOLevelGet +#define MAP_I2STxFIFOLevelGet \ + ROM_I2STxFIFOLevelGet +#else +#define MAP_I2STxFIFOLevelGet \ + I2STxFIFOLevelGet +#endif +#ifdef ROM_I2SRxEnable +#define MAP_I2SRxEnable \ + ROM_I2SRxEnable +#else +#define MAP_I2SRxEnable \ + I2SRxEnable +#endif +#ifdef ROM_I2SRxDisable +#define MAP_I2SRxDisable \ + ROM_I2SRxDisable +#else +#define MAP_I2SRxDisable \ + I2SRxDisable +#endif +#ifdef ROM_I2SRxDataGet +#define MAP_I2SRxDataGet \ + ROM_I2SRxDataGet +#else +#define MAP_I2SRxDataGet \ + I2SRxDataGet +#endif +#ifdef ROM_I2SRxDataGetNonBlocking +#define MAP_I2SRxDataGetNonBlocking \ + ROM_I2SRxDataGetNonBlocking +#else +#define MAP_I2SRxDataGetNonBlocking \ + I2SRxDataGetNonBlocking +#endif +#ifdef ROM_I2SRxConfigSet +#define MAP_I2SRxConfigSet \ + ROM_I2SRxConfigSet +#else +#define MAP_I2SRxConfigSet \ + I2SRxConfigSet +#endif +#ifdef ROM_I2SRxFIFOLimitSet +#define MAP_I2SRxFIFOLimitSet \ + ROM_I2SRxFIFOLimitSet +#else +#define MAP_I2SRxFIFOLimitSet \ + I2SRxFIFOLimitSet +#endif +#ifdef ROM_I2SRxFIFOLimitGet +#define MAP_I2SRxFIFOLimitGet \ + ROM_I2SRxFIFOLimitGet +#else +#define MAP_I2SRxFIFOLimitGet \ + I2SRxFIFOLimitGet +#endif +#ifdef ROM_I2SRxFIFOLevelGet +#define MAP_I2SRxFIFOLevelGet \ + ROM_I2SRxFIFOLevelGet +#else +#define MAP_I2SRxFIFOLevelGet \ + I2SRxFIFOLevelGet +#endif +#ifdef ROM_I2STxRxEnable +#define MAP_I2STxRxEnable \ + ROM_I2STxRxEnable +#else +#define MAP_I2STxRxEnable \ + I2STxRxEnable +#endif +#ifdef ROM_I2STxRxDisable +#define MAP_I2STxRxDisable \ + ROM_I2STxRxDisable +#else +#define MAP_I2STxRxDisable \ + I2STxRxDisable +#endif +#ifdef ROM_I2STxRxConfigSet +#define MAP_I2STxRxConfigSet \ + ROM_I2STxRxConfigSet +#else +#define MAP_I2STxRxConfigSet \ + I2STxRxConfigSet +#endif +#ifdef ROM_I2SMasterClockSelect +#define MAP_I2SMasterClockSelect \ + ROM_I2SMasterClockSelect +#else +#define MAP_I2SMasterClockSelect \ + I2SMasterClockSelect +#endif +#ifdef ROM_I2SIntEnable +#define MAP_I2SIntEnable \ + ROM_I2SIntEnable +#else +#define MAP_I2SIntEnable \ + I2SIntEnable +#endif +#ifdef ROM_I2SIntDisable +#define MAP_I2SIntDisable \ + ROM_I2SIntDisable +#else +#define MAP_I2SIntDisable \ + I2SIntDisable +#endif +#ifdef ROM_I2SIntClear +#define MAP_I2SIntClear \ + ROM_I2SIntClear +#else +#define MAP_I2SIntClear \ + I2SIntClear +#endif + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif + +//***************************************************************************** +// +// Macros for the LPC API. +// +//***************************************************************************** +#ifdef ROM_LPCIntClear +#define MAP_LPCIntClear \ + ROM_LPCIntClear +#else +#define MAP_LPCIntClear \ + LPCIntClear +#endif +#ifdef ROM_LPCByteRead +#define MAP_LPCByteRead \ + ROM_LPCByteRead +#else +#define MAP_LPCByteRead \ + LPCByteRead +#endif +#ifdef ROM_LPCByteWrite +#define MAP_LPCByteWrite \ + ROM_LPCByteWrite +#else +#define MAP_LPCByteWrite \ + LPCByteWrite +#endif +#ifdef ROM_LPCChannelConfigCOMxSet +#define MAP_LPCChannelConfigCOMxSet \ + ROM_LPCChannelConfigCOMxSet +#else +#define MAP_LPCChannelConfigCOMxSet \ + LPCChannelConfigCOMxSet +#endif +#ifdef ROM_LPCChannelConfigGet +#define MAP_LPCChannelConfigGet \ + ROM_LPCChannelConfigGet +#else +#define MAP_LPCChannelConfigGet \ + LPCChannelConfigGet +#endif +#ifdef ROM_LPCChannelConfigEPSet +#define MAP_LPCChannelConfigEPSet \ + ROM_LPCChannelConfigEPSet +#else +#define MAP_LPCChannelConfigEPSet \ + LPCChannelConfigEPSet +#endif +#ifdef ROM_LPCChannelConfigMBSet +#define MAP_LPCChannelConfigMBSet \ + ROM_LPCChannelConfigMBSet +#else +#define MAP_LPCChannelConfigMBSet \ + LPCChannelConfigMBSet +#endif +#ifdef ROM_LPCChannelDMAConfigGet +#define MAP_LPCChannelDMAConfigGet \ + ROM_LPCChannelDMAConfigGet +#else +#define MAP_LPCChannelDMAConfigGet \ + LPCChannelDMAConfigGet +#endif +#ifdef ROM_LPCChannelDMAConfigSet +#define MAP_LPCChannelDMAConfigSet \ + ROM_LPCChannelDMAConfigSet +#else +#define MAP_LPCChannelDMAConfigSet \ + LPCChannelDMAConfigSet +#endif +#ifdef ROM_LPCChannelDisable +#define MAP_LPCChannelDisable \ + ROM_LPCChannelDisable +#else +#define MAP_LPCChannelDisable \ + LPCChannelDisable +#endif +#ifdef ROM_LPCChannelEnable +#define MAP_LPCChannelEnable \ + ROM_LPCChannelEnable +#else +#define MAP_LPCChannelEnable \ + LPCChannelEnable +#endif +#ifdef ROM_LPCChannelStatusClear +#define MAP_LPCChannelStatusClear \ + ROM_LPCChannelStatusClear +#else +#define MAP_LPCChannelStatusClear \ + LPCChannelStatusClear +#endif +#ifdef ROM_LPCChannelStatusGet +#define MAP_LPCChannelStatusGet \ + ROM_LPCChannelStatusGet +#else +#define MAP_LPCChannelStatusGet \ + LPCChannelStatusGet +#endif +#ifdef ROM_LPCChannelStatusSet +#define MAP_LPCChannelStatusSet \ + ROM_LPCChannelStatusSet +#else +#define MAP_LPCChannelStatusSet \ + LPCChannelStatusSet +#endif +#ifdef ROM_LPCCOMxIntClear +#define MAP_LPCCOMxIntClear \ + ROM_LPCCOMxIntClear +#else +#define MAP_LPCCOMxIntClear \ + LPCCOMxIntClear +#endif +#ifdef ROM_LPCCOMxIntDisable +#define MAP_LPCCOMxIntDisable \ + ROM_LPCCOMxIntDisable +#else +#define MAP_LPCCOMxIntDisable \ + LPCCOMxIntDisable +#endif +#ifdef ROM_LPCCOMxIntEnable +#define MAP_LPCCOMxIntEnable \ + ROM_LPCCOMxIntEnable +#else +#define MAP_LPCCOMxIntEnable \ + LPCCOMxIntEnable +#endif +#ifdef ROM_LPCCOMxIntStatus +#define MAP_LPCCOMxIntStatus \ + ROM_LPCCOMxIntStatus +#else +#define MAP_LPCCOMxIntStatus \ + LPCCOMxIntStatus +#endif +#ifdef ROM_LPCConfigGet +#define MAP_LPCConfigGet \ + ROM_LPCConfigGet +#else +#define MAP_LPCConfigGet \ + LPCConfigGet +#endif +#ifdef ROM_LPCConfigSet +#define MAP_LPCConfigSet \ + ROM_LPCConfigSet +#else +#define MAP_LPCConfigSet \ + LPCConfigSet +#endif +#ifdef ROM_LPCHalfWordRead +#define MAP_LPCHalfWordRead \ + ROM_LPCHalfWordRead +#else +#define MAP_LPCHalfWordRead \ + LPCHalfWordRead +#endif +#ifdef ROM_LPCHalfWordWrite +#define MAP_LPCHalfWordWrite \ + ROM_LPCHalfWordWrite +#else +#define MAP_LPCHalfWordWrite \ + LPCHalfWordWrite +#endif +#ifdef ROM_LPCIRQClear +#define MAP_LPCIRQClear \ + ROM_LPCIRQClear +#else +#define MAP_LPCIRQClear \ + LPCIRQClear +#endif +#ifdef ROM_LPCIRQConfig +#define MAP_LPCIRQConfig \ + ROM_LPCIRQConfig +#else +#define MAP_LPCIRQConfig \ + LPCIRQConfig +#endif +#ifdef ROM_LPCIRQGet +#define MAP_LPCIRQGet \ + ROM_LPCIRQGet +#else +#define MAP_LPCIRQGet \ + LPCIRQGet +#endif +#ifdef ROM_LPCIRQSend +#define MAP_LPCIRQSend \ + ROM_LPCIRQSend +#else +#define MAP_LPCIRQSend \ + LPCIRQSend +#endif +#ifdef ROM_LPCIRQSet +#define MAP_LPCIRQSet \ + ROM_LPCIRQSet +#else +#define MAP_LPCIRQSet \ + LPCIRQSet +#endif +#ifdef ROM_LPCIntDisable +#define MAP_LPCIntDisable \ + ROM_LPCIntDisable +#else +#define MAP_LPCIntDisable \ + LPCIntDisable +#endif +#ifdef ROM_LPCIntEnable +#define MAP_LPCIntEnable \ + ROM_LPCIntEnable +#else +#define MAP_LPCIntEnable \ + LPCIntEnable +#endif +#ifdef ROM_LPCIntStatus +#define MAP_LPCIntStatus \ + ROM_LPCIntStatus +#else +#define MAP_LPCIntStatus \ + LPCIntStatus +#endif +#ifdef ROM_LPCSCIAssert +#define MAP_LPCSCIAssert \ + ROM_LPCSCIAssert +#else +#define MAP_LPCSCIAssert \ + LPCSCIAssert +#endif +#ifdef ROM_LPCStatusGet +#define MAP_LPCStatusGet \ + ROM_LPCStatusGet +#else +#define MAP_LPCStatusGet \ + LPCStatusGet +#endif +#ifdef ROM_LPCWordRead +#define MAP_LPCWordRead \ + ROM_LPCWordRead +#else +#define MAP_LPCWordRead \ + LPCWordRead +#endif +#ifdef ROM_LPCWordWrite +#define MAP_LPCWordWrite \ + ROM_LPCWordWrite +#else +#define MAP_LPCWordWrite \ + LPCWordWrite +#endif +#ifdef ROM_LPCChannelPoolAddressGet +#define MAP_LPCChannelPoolAddressGet \ + ROM_LPCChannelPoolAddressGet +#else +#define MAP_LPCChannelPoolAddressGet \ + LPCChannelPoolAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressGet +#define MAP_LPCStatusBlockAddressGet \ + ROM_LPCStatusBlockAddressGet +#else +#define MAP_LPCStatusBlockAddressGet \ + LPCStatusBlockAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressSet +#define MAP_LPCStatusBlockAddressSet \ + ROM_LPCStatusBlockAddressSet +#else +#define MAP_LPCStatusBlockAddressSet \ + LPCStatusBlockAddressSet +#endif + +//***************************************************************************** +// +// Macros for the MPU API. +// +//***************************************************************************** +#ifdef ROM_MPUEnable +#define MAP_MPUEnable \ + ROM_MPUEnable +#else +#define MAP_MPUEnable \ + MPUEnable +#endif +#ifdef ROM_MPUDisable +#define MAP_MPUDisable \ + ROM_MPUDisable +#else +#define MAP_MPUDisable \ + MPUDisable +#endif +#ifdef ROM_MPURegionCountGet +#define MAP_MPURegionCountGet \ + ROM_MPURegionCountGet +#else +#define MAP_MPURegionCountGet \ + MPURegionCountGet +#endif +#ifdef ROM_MPURegionEnable +#define MAP_MPURegionEnable \ + ROM_MPURegionEnable +#else +#define MAP_MPURegionEnable \ + MPURegionEnable +#endif +#ifdef ROM_MPURegionDisable +#define MAP_MPURegionDisable \ + ROM_MPURegionDisable +#else +#define MAP_MPURegionDisable \ + MPURegionDisable +#endif +#ifdef ROM_MPURegionSet +#define MAP_MPURegionSet \ + ROM_MPURegionSet +#else +#define MAP_MPURegionSet \ + MPURegionSet +#endif +#ifdef ROM_MPURegionGet +#define MAP_MPURegionGet \ + ROM_MPURegionGet +#else +#define MAP_MPURegionGet \ + MPURegionGet +#endif + +//***************************************************************************** +// +// Macros for the PECI API. +// +//***************************************************************************** +#ifdef ROM_PECIIntClear +#define MAP_PECIIntClear \ + ROM_PECIIntClear +#else +#define MAP_PECIIntClear \ + PECIIntClear +#endif +#ifdef ROM_PECIAdvCmdSend +#define MAP_PECIAdvCmdSend \ + ROM_PECIAdvCmdSend +#else +#define MAP_PECIAdvCmdSend \ + PECIAdvCmdSend +#endif +#ifdef ROM_PECIAdvCmdSendNonBlocking +#define MAP_PECIAdvCmdSendNonBlocking \ + ROM_PECIAdvCmdSendNonBlocking +#else +#define MAP_PECIAdvCmdSendNonBlocking \ + PECIAdvCmdSendNonBlocking +#endif +#ifdef ROM_PECIAdvCmdStatusGet +#define MAP_PECIAdvCmdStatusGet \ + ROM_PECIAdvCmdStatusGet +#else +#define MAP_PECIAdvCmdStatusGet \ + PECIAdvCmdStatusGet +#endif +#ifdef ROM_PECIConfigGet +#define MAP_PECIConfigGet \ + ROM_PECIConfigGet +#else +#define MAP_PECIConfigGet \ + PECIConfigGet +#endif +#ifdef ROM_PECIConfigSet +#define MAP_PECIConfigSet \ + ROM_PECIConfigSet +#else +#define MAP_PECIConfigSet \ + PECIConfigSet +#endif +#ifdef ROM_PECIDomainMaxReadClear +#define MAP_PECIDomainMaxReadClear \ + ROM_PECIDomainMaxReadClear +#else +#define MAP_PECIDomainMaxReadClear \ + PECIDomainMaxReadClear +#endif +#ifdef ROM_PECIDomainValueClear +#define MAP_PECIDomainValueClear \ + ROM_PECIDomainValueClear +#else +#define MAP_PECIDomainValueClear \ + PECIDomainValueClear +#endif +#ifdef ROM_PECIDomainConfigGet +#define MAP_PECIDomainConfigGet \ + ROM_PECIDomainConfigGet +#else +#define MAP_PECIDomainConfigGet \ + PECIDomainConfigGet +#endif +#ifdef ROM_PECIDomainConfigSet +#define MAP_PECIDomainConfigSet \ + ROM_PECIDomainConfigSet +#else +#define MAP_PECIDomainConfigSet \ + PECIDomainConfigSet +#endif +#ifdef ROM_PECIDomainDisable +#define MAP_PECIDomainDisable \ + ROM_PECIDomainDisable +#else +#define MAP_PECIDomainDisable \ + PECIDomainDisable +#endif +#ifdef ROM_PECIDomainEnable +#define MAP_PECIDomainEnable \ + ROM_PECIDomainEnable +#else +#define MAP_PECIDomainEnable \ + PECIDomainEnable +#endif +#ifdef ROM_PECIDomainMaxReadGet +#define MAP_PECIDomainMaxReadGet \ + ROM_PECIDomainMaxReadGet +#else +#define MAP_PECIDomainMaxReadGet \ + PECIDomainMaxReadGet +#endif +#ifdef ROM_PECIDomainValueGet +#define MAP_PECIDomainValueGet \ + ROM_PECIDomainValueGet +#else +#define MAP_PECIDomainValueGet \ + PECIDomainValueGet +#endif +#ifdef ROM_PECIIntDisable +#define MAP_PECIIntDisable \ + ROM_PECIIntDisable +#else +#define MAP_PECIIntDisable \ + PECIIntDisable +#endif +#ifdef ROM_PECIIntEnable +#define MAP_PECIIntEnable \ + ROM_PECIIntEnable +#else +#define MAP_PECIIntEnable \ + PECIIntEnable +#endif +#ifdef ROM_PECIIntStatus +#define MAP_PECIIntStatus \ + ROM_PECIIntStatus +#else +#define MAP_PECIIntStatus \ + PECIIntStatus +#endif +#ifdef ROM_PECIBypassEnable +#define MAP_PECIBypassEnable \ + ROM_PECIBypassEnable +#else +#define MAP_PECIBypassEnable \ + PECIBypassEnable +#endif +#ifdef ROM_PECIBypassDisable +#define MAP_PECIBypassDisable \ + ROM_PECIBypassDisable +#else +#define MAP_PECIBypassDisable \ + PECIBypassDisable +#endif + +//***************************************************************************** +// +// Macros for the PWM API. +// +//***************************************************************************** +#ifdef ROM_PWMPulseWidthSet +#define MAP_PWMPulseWidthSet \ + ROM_PWMPulseWidthSet +#else +#define MAP_PWMPulseWidthSet \ + PWMPulseWidthSet +#endif +#ifdef ROM_PWMGenConfigure +#define MAP_PWMGenConfigure \ + ROM_PWMGenConfigure +#else +#define MAP_PWMGenConfigure \ + PWMGenConfigure +#endif +#ifdef ROM_PWMGenPeriodSet +#define MAP_PWMGenPeriodSet \ + ROM_PWMGenPeriodSet +#else +#define MAP_PWMGenPeriodSet \ + PWMGenPeriodSet +#endif +#ifdef ROM_PWMGenPeriodGet +#define MAP_PWMGenPeriodGet \ + ROM_PWMGenPeriodGet +#else +#define MAP_PWMGenPeriodGet \ + PWMGenPeriodGet +#endif +#ifdef ROM_PWMGenEnable +#define MAP_PWMGenEnable \ + ROM_PWMGenEnable +#else +#define MAP_PWMGenEnable \ + PWMGenEnable +#endif +#ifdef ROM_PWMGenDisable +#define MAP_PWMGenDisable \ + ROM_PWMGenDisable +#else +#define MAP_PWMGenDisable \ + PWMGenDisable +#endif +#ifdef ROM_PWMPulseWidthGet +#define MAP_PWMPulseWidthGet \ + ROM_PWMPulseWidthGet +#else +#define MAP_PWMPulseWidthGet \ + PWMPulseWidthGet +#endif +#ifdef ROM_PWMDeadBandEnable +#define MAP_PWMDeadBandEnable \ + ROM_PWMDeadBandEnable +#else +#define MAP_PWMDeadBandEnable \ + PWMDeadBandEnable +#endif +#ifdef ROM_PWMDeadBandDisable +#define MAP_PWMDeadBandDisable \ + ROM_PWMDeadBandDisable +#else +#define MAP_PWMDeadBandDisable \ + PWMDeadBandDisable +#endif +#ifdef ROM_PWMSyncUpdate +#define MAP_PWMSyncUpdate \ + ROM_PWMSyncUpdate +#else +#define MAP_PWMSyncUpdate \ + PWMSyncUpdate +#endif +#ifdef ROM_PWMSyncTimeBase +#define MAP_PWMSyncTimeBase \ + ROM_PWMSyncTimeBase +#else +#define MAP_PWMSyncTimeBase \ + PWMSyncTimeBase +#endif +#ifdef ROM_PWMOutputState +#define MAP_PWMOutputState \ + ROM_PWMOutputState +#else +#define MAP_PWMOutputState \ + PWMOutputState +#endif +#ifdef ROM_PWMOutputInvert +#define MAP_PWMOutputInvert \ + ROM_PWMOutputInvert +#else +#define MAP_PWMOutputInvert \ + PWMOutputInvert +#endif +#ifdef ROM_PWMOutputFault +#define MAP_PWMOutputFault \ + ROM_PWMOutputFault +#else +#define MAP_PWMOutputFault \ + PWMOutputFault +#endif +#ifdef ROM_PWMGenIntTrigEnable +#define MAP_PWMGenIntTrigEnable \ + ROM_PWMGenIntTrigEnable +#else +#define MAP_PWMGenIntTrigEnable \ + PWMGenIntTrigEnable +#endif +#ifdef ROM_PWMGenIntTrigDisable +#define MAP_PWMGenIntTrigDisable \ + ROM_PWMGenIntTrigDisable +#else +#define MAP_PWMGenIntTrigDisable \ + PWMGenIntTrigDisable +#endif +#ifdef ROM_PWMGenIntStatus +#define MAP_PWMGenIntStatus \ + ROM_PWMGenIntStatus +#else +#define MAP_PWMGenIntStatus \ + PWMGenIntStatus +#endif +#ifdef ROM_PWMGenIntClear +#define MAP_PWMGenIntClear \ + ROM_PWMGenIntClear +#else +#define MAP_PWMGenIntClear \ + PWMGenIntClear +#endif +#ifdef ROM_PWMIntEnable +#define MAP_PWMIntEnable \ + ROM_PWMIntEnable +#else +#define MAP_PWMIntEnable \ + PWMIntEnable +#endif +#ifdef ROM_PWMIntDisable +#define MAP_PWMIntDisable \ + ROM_PWMIntDisable +#else +#define MAP_PWMIntDisable \ + PWMIntDisable +#endif +#ifdef ROM_PWMFaultIntClear +#define MAP_PWMFaultIntClear \ + ROM_PWMFaultIntClear +#else +#define MAP_PWMFaultIntClear \ + PWMFaultIntClear +#endif +#ifdef ROM_PWMIntStatus +#define MAP_PWMIntStatus \ + ROM_PWMIntStatus +#else +#define MAP_PWMIntStatus \ + PWMIntStatus +#endif +#ifdef ROM_PWMOutputFaultLevel +#define MAP_PWMOutputFaultLevel \ + ROM_PWMOutputFaultLevel +#else +#define MAP_PWMOutputFaultLevel \ + PWMOutputFaultLevel +#endif +#ifdef ROM_PWMFaultIntClearExt +#define MAP_PWMFaultIntClearExt \ + ROM_PWMFaultIntClearExt +#else +#define MAP_PWMFaultIntClearExt \ + PWMFaultIntClearExt +#endif +#ifdef ROM_PWMGenFaultConfigure +#define MAP_PWMGenFaultConfigure \ + ROM_PWMGenFaultConfigure +#else +#define MAP_PWMGenFaultConfigure \ + PWMGenFaultConfigure +#endif +#ifdef ROM_PWMGenFaultTriggerSet +#define MAP_PWMGenFaultTriggerSet \ + ROM_PWMGenFaultTriggerSet +#else +#define MAP_PWMGenFaultTriggerSet \ + PWMGenFaultTriggerSet +#endif +#ifdef ROM_PWMGenFaultTriggerGet +#define MAP_PWMGenFaultTriggerGet \ + ROM_PWMGenFaultTriggerGet +#else +#define MAP_PWMGenFaultTriggerGet \ + PWMGenFaultTriggerGet +#endif +#ifdef ROM_PWMGenFaultStatus +#define MAP_PWMGenFaultStatus \ + ROM_PWMGenFaultStatus +#else +#define MAP_PWMGenFaultStatus \ + PWMGenFaultStatus +#endif +#ifdef ROM_PWMGenFaultClear +#define MAP_PWMGenFaultClear \ + ROM_PWMGenFaultClear +#else +#define MAP_PWMGenFaultClear \ + PWMGenFaultClear +#endif + +//***************************************************************************** +// +// Macros for the QEI API. +// +//***************************************************************************** +#ifdef ROM_QEIPositionGet +#define MAP_QEIPositionGet \ + ROM_QEIPositionGet +#else +#define MAP_QEIPositionGet \ + QEIPositionGet +#endif +#ifdef ROM_QEIEnable +#define MAP_QEIEnable \ + ROM_QEIEnable +#else +#define MAP_QEIEnable \ + QEIEnable +#endif +#ifdef ROM_QEIDisable +#define MAP_QEIDisable \ + ROM_QEIDisable +#else +#define MAP_QEIDisable \ + QEIDisable +#endif +#ifdef ROM_QEIConfigure +#define MAP_QEIConfigure \ + ROM_QEIConfigure +#else +#define MAP_QEIConfigure \ + QEIConfigure +#endif +#ifdef ROM_QEIPositionSet +#define MAP_QEIPositionSet \ + ROM_QEIPositionSet +#else +#define MAP_QEIPositionSet \ + QEIPositionSet +#endif +#ifdef ROM_QEIDirectionGet +#define MAP_QEIDirectionGet \ + ROM_QEIDirectionGet +#else +#define MAP_QEIDirectionGet \ + QEIDirectionGet +#endif +#ifdef ROM_QEIErrorGet +#define MAP_QEIErrorGet \ + ROM_QEIErrorGet +#else +#define MAP_QEIErrorGet \ + QEIErrorGet +#endif +#ifdef ROM_QEIVelocityEnable +#define MAP_QEIVelocityEnable \ + ROM_QEIVelocityEnable +#else +#define MAP_QEIVelocityEnable \ + QEIVelocityEnable +#endif +#ifdef ROM_QEIVelocityDisable +#define MAP_QEIVelocityDisable \ + ROM_QEIVelocityDisable +#else +#define MAP_QEIVelocityDisable \ + QEIVelocityDisable +#endif +#ifdef ROM_QEIVelocityConfigure +#define MAP_QEIVelocityConfigure \ + ROM_QEIVelocityConfigure +#else +#define MAP_QEIVelocityConfigure \ + QEIVelocityConfigure +#endif +#ifdef ROM_QEIVelocityGet +#define MAP_QEIVelocityGet \ + ROM_QEIVelocityGet +#else +#define MAP_QEIVelocityGet \ + QEIVelocityGet +#endif +#ifdef ROM_QEIIntEnable +#define MAP_QEIIntEnable \ + ROM_QEIIntEnable +#else +#define MAP_QEIIntEnable \ + QEIIntEnable +#endif +#ifdef ROM_QEIIntDisable +#define MAP_QEIIntDisable \ + ROM_QEIIntDisable +#else +#define MAP_QEIIntDisable \ + QEIIntDisable +#endif +#ifdef ROM_QEIIntStatus +#define MAP_QEIIntStatus \ + ROM_QEIIntStatus +#else +#define MAP_QEIIntStatus \ + QEIIntStatus +#endif +#ifdef ROM_QEIIntClear +#define MAP_QEIIntClear \ + ROM_QEIIntClear +#else +#define MAP_QEIIntClear \ + QEIIntClear +#endif + +//***************************************************************************** +// +// Macros for the SMBus API. +// +//***************************************************************************** +#ifdef ROM_SMBusMasterIntProcess +#define MAP_SMBusMasterIntProcess \ + ROM_SMBusMasterIntProcess +#else +#define MAP_SMBusMasterIntProcess \ + SMBusMasterIntProcess +#endif +#ifdef ROM_SMBusARPDisable +#define MAP_SMBusARPDisable \ + ROM_SMBusARPDisable +#else +#define MAP_SMBusARPDisable \ + SMBusARPDisable +#endif +#ifdef ROM_SMBusARPEnable +#define MAP_SMBusARPEnable \ + ROM_SMBusARPEnable +#else +#define MAP_SMBusARPEnable \ + SMBusARPEnable +#endif +#ifdef ROM_SMBusARPUDIDPacketDecode +#define MAP_SMBusARPUDIDPacketDecode \ + ROM_SMBusARPUDIDPacketDecode +#else +#define MAP_SMBusARPUDIDPacketDecode \ + SMBusARPUDIDPacketDecode +#endif +#ifdef ROM_SMBusARPUDIDPacketEncode +#define MAP_SMBusARPUDIDPacketEncode \ + ROM_SMBusARPUDIDPacketEncode +#else +#define MAP_SMBusARPUDIDPacketEncode \ + SMBusARPUDIDPacketEncode +#endif +#ifdef ROM_SMBusMasterARPAssignAddress +#define MAP_SMBusMasterARPAssignAddress \ + ROM_SMBusMasterARPAssignAddress +#else +#define MAP_SMBusMasterARPAssignAddress \ + SMBusMasterARPAssignAddress +#endif +#ifdef ROM_SMBusMasterARPGetUDIDDir +#define MAP_SMBusMasterARPGetUDIDDir \ + ROM_SMBusMasterARPGetUDIDDir +#else +#define MAP_SMBusMasterARPGetUDIDDir \ + SMBusMasterARPGetUDIDDir +#endif +#ifdef ROM_SMBusMasterARPGetUDIDGen +#define MAP_SMBusMasterARPGetUDIDGen \ + ROM_SMBusMasterARPGetUDIDGen +#else +#define MAP_SMBusMasterARPGetUDIDGen \ + SMBusMasterARPGetUDIDGen +#endif +#ifdef ROM_SMBusMasterARPNotifyMaster +#define MAP_SMBusMasterARPNotifyMaster \ + ROM_SMBusMasterARPNotifyMaster +#else +#define MAP_SMBusMasterARPNotifyMaster \ + SMBusMasterARPNotifyMaster +#endif +#ifdef ROM_SMBusMasterARPPrepareToARP +#define MAP_SMBusMasterARPPrepareToARP \ + ROM_SMBusMasterARPPrepareToARP +#else +#define MAP_SMBusMasterARPPrepareToARP \ + SMBusMasterARPPrepareToARP +#endif +#ifdef ROM_SMBusMasterARPResetDeviceDir +#define MAP_SMBusMasterARPResetDeviceDir \ + ROM_SMBusMasterARPResetDeviceDir +#else +#define MAP_SMBusMasterARPResetDeviceDir \ + SMBusMasterARPResetDeviceDir +#endif +#ifdef ROM_SMBusMasterARPResetDeviceGen +#define MAP_SMBusMasterARPResetDeviceGen \ + ROM_SMBusMasterARPResetDeviceGen +#else +#define MAP_SMBusMasterARPResetDeviceGen \ + SMBusMasterARPResetDeviceGen +#endif +#ifdef ROM_SMBusMasterBlockProcessCall +#define MAP_SMBusMasterBlockProcessCall \ + ROM_SMBusMasterBlockProcessCall +#else +#define MAP_SMBusMasterBlockProcessCall \ + SMBusMasterBlockProcessCall +#endif +#ifdef ROM_SMBusMasterBlockRead +#define MAP_SMBusMasterBlockRead \ + ROM_SMBusMasterBlockRead +#else +#define MAP_SMBusMasterBlockRead \ + SMBusMasterBlockRead +#endif +#ifdef ROM_SMBusMasterBlockWrite +#define MAP_SMBusMasterBlockWrite \ + ROM_SMBusMasterBlockWrite +#else +#define MAP_SMBusMasterBlockWrite \ + SMBusMasterBlockWrite +#endif +#ifdef ROM_SMBusMasterByteReceive +#define MAP_SMBusMasterByteReceive \ + ROM_SMBusMasterByteReceive +#else +#define MAP_SMBusMasterByteReceive \ + SMBusMasterByteReceive +#endif +#ifdef ROM_SMBusMasterByteSend +#define MAP_SMBusMasterByteSend \ + ROM_SMBusMasterByteSend +#else +#define MAP_SMBusMasterByteSend \ + SMBusMasterByteSend +#endif +#ifdef ROM_SMBusMasterByteWordRead +#define MAP_SMBusMasterByteWordRead \ + ROM_SMBusMasterByteWordRead +#else +#define MAP_SMBusMasterByteWordRead \ + SMBusMasterByteWordRead +#endif +#ifdef ROM_SMBusMasterByteWordWrite +#define MAP_SMBusMasterByteWordWrite \ + ROM_SMBusMasterByteWordWrite +#else +#define MAP_SMBusMasterByteWordWrite \ + SMBusMasterByteWordWrite +#endif +#ifdef ROM_SMBusMasterHostNotify +#define MAP_SMBusMasterHostNotify \ + ROM_SMBusMasterHostNotify +#else +#define MAP_SMBusMasterHostNotify \ + SMBusMasterHostNotify +#endif +#ifdef ROM_SMBusMasterI2CRead +#define MAP_SMBusMasterI2CRead \ + ROM_SMBusMasterI2CRead +#else +#define MAP_SMBusMasterI2CRead \ + SMBusMasterI2CRead +#endif +#ifdef ROM_SMBusMasterI2CWrite +#define MAP_SMBusMasterI2CWrite \ + ROM_SMBusMasterI2CWrite +#else +#define MAP_SMBusMasterI2CWrite \ + SMBusMasterI2CWrite +#endif +#ifdef ROM_SMBusMasterI2CWriteRead +#define MAP_SMBusMasterI2CWriteRead \ + ROM_SMBusMasterI2CWriteRead +#else +#define MAP_SMBusMasterI2CWriteRead \ + SMBusMasterI2CWriteRead +#endif +#ifdef ROM_SMBusMasterInit +#define MAP_SMBusMasterInit \ + ROM_SMBusMasterInit +#else +#define MAP_SMBusMasterInit \ + SMBusMasterInit +#endif +#ifdef ROM_SMBusMasterIntEnable +#define MAP_SMBusMasterIntEnable \ + ROM_SMBusMasterIntEnable +#else +#define MAP_SMBusMasterIntEnable \ + SMBusMasterIntEnable +#endif +#ifdef ROM_SMBusMasterProcessCall +#define MAP_SMBusMasterProcessCall \ + ROM_SMBusMasterProcessCall +#else +#define MAP_SMBusMasterProcessCall \ + SMBusMasterProcessCall +#endif +#ifdef ROM_SMBusMasterQuickCommand +#define MAP_SMBusMasterQuickCommand \ + ROM_SMBusMasterQuickCommand +#else +#define MAP_SMBusMasterQuickCommand \ + SMBusMasterQuickCommand +#endif +#ifdef ROM_SMBusPECDisable +#define MAP_SMBusPECDisable \ + ROM_SMBusPECDisable +#else +#define MAP_SMBusPECDisable \ + SMBusPECDisable +#endif +#ifdef ROM_SMBusPECEnable +#define MAP_SMBusPECEnable \ + ROM_SMBusPECEnable +#else +#define MAP_SMBusPECEnable \ + SMBusPECEnable +#endif +#ifdef ROM_SMBusRxPacketSizeGet +#define MAP_SMBusRxPacketSizeGet \ + ROM_SMBusRxPacketSizeGet +#else +#define MAP_SMBusRxPacketSizeGet \ + SMBusRxPacketSizeGet +#endif +#ifdef ROM_SMBusSlaveACKSend +#define MAP_SMBusSlaveACKSend \ + ROM_SMBusSlaveACKSend +#else +#define MAP_SMBusSlaveACKSend \ + SMBusSlaveACKSend +#endif +#ifdef ROM_SMBusSlaveAddressSet +#define MAP_SMBusSlaveAddressSet \ + ROM_SMBusSlaveAddressSet +#else +#define MAP_SMBusSlaveAddressSet \ + SMBusSlaveAddressSet +#endif +#ifdef ROM_SMBusSlaveARPFlagARGet +#define MAP_SMBusSlaveARPFlagARGet \ + ROM_SMBusSlaveARPFlagARGet +#else +#define MAP_SMBusSlaveARPFlagARGet \ + SMBusSlaveARPFlagARGet +#endif +#ifdef ROM_SMBusSlaveARPFlagARSet +#define MAP_SMBusSlaveARPFlagARSet \ + ROM_SMBusSlaveARPFlagARSet +#else +#define MAP_SMBusSlaveARPFlagARSet \ + SMBusSlaveARPFlagARSet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVGet +#define MAP_SMBusSlaveARPFlagAVGet \ + ROM_SMBusSlaveARPFlagAVGet +#else +#define MAP_SMBusSlaveARPFlagAVGet \ + SMBusSlaveARPFlagAVGet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVSet +#define MAP_SMBusSlaveARPFlagAVSet \ + ROM_SMBusSlaveARPFlagAVSet +#else +#define MAP_SMBusSlaveARPFlagAVSet \ + SMBusSlaveARPFlagAVSet +#endif +#ifdef ROM_SMBusSlaveBlockTransferDisable +#define MAP_SMBusSlaveBlockTransferDisable \ + ROM_SMBusSlaveBlockTransferDisable +#else +#define MAP_SMBusSlaveBlockTransferDisable \ + SMBusSlaveBlockTransferDisable +#endif +#ifdef ROM_SMBusSlaveBlockTransferEnable +#define MAP_SMBusSlaveBlockTransferEnable \ + ROM_SMBusSlaveBlockTransferEnable +#else +#define MAP_SMBusSlaveBlockTransferEnable \ + SMBusSlaveBlockTransferEnable +#endif +#ifdef ROM_SMBusSlaveCommandGet +#define MAP_SMBusSlaveCommandGet \ + ROM_SMBusSlaveCommandGet +#else +#define MAP_SMBusSlaveCommandGet \ + SMBusSlaveCommandGet +#endif +#ifdef ROM_SMBusSlaveI2CDisable +#define MAP_SMBusSlaveI2CDisable \ + ROM_SMBusSlaveI2CDisable +#else +#define MAP_SMBusSlaveI2CDisable \ + SMBusSlaveI2CDisable +#endif +#ifdef ROM_SMBusSlaveI2CEnable +#define MAP_SMBusSlaveI2CEnable \ + ROM_SMBusSlaveI2CEnable +#else +#define MAP_SMBusSlaveI2CEnable \ + SMBusSlaveI2CEnable +#endif +#ifdef ROM_SMBusSlaveInit +#define MAP_SMBusSlaveInit \ + ROM_SMBusSlaveInit +#else +#define MAP_SMBusSlaveInit \ + SMBusSlaveInit +#endif +#ifdef ROM_SMBusSlaveIntAddressGet +#define MAP_SMBusSlaveIntAddressGet \ + ROM_SMBusSlaveIntAddressGet +#else +#define MAP_SMBusSlaveIntAddressGet \ + SMBusSlaveIntAddressGet +#endif +#ifdef ROM_SMBusSlaveIntEnable +#define MAP_SMBusSlaveIntEnable \ + ROM_SMBusSlaveIntEnable +#else +#define MAP_SMBusSlaveIntEnable \ + SMBusSlaveIntEnable +#endif +#ifdef ROM_SMBusSlaveIntProcess +#define MAP_SMBusSlaveIntProcess \ + ROM_SMBusSlaveIntProcess +#else +#define MAP_SMBusSlaveIntProcess \ + SMBusSlaveIntProcess +#endif +#ifdef ROM_SMBusSlaveManualACKDisable +#define MAP_SMBusSlaveManualACKDisable \ + ROM_SMBusSlaveManualACKDisable +#else +#define MAP_SMBusSlaveManualACKDisable \ + SMBusSlaveManualACKDisable +#endif +#ifdef ROM_SMBusSlaveManualACKEnable +#define MAP_SMBusSlaveManualACKEnable \ + ROM_SMBusSlaveManualACKEnable +#else +#define MAP_SMBusSlaveManualACKEnable \ + SMBusSlaveManualACKEnable +#endif +#ifdef ROM_SMBusSlaveManualACKStatusGet +#define MAP_SMBusSlaveManualACKStatusGet \ + ROM_SMBusSlaveManualACKStatusGet +#else +#define MAP_SMBusSlaveManualACKStatusGet \ + SMBusSlaveManualACKStatusGet +#endif +#ifdef ROM_SMBusSlaveProcessCallDisable +#define MAP_SMBusSlaveProcessCallDisable \ + ROM_SMBusSlaveProcessCallDisable +#else +#define MAP_SMBusSlaveProcessCallDisable \ + SMBusSlaveProcessCallDisable +#endif +#ifdef ROM_SMBusSlaveProcessCallEnable +#define MAP_SMBusSlaveProcessCallEnable \ + ROM_SMBusSlaveProcessCallEnable +#else +#define MAP_SMBusSlaveProcessCallEnable \ + SMBusSlaveProcessCallEnable +#endif +#ifdef ROM_SMBusSlaveRxBufferSet +#define MAP_SMBusSlaveRxBufferSet \ + ROM_SMBusSlaveRxBufferSet +#else +#define MAP_SMBusSlaveRxBufferSet \ + SMBusSlaveRxBufferSet +#endif +#ifdef ROM_SMBusSlaveTransferInit +#define MAP_SMBusSlaveTransferInit \ + ROM_SMBusSlaveTransferInit +#else +#define MAP_SMBusSlaveTransferInit \ + SMBusSlaveTransferInit +#endif +#ifdef ROM_SMBusSlaveTxBufferSet +#define MAP_SMBusSlaveTxBufferSet \ + ROM_SMBusSlaveTxBufferSet +#else +#define MAP_SMBusSlaveTxBufferSet \ + SMBusSlaveTxBufferSet +#endif +#ifdef ROM_SMBusSlaveUDIDSet +#define MAP_SMBusSlaveUDIDSet \ + ROM_SMBusSlaveUDIDSet +#else +#define MAP_SMBusSlaveUDIDSet \ + SMBusSlaveUDIDSet +#endif +#ifdef ROM_SMBusStatusGet +#define MAP_SMBusStatusGet \ + ROM_SMBusStatusGet +#else +#define MAP_SMBusStatusGet \ + SMBusStatusGet +#endif +#ifdef ROM_SMBusSlaveDataSend +#define MAP_SMBusSlaveDataSend \ + ROM_SMBusSlaveDataSend +#else +#define MAP_SMBusSlaveDataSend \ + SMBusSlaveDataSend +#endif + +//***************************************************************************** +// +// Macros for the SSI API. +// +//***************************************************************************** +#ifdef ROM_SSIDataPut +#define MAP_SSIDataPut \ + ROM_SSIDataPut +#else +#define MAP_SSIDataPut \ + SSIDataPut +#endif +#ifdef ROM_SSIConfigSetExpClk +#define MAP_SSIConfigSetExpClk \ + ROM_SSIConfigSetExpClk +#else +#define MAP_SSIConfigSetExpClk \ + SSIConfigSetExpClk +#endif +#ifdef ROM_SSIEnable +#define MAP_SSIEnable \ + ROM_SSIEnable +#else +#define MAP_SSIEnable \ + SSIEnable +#endif +#ifdef ROM_SSIDisable +#define MAP_SSIDisable \ + ROM_SSIDisable +#else +#define MAP_SSIDisable \ + SSIDisable +#endif +#ifdef ROM_SSIIntEnable +#define MAP_SSIIntEnable \ + ROM_SSIIntEnable +#else +#define MAP_SSIIntEnable \ + SSIIntEnable +#endif +#ifdef ROM_SSIIntDisable +#define MAP_SSIIntDisable \ + ROM_SSIIntDisable +#else +#define MAP_SSIIntDisable \ + SSIIntDisable +#endif +#ifdef ROM_SSIIntStatus +#define MAP_SSIIntStatus \ + ROM_SSIIntStatus +#else +#define MAP_SSIIntStatus \ + SSIIntStatus +#endif +#ifdef ROM_SSIIntClear +#define MAP_SSIIntClear \ + ROM_SSIIntClear +#else +#define MAP_SSIIntClear \ + SSIIntClear +#endif +#ifdef ROM_SSIDataPutNonBlocking +#define MAP_SSIDataPutNonBlocking \ + ROM_SSIDataPutNonBlocking +#else +#define MAP_SSIDataPutNonBlocking \ + SSIDataPutNonBlocking +#endif +#ifdef ROM_SSIDataGet +#define MAP_SSIDataGet \ + ROM_SSIDataGet +#else +#define MAP_SSIDataGet \ + SSIDataGet +#endif +#ifdef ROM_SSIDataGetNonBlocking +#define MAP_SSIDataGetNonBlocking \ + ROM_SSIDataGetNonBlocking +#else +#define MAP_SSIDataGetNonBlocking \ + SSIDataGetNonBlocking +#endif +#ifdef ROM_SSIDMAEnable +#define MAP_SSIDMAEnable \ + ROM_SSIDMAEnable +#else +#define MAP_SSIDMAEnable \ + SSIDMAEnable +#endif +#ifdef ROM_SSIDMADisable +#define MAP_SSIDMADisable \ + ROM_SSIDMADisable +#else +#define MAP_SSIDMADisable \ + SSIDMADisable +#endif +#ifdef ROM_SSIBusy +#define MAP_SSIBusy \ + ROM_SSIBusy +#else +#define MAP_SSIBusy \ + SSIBusy +#endif +#ifdef ROM_SSIClockSourceGet +#define MAP_SSIClockSourceGet \ + ROM_SSIClockSourceGet +#else +#define MAP_SSIClockSourceGet \ + SSIClockSourceGet +#endif +#ifdef ROM_SSIClockSourceSet +#define MAP_SSIClockSourceSet \ + ROM_SSIClockSourceSet +#else +#define MAP_SSIClockSourceSet \ + SSIClockSourceSet +#endif + +//***************************************************************************** +// +// Macros for the SysCtl API. +// +//***************************************************************************** +#ifdef ROM_SysCtlSleep +#define MAP_SysCtlSleep \ + ROM_SysCtlSleep +#else +#define MAP_SysCtlSleep \ + SysCtlSleep +#endif +#ifdef ROM_SysCtlSRAMSizeGet +#define MAP_SysCtlSRAMSizeGet \ + ROM_SysCtlSRAMSizeGet +#else +#define MAP_SysCtlSRAMSizeGet \ + SysCtlSRAMSizeGet +#endif +#ifdef ROM_SysCtlFlashSizeGet +#define MAP_SysCtlFlashSizeGet \ + ROM_SysCtlFlashSizeGet +#else +#define MAP_SysCtlFlashSizeGet \ + SysCtlFlashSizeGet +#endif +#ifdef ROM_SysCtlPinPresent +#define MAP_SysCtlPinPresent \ + ROM_SysCtlPinPresent +#else +#define MAP_SysCtlPinPresent \ + SysCtlPinPresent +#endif +#ifdef ROM_SysCtlPeripheralPresent +#define MAP_SysCtlPeripheralPresent \ + ROM_SysCtlPeripheralPresent +#else +#define MAP_SysCtlPeripheralPresent \ + SysCtlPeripheralPresent +#endif +#ifdef ROM_SysCtlPeripheralReset +#define MAP_SysCtlPeripheralReset \ + ROM_SysCtlPeripheralReset +#else +#define MAP_SysCtlPeripheralReset \ + SysCtlPeripheralReset +#endif +#ifdef ROM_SysCtlPeripheralEnable +#define MAP_SysCtlPeripheralEnable \ + ROM_SysCtlPeripheralEnable +#else +#define MAP_SysCtlPeripheralEnable \ + SysCtlPeripheralEnable +#endif +#ifdef ROM_SysCtlPeripheralDisable +#define MAP_SysCtlPeripheralDisable \ + ROM_SysCtlPeripheralDisable +#else +#define MAP_SysCtlPeripheralDisable \ + SysCtlPeripheralDisable +#endif +#ifdef ROM_SysCtlPeripheralSleepEnable +#define MAP_SysCtlPeripheralSleepEnable \ + ROM_SysCtlPeripheralSleepEnable +#else +#define MAP_SysCtlPeripheralSleepEnable \ + SysCtlPeripheralSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralSleepDisable +#define MAP_SysCtlPeripheralSleepDisable \ + ROM_SysCtlPeripheralSleepDisable +#else +#define MAP_SysCtlPeripheralSleepDisable \ + SysCtlPeripheralSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepEnable +#define MAP_SysCtlPeripheralDeepSleepEnable \ + ROM_SysCtlPeripheralDeepSleepEnable +#else +#define MAP_SysCtlPeripheralDeepSleepEnable \ + SysCtlPeripheralDeepSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepDisable +#define MAP_SysCtlPeripheralDeepSleepDisable \ + ROM_SysCtlPeripheralDeepSleepDisable +#else +#define MAP_SysCtlPeripheralDeepSleepDisable \ + SysCtlPeripheralDeepSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralClockGating +#define MAP_SysCtlPeripheralClockGating \ + ROM_SysCtlPeripheralClockGating +#else +#define MAP_SysCtlPeripheralClockGating \ + SysCtlPeripheralClockGating +#endif +#ifdef ROM_SysCtlIntEnable +#define MAP_SysCtlIntEnable \ + ROM_SysCtlIntEnable +#else +#define MAP_SysCtlIntEnable \ + SysCtlIntEnable +#endif +#ifdef ROM_SysCtlIntDisable +#define MAP_SysCtlIntDisable \ + ROM_SysCtlIntDisable +#else +#define MAP_SysCtlIntDisable \ + SysCtlIntDisable +#endif +#ifdef ROM_SysCtlIntClear +#define MAP_SysCtlIntClear \ + ROM_SysCtlIntClear +#else +#define MAP_SysCtlIntClear \ + SysCtlIntClear +#endif +#ifdef ROM_SysCtlIntStatus +#define MAP_SysCtlIntStatus \ + ROM_SysCtlIntStatus +#else +#define MAP_SysCtlIntStatus \ + SysCtlIntStatus +#endif +#ifdef ROM_SysCtlLDOSet +#define MAP_SysCtlLDOSet \ + ROM_SysCtlLDOSet +#else +#define MAP_SysCtlLDOSet \ + SysCtlLDOSet +#endif +#ifdef ROM_SysCtlLDOGet +#define MAP_SysCtlLDOGet \ + ROM_SysCtlLDOGet +#else +#define MAP_SysCtlLDOGet \ + SysCtlLDOGet +#endif +#ifdef ROM_SysCtlReset +#define MAP_SysCtlReset \ + ROM_SysCtlReset +#else +#define MAP_SysCtlReset \ + SysCtlReset +#endif +#ifdef ROM_SysCtlDeepSleep +#define MAP_SysCtlDeepSleep \ + ROM_SysCtlDeepSleep +#else +#define MAP_SysCtlDeepSleep \ + SysCtlDeepSleep +#endif +#ifdef ROM_SysCtlResetCauseGet +#define MAP_SysCtlResetCauseGet \ + ROM_SysCtlResetCauseGet +#else +#define MAP_SysCtlResetCauseGet \ + SysCtlResetCauseGet +#endif +#ifdef ROM_SysCtlResetCauseClear +#define MAP_SysCtlResetCauseClear \ + ROM_SysCtlResetCauseClear +#else +#define MAP_SysCtlResetCauseClear \ + SysCtlResetCauseClear +#endif +#ifdef ROM_SysCtlClockSet +#define MAP_SysCtlClockSet \ + ROM_SysCtlClockSet +#else +#define MAP_SysCtlClockSet \ + SysCtlClockSet +#endif +#ifdef ROM_SysCtlClockGet +#define MAP_SysCtlClockGet \ + ROM_SysCtlClockGet +#else +#define MAP_SysCtlClockGet \ + SysCtlClockGet +#endif +#ifdef ROM_SysCtlPWMClockSet +#define MAP_SysCtlPWMClockSet \ + ROM_SysCtlPWMClockSet +#else +#define MAP_SysCtlPWMClockSet \ + SysCtlPWMClockSet +#endif +#ifdef ROM_SysCtlPWMClockGet +#define MAP_SysCtlPWMClockGet \ + ROM_SysCtlPWMClockGet +#else +#define MAP_SysCtlPWMClockGet \ + SysCtlPWMClockGet +#endif +#ifdef ROM_SysCtlADCSpeedSet +#define MAP_SysCtlADCSpeedSet \ + ROM_SysCtlADCSpeedSet +#else +#define MAP_SysCtlADCSpeedSet \ + SysCtlADCSpeedSet +#endif +#ifdef ROM_SysCtlADCSpeedGet +#define MAP_SysCtlADCSpeedGet \ + ROM_SysCtlADCSpeedGet +#else +#define MAP_SysCtlADCSpeedGet \ + SysCtlADCSpeedGet +#endif +#ifdef ROM_SysCtlGPIOAHBEnable +#define MAP_SysCtlGPIOAHBEnable \ + ROM_SysCtlGPIOAHBEnable +#else +#define MAP_SysCtlGPIOAHBEnable \ + SysCtlGPIOAHBEnable +#endif +#ifdef ROM_SysCtlGPIOAHBDisable +#define MAP_SysCtlGPIOAHBDisable \ + ROM_SysCtlGPIOAHBDisable +#else +#define MAP_SysCtlGPIOAHBDisable \ + SysCtlGPIOAHBDisable +#endif +#ifdef ROM_SysCtlUSBPLLEnable +#define MAP_SysCtlUSBPLLEnable \ + ROM_SysCtlUSBPLLEnable +#else +#define MAP_SysCtlUSBPLLEnable \ + SysCtlUSBPLLEnable +#endif +#ifdef ROM_SysCtlUSBPLLDisable +#define MAP_SysCtlUSBPLLDisable \ + ROM_SysCtlUSBPLLDisable +#else +#define MAP_SysCtlUSBPLLDisable \ + SysCtlUSBPLLDisable +#endif +#ifdef ROM_SysCtlI2SMClkSet +#define MAP_SysCtlI2SMClkSet \ + ROM_SysCtlI2SMClkSet +#else +#define MAP_SysCtlI2SMClkSet \ + SysCtlI2SMClkSet +#endif +#ifdef ROM_SysCtlDelay +#define MAP_SysCtlDelay \ + ROM_SysCtlDelay +#else +#define MAP_SysCtlDelay \ + SysCtlDelay +#endif +#ifdef ROM_SysCtlPeripheralReady +#define MAP_SysCtlPeripheralReady \ + ROM_SysCtlPeripheralReady +#else +#define MAP_SysCtlPeripheralReady \ + SysCtlPeripheralReady +#endif +#ifdef ROM_SysCtlPeripheralPowerOn +#define MAP_SysCtlPeripheralPowerOn \ + ROM_SysCtlPeripheralPowerOn +#else +#define MAP_SysCtlPeripheralPowerOn \ + SysCtlPeripheralPowerOn +#endif +#ifdef ROM_SysCtlPeripheralPowerOff +#define MAP_SysCtlPeripheralPowerOff \ + ROM_SysCtlPeripheralPowerOff +#else +#define MAP_SysCtlPeripheralPowerOff \ + SysCtlPeripheralPowerOff +#endif +#ifdef ROM_SysCtlMOSCConfigSet +#define MAP_SysCtlMOSCConfigSet \ + ROM_SysCtlMOSCConfigSet +#else +#define MAP_SysCtlMOSCConfigSet \ + SysCtlMOSCConfigSet +#endif +#ifdef ROM_SysCtlPIOSCCalibrate +#define MAP_SysCtlPIOSCCalibrate \ + ROM_SysCtlPIOSCCalibrate +#else +#define MAP_SysCtlPIOSCCalibrate \ + SysCtlPIOSCCalibrate +#endif +#ifdef ROM_SysCtlDeepSleepClockSet +#define MAP_SysCtlDeepSleepClockSet \ + ROM_SysCtlDeepSleepClockSet +#else +#define MAP_SysCtlDeepSleepClockSet \ + SysCtlDeepSleepClockSet +#endif + +//***************************************************************************** +// +// Macros for the SysExc API. +// +//***************************************************************************** +#ifdef ROM_SysExcIntStatus +#define MAP_SysExcIntStatus \ + ROM_SysExcIntStatus +#else +#define MAP_SysExcIntStatus \ + SysExcIntStatus +#endif +#ifdef ROM_SysExcIntClear +#define MAP_SysExcIntClear \ + ROM_SysExcIntClear +#else +#define MAP_SysExcIntClear \ + SysExcIntClear +#endif +#ifdef ROM_SysExcIntDisable +#define MAP_SysExcIntDisable \ + ROM_SysExcIntDisable +#else +#define MAP_SysExcIntDisable \ + SysExcIntDisable +#endif +#ifdef ROM_SysExcIntEnable +#define MAP_SysExcIntEnable \ + ROM_SysExcIntEnable +#else +#define MAP_SysExcIntEnable \ + SysExcIntEnable +#endif + +//***************************************************************************** +// +// Macros for the SysTick API. +// +//***************************************************************************** +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlTrigger +#define MAP_TimerControlTrigger \ + ROM_TimerControlTrigger +#else +#define MAP_TimerControlTrigger \ + TimerControlTrigger +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerRTCEnable +#define MAP_TimerRTCEnable \ + ROM_TimerRTCEnable +#else +#define MAP_TimerRTCEnable \ + TimerRTCEnable +#endif +#ifdef ROM_TimerRTCDisable +#define MAP_TimerRTCDisable \ + ROM_TimerRTCDisable +#else +#define MAP_TimerRTCDisable \ + TimerRTCDisable +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerControlWaitOnTrigger +#define MAP_TimerControlWaitOnTrigger \ + ROM_TimerControlWaitOnTrigger +#else +#define MAP_TimerControlWaitOnTrigger \ + TimerControlWaitOnTrigger +#endif +#ifdef ROM_TimerLoadSet64 +#define MAP_TimerLoadSet64 \ + ROM_TimerLoadSet64 +#else +#define MAP_TimerLoadSet64 \ + TimerLoadSet64 +#endif +#ifdef ROM_TimerLoadGet64 +#define MAP_TimerLoadGet64 \ + ROM_TimerLoadGet64 +#else +#define MAP_TimerLoadGet64 \ + TimerLoadGet64 +#endif +#ifdef ROM_TimerValueGet64 +#define MAP_TimerValueGet64 \ + ROM_TimerValueGet64 +#else +#define MAP_TimerValueGet64 \ + TimerValueGet64 +#endif +#ifdef ROM_TimerMatchSet64 +#define MAP_TimerMatchSet64 \ + ROM_TimerMatchSet64 +#else +#define MAP_TimerMatchSet64 \ + TimerMatchSet64 +#endif +#ifdef ROM_TimerMatchGet64 +#define MAP_TimerMatchGet64 \ + ROM_TimerMatchGet64 +#else +#define MAP_TimerMatchGet64 \ + TimerMatchGet64 +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTEnableSIR +#define MAP_UARTEnableSIR \ + ROM_UARTEnableSIR +#else +#define MAP_UARTEnableSIR \ + UARTEnableSIR +#endif +#ifdef ROM_UARTDisableSIR +#define MAP_UARTDisableSIR \ + ROM_UARTDisableSIR +#else +#define MAP_UARTDisableSIR \ + UARTDisableSIR +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTClockSourceSet +#define MAP_UARTClockSourceSet \ + ROM_UARTClockSourceSet +#else +#define MAP_UARTClockSourceSet \ + UARTClockSourceSet +#endif +#ifdef ROM_UARTClockSourceGet +#define MAP_UARTClockSourceGet \ + ROM_UARTClockSourceGet +#else +#define MAP_UARTClockSourceGet \ + UARTClockSourceGet +#endif +#ifdef ROM_UART9BitEnable +#define MAP_UART9BitEnable \ + ROM_UART9BitEnable +#else +#define MAP_UART9BitEnable \ + UART9BitEnable +#endif +#ifdef ROM_UART9BitDisable +#define MAP_UART9BitDisable \ + ROM_UART9BitDisable +#else +#define MAP_UART9BitDisable \ + UART9BitDisable +#endif +#ifdef ROM_UART9BitAddrSet +#define MAP_UART9BitAddrSet \ + ROM_UART9BitAddrSet +#else +#define MAP_UART9BitAddrSet \ + UART9BitAddrSet +#endif +#ifdef ROM_UART9BitAddrSend +#define MAP_UART9BitAddrSend \ + ROM_UART9BitAddrSend +#else +#define MAP_UART9BitAddrSend \ + UART9BitAddrSend +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAChannelSelectSecondary +#define MAP_uDMAChannelSelectSecondary \ + ROM_uDMAChannelSelectSecondary +#else +#define MAP_uDMAChannelSelectSecondary \ + uDMAChannelSelectSecondary +#endif +#ifdef ROM_uDMAChannelSelectDefault +#define MAP_uDMAChannelSelectDefault \ + ROM_uDMAChannelSelectDefault +#else +#define MAP_uDMAChannelSelectDefault \ + uDMAChannelSelectDefault +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif + +//***************************************************************************** +// +// Macros for the USB API. +// +//***************************************************************************** +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBDevAddrGet +#define MAP_USBDevAddrGet \ + ROM_USBDevAddrGet +#else +#define MAP_USBDevAddrGet \ + USBDevAddrGet +#endif +#ifdef ROM_USBDevAddrSet +#define MAP_USBDevAddrSet \ + ROM_USBDevAddrSet +#else +#define MAP_USBDevAddrSet \ + USBDevAddrSet +#endif +#ifdef ROM_USBDevConnect +#define MAP_USBDevConnect \ + ROM_USBDevConnect +#else +#define MAP_USBDevConnect \ + USBDevConnect +#endif +#ifdef ROM_USBDevDisconnect +#define MAP_USBDevDisconnect \ + ROM_USBDevDisconnect +#else +#define MAP_USBDevDisconnect \ + USBDevDisconnect +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define MAP_USBDevEndpointConfigSet \ + ROM_USBDevEndpointConfigSet +#else +#define MAP_USBDevEndpointConfigSet \ + USBDevEndpointConfigSet +#endif +#ifdef ROM_USBDevEndpointDataAck +#define MAP_USBDevEndpointDataAck \ + ROM_USBDevEndpointDataAck +#else +#define MAP_USBDevEndpointDataAck \ + USBDevEndpointDataAck +#endif +#ifdef ROM_USBDevEndpointStall +#define MAP_USBDevEndpointStall \ + ROM_USBDevEndpointStall +#else +#define MAP_USBDevEndpointStall \ + USBDevEndpointStall +#endif +#ifdef ROM_USBDevEndpointStallClear +#define MAP_USBDevEndpointStallClear \ + ROM_USBDevEndpointStallClear +#else +#define MAP_USBDevEndpointStallClear \ + USBDevEndpointStallClear +#endif +#ifdef ROM_USBDevEndpointStatusClear +#define MAP_USBDevEndpointStatusClear \ + ROM_USBDevEndpointStatusClear +#else +#define MAP_USBDevEndpointStatusClear \ + USBDevEndpointStatusClear +#endif +#ifdef ROM_USBEndpointDataGet +#define MAP_USBEndpointDataGet \ + ROM_USBEndpointDataGet +#else +#define MAP_USBEndpointDataGet \ + USBEndpointDataGet +#endif +#ifdef ROM_USBEndpointDataPut +#define MAP_USBEndpointDataPut \ + ROM_USBEndpointDataPut +#else +#define MAP_USBEndpointDataPut \ + USBEndpointDataPut +#endif +#ifdef ROM_USBEndpointDataSend +#define MAP_USBEndpointDataSend \ + ROM_USBEndpointDataSend +#else +#define MAP_USBEndpointDataSend \ + USBEndpointDataSend +#endif +#ifdef ROM_USBEndpointDataToggleClear +#define MAP_USBEndpointDataToggleClear \ + ROM_USBEndpointDataToggleClear +#else +#define MAP_USBEndpointDataToggleClear \ + USBEndpointDataToggleClear +#endif +#ifdef ROM_USBEndpointStatus +#define MAP_USBEndpointStatus \ + ROM_USBEndpointStatus +#else +#define MAP_USBEndpointStatus \ + USBEndpointStatus +#endif +#ifdef ROM_USBFIFOAddrGet +#define MAP_USBFIFOAddrGet \ + ROM_USBFIFOAddrGet +#else +#define MAP_USBFIFOAddrGet \ + USBFIFOAddrGet +#endif +#ifdef ROM_USBFIFOConfigGet +#define MAP_USBFIFOConfigGet \ + ROM_USBFIFOConfigGet +#else +#define MAP_USBFIFOConfigGet \ + USBFIFOConfigGet +#endif +#ifdef ROM_USBFIFOConfigSet +#define MAP_USBFIFOConfigSet \ + ROM_USBFIFOConfigSet +#else +#define MAP_USBFIFOConfigSet \ + USBFIFOConfigSet +#endif +#ifdef ROM_USBFIFOFlush +#define MAP_USBFIFOFlush \ + ROM_USBFIFOFlush +#else +#define MAP_USBFIFOFlush \ + USBFIFOFlush +#endif +#ifdef ROM_USBFrameNumberGet +#define MAP_USBFrameNumberGet \ + ROM_USBFrameNumberGet +#else +#define MAP_USBFrameNumberGet \ + USBFrameNumberGet +#endif +#ifdef ROM_USBHostAddrGet +#define MAP_USBHostAddrGet \ + ROM_USBHostAddrGet +#else +#define MAP_USBHostAddrGet \ + USBHostAddrGet +#endif +#ifdef ROM_USBHostAddrSet +#define MAP_USBHostAddrSet \ + ROM_USBHostAddrSet +#else +#define MAP_USBHostAddrSet \ + USBHostAddrSet +#endif +#ifdef ROM_USBHostEndpointConfig +#define MAP_USBHostEndpointConfig \ + ROM_USBHostEndpointConfig +#else +#define MAP_USBHostEndpointConfig \ + USBHostEndpointConfig +#endif +#ifdef ROM_USBHostEndpointDataAck +#define MAP_USBHostEndpointDataAck \ + ROM_USBHostEndpointDataAck +#else +#define MAP_USBHostEndpointDataAck \ + USBHostEndpointDataAck +#endif +#ifdef ROM_USBHostEndpointDataToggle +#define MAP_USBHostEndpointDataToggle \ + ROM_USBHostEndpointDataToggle +#else +#define MAP_USBHostEndpointDataToggle \ + USBHostEndpointDataToggle +#endif +#ifdef ROM_USBHostEndpointStatusClear +#define MAP_USBHostEndpointStatusClear \ + ROM_USBHostEndpointStatusClear +#else +#define MAP_USBHostEndpointStatusClear \ + USBHostEndpointStatusClear +#endif +#ifdef ROM_USBHostHubAddrGet +#define MAP_USBHostHubAddrGet \ + ROM_USBHostHubAddrGet +#else +#define MAP_USBHostHubAddrGet \ + USBHostHubAddrGet +#endif +#ifdef ROM_USBHostHubAddrSet +#define MAP_USBHostHubAddrSet \ + ROM_USBHostHubAddrSet +#else +#define MAP_USBHostHubAddrSet \ + USBHostHubAddrSet +#endif +#ifdef ROM_USBHostPwrDisable +#define MAP_USBHostPwrDisable \ + ROM_USBHostPwrDisable +#else +#define MAP_USBHostPwrDisable \ + USBHostPwrDisable +#endif +#ifdef ROM_USBHostPwrEnable +#define MAP_USBHostPwrEnable \ + ROM_USBHostPwrEnable +#else +#define MAP_USBHostPwrEnable \ + USBHostPwrEnable +#endif +#ifdef ROM_USBHostPwrConfig +#define MAP_USBHostPwrConfig \ + ROM_USBHostPwrConfig +#else +#define MAP_USBHostPwrConfig \ + USBHostPwrConfig +#endif +#ifdef ROM_USBHostPwrFaultDisable +#define MAP_USBHostPwrFaultDisable \ + ROM_USBHostPwrFaultDisable +#else +#define MAP_USBHostPwrFaultDisable \ + USBHostPwrFaultDisable +#endif +#ifdef ROM_USBHostPwrFaultEnable +#define MAP_USBHostPwrFaultEnable \ + ROM_USBHostPwrFaultEnable +#else +#define MAP_USBHostPwrFaultEnable \ + USBHostPwrFaultEnable +#endif +#ifdef ROM_USBHostRequestIN +#define MAP_USBHostRequestIN \ + ROM_USBHostRequestIN +#else +#define MAP_USBHostRequestIN \ + USBHostRequestIN +#endif +#ifdef ROM_USBHostRequestStatus +#define MAP_USBHostRequestStatus \ + ROM_USBHostRequestStatus +#else +#define MAP_USBHostRequestStatus \ + USBHostRequestStatus +#endif +#ifdef ROM_USBHostReset +#define MAP_USBHostReset \ + ROM_USBHostReset +#else +#define MAP_USBHostReset \ + USBHostReset +#endif +#ifdef ROM_USBHostResume +#define MAP_USBHostResume \ + ROM_USBHostResume +#else +#define MAP_USBHostResume \ + USBHostResume +#endif +#ifdef ROM_USBHostSpeedGet +#define MAP_USBHostSpeedGet \ + ROM_USBHostSpeedGet +#else +#define MAP_USBHostSpeedGet \ + USBHostSpeedGet +#endif +#ifdef ROM_USBHostSuspend +#define MAP_USBHostSuspend \ + ROM_USBHostSuspend +#else +#define MAP_USBHostSuspend \ + USBHostSuspend +#endif +#ifdef ROM_USBIntDisable +#define MAP_USBIntDisable \ + ROM_USBIntDisable +#else +#define MAP_USBIntDisable \ + USBIntDisable +#endif +#ifdef ROM_USBIntEnable +#define MAP_USBIntEnable \ + ROM_USBIntEnable +#else +#define MAP_USBIntEnable \ + USBIntEnable +#endif +#ifdef ROM_USBDevEndpointConfigGet +#define MAP_USBDevEndpointConfigGet \ + ROM_USBDevEndpointConfigGet +#else +#define MAP_USBDevEndpointConfigGet \ + USBDevEndpointConfigGet +#endif +#ifdef ROM_USBEndpointDMAEnable +#define MAP_USBEndpointDMAEnable \ + ROM_USBEndpointDMAEnable +#else +#define MAP_USBEndpointDMAEnable \ + USBEndpointDMAEnable +#endif +#ifdef ROM_USBEndpointDMADisable +#define MAP_USBEndpointDMADisable \ + ROM_USBEndpointDMADisable +#else +#define MAP_USBEndpointDMADisable \ + USBEndpointDMADisable +#endif +#ifdef ROM_USBEndpointDataAvail +#define MAP_USBEndpointDataAvail \ + ROM_USBEndpointDataAvail +#else +#define MAP_USBEndpointDataAvail \ + USBEndpointDataAvail +#endif +#ifdef ROM_USBOTGHostRequest +#define MAP_USBOTGHostRequest \ + ROM_USBOTGHostRequest +#else +#define MAP_USBOTGHostRequest \ + USBOTGHostRequest +#endif +#ifdef ROM_USBModeGet +#define MAP_USBModeGet \ + ROM_USBModeGet +#else +#define MAP_USBModeGet \ + USBModeGet +#endif +#ifdef ROM_USBEndpointDMAChannel +#define MAP_USBEndpointDMAChannel \ + ROM_USBEndpointDMAChannel +#else +#define MAP_USBEndpointDMAChannel \ + USBEndpointDMAChannel +#endif +#ifdef ROM_USBIntDisableControl +#define MAP_USBIntDisableControl \ + ROM_USBIntDisableControl +#else +#define MAP_USBIntDisableControl \ + USBIntDisableControl +#endif +#ifdef ROM_USBIntEnableControl +#define MAP_USBIntEnableControl \ + ROM_USBIntEnableControl +#else +#define MAP_USBIntEnableControl \ + USBIntEnableControl +#endif +#ifdef ROM_USBIntStatusControl +#define MAP_USBIntStatusControl \ + ROM_USBIntStatusControl +#else +#define MAP_USBIntStatusControl \ + USBIntStatusControl +#endif +#ifdef ROM_USBIntDisableEndpoint +#define MAP_USBIntDisableEndpoint \ + ROM_USBIntDisableEndpoint +#else +#define MAP_USBIntDisableEndpoint \ + USBIntDisableEndpoint +#endif +#ifdef ROM_USBIntEnableEndpoint +#define MAP_USBIntEnableEndpoint \ + ROM_USBIntEnableEndpoint +#else +#define MAP_USBIntEnableEndpoint \ + USBIntEnableEndpoint +#endif +#ifdef ROM_USBIntStatusEndpoint +#define MAP_USBIntStatusEndpoint \ + ROM_USBIntStatusEndpoint +#else +#define MAP_USBIntStatusEndpoint \ + USBIntStatusEndpoint +#endif +#ifdef ROM_USBHostMode +#define MAP_USBHostMode \ + ROM_USBHostMode +#else +#define MAP_USBHostMode \ + USBHostMode +#endif +#ifdef ROM_USBDevMode +#define MAP_USBDevMode \ + ROM_USBDevMode +#else +#define MAP_USBDevMode \ + USBDevMode +#endif +#ifdef ROM_USBPHYPowerOff +#define MAP_USBPHYPowerOff \ + ROM_USBPHYPowerOff +#else +#define MAP_USBPHYPowerOff \ + USBPHYPowerOff +#endif +#ifdef ROM_USBPHYPowerOn +#define MAP_USBPHYPowerOn \ + ROM_USBPHYPowerOn +#else +#define MAP_USBPHYPowerOn \ + USBPHYPowerOn +#endif +#ifdef ROM_USBOTGMode +#define MAP_USBOTGMode \ + ROM_USBOTGMode +#else +#define MAP_USBOTGMode \ + USBOTGMode +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogResetEnable +#define MAP_WatchdogResetEnable \ + ROM_WatchdogResetEnable +#else +#define MAP_WatchdogResetEnable \ + WatchdogResetEnable +#endif +#ifdef ROM_WatchdogResetDisable +#define MAP_WatchdogResetDisable \ + ROM_WatchdogResetDisable +#else +#define MAP_WatchdogResetDisable \ + WatchdogResetDisable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntEnable +#define MAP_WatchdogIntEnable \ + ROM_WatchdogIntEnable +#else +#define MAP_WatchdogIntEnable \ + WatchdogIntEnable +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntTypeSet +#define MAP_WatchdogIntTypeSet \ + ROM_WatchdogIntTypeSet +#else +#define MAP_WatchdogIntTypeSet \ + WatchdogIntTypeSet +#endif + +//***************************************************************************** +// +// Macros for the Software API. +// +//***************************************************************************** +#ifdef ROM_Crc16Array +#define MAP_Crc16Array \ + ROM_Crc16Array +#else +#define MAP_Crc16Array \ + Crc16Array +#endif +#ifdef ROM_Crc16Array3 +#define MAP_Crc16Array3 \ + ROM_Crc16Array3 +#else +#define MAP_Crc16Array3 \ + Crc16Array3 +#endif +#ifdef ROM_Crc16 +#define MAP_Crc16 \ + ROM_Crc16 +#else +#define MAP_Crc16 \ + Crc16 +#endif +#ifdef ROM_Crc8CCITT +#define MAP_Crc8CCITT \ + ROM_Crc8CCITT +#else +#define MAP_Crc8CCITT \ + Crc8CCITT +#endif + +#endif // __ROM_MAP_H__ diff --git a/driverlib/rtos_bindings.h b/driverlib/rtos_bindings.h new file mode 100644 index 0000000..b65e90d --- /dev/null +++ b/driverlib/rtos_bindings.h @@ -0,0 +1,107 @@ +//***************************************************************************** +// +// rtos_bindings.h - Macros ulIntIDended to aid porting of StellarisWare modules +// for use with an RTOS. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** +#ifndef RTOS_BINDINGS_H_ +#define RTOS_BINDINGS_H_ + +#ifdef USE_RTOS +//***************************************************************************** +// +// If an RTOS is in use, implement a header file called "stellaris_rtos.h" +// which contains RTOS-specific versions of each of the macros defined below +// and make sure it appears on the include path set when you build your +// project. +// +// Note that there is no default implementation of this header file included +// in StellarisWare - it is your responsibility to create it specifically for +// your RTOS. +// +//***************************************************************************** +#include "stellaris_rtos.h" + +#else +//***************************************************************************** +// +// When no RTOS is in use, the follow macros compile to either nothing or a +// minimal implementation that works in a bare-metal environment. +// +// Each of these macros must be redefined in stellaris_rtos.h if you are using +// StellarisWare under an RTOS. +// +//***************************************************************************** + +//***************************************************************************** +// +// A simple macro used to yield within polling loops. In the default, non-RTOS +// implementation, this compiles to nothing. +// +//***************************************************************************** +#define OS_YIELD() + +//***************************************************************************** +// +// A simple macro around the SysCtlDelay function. The parameter is the number +// of 3 cycle loops to wait before returning (as for SysCtlDelay). In an RTOS +// implementation, this could be replaced with an OS delay call with +// appropriate parameter scaling. +// +//***************************************************************************** +#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles) + +//***************************************************************************** +// +// Wrappers around low level interrupt control functions. For information +// on each of these functions, please see the appropriate API documentation +// for the DriverLib Interrupt driver. +// +// The macros defined here represent interrupt-control functions that may be +// called from within StellarisWare code. It is expected that application +// code will use RTOS-specific functions to control interrupt priority, to +// pend interrupts and to perform runtime vector manipulation. As a result, +// no macros are defined to wrap any of these functions from interrupt.c. +// +//***************************************************************************** +#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable() +#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable() +#define OS_INT_DISABLE(ulIntID) MAP_IntDisable(ulIntID) +#define OS_INT_ENABLE(ulIntID) MAP_IntEnable(ulIntID) + +#endif // USE_RTOS + +#endif // RTOS_BINDINGS_H_ diff --git a/driverlib/rvmdk-cm3/driverlib-cm3.lib b/driverlib/rvmdk-cm3/driverlib-cm3.lib new file mode 100644 index 0000000..4c872ea Binary files /dev/null and b/driverlib/rvmdk-cm3/driverlib-cm3.lib differ diff --git a/driverlib/rvmdk-cm4f/driverlib-cm4f.lib b/driverlib/rvmdk-cm4f/driverlib-cm4f.lib new file mode 100644 index 0000000..8c6b1ce Binary files /dev/null and b/driverlib/rvmdk-cm4f/driverlib-cm4f.lib differ diff --git a/driverlib/ssi.c b/driverlib/ssi.c new file mode 100644 index 0000000..e1f89b5 --- /dev/null +++ b/driverlib/ssi.c @@ -0,0 +1,870 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ssi.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/ssi.h" + +//***************************************************************************** +// +// A mapping of timer base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulSSIIntMap[][2] = +{ + { SSI0_BASE, INT_SSI0 }, + { SSI1_BASE, INT_SSI1 }, + { SSI2_BASE, INT_SSI2 }, + { SSI3_BASE, INT_SSI3 }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks an SSI base address. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function determines if a SSI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +SSIBaseValid(unsigned long ulBase) +{ + return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) || + (ulBase == SSI2_BASE) || (ulBase == SSI3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the SSI interrupt number. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! Given a SSI base address, returns the corresponding interrupt number. +//! +//! \return Returns an SSI interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +SSIIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps SSI base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulSSIIntMap) / + sizeof(g_ppulSSIIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulSSIIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulSSIIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulSSIClk is the rate of the clock supplied to the SSI module. +//! \param ulProtocol specifies the data transfer protocol. +//! \param ulMode specifies the mode of operation. +//! \param ulBitRate specifies the clock rate. +//! \param ulDataWidth specifies number of bits transferred per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \e ulProtocol parameter defines the data frame format. The +//! \e ulProtocol parameter can be one of the following values: +//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, +//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola +//! frame formats encode the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \e ulMode parameter defines the operating mode of the SSI module. The +//! SSI module can operate as a master or slave; if it is a slave, the SSI can +//! be configured to disable output on its serial output line. The \e ulMode +//! parameter can be one of the following values: \b SSI_MODE_MASTER, +//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. +//! +//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate +//! must satisfy the following clock ratio criteria: +//! +//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz. +//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the +//! capability of the specific microcontroller +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The \e ulDataWidth parameter defines the width of the data transfers and +//! can be a value between 4 and 16, inclusive. +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! This function replaces the original SSIConfig() API and performs the same +//! actions. A macro is provided in ssi.h to map the original API to +//! this API. +//! +//! \return None. +// +//***************************************************************************** +void +SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, unsigned long ulDataWidth) +{ + unsigned long ulMaxBitRate; + unsigned long ulRegVal; + unsigned long ulPreDiv; + unsigned long ulSCR; + unsigned long ulSPH_SPO; + + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || + (ulProtocol == SSI_FRF_MOTO_MODE_1) || + (ulProtocol == SSI_FRF_MOTO_MODE_2) || + (ulProtocol == SSI_FRF_MOTO_MODE_3) || + (ulProtocol == SSI_FRF_TI) || + (ulProtocol == SSI_FRF_NMW)); + ASSERT((ulMode == SSI_MODE_MASTER) || + (ulMode == SSI_MODE_SLAVE) || + (ulMode == SSI_MODE_SLAVE_OD)); + ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) || + ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12)))); + ASSERT((ulSSIClk / ulBitRate) <= (254 * 256)); + ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); + + // + // Set the mode. + // + ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ulBase + SSI_O_CR1) = ulRegVal; + + // + // Set the clock predivider. + // + ulMaxBitRate = ulSSIClk / ulBitRate; + ulPreDiv = 0; + do + { + ulPreDiv += 2; + ulSCR = (ulMaxBitRate / ulPreDiv) - 1; + } + while(ulSCR > 255); + HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; + + // + // Set protocol and clock rate. + // + ulSPH_SPO = (ulProtocol & 3) << 6; + ulProtocol &= SSI_CR0_FRF_M; + ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); + HWREG(ulBase + SSI_O_CR0) = ulRegVal; +} + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function enables operation of the synchronous serial interface. The +//! synchronous serial interface must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SSIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function disables operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This function registers the handler to be called when an SSI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Determine the interrupt number based on the SSI port. + // + ulInt = SSIIntNumberGet(ulBase); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function clears the handler to be called when an SSI interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Determine the interrupt number based on the SSI port. + // + ulInt = SSIIntNumberGet(ulBase); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SSI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. The \e ulIntFlags +//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or +//! \b SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SSI interrupt sources. The +//! \e ulIntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, +//! \b SSI_RXTO, or \b SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the SSI module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the SSI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR. +// +//***************************************************************************** +unsigned long +SSIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + SSI_O_MIS)); + } + else + { + return(HWREG(ulBase + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified SSI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and +//! \b SSI_RXOR values. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + SSI_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData is the data to be transmitted over the SSI interface. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space available in the transmit FIFO, +//! this function waits until there is space available before returning. +//! +//! \note The upper 32 - N bits of \e ulData are discarded by the hardware, +//! where N is the data width as configured by SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \e ulData are discarded. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ulBase + SSI_O_DR) = ulData; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData is the data to be transmitted over the SSI interface. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! This function replaces the original SSIDataNonBlockingPut() API and +//! performs the same actions. A macro is provided in ssi.h to map +//! the original API to this API. +//! +//! \note The upper 32 - N bits of \e ulData are discarded by the hardware, +//! where N is the data width as configured by SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \e ulData are discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +long +SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Check for space to write. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ulBase + SSI_O_DR) = ulData; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! This function gets received data from the receive FIFO of the specified +//! SSI module and places that data into the location specified by the +//! \e pulData parameter. If there is no data available, this function waits +//! until data is received before returning. +//! +//! \note Only the lower N bits of the value written to \e pulData contain +//! valid data, where N is the data width as configured by +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \e pulData +//! contain valid data. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pulData = HWREG(ulBase + SSI_O_DR); +} + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \e ulData +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! This function replaces the original SSIDataNonBlockingGet() API and +//! performs the same actions. A macro is provided in ssi.h to map +//! the original API to this API. +//! +//! \note Only the lower N bits of the value written to \e pulData contain +//! valid data, where N is the data width as configured by +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \e pulData +//! contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +long +SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Check for data to read. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) + { + *pulData = HWREG(ulBase + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Enables SSI DMA operation. +//! +//! \param ulBase is the base address of the SSI port. +//! \param ulDMAFlags is a bit mask of the DMA features to enable. +//! +//! This function enables the specified SSI DMA features. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! The \e ulDMAFlags parameter is the logical OR of any of the following +//! values: +//! +//! - SSI_DMA_RX - enable DMA for receive +//! - SSI_DMA_TX - enable DMA for transmit +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Set the requested bits in the SSI DMA control register. + // + HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags; +} + +//***************************************************************************** +// +//! Disables SSI DMA operation. +//! +//! \param ulBase is the base address of the SSI port. +//! \param ulDMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The +//! \e ulDMAFlags parameter is the logical OR of any of the following values: +//! +//! - SSI_DMA_RX - disable DMA for receive +//! - SSI_DMA_TX - disable DMA for transmit +//! +//! \return None. +// +//***************************************************************************** +void +SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Clear the requested bits in the SSI DMA control register. + // + HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags; +} + +//***************************************************************************** +// +//! Determines whether the SSI transmitter is busy or not. +//! +//! \param ulBase is the base address of the SSI port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. +//! +//! \return Returns \b true if the SSI is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +tBoolean +SSIBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Determine if the SSI is busy. + // + return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false); +} + +//***************************************************************************** +// +//! Sets the data clock source for the specified SSI peripheral. +//! +//! \param ulBase is the base address of the SSI port. +//! \param ulSource is the baud clock source for the SSI. +//! +//! This function allows the baud clock source for the SSI to be selected. +//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). +//! +//! Changing the baud clock source changes the data rate generated by the +//! SSI. Therefore, the data rate should be reconfigured after any change to +//! the SSI clock source. +//! +//! \note The ability to specify the SSI baud clock source varies with the +//! Stellaris part and SSI in use. Please consult the data sheet for the part +//! in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + ASSERT((ulSource == SSI_CLOCK_SYSTEM) || (ulSource == SSI_CLOCK_PIOSC)); + + // + // Set the SSI clock source. + // + HWREG(ulBase + SSI_O_CC) = ulSource; +} + +//***************************************************************************** +// +//! Gets the data clock source for the specified SSI peripheral. +//! +//! \param ulBase is the base address of the SSI port. +//! +//! This function returns the data clock source for the specified SSI. The +//! possible data clock source are the system clock (\b SSI_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). +//! +//! \note The ability to specify the SSI data clock source varies with the +//! Stellaris part and SSI in use. Please consult the data sheet for the part +//! in use to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +SSIClockSourceGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Return the SSI clock source. + // + return(HWREG(ulBase + SSI_O_CC)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/ssi.h b/driverlib/ssi.h new file mode 100644 index 0000000..1a40214 --- /dev/null +++ b/driverlib/ssi.h @@ -0,0 +1,151 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +#define SSI_CLOCK_SYSTEM 0x00000000 +#define SSI_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern tBoolean SSIBusy(unsigned long ulBase); +extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource); +extern unsigned long SSIClockSourceGet(unsigned long ulBase); + +//***************************************************************************** +// +// Several SSI APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define SSIConfig(a, b, c, d, e) \ + SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e) +#define SSIDataNonBlockingGet(a, b) \ + SSIDataGetNonBlocking(a, b) +#define SSIDataNonBlockingPut(a, b) \ + SSIDataPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/driverlib/sysctl.c b/driverlib/sysctl.c new file mode 100644 index 0000000..81d110e --- /dev/null +++ b/driverlib/sysctl.c @@ -0,0 +1,3147 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/cpu.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +// A macro used to determine whether the target part uses the new SysCtl +// register layout. +// +//***************************************************************************** + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number. +// +//***************************************************************************** +#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf) + +//***************************************************************************** +// +// This macro constructs the peripheral bit mask from the peripheral number. +// +//***************************************************************************** +#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16)) + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that +// contains the peripheral present bit for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulDCRegs[] = +{ + SYSCTL_DC1, + SYSCTL_DC2, + SYSCTL_DC4, + SYSCTL_DC1 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that +// controls the software reset for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulSRCRRegs[] = +{ + SYSCTL_SRCR0, + SYSCTL_SRCR1, + SYSCTL_SRCR2 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that +// controls the run-mode enable for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulRCGCRegs[] = +{ + SYSCTL_RCGC0, + SYSCTL_RCGC1, + SYSCTL_RCGC2 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that +// controls the sleep-mode enable for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulSCGCRegs[] = +{ + SYSCTL_SCGC0, + SYSCTL_SCGC1, + SYSCTL_SCGC2 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that +// controls the deep-sleep-mode enable for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulDCGCRegs[] = +{ + SYSCTL_DCGC0, + SYSCTL_DCGC1, + SYSCTL_DCGC2 +}; + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +static const unsigned long g_pulXtals[] = +{ + 1000000, + 1843200, + 2000000, + 2457600, + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000, + 10000000, + 12000000, + 12288000, + 13560000, + 14318180, + 16000000, + 16384000, + 18000000, + 20000000, + 24000000, + 25000000 +}; + +//***************************************************************************** +// +// The base addresses of the various peripheral control registers. +// +//***************************************************************************** +#define SYSCTL_PPBASE 0x400fe300 +#define SYSCTL_SRBASE 0x400fe500 +#define SYSCTL_RCGCBASE 0x400fe600 +#define SYSCTL_SCGCBASE 0x400fe700 +#define SYSCTL_DCGCBASE 0x400fe800 +#define SYSCTL_PCBASE 0x400fe900 +#define SYSCTL_PRBASE 0x400fea00 + +//***************************************************************************** +// +//! \internal +//! Checks a peripheral identifier. +//! +//! \param ulPeripheral is the peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \return Returns \b true if the peripheral identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +SysCtlPeripheralValid(unsigned long ulPeripheral) +{ + return((ulPeripheral == SYSCTL_PERIPH_ADC0) || + (ulPeripheral == SYSCTL_PERIPH_ADC1) || + (ulPeripheral == SYSCTL_PERIPH_CAN0) || + (ulPeripheral == SYSCTL_PERIPH_CAN1) || + (ulPeripheral == SYSCTL_PERIPH_CAN2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_EEPROM0) || + (ulPeripheral == SYSCTL_PERIPH_EPI0) || + (ulPeripheral == SYSCTL_PERIPH_ETH) || + (ulPeripheral == SYSCTL_PERIPH_FAN0) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulPeripheral == SYSCTL_PERIPH_GPIOF) || + (ulPeripheral == SYSCTL_PERIPH_GPIOG) || + (ulPeripheral == SYSCTL_PERIPH_GPIOH) || + (ulPeripheral == SYSCTL_PERIPH_GPIOJ) || + (ulPeripheral == SYSCTL_PERIPH_GPIOK) || + (ulPeripheral == SYSCTL_PERIPH_GPIOL) || + (ulPeripheral == SYSCTL_PERIPH_GPIOM) || + (ulPeripheral == SYSCTL_PERIPH_GPION) || + (ulPeripheral == SYSCTL_PERIPH_GPIOP) || + (ulPeripheral == SYSCTL_PERIPH_GPIOQ) || + (ulPeripheral == SYSCTL_PERIPH_GPIOR) || + (ulPeripheral == SYSCTL_PERIPH_GPIOS) || + (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) || + (ulPeripheral == SYSCTL_PERIPH_I2C0) || + (ulPeripheral == SYSCTL_PERIPH_I2C1) || + (ulPeripheral == SYSCTL_PERIPH_I2C2) || + (ulPeripheral == SYSCTL_PERIPH_I2C3) || + (ulPeripheral == SYSCTL_PERIPH_I2C4) || + (ulPeripheral == SYSCTL_PERIPH_I2C5) || + (ulPeripheral == SYSCTL_PERIPH_I2S0) || + (ulPeripheral == SYSCTL_PERIPH_IEEE1588) || + (ulPeripheral == SYSCTL_PERIPH_LPC0) || + (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_PECI0) || + (ulPeripheral == SYSCTL_PERIPH_PLL) || + (ulPeripheral == SYSCTL_PERIPH_PWM0) || + (ulPeripheral == SYSCTL_PERIPH_PWM1) || + (ulPeripheral == SYSCTL_PERIPH_QEI0) || + (ulPeripheral == SYSCTL_PERIPH_QEI1) || + (ulPeripheral == SYSCTL_PERIPH_SSI0) || + (ulPeripheral == SYSCTL_PERIPH_SSI1) || + (ulPeripheral == SYSCTL_PERIPH_SSI2) || + (ulPeripheral == SYSCTL_PERIPH_SSI3) || + (ulPeripheral == SYSCTL_PERIPH_TEMP) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_TIMER3) || + (ulPeripheral == SYSCTL_PERIPH_TIMER4) || + (ulPeripheral == SYSCTL_PERIPH_TIMER5) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_UART2) || + (ulPeripheral == SYSCTL_PERIPH_UART3) || + (ulPeripheral == SYSCTL_PERIPH_UART4) || + (ulPeripheral == SYSCTL_PERIPH_UART5) || + (ulPeripheral == SYSCTL_PERIPH_UART6) || + (ulPeripheral == SYSCTL_PERIPH_UART7) || + (ulPeripheral == SYSCTL_PERIPH_UDMA) || + (ulPeripheral == SYSCTL_PERIPH_USB0) || + (ulPeripheral == SYSCTL_PERIPH_WDOG0) || + (ulPeripheral == SYSCTL_PERIPH_WDOG1) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER0) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER1) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER2) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER3) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER4) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER5)); +} +#endif + +//***************************************************************************** +// +// A map of old peripheral defines to new peripheral defines. Note that the +// new peripheral defines do not work on parts that precede Blizzard class. +// +//***************************************************************************** +static const unsigned long g_ppulPeripheralMap[][2] = +{ + { SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH2_ADC0 }, + { SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH2_ADC1 }, + { SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH2_CAN0 }, + { SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH2_CAN1 }, + { SYSCTL_PERIPH_CAN2, SYSCTL_PERIPH2_CAN2 }, + { SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH2_COMP0 }, + { SYSCTL_PERIPH_COMP1, SYSCTL_PERIPH2_COMP0 }, + { SYSCTL_PERIPH_COMP2, SYSCTL_PERIPH2_COMP0 }, + { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH2_GPIOA }, + { SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH2_GPIOB }, + { SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH2_GPIOC }, + { SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH2_GPIOD }, + { SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH2_GPIOE }, + { SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH2_GPIOF }, + { SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH2_GPIOG }, + { SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH2_GPIOH }, + { SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH2_GPIOJ }, + { SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH2_HIBERNATE }, + { SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH2_I2C0 }, + { SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH2_I2C1 }, + { SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH2_PWM0 }, + { SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH2_QEI0 }, + { SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH2_QEI1 }, + { SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH2_SSI0 }, + { SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH2_SSI1 }, + { SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH2_TIMER0 }, + { SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH2_TIMER1 }, + { SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH2_TIMER2 }, + { SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH2_TIMER3 }, + { SYSCTL_PERIPH_UART0, SYSCTL_PERIPH2_UART0 }, + { SYSCTL_PERIPH_UART1, SYSCTL_PERIPH2_UART1 }, + { SYSCTL_PERIPH_UART2, SYSCTL_PERIPH2_UART2 }, + { SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH2_UDMA }, + { SYSCTL_PERIPH_USB0, SYSCTL_PERIPH2_USB0 }, + { SYSCTL_PERIPH_WDOG0, SYSCTL_PERIPH2_WDOG0 }, + { SYSCTL_PERIPH_WDOG1, SYSCTL_PERIPH2_WDOG1 }, +}; + +//***************************************************************************** +// +// Maps a SYSCTL_PERIPH_foo identifier into its new-style SYSCTL_PERIPH2_foo +// identifier. +// +//***************************************************************************** +static unsigned long +SysCtlPeripheralMapToNew(unsigned long ulPeripheral) +{ + unsigned long ulIndex; + + // + // Loop through the table of old-style identifiers. + // + for(ulIndex = 0; ulIndex < (sizeof(g_ppulPeripheralMap) / + sizeof(g_ppulPeripheralMap[0])); ulIndex++) + { + // + // See if this peripheral matches the old-style identifier. + // + if(g_ppulPeripheralMap[ulIndex][0] == ulPeripheral) + { + // + // Return the new-style identifier that corresponds to this + // peripheral. + // + return(g_ppulPeripheralMap[ulIndex][1]); + } + } + + // + // No old-style identifier was found, so return the identifier unchanged + // (on the assumption that it is already a new-style identifier). + // + return(ulPeripheral); +} + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Stellaris device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +unsigned long +SysCtlSRAMSizeGet(void) +{ + // + // Compute the size of the SRAM. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_M) >> 8) + 0x100); +} + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Stellaris device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +unsigned long +SysCtlFlashSizeGet(void) +{ + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800); +} + +//***************************************************************************** +// +//! Determines if a pin is present. +//! +//! \param ulPin is the pin in question. +//! +//! This function determines if a particular pin is present in the device. The +//! PWM, analog comparators, ADC, and timers have a varying number of pins +//! across members of the Stellaris family; this function determines which pins +//! are present on this device. +//! +//! The \e ulPin argument must be only one of the following values: +//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, +//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, +//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, +//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, +//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, +//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, +//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, +//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, +//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, +//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, \b SYSCTL_PIN_CCP6, +//! \b SYSCTL_PIN_CCP7, \b SYSCTL_PIN_32KHZ, or \b SYSCTL_PIN_MC_FAULT0. +//! +//! \return Returns \b true if the specified pin is present and \b false if it +//! is not. +// +//***************************************************************************** +tBoolean +SysCtlPinPresent(unsigned long ulPin) +{ + // + // Check the arguments. + // + ASSERT((ulPin == SYSCTL_PIN_PWM0) || + (ulPin == SYSCTL_PIN_PWM1) || + (ulPin == SYSCTL_PIN_PWM2) || + (ulPin == SYSCTL_PIN_PWM3) || + (ulPin == SYSCTL_PIN_PWM4) || + (ulPin == SYSCTL_PIN_PWM5) || + (ulPin == SYSCTL_PIN_C0MINUS) || + (ulPin == SYSCTL_PIN_C0PLUS) || + (ulPin == SYSCTL_PIN_C0O) || + (ulPin == SYSCTL_PIN_C1MINUS) || + (ulPin == SYSCTL_PIN_C1PLUS) || + (ulPin == SYSCTL_PIN_C1O) || + (ulPin == SYSCTL_PIN_C2MINUS) || + (ulPin == SYSCTL_PIN_C2PLUS) || + (ulPin == SYSCTL_PIN_C2O) || + (ulPin == SYSCTL_PIN_MC_FAULT0) || + (ulPin == SYSCTL_PIN_ADC0) || + (ulPin == SYSCTL_PIN_ADC1) || + (ulPin == SYSCTL_PIN_ADC2) || + (ulPin == SYSCTL_PIN_ADC3) || + (ulPin == SYSCTL_PIN_ADC4) || + (ulPin == SYSCTL_PIN_ADC5) || + (ulPin == SYSCTL_PIN_ADC6) || + (ulPin == SYSCTL_PIN_ADC7) || + (ulPin == SYSCTL_PIN_CCP0) || + (ulPin == SYSCTL_PIN_CCP1) || + (ulPin == SYSCTL_PIN_CCP2) || + (ulPin == SYSCTL_PIN_CCP3) || + (ulPin == SYSCTL_PIN_CCP4) || + (ulPin == SYSCTL_PIN_CCP5) || + (ulPin == SYSCTL_PIN_32KHZ)); + + // + // Determine if this pin is present. + // + if(HWREG(SYSCTL_DC3) & ulPin) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is present in the +//! device. Each member of the Stellaris family has a different peripheral +//! set; this function determines which peripherals are present on this device. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, +//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_GPIOK, +//! \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, \b SYSCTL_PERIPH_GPION, +//! \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PLL, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5, +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +SysCtlPeripheralPresent(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_PPperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // See if this peripheral is present. + // + return(HWREGBITW(SYSCTL_PPBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff)); + } + else if(ulPeripheral == SYSCTL_PERIPH_USB0) + { + // + // USB is a special case because the DC bit is missing for USB0. + // + if(HWREG(SYSCTL_DC6) & SYSCTL_DC6_USB0_M) + { + return(true); + } + else + { + return(false); + } + } + else if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) & + SYSCTL_PERIPH_MASK(ulPeripheral)) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note The ability to check for a peripheral being ready varies based on the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine if this feature is available. +//! +//! \return Returns \b true if the specified peripheral is ready and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +SysCtlPeripheralReady(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Map the peripheral identifier to the new style identifiers. If it is + // already a new style identifier, this is a NOP. + // + ulPeripheral = SysCtlPeripheralMapToNew(ulPeripheral); + + // + // See if this peripheral is ready. + // + return(HWREGBITW(SYSCTL_PRBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff)); +} + +//***************************************************************************** +// +//! Powers on a peripheral. +//! +//! \param ulPeripheral is the peripheral to be powered on. +//! +//! This function turns on the power to a peripheral. The peripheral continues +//! to receive power even when its clock is not enabled. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note The ability to power off a peripheral varies based on the Stellaris +//! part in use. Please consult the data sheet for the part you are using to +//! determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralPowerOn(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Map the peripheral identifier to the new style identifiers. If it is + // already a new style identifier, this is a NOP. + // + ulPeripheral = SysCtlPeripheralMapToNew(ulPeripheral); + + // + // Power on this peripheral. + // + HWREGBITW(SYSCTL_PCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; +} + +//***************************************************************************** +// +//! Powers off a peripheral. +//! +//! \param ulPeripheral is the peripheral to be powered off. +//! +//! This function allows the power to a peripheral to be turned off. The +//! peripheral continues to receive power when its clock is enabled, but +//! the power is removed when its clock is disabled. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note The ability to power off a peripheral varies based on the Stellaris +//! part in use. Please consult the data sheet for the part you are using to +//! determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralPowerOff(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Map the peripheral identifier to the new style identifiers. If it is + // already a new style identifier, this is a NOP. + // + ulPeripheral = SysCtlPeripheralMapToNew(ulPeripheral); + + // + // Power off this peripheral. + // + HWREGBITW(SYSCTL_PCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; +} + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! de-asserted, returning the internal state of the peripheral to its reset +//! condition. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_SRperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Put the peripheral into the reset state. + // + HWREGBITW(SYSCTL_SRBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREGBITW(SYSCTL_SRBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ulPeripheral is the peripheral to enable. +//! +//! This function enables peripherals. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note It takes five clock cycles after the write to enable a peripheral +//! before the the peripheral is actually enabled. During this time, attempts +//! to access the peripheral result in a bus fault. Care should be taken +//! to ensure that the peripheral is not accessed during this brief time +//! period. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_RCGCperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Enable this peripheral. + // + HWREGBITW(SYSCTL_RCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + } + else + { + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ulPeripheral is the peripheral to disable. +//! +//! This function disables peripherals are disabled with this function. Once +//! disabled, they do not operate or respond to register reads/writes. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_RCGCperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Disable this peripheral. + // + HWREGBITW(SYSCTL_RCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Because the clocking configuration of the device +//! does not change, any peripheral can safely continue operating while the +//! processor is in sleep mode and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_SCGCperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Enable this peripheral in sleep mode. + // + HWREGBITW(SYSCTL_SCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + } + else + { + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral automatically resumes operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_SCGCperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Disable this peripheral in sleep mode. + // + HWREGBITW(SYSCTL_SCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Because the clocking configuration of the +//! device may change, not all peripherals can safely continue operating while +//! the processor is in sleep mode. Those that must run at a particular +//! frequency (such as a UART) do not work as expected if the clock changes. +//! It is the responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_DCGCperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Enable this peripheral in deep-sleep mode. + // + HWREGBITW(SYSCTL_DCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + } + else + { + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral automatically resumes +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_DCGCperiph registers. + // + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Disable this peripheral in deep-sleep mode. + // + HWREGBITW(SYSCTL_DCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } +} + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled, they are +//! clocked according to the configuration set by +//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), +//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralClockGating(tBoolean bEnable) +{ + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This function registers the handler to be called when a system control +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific system control interrupts must be enabled +//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The events that cause system control interrupts vary based on the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function unregisters the handler to be called when a system control +//! interrupt occurs. This function also masks off the interrupt in the +//! interrupt controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL); +} + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! This function enables the indicated system control interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntEnable(unsigned long ulInts) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ulInts; +} + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! This function disables the indicated system control interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntDisable(unsigned long ulInts) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ulInts); +} + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep it from being called again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntClear(unsigned long ulInts) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ulInts; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the system controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, +//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and +//! \b SYSCTL_INT_PLL_FAIL. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +// +//***************************************************************************** +unsigned long +SysCtlIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} + +//***************************************************************************** +// +//! Sets the output voltage of the LDO. +//! +//! \param ulVoltage is the required output voltage from the LDO. +//! +//! This function sets the output voltage of the LDO. The \e ulVoltage +//! parameter specifies the LDO voltage and must be one of the following +//! values: +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +//! +//! \note The default LDO voltage and the adjustment range varies with the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine the default voltage and range available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlLDOSet(unsigned long ulVoltage) +{ + // + // Check the arguments. + // + ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || + (ulVoltage == SYSCTL_LDO_2_30V) || + (ulVoltage == SYSCTL_LDO_2_35V) || + (ulVoltage == SYSCTL_LDO_2_40V) || + (ulVoltage == SYSCTL_LDO_2_45V) || + (ulVoltage == SYSCTL_LDO_2_50V) || + (ulVoltage == SYSCTL_LDO_2_55V) || + (ulVoltage == SYSCTL_LDO_2_60V) || + (ulVoltage == SYSCTL_LDO_2_65V) || + (ulVoltage == SYSCTL_LDO_2_70V) || + (ulVoltage == SYSCTL_LDO_2_75V)); + + // + // Set the LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOPCTL) = ulVoltage; +} + +//***************************************************************************** +// +//! Gets the output voltage of the LDO. +//! +//! This function determines the output voltage of the LDO, as specified by the +//! control register. +//! +//! \return Returns the current voltage of the LDO and is one of: +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +// +//***************************************************************************** +unsigned long +SysCtlLDOGet(void) +{ + // + // Return the LDO voltage setting. + // + return(HWREG(SYSCTL_LDOPCTL)); +} + +//***************************************************************************** +// +//! Configures the LDO failure control. +//! +//! \param ulConfig is the required LDO failure control setting; can be either +//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. +//! +//! This function allows the LDO to be configured to cause a processor reset +//! when the output voltage becomes unregulated. +//! +//! The LDO failure control is only available on Sandstorm-class devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlLDOConfigSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || + (ulConfig == SYSCTL_LDOCFG_NORST)); + + // + // Set the reset control as requested. + // + HWREG(SYSCTL_LDOARST) = ulConfig; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a software reset of the entire device. The +//! processor and all peripherals are reset and all device registers are +//! returned to their default values (with the exception of the reset cause +//! register, which maintains its current value but has the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This request causes the device to + // reset, no further code is executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep works correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function returns the reason(s) for a reset. Because the reset +//! reasons are sticky until either cleared by software or an external reset +//! (for Sandstorm-class devices) or a power-on reset (for all other classes), +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason is a logical OR of \b SYSCTL_CAUSE_LDO, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +unsigned long +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ulCauses are the reset causes to be cleared; must be a logical OR of +//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, +//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlResetCauseClear(unsigned long ulCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ulCauses); +} + +//***************************************************************************** +// +//! Configures the brown-out control. +//! +//! \param ulConfig is the desired configuration of the brown-out control. +//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or +//! \b SYSCTL_BOR_RESAMPLE. +//! \param ulDelay is the number of internal oscillator cycles to wait before +//! resampling an asserted brown-out signal. This value only has meaning when +//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. +//! +//! This function configures how the brown-out control operates. It can detect +//! a brown-out by looking at only the brown-out output, or it can wait for it +//! to be active for two consecutive samples separated by a configurable time. +//! When it detects a brown-out condition, it can either reset the device or +//! generate a processor interrupt. +//! +//! \note The availability of the resample feature is only available on +//! Sandstorm-class devices. Please consult the data sheet for the part you +//! are using to determine whether this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) +{ + // + // Check the arguments. + // + ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); + ASSERT(ulDelay < 8192); + + // + // Configure the brown-out reset control. + // + HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BORTIM_S) | ulConfig; +} + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! The loop takes 3 cycles/loop. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) || defined(DOXYGEN) +void +SysCtlDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne.n SysCtlDelay\n" + " bx lr"); +} +#endif +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +SysCtlDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne SysCtlDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +SysCtlDelay(unsigned long ulCount) +{ + subs r0, #1; + bne SysCtlDelay; + bx lr; +} +#endif +// +// For CCS implement this function in pure assembly. This prevents the TI +// compiler from doing funny things with the optimizer. +// +#if defined(ccs) + __asm(" .sect \".text:SysCtlDelay\"\n" + " .clink\n" + " .thumbfunc SysCtlDelay\n" + " .thumb\n" + " .global SysCtlDelay\n" + "SysCtlDelay:\n" + " subs r0, #1\n" + " bne.n SysCtlDelay\n" + " bx lr\n"); +#endif + +//***************************************************************************** +// +//! Sets the configuration of the main oscillator (MOSC) control. +//! +//! \param ulConfig is the required configuration of the MOSC control. +//! +//! This function configures the control of the main oscillator. The +//! \e ulConfig is specified as follows: +//! +//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that +//! detects a failure of the main oscillator (such as a loss of the clock). +//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an +//! interrupt instead of resetting the processor. +//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal connected to +//! the OSC0/OSC1 pins, allowing power consumption to be reduced. +//! +//! \note The availability of MOSC control varies based on the Stellaris part +//! in use. Please consult the data sheet for the part you are using to +//! determine whether this support is available. In addition, the capability +//! of MOSC control varies based on the Stellaris part in use. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlMOSCConfigSet(unsigned long ulConfig) +{ + // + // Configure the MOSC control. + // + HWREG(SYSCTL_MOSCCTL) = ulConfig; +} + +//***************************************************************************** +// +//! Calibrates the precision internal oscillator. +//! +//! \param ulType is the type of calibration to perform. +//! +//! This function performs a calibration of the PIOSC. There are three types +//! of calibration available; the desired calibration type as specified in +//! \e ulType is one of: +//! +//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the +//! 32-kHz clock from the hibernate module as a reference. This type is +//! only possible on parts that have a hibernate module, and then only if +//! it is enabled and the hibernate module's RTC is also enabled. +//! +//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory +//! provided calibration. +//! +//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied +//! value. The value to be used is ORed into the lower 7-bits of this value, +//! with 0x40 being the ``nominal'' value (in other words, if everything were +//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 +//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC. +//! +//! \return Returns 1 if the calibration was successful and 0 if it failed. +// +//***************************************************************************** +unsigned long +SysCtlPIOSCCalibrate(unsigned long ulType) +{ + // + // Perform the requested calibration. If performing user calibration, the + // UTEN bit must be set with one write, then the UT field in a second + // write, and the UPDATE bit in a final write. For other calibration + // types, a single write to set UPDATE or CAL is all that is required. + // + if(ulType & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE)) + { + HWREG(SYSCTL_PIOSCCAL) = ulType & SYSCTL_PIOSCCAL_UTEN; + HWREG(SYSCTL_PIOSCCAL) = + ulType & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M); + } + HWREG(SYSCTL_PIOSCCAL) = ulType; + + // + // See if an automatic calibration was requested. + // + if(ulType & SYSCTL_PIOSCCAL_CAL) + { + // + // Wait for the automatic calibration to complete. + // + while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0) + { + } + + // + // If the automatic calibration failed, return an error. + // + if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) != + SYSCTL_PIOSCSTAT_CRPASS) + { + return(0); + } + } + + // + // The calibration was successful. + // + return(1); +} + unsigned long ulSysDiv, ulOsc, ulOscSelect; + tBoolean bNewPLL; + + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ulConfig is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e ulConfig parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... +//! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16 +//! are valid on Sandstorm-class devices. Half-dividers, such as +//! \b SYSCTL_SYSDIV_2_5 and \b SYSCTL_SYSDIV_3_5. are available on Tempest-, +//! Firestorm-, and Blizzard-class devices. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_1MHZ, \b SYSCTL_XTAL_1_84MHZ, \b SYSCTL_XTAL_2MHZ, +//! \b SYSCTL_XTAL_2_45MHZ, \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, +//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, +//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, +//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, +//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, +//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. +//! Values below \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in +//! operation on Sandstorm-, Fury-, Dustdevil-, Tempest-, and Firestorm-class. +//! devices. Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in +//! operation on Blizzard-class devices. Values below \b SYSCTL_XTAL_4MHZ +//! are never valid on Blizzard-class devices. On Sandstorm- and Fury-class +//! devices, values above \b SYSCTL_XTAL_8_19MHZ are not valid. On Dustdevil-, +//! Tempest-, and Firestorm-class devices, values above \b SYSCTL_XTAL_16_3MHZ +//! are not valid. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, +//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. On Sandstorm-class devices, +//! \b SYSCTL_OSC_INT30 and \b SYSCTL_OSC_EXT32 are not valid. +//! \b SYSCTL_OSC_EXT32 is only available on devices with the hibernate module, +//! and then only when the hibernate module has been enabled. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device is prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (that is, via +//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function delays until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClockSet(unsigned long ulConfig) +{ + unsigned long ulDelay, ulRCC, ulRCC2; + + // + // See if this is a Sandstorm-class device and clocking features from newer + // devices were requested. + // + if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2)) + { + // + // Return without changing the clocking because the requested + // configuration can not be achieved. + // + return; + } + + // + // Get the current value of the RCC and RCC2 registers. If using a + // Sandstorm-class device, the RCC2 register reads back as zero and the + // writes to it from within this function are ignored. + // + ulRCC = HWREG(SYSCTL_RCC); + ulRCC2 = HWREG(SYSCTL_RCC2); + + // + // Bypass the PLL and system clock dividers for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USESYSDIV); + ulRCC2 |= SYSCTL_RCC2_BYPASS2; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + + // + // See if either oscillator needs to be enabled. + // + if(((ulRCC & SYSCTL_RCC_IOSCDIS) && !(ulConfig & SYSCTL_RCC_IOSCDIS)) || + ((ulRCC & SYSCTL_RCC_MOSCDIS) && !(ulConfig & SYSCTL_RCC_MOSCDIS))) + { + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | + (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Wait for a bit, giving the oscillator time to stabilize. The number + // of iterations is adjusted based on the current clock source; a + // smaller number of iterations is required for slower clock rates. + // + if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && + (((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) || + ((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_32))) || + (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && + ((ulRCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30))) + { + // + // Delay for 4096 iterations. + // + SysCtlDelay(4096); + } + else + { + // + // Delay for 524,288 iterations. + // + SysCtlDelay(524288); + } + } + + // + // Set the new crystal value and oscillator source. Because the OSCSRC2 + // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a + // special encoding within ulConfig to avoid the overlap. + // + ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); + ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M); + ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M); + ulRCC2 |= (ulConfig & 0x00000008) << 3; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. + // + SysCtlDelay(16); + + // + // Set the PLL configuration. + // + ulRCC &= ~(SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); + ulRCC |= ulConfig & (SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); + ulRCC2 &= ~(SYSCTL_RCC2_PWRDN2); + ulRCC2 |= ulConfig & SYSCTL_RCC2_PWRDN2; + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + // + // Write the new RCC value. + // + if(ulRCC2 & SYSCTL_RCC2_USERCC2) + { + HWREG(SYSCTL_RCC2) = ulRCC2; + HWREG(SYSCTL_RCC) = ulRCC; + } + else + { + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + } + + // + // Set the requested system divider and disable the appropriate + // oscillators. This value is not written immediately. + // + ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | + SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | + SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M); + ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M; + if(ulConfig & SYSCTL_RCC2_DIV400) + { + ulRCC |= SYSCTL_RCC_USESYSDIV; + ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV); + ulRCC2 |= ulConfig & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB); + } + else + { + ulRCC2 &= ~(SYSCTL_RCC2_DIV400); + } + + // + // See if the PLL output is being used to clock the system. + // + if(!(ulConfig & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ulDelay = 32768; ulDelay > 0; ulDelay--) + { + if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + { + break; + } + } + + // + // Enable use of the PLL. + // + ulRCC &= ~(SYSCTL_RCC_BYPASS); + ulRCC2 &= ~(SYSCTL_RCC2_BYPASS2); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + + // + // Delay for a little bit so that the system divider takes effect. + // + SysCtlDelay(16); +} + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock, which is +//! also the clock rate of the peripheral modules (with the exception of +//! PWM, which has its own clock divider; other peripherals may have different +//! clocking, see the device data sheet for details). +//! +//! \note This cannot return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the latter case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +unsigned long +SysCtlClockGet(void) +{ + unsigned long ulRCC, ulRCC2, ulPLL, ulClk; + unsigned long ulPLL1; + + // + // Read RCC and RCC2. For Sandstorm-class devices (which do not have + // RCC2), the RCC2 read returns 0, indicating that RCC2 is + // disabled (because the SYSCTL_RCC2_USERCC2 bit is clear). + // + ulRCC = HWREG(SYSCTL_RCC); + ulRCC2 = HWREG(SYSCTL_RCC2); + + // + // Get the base clock rate. + // + switch((ulRCC2 & SYSCTL_RCC2_USERCC2) ? + (ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) : + (ulRCC & SYSCTL_RCC_OSCSRC_M)) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ulClk = g_pulXtals[(ulRCC & SYSCTL_RCC_XTAL_M) >> + SYSCTL_RCC_XTAL_S]; + break; + } + + // + // The internal oscillator is the source clock. + // + case SYSCTL_RCC_OSCSRC_INT: + { + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // The internal oscillator on a Sandstorm-class device is + // 15 MHz +/- 50%. + // + ulClk = 15000000; + } + else if((CLASS_IS_FURY && REVISION_IS_A2) || + (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) + { + // + // The internal oscillator on a rev A2 Fury-class device and a + // Dustdevil-class device is 12 MHz +/- 30%. + // + ulClk = 12000000; + } + else + { + // + // The internal oscillator on all other devices is 16 MHz. + // + ulClk = 16000000; + } + break; + } + + // + // The internal oscillator divided by four is the source clock. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // The internal oscillator on a Sandstorm-class device is + // 15 MHz +/- 50%. + // + ulClk = 15000000 / 4; + } + else if((CLASS_IS_FURY && REVISION_IS_A2) || + (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) + { + // + // The internal oscillator on a rev A2 Fury-class device and a + // Dustdevil-class device is 12 MHz +/- 30%. + // + ulClk = 12000000 / 4; + } + else + { + // + // The internal oscillator on a Tempest-class device is 16 MHz. + // + ulClk = 16000000 / 4; + } + break; + } + + // + // The internal 30-KHz oscillator is the source clock. + // + case SYSCTL_RCC_OSCSRC_30: + { + // + // The internal 30-KHz oscillator has an accuracy of +/- 30%. + // + ulClk = 30000; + break; + } + + // + // The 4.194304-MHz clock from the hibernate module is the clock + // source. + // + case SYSCTL_RCC2_OSCSRC2_419: + { + ulClk = 4194304; + break; + } + + // + // The 32.768-KHz clock from the hibernate module is the source clock. + // + case SYSCTL_RCC2_OSCSRC2_32: + { + ulClk = 32768; + break; + } + + // + // An unknown setting, so return a zero clock (that is, an unknown + // clock rate). + // + default: + { + return(0); + } + } + + // + // See if the PLL is being used. + // + if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) || + (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS))) + { + // + // See if this is a Blizzard-class device. + // + if(CLASS_IS_BLIZZARD) + { + // + // Read the two PLL frequency registers. The formula for a + // Blizzard-class device is "(xtal * m) / ((q + 1) * (n + 1))". + // + ulPLL = HWREG(SYSCTL_PLLFREQ0); + ulPLL1 = HWREG(SYSCTL_PLLFREQ1); + + // + // Divide the input clock by the dividers. + // + ulClk /= ((((ulPLL1 & SYSCTL_PLLFREQ1_Q_M) >> + SYSCTL_PLLFREQ1_Q_S) + 1) * + (((ulPLL1 & SYSCTL_PLLFREQ1_N_M) >> + SYSCTL_PLLFREQ1_N_S) + 1) * 2); + + // + // Multiply the clock by the multiplier, which is split into an + // integer part and a fractional part. + // + ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLFREQ0_MINT_M) >> + SYSCTL_PLLFREQ0_MINT_S)) + + ((ulClk * ((ulPLL & SYSCTL_PLLFREQ0_MFRAC_M) >> + SYSCTL_PLLFREQ0_MFRAC_S)) >> 10)); + } + + // + // Older device classes used a different PLL. + // + else + { + // + // Get the PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // Compute the PLL output frequency based on its input + // frequency. The formula for a Sandstorm-class devices is + // "(xtal * (f + 2)) / (r + 2)". + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 2)); + } + else + { + // + // Compute the PLL output frequency based on its input + // frequency. The formula for a Fury-class device is + // "(xtal * f) / ((r + 1) * 2)". + // + ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S)) / + ((((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 1) * 2)); + } + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } + } + + // + // Force the system divider to be enabled. It is always used when + // using the PLL, but in some cases it does not read as being enabled. + // + ulRCC |= SYSCTL_RCC_USESYSDIV; + } + + // + // See if the system divider is being used. + // + if(ulRCC & SYSCTL_RCC_USESYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + if(ulRCC2 & SYSCTL_RCC2_USERCC2) + { + if((ulRCC2 & SYSCTL_RCC2_DIV400) && + (((ulRCC2 & SYSCTL_RCC2_USERCC2) && + !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) || + (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && + !(ulRCC & SYSCTL_RCC_BYPASS)))) + + { + ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M | + SYSCTL_RCC2_SYSDIV2LSB)) >> + (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1)); + } + else + { + ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >> + SYSCTL_RCC2_SYSDIV2_S) + 1); + } + } + else + { + ulClk /= (((ulRCC & SYSCTL_RCC_SYSDIV_M) >> SYSCTL_RCC_SYSDIV_S) + + 1); + } + } + + // + // Return the computed clock rate. + // + return(ulClk); +} + +//***************************************************************************** +// +//! Sets the clocking of the device while in deep-sleep mode. +//! +//! \param ulConfig is the required configuration of the device clocking while +//! in deep-sleep mode. +//! +//! This function configures the clocking of the device while in deep-sleep +//! mode. The oscillator to be used and the system clock divider are +//! configured with this function. +//! +//! The \e ulConfig parameter is the logical OR of the following values: +//! +//! The system clock divider is chosen from one of the following values: +//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ... +//! \b SYSCTL_DSLP_DIV_64. +//! +//! The oscillator source is chosen from one of the following values: +//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, +//! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on +//! devices with the hibernation module, and then only when the hibernation +//! module has been enabled. +//! +//! The precision internal oscillator can be powered down in deep-sleep mode by +//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is +//! not powered down if it is required for operation while in deep-sleep +//! (based on other configuration settings.) +//! +//! \note The availability of deep-sleep clocking configuration varies with the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleepClockSet(unsigned long ulConfig) +{ + // + // Set the deep-sleep clock configuration. + // + HWREG(SYSCTL_DSLPCLKCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ulConfig is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function configures the rate of the clock provided to the PWM module +//! as a ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPWMClockSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_PWMDIV_1) || + (ulConfig == SYSCTL_PWMDIV_2) || + (ulConfig == SYSCTL_PWMDIV_4) || + (ulConfig == SYSCTL_PWMDIV_8) || + (ulConfig == SYSCTL_PWMDIV_16) || + (ulConfig == SYSCTL_PWMDIV_32) || + (ulConfig == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM0); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) | + ulConfig); +} + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return Returns the current PWM clock configuration; is one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +// +//***************************************************************************** +unsigned long +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM0); + + // + // Return the current PWM clock configuration. Make sure that + // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled. + // + if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV)) + { + // + // The divider is not active so reflect this in the value we return. + // + return(SYSCTL_PWMDIV_1); + } + else + { + // + // The divider is active so directly return the masked register value. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)); + } +} + +//***************************************************************************** +// +//! Sets the sample rate of the ADC. +//! +//! \param ulSpeed is the desired sample rate of the ADC; must be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +//! +//! This function configures the rate at which the ADC samples are captured by +//! the ADC block. The sampling speed may be limited by the hardware, so the +//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() +//! returns the actual speed in use. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlADCSpeedSet(unsigned long ulSpeed) +{ + // + // Check the arguments. + // + ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || + (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); + + // + // Set the ADC speed in run and sleep mode. + // + HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) | + ulSpeed); + HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) | + ulSpeed); +} + +//***************************************************************************** +// +//! Gets the sample rate of the ADC. +//! +//! This function gets the current sample rate of the ADC. +//! +//! \return Returns the current ADC sample rate; is one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +// +//***************************************************************************** +unsigned long +SysCtlADCSpeedGet(void) +{ + // + // Return the current ADC speed. + // + return(HWREG(SYSCTL_RCGC0) & SYSCTL_RCGC0_ADCSPD_M); +} + +//***************************************************************************** +// +//! Configures the internal oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the internal oscillator +//! verification timer should be enabled. +//! +//! This function allows the internal oscillator verification timer to be +//! enabled or disabled. When enabled, an interrupt is generated if the +//! internal oscillator ceases to operate. +//! +//! The internal oscillator verification timer is only available on +//! Sandstorm-class devices. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the main oscillator verifies the +//! internal oscillator. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the internal oscillator verification timer as + // requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); + } +} + +//***************************************************************************** +// +//! Configures the main oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the main oscillator +//! verification timer should be enabled. +//! +//! This function allows the main oscillator verification timer to be enabled +//! or disabled. When enabled, an interrupt is generated if the main +//! oscillator ceases to operate. +//! +//! The main oscillator verification timer is only available on +//! Sandstorm-class devices. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the internal oscillator verifies the +//! main oscillator. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlMOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the main oscillator verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); + } +} + +//***************************************************************************** +// +//! Configures the PLL verification timer. +//! +//! \param bEnable is a boolean that is \b true if the PLL verification timer +//! should be enabled. +//! +//! This function allows the PLL verification timer to be enabled or disabled. +//! When enabled, an interrupt is generated if the PLL ceases to operate. +//! +//! The PLL verification timer is only available on Sandstorm-class devices. +//! +//! \note The main oscillator must be enabled for this verification timer to +//! operate as it is used to check the PLL. Also, the verification timer +//! should be disabled while the PLL is being reconfigured via +//! SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPLLVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the PLL verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); + } +} + +//***************************************************************************** +// +//! Clears the clock verification status. +//! +//! This function clears the status of the clock verification timers, allowing +//! them to assert another failure if detected. +//! +//! The clock verification timers are only available on Sandstorm-class +//! devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClkVerificationClear(void) +{ + // + // Clear the clock verification. + // + HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_VERCLR; + + // + // The bit does not self-reset, so clear it. + // + HWREG(SYSCTL_CLKVCLR) = 0; +} + +//***************************************************************************** +// +//! Enables a GPIO peripheral for access from the AHB. +//! +//! \param ulGPIOPeripheral is the GPIO peripheral to enable. +//! +//! This function is used to enable the specified GPIO peripheral to be +//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced +//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access, +//! the \b _AHB_BASE form of the base address should be used for GPIO +//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base +//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead. +//! +//! The \e ulGPIOPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); + + // + // Enable this GPIO for AHB access. + // + HWREG(SYSCTL_GPIOHBCTL) |= ulGPIOPeripheral & 0xFFFF; +} + +//***************************************************************************** +// +//! Disables a GPIO peripheral for access from the AHB. +//! +//! \param ulGPIOPeripheral is the GPIO peripheral to disable. +//! +//! This function disables the specified GPIO peripheral for access from the +//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed +//! from the legacy Advanced Peripheral Bus (APB). +//! +//! The \b ulGPIOPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); + + // + // Disable this GPIO for AHB access. + // + HWREG(SYSCTL_GPIOHBCTL) &= ~(ulGPIOPeripheral & 0xFFFF); +} + +//***************************************************************************** +// +//! Powers up the USB PLL. +//! +//! This function enables the USB controller's PLL, which is used by it's +//! physical layer. This call is necessary before connecting to any external +//! devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLEnable(void) +{ + // + // Turn on the USB PLL. + // + HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN; +} + +//***************************************************************************** +// +//! Powers down the USB PLL. +//! +//! This function disables the USB controller's PLL, which is used by it's +//! physical layer. The USB registers are still accessible, but the physical +//! layer no longer functions. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLDisable(void) +{ + // + // Turn off the USB PLL. + // + HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; +} + +//***************************************************************************** +// +//! Sets the MCLK frequency provided to the I2S module. +//! +//! \param ulInputClock is the input clock to the MCLK divider. If this value +//! is zero, the value is computed from the current PLL configuration. +//! \param ulMClk is the desired MCLK frequency. If this value is zero, MCLK +//! output is disabled. +//! +//! This function configures the dividers to provide MCLK to the I2S module. A +//! MCLK divider is chosen that produces the MCLK frequency that is the closest +//! possible to the requested frequency, which may be above or below the +//! requested frequency. +//! +//! The actual MCLK frequency is returned. It is the responsibility of the +//! application to determine if the selected MCLK is acceptable; in general the +//! human ear can not discern the frequency difference if it is within 0.3% of +//! the desired frequency (although there is a very small percentage of the +//! population that can discern lower frequency deviations). +//! +//! \return Returns the actual MCLK frequency. +// +//***************************************************************************** +unsigned long +SysCtlI2SMClkSet(unsigned long ulInputClock, unsigned long ulMClk) +{ + unsigned long ulDivInt, ulDivFrac, ulPLL; + + // + // See if the I2S MCLK should be disabled. + // + if(ulMClk == 0) + { + // + // Disable the I2S MCLK and return. + // + HWREG(SYSCTL_I2SMCLKCFG) = 0; + return(0); + } + + // + // See if the input clock was specified. + // + if(ulInputClock == 0) + { + // + // The input clock was not specified, so compute the output frequency + // of the PLL. Get the current PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // Get the frequency of the crystal in use. + // + ulInputClock = g_pulXtals[(HWREG(SYSCTL_RCC) & SYSCTL_RCC_XTAL_M) >> + SYSCTL_RCC_XTAL_S]; + + // + // Calculate the PLL output frequency. + // + ulInputClock = ((ulInputClock * ((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S)) / + ((((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 1))); + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulInputClock /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulInputClock /= 4; + } + } + + // + // Verify that the requested MCLK frequency is attainable. + // + ASSERT(ulMClk < ulInputClock); + + // + // Add a rounding factor to the input clock, so that the MCLK frequency + // that is closest to the desire value is selected. + // + ulInputClock += (ulMClk / 32) - 1; + + // + // Compute the integer portion of the MCLK divider. + // + ulDivInt = ulInputClock / ulMClk; + + // + // If the divisor is too large, then simply use the maximum divisor. + // + if(CLASS_IS_TEMPEST && REVISION_IS_B1 && (ulDivInt > 255)) + { + ulDivInt = 255; + ulDivFrac = 15; + } + else if(ulDivInt > 1023) + { + ulDivInt = 1023; + ulDivFrac = 15; + } + else + { + // + // Compute the fractional portion of the MCLK divider. + // + ulDivFrac = ((ulInputClock - (ulDivInt * ulMClk)) * 16) / ulMClk; + } + + // + // Set the divisor for the TX and RX MCLK generators and enable the clocks. + // + HWREG(SYSCTL_I2SMCLKCFG) = (SYSCTL_I2SMCLKCFG_RXEN | + (ulDivInt << SYSCTL_I2SMCLKCFG_RXI_S) | + (ulDivFrac << SYSCTL_I2SMCLKCFG_RXF_S) | + SYSCTL_I2SMCLKCFG_TXEN | + (ulDivInt << SYSCTL_I2SMCLKCFG_TXI_S) | + (ulDivFrac << SYSCTL_I2SMCLKCFG_TXF_S)); + + // + // Return the actual MCLK frequency. + // + ulInputClock -= (ulMClk / 32) - 1; + ulDivInt = (ulDivInt * 16) + ulDivFrac; + ulMClk = (ulInputClock / ulDivInt) * 16; + ulMClk += ((ulInputClock - ((ulMClk / 16) * ulDivInt)) * 16) / ulDivInt; + return(ulMClk); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/sysctl.h b/driverlib/sysctl.h new file mode 100644 index 0000000..97efb2e --- /dev/null +++ b/driverlib/sysctl.h @@ -0,0 +1,642 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#ifndef DEPRECATED +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#endif +#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0 +#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module +#ifndef DEPRECATED +#define SYSCTL_PERIPH_ADC 0x00100001 // ADC +#endif +#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0 +#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#endif +#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM +#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 +#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 +#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1 +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#endif +#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#endif +#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#endif +#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 +#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 +#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 +#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0 +#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J +#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA +#define SYSCTL_PERIPH_USB0 0x20100001 // USB0 +#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet +#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2 +#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0 +#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0 +#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0 +#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0 +#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 +#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1 +#define SYSCTL_PERIPH2_HIBERNATE \ + 0xf0001400 // Hibernate + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin +#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlDelay(unsigned long ulCount); +extern void SysCtlMOSCConfigSet(unsigned long ulConfig); +extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(unsigned long ulConfig); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); +extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock, + unsigned long ulMClk); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/driverlib/sysexc.c b/driverlib/sysexc.c new file mode 100644 index 0000000..3e983eb --- /dev/null +++ b/driverlib/sysexc.c @@ -0,0 +1,256 @@ +//***************************************************************************** +// +// sysexc.c - Routines for the System Exception Module. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysexc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_sysexc.h" +#include "inc/hw_types.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Registers an interrupt handler for the system exception interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! exception interrupt occurs. +//! +//! This function places the address of the system exception interrupt handler +//! into the interrupt vector table in SRAM. This function also enables the +//! global interrupt in the interrupt controller; specific system exception +//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_SYSEXC, pfnHandler); + + // + // Enable the system exception interrupt. + // + IntEnable(INT_SYSEXC); +} + +//***************************************************************************** +// +//! Unregisters the system exception interrupt handler. +//! +//! This function removes the system exception interrupt handler from the +//! vector table in SRAM. This function also masks off the system exception +//! interrupt in the interrupt controller so that the interrupt handler is no +//! longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntUnregister(void) +{ + // + // Disable the system exception interrupt. + // + IntDisable(INT_SYSEXC); + + // + // Unregister the system exception interrupt handler. + // + IntUnregister(INT_SYSEXC); +} + +//***************************************************************************** +// +//! Enables individual system exception interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated system exception interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSEXC_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual system exception interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated system exception interrupt sources. +//! Only sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSEXC_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current system exception interrupt status. +//! +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the system exception interrupt status. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current system exception interrupt status, enumerated +//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC, +//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and +//! \b SYSEXC_INT_FP_IDC. +// +//***************************************************************************** +unsigned long +SysExcIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSEXC_MIS)); + } + else + { + return(HWREG(SYSEXC_RIS)); + } +} + +//***************************************************************************** +// +//! Clears system exception interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified system exception interrupt sources, so +//! that they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being recognized again immediately upon +//! exit. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntClear(unsigned long ulIntFlags) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSEXC_IC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/sysexc.h b/driverlib/sysexc.h new file mode 100644 index 0000000..05b6263 --- /dev/null +++ b/driverlib/sysexc.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// sysexc.h - Prototypes for the System Exception Module routines. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSEXC_H__ +#define __SYSEXC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and +// SysExcIntClear as the ulIntFlags parameter, and returned from +// SysExcIntStatus. +// +//***************************************************************************** +#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt +#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt +#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt +#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt +#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int +#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void SysExcIntRegister(void (*pfnHandler)(void)); +extern void SysExcIntUnregister(void); +extern void SysExcIntEnable(unsigned long ulIntFlags); +extern void SysExcIntDisable(unsigned long ulIntFlags); +extern unsigned long SysExcIntStatus(tBoolean bMasked); +extern void SysExcIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSEXC_H__ diff --git a/driverlib/systick.c b/driverlib/systick.c new file mode 100644 index 0000000..d4e7548 --- /dev/null +++ b/driverlib/systick.c @@ -0,0 +1,275 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This function starts the SysTick counter. If an interrupt handler has been +//! registered, it is called when the SysTick counter rolls over. +//! +//! \note Calling this function causes the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to SysTickPeriodSet(). If +//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be +//! written to force the reload. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the supplied period on the next +//! clock. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This function stops the SysTick counter. If an interrupt handler has been +//! registered, it is not called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This function registers the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function unregisters the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function enables the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler is not required to clear the SysTick +//! interrupt source because it is cleared automatically by the NVIC when the +//! interrupt handler is called. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function disables the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter and must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the \e ulPeriod supplied here on +//! the next clock after SysTick is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter, which is +//! a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/systick.h b/driverlib/systick.h new file mode 100644 index 0000000..e53751a --- /dev/null +++ b/driverlib/systick.h @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/driverlib/timer.c b/driverlib/timer.c new file mode 100644 index 0000000..039024f --- /dev/null +++ b/driverlib/timer.c @@ -0,0 +1,1549 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_timer.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/timer.h" + +//***************************************************************************** +// +// A mapping of timer base address to interrupt number. +// +//***************************************************************************** +static const unsigned long g_ppulTimerIntMap[][2] = +{ + { TIMER0_BASE, INT_TIMER0A }, + { TIMER1_BASE, INT_TIMER1A }, + { TIMER2_BASE, INT_TIMER2A }, + { TIMER3_BASE, INT_TIMER3A }, + { TIMER4_BASE, INT_TIMER4A }, + { TIMER5_BASE, INT_TIMER5A }, + { WTIMER0_BASE, INT_WTIMER0A }, + { WTIMER1_BASE, INT_WTIMER1A }, + { WTIMER2_BASE, INT_WTIMER2A }, + { WTIMER3_BASE, INT_WTIMER3A }, + { WTIMER4_BASE, INT_WTIMER4A }, + { WTIMER5_BASE, INT_WTIMER5A }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a timer base address. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function determines if a timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +TimerBaseValid(unsigned long ulBase) +{ + return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE) || + (ulBase == TIMER4_BASE) || (ulBase == TIMER5_BASE) || + (ulBase == WTIMER0_BASE) || (ulBase == WTIMER1_BASE) || + (ulBase == WTIMER2_BASE) || (ulBase == WTIMER3_BASE) || + (ulBase == WTIMER4_BASE) || (ulBase == WTIMER5_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the timer interrupt number. +//! +//! \param ulBase is the base address of the timer module. +//! +//! Given a timer base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a timer interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +TimerIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps timer base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulTimerIntMap) / + sizeof(g_ppulTimerIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulTimerIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulTimerIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function disables operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured and is left in the disabled +//! state. The timer can be configured to be a single full-width timer +//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the +//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ulConfig +//! parameter. +//! +//! The configuration is specified in \e ulConfig as one of the following +//! values: +//! +//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer +//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer +//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_RTC - Full-width real time clock timer +//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers +//! +//! When configured for a pair of half-width timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer +//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer +//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture +//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts +//! up instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture +//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PWM - Half-width PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulConfig == TIMER_CFG_ONE_SHOT) || + (ulConfig == TIMER_CFG_ONE_SHOT_UP) || + (ulConfig == TIMER_CFG_PERIODIC) || + (ulConfig == TIMER_CFG_PERIODIC_UP) || + (ulConfig == TIMER_CFG_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = (ulConfig & 255) | TIMER_TAMR_TAPWMIE; + HWREG(ulBase + TIMER_O_TBMR) = + ((ulConfig >> 8) & 255) | TIMER_TBMR_TBPWMIE; +} + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function configures the PWM output level for the specified timer. If +//! the \e bInvert parameter is \b true, then the timer's output is made active +//! low; otherwise, it is made active high. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Enables or disables the ADC trigger output. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired ADC trigger state. +//! +//! This function controls the ADC trigger output for the specified timer. If +//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the trigger output as requested. + // Set the ADC trigger output as requested. + // + ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ulBase + TIMER_O_CTL) = (bEnable ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulTimer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M; + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) | + (ulEvent & ulTimer)); +} + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Controls the wait on trigger handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bWait specifies if the timer should wait for a trigger input. +//! +//! This function controls whether or not a timer waits for a trigger input to +//! start counting. When enabled, the previous timer in the trigger chain must +//! count to its timeout in order for this timer to start counting. Refer to +//! the part's data sheet for a description of the trigger chain. +//! +//! \note This functionality is not available on all parts. This function +//! should not be used for Timer 0A or Wide Timer 0A. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bWait) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the wait on trigger mode for timer A. + // + if((ulTimer & TIMER_A) != 0) + { + if(bWait) + { + HWREG(ulBase + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT; + } + else + { + HWREG(ulBase + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT); + } + } + + // + // Set the wait on trigger mode for timer B. + // + if((ulTimer & TIMER_B) != 0) + { + if(bWait) + { + HWREG(ulBase + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT; + } + else + { + HWREG(ulBase + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT); + } + } +} + +//***************************************************************************** +// +//! Enable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this function does nothing. +//! +//! \return None. +// +//***************************************************************************** +void +TimerRTCEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Enable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} + +//***************************************************************************** +// +//! Disable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerRTCDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value which must be between 0 and 255 +//! (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) for +//! 32/64-bit timers. +//! +//! This function configures the value of the input clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. The prescaler provides the least +//! significant bits when counting down in periodic and one-shot modes; in all +//! other modes, the prescaler provides the most significant bits. +//! +//! \note The availability of the prescaler varies with the Stellaris part and +//! timer mode in use. Please consult the datasheet for the part you are using +//! to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in half-width mode and is used to extend the range +//! of the half-width timer modes. The prescaler provides the least significant +//! bits when counting down in periodic and one-shot modes; in all other modes, +//! the prescaler provides the most significant bits. +//! +//! \note The availability of the prescaler varies with the Stellaris part and +//! timer mode in use. Please consult the datasheet for the part you are using +//! to determine whether this support is available. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} + +//***************************************************************************** +// +//! Set the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale match value which must be between 0 +//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 +//! (inclusive) for 32/64-bit timers. +//! +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. +//! +//! \note The availability of the prescaler match varies with the Stellaris +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescale match if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPMR) = ulValue; + } + + // + // Set the timer B prescale match if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPMR) = ulValue; + } +} + +//***************************************************************************** +// +//! Get the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. +//! +//! \note The availability of the prescaler match varies with the Stellaris +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +unsigned long +TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : + HWREG(ulBase + TIMER_O_TBPMR)); +} + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for full-width operation. +//! \param ulValue is the load value. +//! +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerLoadSet64() for full-width modes of 32/64-bit timers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerLoadGet64() for full-width modes of 32/64-bit timers. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} + +//***************************************************************************** +// +//! Sets the timer load value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! \param ullValue is the load value. +//! +//! This function configures the timer load value for a 64-bit timer; if the +//! timer is running, then the value is immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Set the timer load value. The upper 32-bits must be written before the + // lower 32-bits in order to adhere to the hardware interlocks on the + // 64-bit value. + // + HWREG(ulBase + TIMER_O_TBILR) = ullValue >> 32; + HWREG(ulBase + TIMER_O_TAILR) = ullValue & 0xffffffff; +} + +//***************************************************************************** +// +//! Gets the timer load value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function gets the currently programmed interval load value for the +//! specified 64-bit timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +unsigned long long +TimerLoadGet64(unsigned long ulBase) +{ + unsigned long ulHigh1, ulHigh2, ulLow; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Read the 64-bit load value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ulHigh1 = HWREG(ulBase + TIMER_O_TBILR); + ulLow = HWREG(ulBase + TIMER_O_TAILR); + ulHigh2 = HWREG(ulBase + TIMER_O_TBILR); + } + while(ulHigh1 != ulHigh2); + + // + // Return the load value. + // + return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow); +} + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerValueGet64() for full-width modes of 32/64-bit timers. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : + HWREG(ulBase + TIMER_O_TBR)); +} + +//***************************************************************************** +// +//! Gets the current 64-bit timer value. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +unsigned long long +TimerValueGet64(unsigned long ulBase) +{ + unsigned long ulHigh1, ulHigh2, ulLow; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Read the 64-bit timer value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ulHigh1 = HWREG(ulBase + TIMER_O_TBR); + ulLow = HWREG(ulBase + TIMER_O_TAR); + ulHigh2 = HWREG(ulBase + TIMER_O_TBR); + } + while(ulHigh1 != ulHigh2); + + // + // Return the timer value. + // + return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow); +} + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for full-width operation. +//! \param ulValue is the match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. On some +//! Stellaris devices, match interrupts can also be generated in periodic and +//! one-shot modes. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerMatchSet64() for full-width modes of 32/64-bit timers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerMatchGet64() for full-width modes of 32/64-bit timers. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! Sets the timer match value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! \param ullValue is the match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Set the timer match value. The upper 32-bits must be written before the + // lower 32-bits in order to adhere to the hardware interlocks on the + // 64-bit value. + // + HWREG(ulBase + TIMER_O_TBMATCHR) = ullValue >> 32; + HWREG(ulBase + TIMER_O_TAMATCHR) = ullValue & 0xffffffff; +} + +//***************************************************************************** +// +//! Gets the timer match value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +unsigned long long +TimerMatchGet64(unsigned long ulBase) +{ + unsigned long ulHigh1, ulHigh2, ulLow; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Read the 64-bit match value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ulHigh1 = HWREG(ulBase + TIMER_O_TBMATCHR); + ulLow = HWREG(ulBase + TIMER_O_TAMATCHR); + ulHigh2 = HWREG(ulBase + TIMER_O_TBMATCHR); + } + while(ulHigh1 != ulHigh2); + + // + // Return the match value. + // + return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This function registers the handler to be called when a timer interrupt +//! occurs. In addition, this function enables the global interrupt in the +//! interrupt controller; specific timer interrupts must be enabled via +//! TimerIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = TimerIntNumberGet(ulBase); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = TimerIntNumberGet(ulBase); + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b TIMER_CAPB_EVENT - Capture B event interrupt +//! - \b TIMER_CAPB_MATCH - Capture B match interrupt +//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - \b TIMER_RTC_MATCH - RTC interrupt mask +//! - \b TIMER_CAPA_EVENT - Capture A event interrupt +//! - \b TIMER_CAPA_MATCH - Capture A match interrupt +//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Synchronizes the counters in a set of timers. +//! +//! \param ulBase is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b TIMER0_BASE). +//! \param ulTimers is the set of timers to synchronize. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! The \e ulTimers parameter is the logical OR of any of the following +//! defines: +//! +//! - \b TIMER_0A_SYNC +//! - \b TIMER_0B_SYNC +//! - \b TIMER_1A_SYNC +//! - \b TIMER_1B_SYNC +//! - \b TIMER_2A_SYNC +//! - \b TIMER_2B_SYNC +//! - \b TIMER_3A_SYNC +//! - \b TIMER_3B_SYNC +//! - \b TIMER_4A_SYNC +//! - \b TIMER_4B_SYNC +//! - \b TIMER_5A_SYNC +//! - \b TIMER_5B_SYNC +//! - \b WTIMER_0A_SYNC +//! - \b WTIMER_0B_SYNC +//! - \b WTIMER_1A_SYNC +//! - \b WTIMER_1B_SYNC +//! - \b WTIMER_2A_SYNC +//! - \b WTIMER_2B_SYNC +//! - \b WTIMER_3A_SYNC +//! - \b WTIMER_3B_SYNC +//! - \b WTIMER_4A_SYNC +//! - \b WTIMER_4B_SYNC +//! - \b WTIMER_5A_SYNC +//! - \b WTIMER_5B_SYNC +//! +//! \note This functionality is not available on all parts. +//! +//! \return None. +// +//***************************************************************************** +void +TimerSynchronize(unsigned long ulBase, unsigned long ulTimers) +{ + // + // Check the arguments. + // + ASSERT(ulBase == TIMER0_BASE); + + // + // Synchronize the specified timers. + // + HWREG(ulBase + TIMER_O_SYNC) = ulTimers; +} + +//***************************************************************************** +// +// Puts the timer into its reset state. +// +// \param ulBase is the base address of the timer module. +// +// This function disables the specified timer, and all its interrupts are +// disabled, cleared, and unregistered. Then the timer registers are set to +// their reset value. +// +// \return None. +// +//***************************************************************************** +#ifndef DEPRECATED +void +TimerQuiesce(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable the timer. + // + HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; + + // + // Disable all the timer interrupts. + // + HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; + + // + // Clear all the timer interrupts. + // + HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; + + // + // Unregister the interrupt handler, which also disables interrupts to the + // core. + // + TimerIntUnregister(ulBase, TIMER_BOTH); + + // + // Set all the registers to their reset value. + // + HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; + HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; + HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; + HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; + HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; + HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; + HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; + HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; + HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; + HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; + HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; + HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; + HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; + HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; + HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; +} +#endif // DEPRECATED + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/timer.h b/driverlib/timer.h new file mode 100644 index 0000000..a4a49eb --- /dev/null +++ b/driverlib/timer.h @@ -0,0 +1,236 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ulTimers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A +#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B +#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A +#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B +#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A +#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B +#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A +#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B +#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A +#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B +#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A +#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B +#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A +#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B +#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A +#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerControlWaitOnTrigger(unsigned long ulBase, + unsigned long ulTimer, + tBoolean bWait); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue); +extern unsigned long long TimerLoadGet64(unsigned long ulBase); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern unsigned long long TimerValueGet64(unsigned long ulBase); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue); +extern unsigned long long TimerMatchGet64(unsigned long ulBase); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers); + +//***************************************************************************** +// +// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used +// instead to return the timer to its reset state. +// +//***************************************************************************** +#ifndef DEPRECATED +extern void TimerQuiesce(unsigned long ulBase); +#endif + +//***************************************************************************** +// +// These values for TimerConfigure have been deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED +#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer +#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer +#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/driverlib/uart.c b/driverlib/uart.c new file mode 100644 index 0000000..f71bc19 --- /dev/null +++ b/driverlib/uart.c @@ -0,0 +1,1948 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/uart.h" + +//***************************************************************************** +// +// The system clock divider defining the maximum baud rate supported by the +// UART. +// +//***************************************************************************** +#define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \ + (CLASS_IS_FURY && REVISION_IS_A2) || \ + (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \ + 16 : 8) + +//***************************************************************************** +// +// A mapping of UART base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulUARTIntMap[][2] = +{ + { UART0_BASE, INT_UART0 }, + { UART1_BASE, INT_UART1 }, + { UART2_BASE, INT_UART2 }, + { UART3_BASE, INT_UART3 }, + { UART4_BASE, INT_UART4 }, + { UART5_BASE, INT_UART5 }, + { UART6_BASE, INT_UART6 }, + { UART7_BASE, INT_UART7 }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a UART base address. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function determines if a UART port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +UARTBaseValid(unsigned long ulBase) +{ + return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE) || (ulBase == UART3_BASE) || + (ulBase == UART4_BASE) || (ulBase == UART5_BASE) || + (ulBase == UART6_BASE) || (ulBase == UART7_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the UART interrupt number. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Given a UART base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +UARTIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps UART base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) / + sizeof(g_ppulUARTIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulUARTIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulUARTIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! This function configures the type of parity to use for transmitting and +//! expect when receiving. The \e ulParity parameter must be one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two +//! parameters allow direct control of the parity bit; it is always either one +//! or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ulParity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of +//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, +//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of +//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, +//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function configures the FIFO level at which transmit and receive +//! interrupts are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulTxLevel == UART_FIFO_TX1_8) || + (ulTxLevel == UART_FIFO_TX2_8) || + (ulTxLevel == UART_FIFO_TX4_8) || + (ulTxLevel == UART_FIFO_TX6_8) || + (ulTxLevel == UART_FIFO_TX7_8)); + ASSERT((ulRxLevel == UART_FIFO_RX1_8) || + (ulRxLevel == UART_FIFO_RX2_8) || + (ulRxLevel == UART_FIFO_RX4_8) || + (ulRxLevel == UART_FIFO_RX6_8) || + (ulRxLevel == UART_FIFO_RX7_8)); + + // + // Set the FIFO interrupt levels. + // + HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulTxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pulRxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Read the FIFO level register. + // + ulTemp = HWREG(ulBase + UART_O_IFLS); + + // + // Extract the transmit and receive FIFO levels. + // + *pulTxLevel = ulTemp & UART_IFLS_TX_M; + *pulRxLevel = ulTemp & UART_IFLS_RX_M; +} + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulUARTClk is the rate of the clock supplied to the UART module. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the data +//! format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet(), or it can be +//! explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet()). +//! +//! For Stellaris parts that have the ability to specify the UART baud clock +//! source (via UARTClockSourceSet()), the peripheral clock can be changed to +//! PIOSC. In this case, the peripheral clock should be specified as +//! 16,000,000 (the nominal rate of PIOSC). +//! +//! This function replaces the original UARTConfigSet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig) +{ + unsigned long ulDiv; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT(ulBaud != 0); + ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER)); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Is the required baud rate greater than the maximum rate supported + // without the use of high speed mode? + // + if((ulBaud * 16) > ulUARTClk) + { + // + // Enable high speed mode. + // + HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; + + // + // Half the supplied baud rate to compensate for enabling high speed + // mode. This allows the following code to be common to both cases. + // + ulBaud /= 2; + } + else + { + // + // Disable high speed mode. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); + } + + // + // Compute the fractional baud rate divider. + // + ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2; + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; + HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCRH) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulUARTClk is the rate of the clock supplied to the UART module. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! This function determines the baud rate and data format for the UART, given +//! an explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSetExpClk(). +//! +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet(), or it can be +//! explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet()). +//! +//! For Stellaris parts that have the ability to specify the UART baud clock +//! source (via UARTClockSourceSet()), the peripheral clock can be changed to +//! PIOSC. In this case, the peripheral clock should be specified as +//! 16,000,000 (the nominal rate of PIOSC). +//! +//! This function replaces the original UARTConfigGet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, unsigned long *pulConfig) +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac); + + // + // See if high speed mode enabled. + // + if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) + { + // + // High speed mode is enabled so the actual baud rate is actually + // double what was just calculated. + // + *pulBaud *= 2; + } + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function sets the UARTEN, TXE, and RXE bits and enables the transmit +//! and receive FIFOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function disables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFODisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! Enables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param bLowPower indicates if SIR Low Power Mode is to be used. +//! +//! This function enables the SIREN control bit for IrDA mode on the UART. If +//! the \e bLowPower flag is set, then SIRLP bit is also set. This +//! function only has an effect if the UART has not been enabled +//! by a call to UARTEnable(). The call UARTEnableSIR() must be made before +//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function +//! calls the UARTEnable() function. Another option is to call UARTDisable() +//! followed by UARTEnableSIR() and then enable the UART by calling +//! UARTEnable(). +//! +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable SIR and SIRLP (if appropriate). + // + if(bLowPower) + { + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); + } + else + { + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN); + } +} + +//***************************************************************************** +// +//! Disables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function clears the SIREN (IrDA) and SIRLP (Low Power) bits. This +//! function only has an effect if the UART has not been enabled by a +//! call to UARTEnable(). The call UARTEnableSIR() must be made before +//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function +//! calls the UARTEnable() function. Another option is to call UARTDisable() +//! followed by UARTEnableSIR() and then enable the UART by calling +//! UARTEnable(). +//! +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisableSIR(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable SIR and SIRLP (if appropriate). + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); +} + +//***************************************************************************** +// +//! Enables ISO7816 smart card mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function enables the SMART control bit for the ISO7816 smart card mode +//! on the UART. This call also sets 8-bit word length and even parity as +//! required by ISO7816. +//! +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTSmartCardEnable(unsigned long ulBase) +{ + unsigned long ulVal; + + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(UARTBaseValid(ulBase)); + + // + // Set 8-bit word length, even parity, 2 stop bits (note that although the + // STP2 bit is ignored when in smartcard mode, this code lets the caller + // read back the actual setting in use). + // + ulVal = HWREG(ulBase + UART_O_LCRH); + ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | + UART_LCRH_WLEN_M); + ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2; + HWREG(ulBase + UART_O_LCRH) = ulVal; + + // + // Enable SMART mode. + // + HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART; +} + +//***************************************************************************** +// +//! Disables ISO7816 smart card mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function clears the SMART (ISO7816 smart card) bit in the UART +//! control register. +//! +//! \note The availability of ISO7816 smart card mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTSmartCardDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the SMART bit. + // + HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART; +} + +//***************************************************************************** +// +//! Sets the states of the DTR and/or RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! This function configures the states of the DTR or RTS modem handshake +//! outputs from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal +//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note The availability of ISO7816 smart card mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); + + // + // Set the appropriate modem control output bits. + // + ulTemp = HWREG(ulBase + UART_O_CTL); + ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); + HWREG(ulBase + UART_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Clears the states of the DTR and/or RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! This function clears the states of the DTR or RTS modem handshake outputs +//! from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal +//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); + + // + // Set the appropriate modem control output bits. + // + ulTemp = HWREG(ulBase + UART_O_CTL); + ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); + HWREG(ulBase + UART_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the states of the DTR and RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current states of each of the two UART modem +//! control signals, DTR and RTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signals. This value is +//! a logical OR combination of values \b UART_OUTPUT_RTS and +//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the +//! associated signal is asserted. +// +//***************************************************************************** +unsigned long +UARTModemControlGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + + return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); +} + +//***************************************************************************** +// +//! Gets the states of the RI, DCD, DSR and CTS modem status signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current states of each of the four UART modem +//! status signals, RI, DCD, DSR and CTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signals. This value +//! is a logical OR combination of values \b UART_INPUT_RI, +//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the +//! presence of each flag indicates that the associated signal is asserted. +// +//***************************************************************************** +unsigned long +UARTModemStatusGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + + return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | + UART_INPUT_CTS | UART_INPUT_DSR)); +} + +//***************************************************************************** +// +//! Sets the UART hardware flow control mode to be used. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode indicates the flow control modes to be used. This parameter +//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and +//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) +//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. +//! +//! This function configures the required hardware flow control modes. If +//! \e ulMode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted +//! if the incoming CTS signal is asserted. If \e ulMode contains flag +//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is +//! asserted only when there is space available in the receive FIFO. If no +//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be +//! passed. +//! +//! \note The availability of hardware flow control varies with the Stellaris +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); + + // + // Set the flow control mode as requested. + // + HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & + ~(UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)) | ulMode); +} + +//***************************************************************************** +// +//! Returns the UART hardware flow control mode currently in use. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current hardware flow control mode. +//! +//! \note The availability of hardware flow control varies with the Stellaris +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns the current flow control mode in use. This value is a +//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit +//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) +//! flow control is in use. If hardware flow control is disabled, +//! \b UART_FLOWCONTROL_NONE is returned. +// +//***************************************************************************** +unsigned long +UARTFlowControlGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(UARTBaseValid(ulBase)); + + return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)); +} + +//***************************************************************************** +// +//! Sets the operating mode for the UART transmit interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode is the operating mode for the transmit interrupt. It may be +//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle +//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO +//! level. +//! +//! This function allows the mode of the UART transmit interrupt to be set. By +//! default, the transmit interrupt is asserted when the FIFO level falls past +//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this +//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the +//! transmit interrupt is asserted once the transmitter is completely idle - +//! the transmit FIFO is empty and all bits, including any stop bits, have +//! cleared the transmitter. +//! +//! \note The availability of end-of-transmission mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulMode == UART_TXINT_MODE_EOT) || + (ulMode == UART_TXINT_MODE_FIFO)); + + // + // Set or clear the EOT bit of the UART control register as appropriate. + // + HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & + ~(UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)) | ulMode); +} + +//***************************************************************************** +// +//! Returns the current operating mode for the UART transmit interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current operating mode for the UART transmit +//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit +//! interrupt is currently configured to be asserted once the transmitter is +//! completely idle - the transmit FIFO is empty and all bits, including any +//! stop bits, have cleared the transmitter. The return value is +//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based +//! on the level of the transmit FIFO. +//! +//! \note The availability of end-of-transmission mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. +// +//***************************************************************************** +unsigned long +UARTTxIntModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current transmit interrupt mode. + // + return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)); +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO or \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO +//! or \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! This function replaces the original UARTCharNonBlockingGet() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +long +UARTCharGetNonBlocking(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. +// +//***************************************************************************** +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! This function writes the character \e ucData to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \b false is returned and the application must retry the +//! function later. +//! +//! This function replaces the original UARTCharNonBlockingPut() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +tBoolean +UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! This function sends the character \e ucData to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true asserts a break +//! condition on the UART. Calling this function with \e bBreakState set to +//! \b false removes the break condition. For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCRH) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! Determines whether the UART transmitter is busy or not. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, the +//! transmit FIFO is empty and all bits of the last transmitted character, +//! including all stop bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +tBoolean +UARTBusy(unsigned long ulBase) +{ + // + // Check the argument. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine if the UART is busy. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = UARTIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = UARTIntNumberGet(ulBase); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b UART_INT_9BIT - 9-bit Address Match interrupt +//! - \b UART_INT_OE - Overrun Error interrupt +//! - \b UART_INT_BE - Break Error interrupt +//! - \b UART_INT_PE - Parity Error interrupt +//! - \b UART_INT_FE - Framing Error interrupt +//! - \b UART_INT_RT - Receive Timeout interrupt +//! - \b UART_INT_TX - Transmit interrupt +//! - \b UART_INT_RX - Receive interrupt +//! - \b UART_INT_DSR - DSR interrupt +//! - \b UART_INT_DCD - DCD interrupt +//! - \b UART_INT_CTS - CTS interrupt +//! - \b UART_INT_RI - RI interrupt +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Enable UART DMA operation. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulDMAFlags is a bit mask of the DMA features to enable. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive and to disable +//! receive if an error occurs. The \e ulDMAFlags parameter is the +//! logical OR of any of the following values: +//! +//! - UART_DMA_RX - enable DMA for receive +//! - UART_DMA_TX - enable DMA for transmit +//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the requested bits in the UART DMA control register. + // + HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; +} + +//***************************************************************************** +// +//! Disable UART DMA operation. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulDMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable UART DMA features that were enabled +//! by UARTDMAEnable(). The specified UART DMA features are disabled. The +//! \e ulDMAFlags parameter is the logical OR of any of the following values: +//! +//! - UART_DMA_RX - disable DMA for receive +//! - UART_DMA_TX - disable DMA for transmit +//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Clear the requested bits in the UART DMA control register. + // + HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; +} + +//***************************************************************************** +// +//! Gets current receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately when the +//! overrun occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK +//! and \b UART_RXERROR_OVERRUN. +// +//***************************************************************************** +unsigned long +UARTRxErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current value of the receive status register. + // + return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! Clears all reported receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRxErrorClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Any write to the Error Clear Register clears all bits which are + // currently set. + // + HWREG(ulBase + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +//! Sets the baud clock source for the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulSource is the baud clock source for the UART. +//! +//! This function allows the baud clock source for the UART to be selected. +//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b UART_CLOCK_PIOSC). +//! +//! Changing the baud clock source changes the baud rate generated by the +//! UART. Therefore, the baud rate should be reconfigured after any change to +//! the baud clock source. +//! +//! \note The ability to specify the UART baud clock source varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulSource == UART_CLOCK_SYSTEM) || (ulSource == UART_CLOCK_PIOSC)); + + // + // Set the UART clock source. + // + HWREG(ulBase + UART_O_CC) = ulSource; +} + +//***************************************************************************** +// +//! Gets the baud clock source for the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the baud clock source for the specified UART. The +//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b UART_CLOCK_PIOSC). +//! +//! \note The ability to specify the UART baud clock source varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +UARTClockSourceGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the UART clock source. + // + return(HWREG(ulBase + UART_O_CC)); +} + +//***************************************************************************** +// +//! Enables 9-bit mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function enables the 9-bit operational mode of the UART. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable 9-bit mode. + // + HWREG(ulBase + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; +} + +//***************************************************************************** +// +//! Disables 9-bit mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function disables the 9-bit operational mode of the UART. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable 9-bit mode. + // + HWREG(ulBase + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; +} + +//***************************************************************************** +// +//! Sets the device address(es) for 9-bit mode. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucAddr is the device address. +//! \param ucMask is the device address mask. +//! +//! This function configures the device address or range of device addresses +//! that respond to requests on the 9-bit UART port. The received address is +//! masked with the mask and then compared against the given address, allowing +//! either a single address (if \b ucMask is 0xff) or a set of addresses to be +//! matched. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, + unsigned char ucMask) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the address and mask. + // + HWREG(ulBase + UART_O_9BITADDR) = ucAddr << UART_9BITADDR_ADDR_S; + HWREG(ulBase + UART_O_9BITAMASK) = ucMask << UART_9BITAMASK_MASK_S; +} + +//***************************************************************************** +// +//! Sends an address character from the specified port when operating in 9-bit +//! mode. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucAddr is the address to be transmitted. +//! +//! This function waits until all data has been sent from the specified port +//! and then sends the given address as an address byte. It then waits until +//! the address byte has been transmitted before returning. +//! +//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(), +//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive +//! data characters in 9-bit mode. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr) +{ + unsigned long ulLCRH; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until the FIFO is empty and the UART is not busy. + // + while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) + { + } + + // + // Force the address/data bit to 1 to indicate this is an address byte. + // + ulLCRH = HWREG(ulBase + UART_O_LCRH); + HWREG(ulBase + UART_O_LCRH) = ((ulLCRH & ~UART_LCRH_EPS) | UART_LCRH_SPS | + UART_LCRH_PEN); + + // + // Send the address. + // + HWREG(ulBase + UART_O_DR) = ucAddr; + + // + // Wait until the address has been sent. + // + while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) + { + } + + // + // Restore the address/data setting. + // + HWREG(ulBase + UART_O_LCRH) = ulLCRH; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/uart.h b/driverlib/uart.h new file mode 100644 index 0000000..0640352 --- /dev/null +++ b/driverlib/uart.h @@ -0,0 +1,275 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask +#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask +#define UART_INT_RI 0x001 // RI Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +#define UART_CLOCK_SYSTEM 0x00000000 +#define UART_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTFIFOEnable(unsigned long ulBase); +extern void UARTFIFODisable(unsigned long ulBase); +extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); +extern void UARTDisableSIR(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern tBoolean UARTBusy(unsigned long ulBase); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern unsigned long UARTRxErrorGet(unsigned long ulBase); +extern void UARTRxErrorClear(unsigned long ulBase); +extern void UARTSmartCardEnable(unsigned long ulBase); +extern void UARTSmartCardDisable(unsigned long ulBase); +extern void UARTModemControlSet(unsigned long ulBase, + unsigned long ulControl); +extern void UARTModemControlClear(unsigned long ulBase, + unsigned long ulControl); +extern unsigned long UARTModemControlGet(unsigned long ulBase); +extern unsigned long UARTModemStatusGet(unsigned long ulBase); +extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTFlowControlGet(unsigned long ulBase); +extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTTxIntModeGet(unsigned long ulBase); +extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource); +extern unsigned long UARTClockSourceGet(unsigned long ulBase); +extern void UART9BitEnable(unsigned long ulBase); +extern void UART9BitDisable(unsigned long ulBase); +extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, + unsigned char ucMask); +extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr); + +//***************************************************************************** +// +// Several UART APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define UARTConfigSet(a, b, c) \ + UARTConfigSetExpClk(a, SysCtlClockGet(), b, c) +#define UARTConfigGet(a, b, c) \ + UARTConfigGetExpClk(a, SysCtlClockGet(), b, c) +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/driverlib/udma.c b/driverlib/udma.c new file mode 100644 index 0000000..cade462 --- /dev/null +++ b/driverlib/udma.c @@ -0,0 +1,1383 @@ +//***************************************************************************** +// +// udma.c - Driver for the micro-DMA controller. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "inc/hw_udma.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/udma.h" + +//***************************************************************************** +// +//! Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAEnable(void) +{ + // + // Set the master enable bit in the config register. + // + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; +} + +//***************************************************************************** +// +//! Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller cannot operate until re-enabled with uDMAEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMADisable(void) +{ + // + // Clear the master enable bit in the config register. + // + HWREG(UDMA_CFG) = 0; +} + +//***************************************************************************** +// +//! Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +unsigned long +uDMAErrorStatusGet(void) +{ + // + // Return the uDMA error status. + // + return(HWREG(UDMA_ERRCLR)); +} + +//***************************************************************************** +// +//! Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. This function should +//! be called from within the uDMA error interrupt handler to clear the +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAErrorStatusClear(void) +{ + // + // Clear the uDMA error interrupt. + // + HWREG(UDMA_ERRCLR) = 1; +} + +//***************************************************************************** +// +//! Enables a uDMA channel for operation. +//! +//! \param ulChannelNum is the channel number to enable. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel is automatically disabled by +//! the uDMA controller. Therefore, this function should be called prior to +//! starting up any new transfer. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelEnable(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable set register. + // + HWREG(UDMA_ENASET) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Disables a uDMA channel for operation. +//! +//! \param ulChannelNum is the channel number to disable. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! cannot respond to uDMA transfer requests until re-enabled via +//! uDMAChannelEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelDisable(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable clear register. + // + HWREG(UDMA_ENACLR) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Checks if a uDMA channel is enabled for operation. +//! +//! \param ulChannelNum is the channel number to check. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! function can be used to check the status of a transfer, as the channel is +//! automatically disabled at the end of a transfer. +//! +//! \return Returns \b true if the channel is enabled, \b false if disabled. +// +//***************************************************************************** +tBoolean +uDMAChannelIsEnabled(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // AND the specified channel bit with the enable register and return the + // result. + // + return((HWREG(UDMA_ENASET) & (1 << (ulChannelNum & 0x1f))) ? true : false); +} + +//***************************************************************************** +// +//! Sets the base address for the channel control table. +//! +//! \param pControlTable is a pointer to the 1024-byte-aligned base address +//! of the uDMA channel control table. +//! +//! This function configures the base address of the channel control table. +//! This table resides in system memory and holds control information for each +//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base +//! address must be configured before any of the channel functions can be used. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels and the transfer modes that are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAControlBaseSet(void *pControlTable) +{ + // + // Check the arguments. + // + ASSERT(((unsigned long)pControlTable & ~0x3FF) == + (unsigned long)pControlTable); + ASSERT((unsigned long)pControlTable >= 0x20000000); + + // + // Program the base address into the register. + // + HWREG(UDMA_CTLBASE) = (unsigned long)pControlTable; +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +void * +uDMAControlBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_CTLBASE)); +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +void * +uDMAControlAlternateBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_ALTBASE)); +} + +//***************************************************************************** +// +//! Requests a uDMA channel to start a transfer. +//! +//! \param ulChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This function could be used for performing a memory-to-memory +//! transfer or if for some reason, a transfer needs to be initiated by +//! software instead of the peripheral associated with that channel. +//! +//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then +//! the completion is signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion is signaled on the +//! peripheral's interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelRequest(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the software uDMA request register. + // + HWREG(UDMA_SWREQ) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Enables attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Set the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_USEBURSTSET) = 1 << ulChannelNum; + } + + // + // Set the alternate control select bit for this channel, + // if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_ALTSET) = 1 << ulChannelNum; + } + + // + // Set the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_PRIOSET) = 1 << ulChannelNum; + } + + // + // Set the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_REQMASKSET) = 1 << ulChannelNum; + } +} + +//***************************************************************************** +// +//! Disables attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Clear the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_USEBURSTCLR) = 1 << ulChannelNum; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_ALTCLR) = 1 << ulChannelNum; + } + + // + // Clear the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_PRIOCLR) = 1 << ulChannelNum; + } + + // + // Clear the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_REQMASKCLR) = 1 << ulChannelNum; + } +} + +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \return Returns the logical OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +unsigned long +uDMAChannelAttributeGet(unsigned long ulChannelNum) +{ + unsigned long ulAttr = 0; + + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(UDMA_ALTSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(UDMA_PRIOSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(UDMA_REQMASKSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ulAttr); +} + +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulControl is logical OR of several control values to set the control +//! parameters for the channel. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! parameters are typically not changed often. +//! +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ulControl parameter is the logical OR of five values: the data size, +//! the source address increment, the destination address increment, the +//! arbitration size, and the use burst flag. The choices available for each +//! of these values is described below. +//! +//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or +//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. +//! +//! Choose the source address increment from one of \b UDMA_SRC_INC_8, +//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or +//! to select non-incrementing. +//! +//! Choose the destination address increment from one of \b UDMA_DST_INC_8, +//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or +//! to select non-incrementing. +//! +//! The arbitration size determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size +//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, +//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 +//! items, in powers of 2. +//! +//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only +//! respond to burst requests at the tail end of a scatter-gather transfer. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl) +{ + tDMAControlTable *pCtl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + pCtl[ulChannelStructIndex].ulControl = + ((pCtl[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_DSTINC_M | + UDMA_CHCTL_DSTSIZE_M | + UDMA_CHCTL_SRCINC_M | + UDMA_CHCTL_SRCSIZE_M | + UDMA_CHCTL_ARBSIZE_M | + UDMA_CHCTL_NXTUSEBURST)) | + ulControl); +} + +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulMode is the type of uDMA transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ulTransferSize is the number of data items to transfer. +//! +//! This function is used to configure the parameters for a uDMA transfer. +//! These parameters are typically changed often. The function +//! uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ulMode parameter should be one of the following values: +//! +//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. +//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once +//! started even if the request is removed. +//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the +//! primary and alternate control structures for the channel. This mode +//! allows use of ping-pong buffering for uDMA transfers. +//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather +//! transfer. +//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather +//! transfer. +//! +//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler takes care of this alignment if +//! the pointers are pointing to storage of the appropriate data type. +//! +//! The \e ulTransferSize parameter is the number of data items, not the number +//! of bytes. +//! +//! The two scatter-gather modes, memory and peripheral, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function looks for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and sets the +//! scatter-gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using uDMAChannelEnable() after calling +//! this function. The transfer does not begin until the channel has been +//! configured and enabled. Note that the channel is automatically disabled +//! after the transfer is completed, meaning that uDMAChannelEnable() must be +//! called again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results are unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, + unsigned long ulTransferSize) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + unsigned long ulInc; + unsigned long ulBufferBytes; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((unsigned long)pvSrcAddr >= 0x20000000); + ASSERT((unsigned long)pvDstAddr >= 0x20000000); + ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ulChannelStructIndex & UDMA_ALT_SELECT) + { + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulMode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + // + ulControl |= ulMode | ((ulTransferSize - 1) << 4); + + // + // Get the address increment value for the source, from the control word. + // + ulInc = (ulControl & UDMA_CHCTL_SRCINC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ulInc != UDMA_SRC_INC_NONE) + { + ulInc = ulInc >> 26; + ulBufferBytes = ulTransferSize << ulInc; + pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1); + } + + // + // Load the source ending address into the control block. + // + pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ulInc = ulControl & UDMA_CHCTL_DSTINC_M; + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ulInc != UDMA_DST_INC_NONE) + { + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer must point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ulChannelStructIndex | + UDMA_ALT_SELECT].ulSpare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ulInc = ulInc >> 30; + ulBufferBytes = ulTransferSize << ulInc; + pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1); + } + } + + // + // Load the destination ending address into the control block. + // + pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + pControlTable[ulChannelStructIndex].ulControl = ulControl; +} + +//***************************************************************************** +// +//! Configures a uDMA channel for scatter-gather mode. +//! +//! \param ulChannelNum is the uDMA channel number. +//! \param ulTaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather +//! transfer (else it is memory scatter-gather transfer) +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list and must pass a pointer to +//! the start of the task list as the \e pvTaskList parameter. The +//! \e ulTaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. The flag \e bIsPeriphSG should be used to indicate +//! if scatter-gather should be configured for peripheral or memory +//! operation. +//! +//! \sa uDMATaskStructEntry +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, + void *pvTaskList, unsigned long ulIsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // + // Check the parameters + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ulTaskCount <= 1024); + ASSERT(ulTaskCount != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get a handy pointer to the task list + // + pTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This address is the + // last element of the last task in the task table + // + pControlTable[ulChannelNum].pvSrcEndAddr = + &pTaskTable[ulTaskCount - 1].ulSpare; + + // + // Compute the ending address for the destination pointer. This address + // is the end of the alternate structure for this channel. + // + pControlTable[ulChannelNum].pvDstEndAddr = + &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + pControlTable[ulChannelNum].ulControl = + (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | + UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | + UDMA_CHCTL_ARBSIZE_4 | + (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | + (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : + UDMA_CHCTL_XFERMODE_MEM_SG)); +} + +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items is returned. If the transfer is +//! complete, then 0 is returned. +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +unsigned long +uDMAChannelSizeGet(unsigned long ulChannelStructIndex) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off all but the size field + // and the mode field. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer + // + if(ulControl == 0) + { + return(0); + } + + // + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + // + else + { + // + // Shift the size field and add one, then return to user. + // + return((ulControl >> 4) + 1); + } +} + +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the transfer mode for the uDMA channel and +//! to query the status of a transfer on a channel. When the transfer is +//! complete the mode is \b UDMA_MODE_STOP. +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which is one of the following values: \b UDMA_MODE_STOP, +//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. +// +//***************************************************************************** +unsigned long +uDMAChannelModeGet(unsigned long ulChannelStructIndex) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off all but the mode field. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + UDMA_CHCTL_XFERMODE_M); + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulControl &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ulControl); +} + +//***************************************************************************** +// +//! Selects the secondary peripheral for a set of uDMA channels. +//! +//! \param ulSecPeriphs is the logical OR of the uDMA channels for which to use +//! the secondary peripheral, instead of the default peripheral. +//! +//! This function is used to select the secondary peripheral assignment for a +//! set of uDMA channels. By selecting the secondary peripheral assignment for +//! a channel, the default peripheral assignment is no longer available for +//! that channel. +//! +//! The parameter \e ulSecPeriphs can be the logical OR of any of the following +//! macros. If one of the macros below is in the list passed to this function, +//! then the secondary peripheral (marked as \b _SEC_) is selected. +//! +//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX +//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX +//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A +//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B +//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A +//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B +//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A +//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B +//! - \b UDMA_DEF_UART0RX_SEC_UART1RX +//! - \b UDMA_DEF_UART0TX_SEC_UART1TX +//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX +//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX +//! - \b UDMA_DEF_RESERVED_SEC_UART2RX +//! - \b UDMA_DEF_RESERVED_SEC_UART2TX +//! - \b UDMA_DEF_ADC00_SEC_TMR2A +//! - \b UDMA_DEF_ADC01_SEC_TMR2B +//! - \b UDMA_DEF_ADC02_SEC_RESERVED +//! - \b UDMA_DEF_ADC03_SEC_RESERVED +//! - \b UDMA_DEF_TMR0A_SEC_TMR1A +//! - \b UDMA_DEF_TMR0B_SEC_TMR1B +//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX +//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX +//! - \b UDMA_DEF_UART1RX_SEC_RESERVED +//! - \b UDMA_DEF_UART1TX_SEC_RESERVED +//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 +//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 +//! - \b UDMA_DEF_RESERVED_SEC_ADC12 +//! - \b UDMA_DEF_RESERVED_SEC_ADC13 +//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED +//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelSelectSecondary(unsigned long ulSecPeriphs) +{ + // + // Select the secondary peripheral for the specified channels. + // + HWREG(UDMA_CHASGN) |= ulSecPeriphs; +} + +//***************************************************************************** +// +//! Selects the default peripheral for a set of uDMA channels. +//! +//! \param ulDefPeriphs is the logical OR of the uDMA channels for which to use +//! the default peripheral, instead of the secondary peripheral. +//! +//! This function is used to select the default peripheral assignment for a set +//! of uDMA channels. +//! +//! The parameter \e ulDefPeriphs can be the logical OR of any of the following +//! macros. If one of the macros below is in the list passed to this function, +//! then the default peripheral (marked as \b _DEF_) is selected. +//! +//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX +//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX +//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A +//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B +//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A +//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B +//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A +//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B +//! - \b UDMA_DEF_UART0RX_SEC_UART1RX +//! - \b UDMA_DEF_UART0TX_SEC_UART1TX +//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX +//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX +//! - \b UDMA_DEF_RESERVED_SEC_UART2RX +//! - \b UDMA_DEF_RESERVED_SEC_UART2TX +//! - \b UDMA_DEF_ADC00_SEC_TMR2A +//! - \b UDMA_DEF_ADC01_SEC_TMR2B +//! - \b UDMA_DEF_ADC02_SEC_RESERVED +//! - \b UDMA_DEF_ADC03_SEC_RESERVED +//! - \b UDMA_DEF_TMR0A_SEC_TMR1A +//! - \b UDMA_DEF_TMR0B_SEC_TMR1B +//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX +//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX +//! - \b UDMA_DEF_UART1RX_SEC_RESERVED +//! - \b UDMA_DEF_UART1TX_SEC_RESERVED +//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 +//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 +//! - \b UDMA_DEF_RESERVED_SEC_ADC12 +//! - \b UDMA_DEF_RESERVED_SEC_ADC13 +//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED +//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelSelectDefault(unsigned long ulDefPeriphs) +{ + // + // Select the default peripheral for the specified channels. + // + HWREG(UDMA_CHASGN) &= ~ulDefPeriphs; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt is to be registered. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function registers and enables the handler to be called when the uDMA +//! controller generates an interrupt. The \e ulIntChannel parameter should be +//! one of the following: +//! +//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts +//! from the uDMA software channel (UDMA_CHANNEL_SW) +//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error +//! interrupts +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The interrupt handler for the uDMA is for transfer completion when +//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The +//! interrupts for each peripheral channel are handled through the individual +//! peripheral interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR)); + + // + // Register the interrupt handler. + // + IntRegister(ulIntChannel, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(ulIntChannel); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt to unregister. +//! +//! This function disables and unregisters the handler to be called for the +//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of +//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function +//! uDMAIntRegister(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntUnregister(unsigned long ulIntChannel) +{ + // + // Disable the interrupt. + // + IntDisable(ulIntChannel); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulIntChannel); +} + +//***************************************************************************** +// +//! Gets the uDMA controller channel interrupt status. +//! +//! This function is used to get the interrupt status of the uDMA controller. +//! The returned value is a 32-bit bit mask that indicates which channels are +//! requesting an interrupt. This function can be used from within an +//! interrupt handler to determine or confirm which uDMA channel has requested +//! an interrupt. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return Returns a 32-bit mask which indicates requesting uDMA channels. +//! There is a bit for each channel and a 1 indicates that the channel +//! is requesting an interrupt. Multiple bits can be set. +// +//***************************************************************************** +unsigned long +uDMAIntStatus(void) +{ + // + // Check feature availability + // + ASSERT(!CLASS_IS_SANDSTORM); + ASSERT(!CLASS_IS_FURY); + ASSERT(!CLASS_IS_DUSTDEVIL); + ASSERT(!CLASS_IS_TEMPEST); + + // + // Return the value of the uDMA interrupt status register + // + return(HWREG(UDMA_CHIS)); +} + +//***************************************************************************** +// +//! Clears uDMA interrupt status. +//! +//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! This function clears bits in the uDMA interrupt status register according +//! to which bits are set in \e ulChanMask. There is one bit for each channel. +//! If a a bit is set in \e ulChanMask, then that corresponding channel's +//! interrupt status is cleared (if it was set). +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntClear(unsigned long ulChanMask) +{ + // + // Check feature availability + // + ASSERT(!CLASS_IS_SANDSTORM); + ASSERT(!CLASS_IS_FURY); + ASSERT(!CLASS_IS_DUSTDEVIL); + ASSERT(!CLASS_IS_TEMPEST); + + // + // Clear the requested bits in the uDMA interrupt status register + // + HWREG(UDMA_CHIS) = ulChanMask; +} + +//***************************************************************************** +// +//! Assigns a peripheral mapping for a uDMA channel. +//! +//! \param ulMapping is a macro specifying the peripheral assignment for +//! a channel. +//! +//! This function assigns a peripheral mapping to a uDMA channel. It is +//! used to select which peripheral is used for a uDMA channel. The parameter +//! \e ulMapping should be one of the macros named \b UDMA_CHn_tttt from the +//! header file \e udma.h. For example, to assign uDMA channel 0 to the +//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX. +//! +//! Please consult the Stellaris data sheet for a table showing all the +//! possible peripheral assignments for the uDMA channels for a particular +//! device. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAssign(unsigned long ulMapping) +{ + unsigned long ulMapReg; + unsigned long ulMapShift; + unsigned long ulChannelNum; + + // + // Check the parameters + // + ASSERT((ulMapping & 0xffffff00) < 0x00050000); + ASSERT(!CLASS_IS_SANDSTORM); + ASSERT(!CLASS_IS_FURY); + ASSERT(!CLASS_IS_DUSTDEVIL); + ASSERT(!CLASS_IS_TEMPEST); + ASSERT(!CLASS_IS_FIRESTORM); + + // + // Extract the channel number and map encoding value from the parameter. + // + ulChannelNum = ulMapping & 0xff; + ulMapping = ulMapping >> 16; + + // + // Find the uDMA channel mapping register and shift value to use for this + // channel + // + ulMapReg = UDMA_CHMAP0 + ((ulChannelNum / 8) * 4); + ulMapShift = (ulChannelNum % 8) * 4; + + // + // Set the channel map encoding for this channel + // + HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | + ulMapping << ulMapShift; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/udma.h b/driverlib/udma.h new file mode 100644 index 0000000..877b4fc --- /dev/null +++ b/driverlib/udma.h @@ -0,0 +1,755 @@ +//***************************************************************************** +// +// udma.h - Prototypes and macros for the uDMA controller. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// A structure that defines an entry in the channel control table. These +// fields are used by the uDMA controller and normally it is not necessary for +// software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + // + // The ending source address of the data transfer. + // + volatile void *pvSrcEndAddr; + + // + // The ending destination address of the data transfer. + // + volatile void *pvDstEndAddr; + + // + // The channel control mode. + // + volatile unsigned long ulControl; + + // + // An unused location. + // + volatile unsigned long ulSpare; +} +tDMAControlTable; + +//***************************************************************************** +// +//! A helper macro for building scatter-gather task table entries. +//! +//! \param ulTransferCount is the count of items to transfer for this task. +//! \param ulItemSize is the bit size of the items to transfer for this task. +//! \param ulSrcIncrement is the bit size increment for source data. +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ulDstIncrement is the bit size increment for destination data. +//! \param pvDstAddr is the starting address of the destination data. +//! \param ulArbSize is the arbitration size to use for the transfer task. +//! \param ulMode is the transfer mode for this task. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! The \e ulTransferCount parameter is the number of items that will be +//! transferred by this task. It must be in the range 1-1024. +//! +//! The \e ulItemSize parameter is the bit size of the transfer data. It must +//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. +//! +//! The \e ulSrcIncrement parameter is the increment size for the source data. +//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, +//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. +//! +//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source +//! data. +//! +//! The \e ulDstIncrement parameter is the increment size for the destination +//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, +//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. +//! +//! The \e pvDstAddr parameter is a void pointer to the beginning of the +//! location where the data will be transferred. +//! +//! The \e ulArbSize parameter is the arbitration size for the transfer, and +//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on +//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in +//! powers of 2, from 1 to 1024. +//! +//! The \e ulMode parameter is the mode to use for this transfer task. It +//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note +//! that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +//! \verbatim +//! tDMAControlTable MyTaskList[] = +//! { +//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, +//! UDMA_SRC_INC_8, MySourceBuf, +//! UDMA_DST_INC_8, MyDestBuf, +//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), +//! uDMATaskStructEntry(Task2Count, ... ), +//! } +//! \endverbatim +//! +//! \return Nothing; this is not a function. +// +//***************************************************************************** +#define uDMATaskStructEntry(ulTransferCount, \ + ulItemSize, \ + ulSrcIncrement, \ + pvSrcAddr, \ + ulDstIncrement, \ + pvDstAddr, \ + ulArbSize, \ + ulMode) \ + { \ + (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ + ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ + ((ulSrcIncrement) >> 26)) - 1]))), \ + (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ + ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ + ((ulDstIncrement) >> 30)) - 1]))), \ + (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ + (((ulTransferCount) - 1) << 4) | \ + ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ + } + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAModeSet() and returned +// uDMAModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xc0000000 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHANNEL_USBEP1RX 0 +#define UDMA_CHANNEL_USBEP1TX 1 +#define UDMA_CHANNEL_USBEP2RX 2 +#define UDMA_CHANNEL_USBEP2TX 3 +#define UDMA_CHANNEL_USBEP3RX 4 +#define UDMA_CHANNEL_USBEP3TX 5 +#define UDMA_CHANNEL_ETH0RX 6 +#define UDMA_CHANNEL_ETH0TX 7 +#define UDMA_CHANNEL_UART0RX 8 +#define UDMA_CHANNEL_UART0TX 9 +#define UDMA_CHANNEL_SSI0RX 10 +#define UDMA_CHANNEL_SSI0TX 11 +#define UDMA_CHANNEL_ADC0 14 +#define UDMA_CHANNEL_ADC1 15 +#define UDMA_CHANNEL_ADC2 16 +#define UDMA_CHANNEL_ADC3 17 +#define UDMA_CHANNEL_TMR0A 18 +#define UDMA_CHANNEL_TMR0B 19 +#define UDMA_CHANNEL_TMR1A 20 +#define UDMA_CHANNEL_TMR1B 21 +#define UDMA_CHANNEL_UART1RX 22 +#define UDMA_CHANNEL_UART1TX 23 +#define UDMA_CHANNEL_SSI1RX 24 +#define UDMA_CHANNEL_SSI1TX 25 +#define UDMA_CHANNEL_I2S0RX 28 +#define UDMA_CHANNEL_I2S0TX 29 +#define UDMA_CHANNEL_SW 30 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// uDMA interrupt sources, to be passed to uDMAIntRegister() and +// uDMAIntUnregister(). +// +//***************************************************************************** +#define UDMA_INT_SW 62 +#define UDMA_INT_ERR 63 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. These are for secondary peripheral assignments. +// +//***************************************************************************** +#define UDMA_SEC_CHANNEL_UART2RX_0 \ + 0 +#define UDMA_SEC_CHANNEL_UART2TX_1 \ + 1 +#define UDMA_SEC_CHANNEL_TMR3A 2 +#define UDMA_SEC_CHANNEL_TMR3B 3 +#define UDMA_SEC_CHANNEL_TMR2A_4 \ + 4 +#define UDMA_SEC_CHANNEL_TMR2B_5 \ + 5 +#define UDMA_SEC_CHANNEL_TMR2A_6 \ + 6 +#define UDMA_SEC_CHANNEL_TMR2B_7 \ + 7 +#define UDMA_SEC_CHANNEL_UART1RX \ + 8 +#define UDMA_SEC_CHANNEL_UART1TX \ + 9 +#define UDMA_SEC_CHANNEL_SSI1RX 10 +#define UDMA_SEC_CHANNEL_SSI1TX 11 +#define UDMA_SEC_CHANNEL_UART2RX_12 \ + 12 +#define UDMA_SEC_CHANNEL_UART2TX_13 \ + 13 +#define UDMA_SEC_CHANNEL_TMR2A_14 \ + 14 +#define UDMA_SEC_CHANNEL_TMR2B_15 \ + 15 +#define UDMA_SEC_CHANNEL_TMR1A 18 +#define UDMA_SEC_CHANNEL_TMR1B 19 +#define UDMA_SEC_CHANNEL_EPI0RX 20 +#define UDMA_SEC_CHANNEL_EPI0TX 21 +#define UDMA_SEC_CHANNEL_ADC10 24 +#define UDMA_SEC_CHANNEL_ADC11 25 +#define UDMA_SEC_CHANNEL_ADC12 26 +#define UDMA_SEC_CHANNEL_ADC13 27 +#define UDMA_SEC_CHANNEL_SW 30 + +//***************************************************************************** +// +// uDMA default/secondary peripheral selections, to be passed to +// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). +// +//***************************************************************************** +#define UDMA_DEF_USBEP1RX_SEC_UART2RX \ + 0x00000001 +#define UDMA_DEF_USBEP1TX_SEC_UART2TX \ + 0x00000002 +#define UDMA_DEF_USBEP2RX_SEC_TMR3A \ + 0x00000004 +#define UDMA_DEF_USBEP2TX_SEC_TMR3B \ + 0x00000008 +#define UDMA_DEF_USBEP3RX_SEC_TMR2A \ + 0x00000010 +#define UDMA_DEF_USBEP3TX_SEC_TMR2B \ + 0x00000020 +#define UDMA_DEF_ETH0RX_SEC_TMR2A \ + 0x00000040 +#define UDMA_DEF_ETH0TX_SEC_TMR2B \ + 0x00000080 +#define UDMA_DEF_UART0RX_SEC_UART1RX \ + 0x00000100 +#define UDMA_DEF_UART0TX_SEC_UART1TX \ + 0x00000200 +#define UDMA_DEF_SSI0RX_SEC_SSI1RX \ + 0x00000400 +#define UDMA_DEF_SSI0TX_SEC_SSI1TX \ + 0x00000800 +#define UDMA_DEF_RESERVED_SEC_UART2RX \ + 0x00001000 +#define UDMA_DEF_RESERVED_SEC_UART2TX \ + 0x00002000 +#define UDMA_DEF_ADC00_SEC_TMR2A \ + 0x00004000 +#define UDMA_DEF_ADC01_SEC_TMR2B \ + 0x00008000 +#define UDMA_DEF_ADC02_SEC_RESERVED \ + 0x00010000 +#define UDMA_DEF_ADC03_SEC_RESERVED \ + 0x00020000 +#define UDMA_DEF_TMR0A_SEC_TMR1A \ + 0x00040000 +#define UDMA_DEF_TMR0B_SEC_TMR1B \ + 0x00080000 +#define UDMA_DEF_TMR1A_SEC_EPI0RX \ + 0x00100000 +#define UDMA_DEF_TMR1B_SEC_EPI0TX \ + 0x00200000 +#define UDMA_DEF_UART1RX_SEC_RESERVED \ + 0x00400000 +#define UDMA_DEF_UART1TX_SEC_RESERVED \ + 0x00800000 +#define UDMA_DEF_SSI1RX_SEC_ADC10 \ + 0x01000000 +#define UDMA_DEF_SSI1TX_SEC_ADC11 \ + 0x02000000 +#define UDMA_DEF_RESERVED_SEC_ADC12 \ + 0x04000000 +#define UDMA_DEF_RESERVED_SEC_ADC13 \ + 0x08000000 +#define UDMA_DEF_I2S0RX_SEC_RESERVED \ + 0x10000000 +#define UDMA_DEF_I2S0TX_SEC_RESERVED \ + 0x20000000 + +//***************************************************************************** +// +// Values that can be passed to uDMAChannelAssign() to select peripheral +// mapping for each channel. The channels named RESERVED may be assigned +// to a peripheral in future parts. +// +//***************************************************************************** +// +// Channel 0 +// +#define UDMA_CH0_USB0EP1RX 0x00000000 +#define UDMA_CH0_UART2RX 0x00010000 +#define UDMA_CH0_RESERVED2 0x00020000 +#define UDMA_CH0_TIMER4A 0x00030000 +#define UDMA_CH0_RESERVED4 0x00040000 + +// +// Channel 1 +// +#define UDMA_CH1_USB0EP1TX 0x00000001 +#define UDMA_CH1_UART2TX 0x00010001 +#define UDMA_CH1_RESERVED2 0x00020001 +#define UDMA_CH1_TIMER4B 0x00030001 +#define UDMA_CH1_RESERVED4 0x00040001 + +// +// Channel 2 +// +#define UDMA_CH2_USB0EP2RX 0x00000002 +#define UDMA_CH2_TIMER3A 0x00010002 +#define UDMA_CH2_RESERVED2 0x00020002 +#define UDMA_CH2_RESERVED3 0x00030002 +#define UDMA_CH2_RESERVED4 0x00040002 + +// +// Channel 3 +// +#define UDMA_CH3_USB0EP2TX 0x00000003 +#define UDMA_CH3_TIMER3B 0x00010003 +#define UDMA_CH3_RESERVED2 0x00020003 +#define UDMA_CH3_LPC0_3 0x00030003 +#define UDMA_CH3_RESERVED4 0x00040003 + +// +// Channel 4 +// +#define UDMA_CH4_USB0EP3RX 0x00000004 +#define UDMA_CH4_TIMER2A 0x00010004 +#define UDMA_CH4_RESERVED2 0x00020004 +#define UDMA_CH4_GPIOA 0x00030004 +#define UDMA_CH4_RESERVED4 0x00040004 + +// +// Channel 5 +// +#define UDMA_CH5_USB0EP3TX 0x00000005 +#define UDMA_CH5_TIMER2B 0x00010005 +#define UDMA_CH5_RESERVED2 0x00020005 +#define UDMA_CH5_GPIOB 0x00030005 +#define UDMA_CH5_RESERVED4 0x00040005 + +// +// Channel 6 +// +#define UDMA_CH6_RESERVED0 0x00000006 +#define UDMA_CH6_TIMER2A 0x00010006 +#define UDMA_CH6_UART5RX 0x00020006 +#define UDMA_CH6_GPIOC 0x00030006 +#define UDMA_CH6_I2C0RX 0x00040006 + +// +// Channel 7 +// +#define UDMA_CH7_RESERVED0 0x00000007 +#define UDMA_CH7_TIMER2B 0x00010007 +#define UDMA_CH7_UART5TX 0x00020007 +#define UDMA_CH7_GPIOD 0x00030007 +#define UDMA_CH7_I2C0TX 0x00040007 + +// +// Channel 8 +// +#define UDMA_CH8_UART0RX 0x00000008 +#define UDMA_CH8_UART1RX 0x00010008 +#define UDMA_CH8_RESERVED2 0x00020008 +#define UDMA_CH8_TIMER5A 0x00030008 +#define UDMA_CH8_I2C1RX 0x00040008 + +// +// Channel 9 +// +#define UDMA_CH9_UART0TX 0x00000009 +#define UDMA_CH9_UART1TX 0x00010009 +#define UDMA_CH9_RESERVED2 0x00020009 +#define UDMA_CH9_TIMER5B 0x00030009 +#define UDMA_CH9_I2C1TX 0x00040009 + +// +// Channel 10 +// +#define UDMA_CH10_SSI0RX 0x0000000A +#define UDMA_CH10_SSI1RX 0x0001000A +#define UDMA_CH10_UART6RX 0x0002000A +#define UDMA_CH10_WTIMER0A 0x0003000A +#define UDMA_CH10_I2C2RX 0x0004000A + +// +// Channel 11 +// +#define UDMA_CH11_SSI0TX 0x0000000B +#define UDMA_CH11_SSI1TX 0x0001000B +#define UDMA_CH11_UART6TX 0x0002000B +#define UDMA_CH11_WTIMER0B 0x0003000B +#define UDMA_CH11_I2C2TX 0x0004000B + +// +// Channel 12 +// +#define UDMA_CH12_RESERVED0 0x0000000C +#define UDMA_CH12_UART2RX 0x0001000C +#define UDMA_CH12_SSI2RX 0x0002000C +#define UDMA_CH12_WTIMER1A 0x0003000C +#define UDMA_CH12_GPIOK 0x0004000C + +// +// Channel 13 +// +#define UDMA_CH13_RESERVED0 0x0000000D +#define UDMA_CH13_UART2TX 0x0001000D +#define UDMA_CH13_SSI2TX 0x0002000D +#define UDMA_CH13_WTIMER1B 0x0003000D +#define UDMA_CH13_GPIOL 0x0004000D + +// +// Channel 14 +// +#define UDMA_CH14_ADC0_0 0x0000000E +#define UDMA_CH14_TIMER2A 0x0001000E +#define UDMA_CH14_SSI3RX 0x0002000E +#define UDMA_CH14_GPIOE 0x0003000E +#define UDMA_CH14_GPIOM 0x0004000E + +// +// Channel 15 +// +#define UDMA_CH15_ADC0_1 0x0000000F +#define UDMA_CH15_TIMER2B 0x0001000F +#define UDMA_CH15_SSI3TX 0x0002000F +#define UDMA_CH15_GPIOF 0x0003000F +#define UDMA_CH15_GPION 0x0004000F + +// +// Channel 16 +// +#define UDMA_CH16_ADC0_2 0x00000010 +#define UDMA_CH16_RESERVED1 0x00010010 +#define UDMA_CH16_UART3RX 0x00020010 +#define UDMA_CH16_WTIMER2A 0x00030010 +#define UDMA_CH16_GPIOP 0x00040010 + +// +// Channel 17 +// +#define UDMA_CH17_ADC0_3 0x00000011 +#define UDMA_CH17_RESERVED1 0x00010011 +#define UDMA_CH17_UART3TX 0x00020011 +#define UDMA_CH17_WTIMER2B 0x00030011 +#define UDMA_CH17_RESERVED4 0x00040011 + +// +// Channel 18 +// +#define UDMA_CH18_TIMER0A 0x00000012 +#define UDMA_CH18_TIMER1A 0x00010012 +#define UDMA_CH18_UART4RX 0x00020012 +#define UDMA_CH18_GPIOB 0x00030012 +#define UDMA_CH18_I2C3RX 0x00040012 + +// +// Channel 19 +// +#define UDMA_CH19_TIMER0B 0x00000013 +#define UDMA_CH19_TIMER1B 0x00010013 +#define UDMA_CH19_UART4TX 0x00020013 +#define UDMA_CH19_GPIOG 0x00030013 +#define UDMA_CH19_I2C3TX 0x00040013 + +// +// Channel 20 +// +#define UDMA_CH20_TIMER1A 0x00000014 +#define UDMA_CH20_RESERVED1 0x00010014 +#define UDMA_CH20_UART7RX 0x00020014 +#define UDMA_CH20_GPIOH 0x00030014 +#define UDMA_CH20_I2C4RX 0x00040014 + +// +// Channel 21 +// +#define UDMA_CH21_TIMER1B 0x00000015 +#define UDMA_CH21_RESERVED1 0x00010015 +#define UDMA_CH21_UART7TX 0x00020015 +#define UDMA_CH21_GPIOJ 0x00030015 +#define UDMA_CH21_I2C4TX 0x00040015 + +// +// Channel 22 +// +#define UDMA_CH22_UART1RX 0x00000016 +#define UDMA_CH22_RESERVED1 0x00010016 +#define UDMA_CH22_RESERVED2 0x00020016 +#define UDMA_CH22_LPC0_2 0x00030016 +#define UDMA_CH22_I2C5RX 0x00040016 + +// +// Channel 23 +// +#define UDMA_CH23_UART1TX 0x00000017 +#define UDMA_CH23_RESERVED1 0x00010017 +#define UDMA_CH23_RESERVED2 0x00020017 +#define UDMA_CH23_LPC0_1 0x00030017 +#define UDMA_CH23_I2C5TX 0x00040017 + +// +// Channel 24 +// +#define UDMA_CH24_SSI1RX 0x00000018 +#define UDMA_CH24_ADC1_0 0x00010018 +#define UDMA_CH24_RESERVED2 0x00020018 +#define UDMA_CH24_WTIMER3A 0x00030018 +#define UDMA_CH24_GPIOQ 0x00040018 + +// +// Channel 25 +// +#define UDMA_CH25_SSI1TX 0x00000019 +#define UDMA_CH25_ADC1_1 0x00010019 +#define UDMA_CH25_RESERVED2 0x00020019 +#define UDMA_CH25_WTIMER3B 0x00030019 +#define UDMA_CH25_RESERVED4 0x00040019 + +// +// Channel 26 +// +#define UDMA_CH26_RESERVED0 0x0000001A +#define UDMA_CH26_ADC1_2 0x0001001A +#define UDMA_CH26_RESERVED2 0x0002001A +#define UDMA_CH26_WTIMER4A 0x0003001A +#define UDMA_CH26_RESERVED4 0x0004001A + +// +// Channel 27 +// +#define UDMA_CH27_RESERVED0 0x0000001B +#define UDMA_CH27_ADC1_3 0x0001001B +#define UDMA_CH27_RESERVED2 0x0002001B +#define UDMA_CH27_WTIMER4B 0x0003001B +#define UDMA_CH27_RESERVED4 0x0004001B + +// +// Channel 28 +// +#define UDMA_CH28_RESERVED0 0x0000001C +#define UDMA_CH28_RESERVED1 0x0001001C +#define UDMA_CH28_RESERVED2 0x0002001C +#define UDMA_CH28_WTIMER5A 0x0003001C +#define UDMA_CH28_RESERVED4 0x0004001C + +// +// Channel 29 +// +#define UDMA_CH29_RESERVED0 0x0000001D +#define UDMA_CH29_RESERVED1 0x0001001D +#define UDMA_CH29_RESERVED2 0x0002001D +#define UDMA_CH29_WTIMER5B 0x0003001D +#define UDMA_CH29_RESERVED4 0x0004001D + +// +// Channel 30 +// +#define UDMA_CH30_SW 0x0000001E +#define UDMA_CH30_RESERVED1 0x0001001E +#define UDMA_CH30_RESERVED2 0x0002001E +#define UDMA_CH30_RESERVED3 0x0003001E +#define UDMA_CH30_RESERVED4 0x0004001E + +// +// Channel 31 +// +#define UDMA_CH31_RESERVED0 0x0000001F +#define UDMA_CH31_RESERVED1 0x0001001F +#define UDMA_CH31_RESERVED2 0x0002001F +#define UDMA_CH31_LPC0_0 0x0003001F +#define UDMA_CH31_RESERVED4 0x0004001F + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void uDMAEnable(void); +extern void uDMADisable(void); +extern unsigned long uDMAErrorStatusGet(void); +extern void uDMAErrorStatusClear(void); +extern void uDMAChannelEnable(unsigned long ulChannelNum); +extern void uDMAChannelDisable(unsigned long ulChannelNum); +extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); +extern void uDMAControlBaseSet(void *pControlTable); +extern void *uDMAControlBaseGet(void); +extern void *uDMAControlAlternateBaseGet(void); +extern void uDMAChannelRequest(unsigned long ulChannelNum); +extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, + unsigned long ulAttr); +extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, + unsigned long ulAttr); +extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); +extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl); +extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, + void *pvDstAddr, + unsigned long ulTransferSize); +extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, + unsigned ulTaskCount, void *pvTaskList, + unsigned long ulIsPeriphSG); +extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); +extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); +extern void uDMAIntRegister(unsigned long ulIntChannel, + void (*pfnHandler)(void)); +extern void uDMAIntUnregister(unsigned long ulIntChannel); +extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs); +extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs); +extern unsigned long uDMAIntStatus(void); +extern void uDMAIntClear(unsigned long ulChanMask); +extern void uDMAChannelAssign(unsigned long ulMapping); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ diff --git a/driverlib/usb.c b/driverlib/usb.c new file mode 100644 index 0000000..5f83a6b --- /dev/null +++ b/driverlib/usb.c @@ -0,0 +1,4066 @@ +//***************************************************************************** +// +// usb.c - Driver for the USB Interface. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usb_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_usb.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "driverlib/udma.h" +#include "driverlib/usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#ifndef DEPRECATED +#define USB_INT_RX_SHIFT 8 +#endif +#define USB_INTEP_RX_SHIFT 16 + +//***************************************************************************** +// +// Amount to shift the status interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#ifndef DEPRECATED +#define USB_INT_STATUS_SHIFT 24 +#endif + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16 + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ulBase specifies the USB module base address. +// \param ulEndpoint is the endpoint index to target for this write. +// \param ulIndexedReg is the indexed register to write to. +// \param ucValue is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulIndexedReg, unsigned long ulValue, + unsigned long ulSize) +{ + unsigned long ulIndex; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) || + (ulEndpoint == 3)); + ASSERT((ulSize == 1) || (ulSize == 2)); + + // + // Save the old index in case it was in use. + // + ulIndex = HWREGB(ulBase + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint; + + // + // Determine the size of the register value. + // + if(ulSize == 1) + { + // + // Set the value. + // + HWREGB(ulBase + ulIndexedReg) = ulValue; + } + else + { + // + // Set the value. + // + HWREGH(ulBase + ulIndexedReg) = ulValue; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ulBase + USB_O_EPIDX) = ulIndex; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ulBase specifies the USB module base address. +// \param ulEndpoint is the endpoint index to target for this write. +// \param ulIndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static unsigned long +USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulIndexedReg, unsigned long ulSize) +{ + unsigned char ulIndex; + unsigned char ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) || + (ulEndpoint == 3)); + ASSERT((ulSize == 1) || (ulSize == 2)); + + // + // Save the old index in case it was in use. + // + ulIndex = HWREGB(ulBase + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint; + + // + // Determine the size of the register value. + // + if(ulSize == 1) + { + // + // Get the value. + // + ulValue = HWREGB(ulBase + ulIndexedReg); + } + else + { + // + // Get the value. + // + ulValue = HWREGH(ulBase + ulIndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ulBase + USB_O_EPIDX) = ulIndex; + + // + // Return the register's value. + // + return(ulValue); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ulBase specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ulBase specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(unsigned long ulBase, tBoolean bStart) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ulBase specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(unsigned long ulBase, tBoolean bStart) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns either \b USB_LOW_SPEED, \b USB_FULL_SPEED, or +//! \b USB_UNDEF_SPEED. +// +//***************************************************************************** +unsigned long +USBHostSpeedGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Returns the status of the USB interrupts. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function reads the source of the interrupt for the USB controller. +//! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints, +//! and general status changes. This call returns the current status for +//! all of these interrupts. The bit values returned should be compared +//! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0, +//! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values. +//! +//! \note This call clears the source of all of the general status interrupts. +//! +//! \note WARNING: This API cannot be used on endpoint numbers greater than +//! endpoint 3 so USBIntStatusControl() or USBIntStatusEndpoint() should be +//! used instead. +//! +//! \return Returns the status of the sources for the USB controller's +//! interrupt. +// +//***************************************************************************** +#ifndef DEPRECATED +unsigned long +USBIntStatus(unsigned long ulBase) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Get the transmit interrupt status. + // + ulStatus = (HWREGB(ulBase + USB_O_TXIS)); + + // + // Get the receive interrupt status, these bits go into the second byte of + // the returned value. + // + ulStatus |= (HWREGB(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ulStatus |= (HWREGB(ulBase + USB_O_IS) << USB_INT_STATUS_SHIFT); + + // + // Add the power fault status. + // + if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ulStatus |= USB_INT_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection was detected. + // + ulStatus |= USB_INT_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ulStatus); +} +#endif + +//***************************************************************************** +// +//! Disables the sources for USB interrupts. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which interrupts to disable. +//! +//! This function disables the USB controller from generating the +//! interrupts indicated by the \e ulFlags parameter. There are three groups +//! of interrupt sources, IN Endpoints, OUT Endpoints, and general status +//! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT, +//! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS. If +//! \b USB_INT_ALL is specified, then all interrupts are disabled. +//! +//! \note WARNING: This API cannot be used on endpoint numbers greater than +//! endpoint 3 so USBIntDisableControl() or USBIntDisableEndpoint() should be +//! used instead. +//! +//! \return None. +// +//***************************************************************************** +#ifndef DEPRECATED +void +USBIntDisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_INT_ALL)) == 0); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) + { + HWREGH(ulBase + USB_O_TXIE) &= + ~(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)); + } + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) + { + HWREGH(ulBase + USB_O_RXIE) &= + ~((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >> + USB_INT_RX_SHIFT); + } + + // + // If any general interrupts were disabled, then write the general + // interrupt settings out to the hardware. + // + if(ulFlags & USB_INT_STATUS) + { + HWREGB(ulBase + USB_O_IE) &= + ~((ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT); + } + + // + // Disable the power fault interrupt. + // + if(ulFlags & USB_INT_POWER_FAULT) + { + HWREG(ulBase + USB_O_EPCIM) = 0; + } + + // + // Disable the ID pin detect interrupt. + // + if(ulFlags & USB_INT_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = 0; + } +} +#endif + +//***************************************************************************** +// +//! Enables the sources for USB interrupts. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which interrupts to enable. +//! +//! This function enables the USB controller's ability to generate the +//! interrupts indicated by the \e ulFlags parameter. There are three +//! groups of interrupt sources, IN Endpoints, OUT Endpoints, and +//! general status changes, specified by \b USB_INT_HOST_IN, +//! \b USB_INT_HOST_OUT, \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and +//! \b USB_STATUS. If \b USB_INT_ALL is specified then all interrupts are +//! enabled. +//! +//! \note A call must be made to enable the interrupt in the main interrupt +//! controller to receive interrupts. The USBIntRegister() API performs this +//! controller-level interrupt enable. However if static interrupt handlers +//! are used, then then a call to IntEnable() must be made in order to allow +//! any USB interrupts to occur. +//! +//! \note WARNING: This API cannot be used on endpoint numbers greater than +//! endpoint 3 so USBIntEnableControl() or USBIntEnableEndpoint() should be +//! used instead. +//! +//! \return None. +// +//***************************************************************************** +#ifndef DEPRECATED +void +USBIntEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & (~USB_INT_ALL)) == 0); + + // + // If any transmit interrupts were enabled, then write the transmit + // interrupt settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) + { + HWREGH(ulBase + USB_O_TXIE) |= + ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0); + } + + // + // If any receive interrupts were enabled, then write the receive + // interrupt settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) + { + HWREGH(ulBase + USB_O_RXIE) |= + ((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >> + USB_INT_RX_SHIFT); + } + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ulFlags & USB_INT_STATUS) + { + HWREGB(ulBase + USB_O_IE) |= + (ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT; + } + + // + // Enable the power fault interrupt. + // + if(ulFlags & USB_INT_POWER_FAULT) + { + HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ulFlags & USB_INT_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; + } +} +#endif + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies +//! which control interrupts to disable. The flags passed in the \e ulFlags +//! parameters should be the definitions that start with \b USB_INTCTRL_* and +//! not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ulFlags & USB_INTCTRL_STATUS) + { + HWREGB(ulBase + USB_O_IE) &= ~(ulFlags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ulFlags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ulBase + USB_O_EPCIM) = 0; + } + + // + // Disable the ID pin detect interrupt. + // + if(ulFlags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = 0; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies +//! which control interrupts to enable. The flags passed in the \e ulFlags +//! parameters should be the definitions that start with \b USB_INTCTRL_* and +//! not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & (~USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ulFlags & USB_INTCTRL_STATUS) + { + HWREGB(ulBase + USB_O_IE) |= ulFlags; + } + + // + // Enable the power fault interrupt. + // + if(ulFlags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ulFlags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned should be compared against the \b USB_INTCTRL_* +//! values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame. (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device. (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected. (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +unsigned long +USBIntStatusControl(unsigned long ulBase) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ulStatus = HWREGB(ulBase + USB_O_IS); + + // + // Add the power fault status. + // + if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ulStatus |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ulStatus |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ulBase parameter. The \e ulFlags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ulFlags +//! parameters should be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ulBase + USB_O_TXIE) &= + ~(ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive interrupt + // settings out to the hardware. + // + HWREGH(ulBase + USB_O_RXIE) &= + ~((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ulBase parameter. The \e ulFlags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ulFlags +//! parameters should be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ulBase + USB_O_TXIE) |= + ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ulBase + USB_O_RXIE) |= + ((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned should be compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +unsigned long +USBIntStatusEndpoint(unsigned long ulBase) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Get the transmit interrupt status. + // + ulStatus = HWREGH(ulBase + USB_O_TXIS); + + ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! \param pfnHandler is a pointer to the function to be called when a USB +//! interrupt occurs. +//! +//! This function registers the handler to be called when a USB interrupt +//! occurs and enables the global USB interrupt in the interrupt controller. +//! The specific desired USB interrupts must be enabled via a separate call to +//! USBIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt sources via calls to USBIntStatusControl() and +//! USBIntStatusEndpoint(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_USB0, pfnHandler); + + // + // Enable the USB interrupt. + // + IntEnable(INT_USB0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function unregisters the interrupt handler. This function also +//! disables the USB interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering or +//! unregistering interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable the USB interrupt. + // + IntDisable(INT_USB0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_USB0); +} + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions should be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +unsigned long +USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the TX portion of the endpoint status. + // + ulStatus = HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ulStatus |= ((HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1)) << + USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags are the status bits that should be cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned +//! from the USBEndpointStatus() call. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Clear the specified flags for the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + HWREGB(ulBase + USB_O_CSRL0) &= ~ulFlags; + } + else + { + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= ~ulFlags; + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(ulFlags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags are the status bits that should be cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned +//! from the USBEndpointStatus() call. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ulEndpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ulFlags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ulFlags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ulFlags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ulBase + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN should be cleared. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(ulFlags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // should be cleared. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~((ulFlags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ulFlags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ulFlags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ulFlags parameter is ignored for endpoint zero. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint, + tBoolean bDataToggle, unsigned long ulFlags) +{ + unsigned long ulDataToggle; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // The data toggle defaults to DATA0. + // + ulDataToggle = 0; + + // + // See if the data toggle should be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulDataToggle = USB_CSRH0_DT; + } + else if(ulFlags == USB_EP_HOST_IN) + { + ulDataToggle = USB_RXCSRH1_DT; + } + else + { + ulDataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ulBase + USB_O_CSRH0) = + ((HWREGB(ulBase + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ulDataToggle | USB_CSRH0_DTWE)); + } + else if(ulFlags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) = + ((HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ulDataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) = + ((HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ulDataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies the endpoint to reset the data toggle. +//! \param ulFlags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ulFlags parameter should be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive data toggle should be cleared. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies the endpoint to stall. +//! \param ulFlags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN, then the stall +//! is issued on the IN portion of this endpoint. If the \e ulFlags parameter +//! is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion of this +//! endpoint. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0) + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Determine how to stall this endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ulBase + USB_O_CSRL0) |= + (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + } + else if(ulFlags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies which endpoint to remove the stall condition. +//! \param ulFlags specifies whether to remove the stall condition from the IN +//! or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN, then the stall +//! is cleared on the IN portion of this endpoint. If the \e ulFlags parameter +//! is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT portion of this +//! endpoint. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0) + + // + // Determine how to clear the stall on this endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ulFlags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulAddress is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ulBase + USB_O_FADDR) = (unsigned char)ulAddress; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function should only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +unsigned long +USBDevAddrGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Return the function address. + // + return(HWREGB(ulBase + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulMaxPayload is the maximum payload for this endpoint. +//! \param ulNAKPollInterval is the either the NAK timeout limit or the polling +//! interval, depending on the type of endpoint. +//! \param ulTargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ulFlags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ulFlags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ulFlags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ulNAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is simply the number of +//! frames between polling an interrupt endpoint. For isochronous endpoints +//! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1) +//! frames. When used as a NAK timeout, the \e ulNAKPollInterval value +//! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out. +//! There are two special time out values that can be specified when setting +//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is +//! the maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT, which indicates that there should be no limit on the +//! number of NAKs. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ulMaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ulMaxPayload bytes. The \b USB_EP_AUTO_CLEAR +//! bit can be used to clear the data packet ready flag automatically once the +//! data has been read from the FIFO. If this option is not used, this flag +//! must be manually cleared via a call to USBDevEndpointStatusClear() or +//! USBHostEndpointStatusClear(). +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulMaxPayload, + unsigned long ulNAKPollInterval, + unsigned long ulTargetEndpoint, unsigned long ulFlags) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + ASSERT(ulNAKPollInterval <= MAX_NAK_LIMIT); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ulEndpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ulBase + USB_O_NAKLMT) = ulNAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ulBase + USB_O_TYPE0) = + ((ulFlags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ulRegister = ulTargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ulFlags & USB_EP_SPEED_FULL) + { + ulRegister |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ulRegister |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ulFlags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ulRegister |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ulRegister |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ulRegister |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ulRegister |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXTYPE1) = + ulRegister; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXINTERVAL1) = + ulNAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) = + ulMaxPayload; + + // + // Set the transmit control value to zero. + // + ulRegister = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ulFlags & USB_EP_AUTO_SET) + { + ulRegister |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) = + (unsigned char)ulRegister; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXTYPE1) = + ulRegister; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXINTERVAL1) = + ulNAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXMAXP1) = + ulMaxPayload; + + // + // Set the receive control value to zero. + // + ulRegister = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ulFlags & USB_EP_AUTO_CLEAR) + { + ulRegister |= USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA Mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) = + (unsigned char)ulRegister; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulMaxPacketSize is the maximum packet size for this endpoint. +//! \param ulFlags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! should not be called for endpoint zero. The \e ulFlags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ulMaxPacketSize more bytes of data. Also for +//! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data +//! packet ready flag automatically once the data has been read from the FIFO. +//! If this option is not used, this flag must be manually cleared via a call +//! to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulMaxPacketSize, unsigned long ulFlags) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ulFlags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) = + ulMaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ulRegister = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ulFlags & USB_EP_AUTO_SET) + { + ulRegister |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ulRegister |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) = + (unsigned char)ulRegister; + + // + // Reset the Data toggle to zero. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXMAXP1) = + ulMaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ulRegister = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ulFlags & USB_EP_AUTO_CLEAR) + { + ulRegister = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ulRegister |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) = + (unsigned char)ulRegister; + + // + // Reset the Data toggle to zero. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pulMaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pulFlags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are +//! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to +//! USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long *pulMaxPacketSize, + unsigned long *pulFlags) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT(pulMaxPacketSize && pulFlags); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pulFlags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pulFlags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pulMaxPacketSize = (unsigned long)HWREGH(ulBase + + EP_OFFSET(ulEndpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if(ulRegister & USB_TXCSRH1_AUTOSET) + { + *pulFlags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ulRegister & USB_TXCSRH1_DMAEN) + { + if(ulRegister & USB_TXCSRH1_DMAMOD) + { + *pulFlags |= USB_EP_DMA_MODE_1; + } + else + { + *pulFlags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ulRegister & USB_TXCSRH1_ISO) + { + *pulFlags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pulFlags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pulFlags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pulMaxPacketSize = (unsigned long)HWREGH(ulBase + + EP_OFFSET(ulEndpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if(ulRegister & USB_RXCSRH1_AUTOCL) + { + *pulFlags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ulRegister & USB_RXCSRH1_DMAEN) + { + if(ulRegister & USB_RXCSRH1_DMAMOD) + { + *pulFlags |= USB_EP_DMA_MODE_1; + } + else + { + *pulFlags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ulRegister & USB_RXCSRH1_ISO) + { + *pulFlags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pulFlags |= USB_EP_MODE_BULK; + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFIFOAddress is the starting address for the FIFO. +//! \param ulFIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ulFlags specifies what information to set in the FIFO configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ulFIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering, +//! it should use the values with the \b _DB at the end of the value. For +//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16- +//! byte, double-buffered FIFO. If a double-buffered FIFO is used, then the +//! actual size of the FIFO is twice the size indicated by the \e ulFIFOSize +//! parameter. For example, the \b USB_FIFO_SZ_16_DB value uses 32 bytes of +//! the USB controller's FIFO memory. +//! +//! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO should start 64 bytes into +//! the USB controller's FIFO memory. The \e ulFlags value specifies whether +//! the endpoint's OUT or IN FIFO should be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFIFOAddress, unsigned long ulFIFOSize, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOSZ, ulFIFOSize, 1); + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOADD, + ulFIFOAddress >> 3, 2); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOSZ, ulFIFOSize, 1); + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOADD, + ulFIFOAddress >> 3, 2); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pulFIFOAddress is the starting address for the FIFO. +//! \param pulFIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ulFlags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function should not be called for endpoint zero. The +//! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should +//! be read. If in host mode, the \e ulFlags parameter should be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long *pulFIFOAddress, unsigned long *pulFIFOSize, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_TXFIFOADD, + 2)) << 3; + *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_TXFIFOSZ, 1); + + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_RXFIFOADD, + 2)) << 3; + *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_RXFIFOSZ, 1); + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags specifies which direction and what mode to use when enabling +//! DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ulFlags parameter. The \e ulFlags +//! parameter should have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ulFlags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The ulFlags should be +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ulFlags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +unsigned long +USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pucData is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pulSize is initially the size of the buffer passed into this call +//! via the \e pucData parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pulSize parameter should indicate the size of the buffer passed in +//! the \e pulData parameter. The data in the \e pulSize parameter is changed +//! to match the amount of data returned in the \e pucData parameter. If a +//! zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pulSize parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +long +USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long *pulSize) +{ + unsigned long ulRegister, ulByteCount, ulFIFO; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pulSize = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ulByteCount = HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint); + + // + // Determine how many bytes are copied. + // + ulByteCount = (ulByteCount < *pulSize) ? ulByteCount : *pulSize; + + // + // Return the number of bytes we are going to read. + // + *pulSize = ulByteCount; + + // + // Calculate the FIFO address. + // + ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ulByteCount > 0; ulByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pucData++ = HWREGB(ulFIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint, + tBoolean bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Determine which endpoint is being acked. + // + if(ulEndpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ulBase + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Clear RxPktRdy. + // + if(ulEndpoint == USB_EP_0) + { + HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pucData is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ulSize is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pucData parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! should be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +long +USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long ulSize) +{ + unsigned long ulFIFO; + unsigned char ucTxPktRdy; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ucTxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ucTxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & ucTxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ulSize > 0; ulSize--) + { + HWREGB(ulFIFO) = *pucData++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulTransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function should be called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ulTransType parameter allows +//! the appropriate signaling on the USB bus for the type of transaction being +//! requested. The \e ulTransType parameter should be one of the following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +long +USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulTransType) +{ + unsigned long ulTxPktRdy; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ulBase + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ulTxPktRdy = ulTransType & 0xff; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ulTxPktRdy = (ulTransType >> 8) & 0xff; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) = ulTxPktRdy; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags specifies if the IN or OUT endpoint should be accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ulEndpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ulBase + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ulBase + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function should only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ulBase + ulRegister) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is +//! still pending. This function should be used to safely disable any +//! scheduled IN transactions if the endpoint specified by \e ulEndpoint +//! is reconfigured for communications with other devices. +//! +//! \note This function should only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ulBase + ulRegister) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ulBase + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulAddr is the functional address for the controller to use for this +//! endpoint. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ulAddr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ulFlags parameter indicates if the IN or OUT endpoint should be set. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive address should be set. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)) = ulAddr; + } + else + { + // + // Set the receive address. + // + HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ulFlags parameter determines if +//! the IN or OUT endpoint's device address is returned. +//! +//! \note This function should only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +unsigned long +USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive address should be returned. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulAddr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 8 through 15 with the +//! port number in bits 0 through 6. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ulFlags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of \b +//! USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with \b +//! USB_EP_SPEED_LOW. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is being set. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ulEndpoint == USB_EP_0) + { + if(ulFlags & USB_EP_SPEED_FULL) + { + HWREGB(ulBase + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ulBase + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ulFlags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function should only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +unsigned long +USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address should be returned. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note The following values have been deprecated and should no longer be +//! used. +//! - \b USB_HOST_PWREN_LOW - Automatically drive USBnEPEN low when power is +//! enabled. +//! - \b USB_HOST_PWREN_HIGH - Automatically drive USBnEPEN high when power is +//! enabled. +//! - \b USB_HOST_PWREN_VBLOW - Automatically drive USBnEPEN low when power is +//! enabled. +//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power +//! is enabled. +//! +//! \note This function should only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ulBase + USB_O_VDC) = ulFlags >> 16; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ulBase + USB_O_EPC) = + (ulFlags | (HWREGH(ulBase + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function should not be used. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ulBase + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ulBase + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +unsigned long +USBFrameNumberGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ulBase + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ulBase specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ulBase + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ulBase + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint) +{ + // + // Return the FIFO address for this endpoint. + // + return(ulBase + USB_O_FIFO0 + (ulEndpoint >> 2)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +unsigned long +USBModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ulBase + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies which endpoint's FIFO address to return. +//! \param ulChannel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that should be passed into the +//! \e ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulChannel) +{ + unsigned long ulMask; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ulMask = 0xf << (ulChannel * 4); + + // + // Clear out the current selection for the channel. + // + ulMask = HWREG(ulBase + USB_O_DMASEL) & (~ulMask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ulMask |= (USB_EP_TO_INDEX(ulEndpoint)) << (ulChannel * 4); + + // + // Write the value out to the register. + // + HWREG(ulBase + USB_O_DMASEL) = ulMask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function should only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function should only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ulBase + USB_O_GPCS) = 0; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(unsigned long ulBase) +{ + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function should +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(unsigned long ulBase) +{ + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +unsigned long +USBNumEndpointsGet(unsigned long ulBase) +{ + if(CLASS_IS_SANDSTORM || CLASS_IS_FURY) + { + // + // These part families do not support USB. + // + return(0); + } + else if(CLASS_IS_DUSTDEVIL) + { + // + // DustDevil class devices support 3 endpoint pairs. + // + return(3); + } + else if(CLASS_IS_TEMPEST || CLASS_IS_FIRESTORM) + { + // + // Tempest and Firestorm class devices support 15 endpoint pairs. + // + return(15); + } + else if(CLASS_IS_BLIZZARD) + { + // + // Blizzard class devices support 7 endpoint pairs. + // + return(7); + } + else + { + // + // The device class is not recognized so default to assuming no USB + // support. + // + return(0); + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/usb.h b/driverlib/usb.h new file mode 100644 index 0000000..d7c91a7 --- /dev/null +++ b/driverlib/usb.h @@ -0,0 +1,587 @@ +//***************************************************************************** +// +// usb.h - Prototypes for the USB Interface Driver. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __USB_H__ +#define __USB_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ulFlags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ulFlags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ulFlags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as +// the ulFlags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#ifndef DEPRECATED +#define USB_HOST_PWREN_LOW 0x00000002 +#define USB_HOST_PWREN_HIGH 0x00000003 +#define USB_HOST_PWREN_VBLOW 0x00000002 +#define USB_HOST_PWREN_VBHIGH 0x00000003 +#endif +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ulNAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define USB_EP_8 0x00000080 // Endpoint 8 +#define USB_EP_9 0x00000090 // Endpoint 9 +#define USB_EP_10 0x000000A0 // Endpoint 10 +#define USB_EP_11 0x000000B0 // Endpoint 11 +#define USB_EP_12 0x000000C0 // Endpoint 12 +#define USB_EP_13 0x000000D0 // Endpoint 13 +#define USB_EP_14 0x000000E0 // Endpoint 14 +#define USB_EP_15 0x000000F0 // Endpoint 15 +#define NUM_USB_EP 16 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define INDEX_TO_USB_EP(x) ((x) << 4) +#define USB_EP_TO_INDEX(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ulFIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010 +#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \ + (((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ulTransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long USBDevAddrGet(unsigned long ulBase); +extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress); +extern void USBDevConnect(unsigned long ulBase); +extern void USBDevDisconnect(unsigned long ulBase); +extern void USBDevEndpointConfigSet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulMaxPacketSize, + unsigned long ulFlags); +extern void USBDevEndpointConfigGet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long *pulMaxPacketSize, + unsigned long *pulFlags); +extern void USBDevEndpointDataAck(unsigned long ulBase, + unsigned long ulEndpoint, + tBoolean bIsLastPacket); +extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBDevEndpointStallClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBDevEndpointStatusClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBEndpointDataAvail(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBEndpointDMADisable(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long *pulSize); +extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long ulSize); +extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulTransType); +extern void USBEndpointDataToggleClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBEndpointStatus(unsigned long ulBase, + unsigned long ulEndpoint); +extern unsigned long USBFIFOAddrGet(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long *pulFIFOAddress, + unsigned long *pulFIFOSize, + unsigned long ulFlags); +extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFIFOAddress, + unsigned long ulFIFOSize, unsigned long ulFlags); +extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBFrameNumberGet(unsigned long ulBase); +extern unsigned long USBHostAddrGet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags); +extern void USBHostEndpointConfig(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulMaxPacketSize, + unsigned long ulNAKPollInterval, + unsigned long ulTargetEndpoint, + unsigned long ulFlags); +extern void USBHostEndpointDataAck(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBHostEndpointDataToggle(unsigned long ulBase, + unsigned long ulEndpoint, + tBoolean bDataToggle, + unsigned long ulFlags); +extern void USBHostEndpointStatusClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBHostHubAddrGet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags); +extern void USBHostPwrDisable(unsigned long ulBase); +extern void USBHostPwrEnable(unsigned long ulBase); +extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags); +#ifndef DEPRECATED +#define USBHostPwrFaultConfig USBHostPwrConfig +#endif +extern void USBHostPwrFaultDisable(unsigned long ulBase); +extern void USBHostPwrFaultEnable(unsigned long ulBase); +extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint); +extern void USBHostRequestINClear(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBHostRequestStatus(unsigned long ulBase); +extern void USBHostReset(unsigned long ulBase, tBoolean bStart); +extern void USBHostResume(unsigned long ulBase, tBoolean bStart); +extern unsigned long USBHostSpeedGet(unsigned long ulBase); +extern void USBHostSuspend(unsigned long ulBase); +extern void USBIntDisableControl(unsigned long ulBase, + unsigned long ulIntFlags); +extern void USBIntEnableControl(unsigned long ulBase, + unsigned long ulIntFlags); +extern unsigned long USBIntStatusControl(unsigned long ulBase); +extern void USBIntDisableEndpoint(unsigned long ulBase, + unsigned long ulIntFlags); +extern void USBIntEnableEndpoint(unsigned long ulBase, + unsigned long ulIntFlags); +extern unsigned long USBIntStatusEndpoint(unsigned long ulBase); +extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void USBIntUnregister(unsigned long ulBase); +extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart); +extern unsigned long USBModeGet(unsigned long ulBase); +extern void USBEndpointDMAChannel(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulChannel); +extern void USBHostMode(unsigned long ulBase); +extern void USBDevMode(unsigned long ulBase); +extern void USBOTGMode(unsigned long ulBase); +extern void USBPHYPowerOff(unsigned long ulBase); +extern void USBPHYPowerOn(unsigned long ulBase); +extern unsigned long USBNumEndpointsGet(unsigned long ulBase); + +//***************************************************************************** +// +// Several USB APIs have been renamed, with the original function name being +// deprecated. These defines and function prototypes provide backward +// compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +// +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0F // All Interrupt sources +#define USB_INT_STATUS 0xFF000000 // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error +#define USB_INT_SESSION_START 0x40000000 // Session Start Detected +#define USB_INT_SESSION_END 0x20000000 // Session End Detected +#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected +#define USB_INT_CONNECT 0x10000000 // Device Connect Detected +#define USB_INT_SOF 0x08000000 // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000 // Babble signaled +#define USB_INT_RESET 0x04000000 // Reset signaled +#define USB_INT_RESUME 0x02000000 // Resume detected +#define USB_INT_SUSPEND 0x01000000 // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt + +#define USBDevEndpointConfig USBDevEndpointConfigSet +extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long USBIntStatus(unsigned long ulBase); +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __USB_H__ diff --git a/driverlib/watchdog.c b/driverlib/watchdog.c new file mode 100644 index 0000000..c417a9c --- /dev/null +++ b/driverlib/watchdog.c @@ -0,0 +1,628 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_watchdog.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function checks to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function enables the watchdog timer counter and interrupt. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogResetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; +} + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogResetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Disable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function locks out write access to the watchdog timer configuration +//! registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function enables write access to the watchdog timer configuration +//! registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function also enables the global interrupt in the interrupt controller; the +//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note For parts with a watchdog timer module that has the ability to +//! generate an NMI instead of a standard interrupt, this function registers +//! the standard watchdog interrupt handler. To register the NMI watchdog +//! handler, use IntRegister() to register the handler for the +//! \b FAULT_NMI interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note For parts with a watchdog timer module that has the ability to +//! generate an NMI instead of a standard interrupt, this function unregisters +//! the standard watchdog interrupt handler. To unregister the NMI watchdog +//! handler, use IntUnregister() to unregister the handler for the +//! \b FAULT_NMI interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG); +} + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function enables the watchdog timer interrupt. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable the watchdog interrupt. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the watchdog timer module. +//! Either the raw interrupt status or the status of interrupt that is allowed +//! to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, where a 1 indicates that the +//! watchdog interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! Sets the type of interrupt generated by the watchdog. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulType is the type of interrupt to generate. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. \e ulType can be either \b WATCHDOG_INT_TYPE_INT to +//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to +//! generate a non-maskable interrupt (NMI). +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with WatchdogIntClear(). +//! +//! \note The ability to select an NMI interrupt varies with the Stellaris part +//! in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + ASSERT((ulType == WATCHDOG_INT_TYPE_INT) || + (ulType == WATCHDOG_INT_TYPE_NMI)); + + // + // Set the interrupt type. + // + HWREG(ulBase + WDT_O_CTL) = + (HWREG(ulBase + WDT_O_CTL) & ~WDT_CTL_INTTYPE) | ulType; +} + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/driverlib/watchdog.h b/driverlib/watchdog.h new file mode 100644 index 0000000..ca6b12f --- /dev/null +++ b/driverlib/watchdog.h @@ -0,0 +1,95 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ -- cgit v1.3.1