From 2dcbdfe198fe21956aaee154747a56a7250901ef Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Thu, 1 Nov 2012 21:20:41 +0200 Subject: Implemented PWM on project1 --- boards/ek-lm4f120xl/project1/Makefile | 34 +++ boards/ek-lm4f120xl/project1/gcc/project1.axf | Bin 0 -> 36774 bytes boards/ek-lm4f120xl/project1/gcc/project1.bin | Bin 0 -> 1976 bytes boards/ek-lm4f120xl/project1/project1.c | 44 ++++ boards/ek-lm4f120xl/project1/project1.ld | 57 +++++ boards/ek-lm4f120xl/project1/startup_gcc.c | 341 ++++++++++++++++++++++++++ 6 files changed, 476 insertions(+) create mode 100644 boards/ek-lm4f120xl/project1/Makefile create mode 100755 boards/ek-lm4f120xl/project1/gcc/project1.axf create mode 100755 boards/ek-lm4f120xl/project1/gcc/project1.bin create mode 100644 boards/ek-lm4f120xl/project1/project1.c create mode 100644 boards/ek-lm4f120xl/project1/project1.ld create mode 100644 boards/ek-lm4f120xl/project1/startup_gcc.c (limited to 'boards') diff --git a/boards/ek-lm4f120xl/project1/Makefile b/boards/ek-lm4f120xl/project1/Makefile new file mode 100644 index 0000000..27236b3 --- /dev/null +++ b/boards/ek-lm4f120xl/project1/Makefile @@ -0,0 +1,34 @@ +PART=LM4F120H5QR + +VARIANT=cm4f + +ROOT=../../.. + +include ${ROOT}/makedefs + +VPATH=../drivers +VPATH+=../../../utils + +IPATH=.. +IPATH+=../../.. + +all: ${COMPILER} +all: ${COMPILER}/project1.axf + +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +${COMPILER}: + @mkdir -p ${COMPILER} + +${COMPILER}/project1.axf: ${COMPILER}/project1.o +${COMPILER}/project1.axf: ${COMPILER}/startup_${COMPILER}.o +${COMPILER}/project1.axf: ${ROOT}/driverlib/${COMPILER}-cm4f/libdriver-cm4f.a +${COMPILER}/project1.axf: project1.ld +SCATTERgcc_project1=project1.ld +ENTRY_project1=ResetISR +CFLAGSgcc=-DTARGET_IS_BLIZZARD_RA2 + +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/ek-lm4f120xl/project1/gcc/project1.axf b/boards/ek-lm4f120xl/project1/gcc/project1.axf new file mode 100755 index 0000000..b174be0 Binary files /dev/null and b/boards/ek-lm4f120xl/project1/gcc/project1.axf differ diff --git a/boards/ek-lm4f120xl/project1/gcc/project1.bin b/boards/ek-lm4f120xl/project1/gcc/project1.bin new file mode 100755 index 0000000..0546b44 Binary files /dev/null and b/boards/ek-lm4f120xl/project1/gcc/project1.bin differ diff --git a/boards/ek-lm4f120xl/project1/project1.c b/boards/ek-lm4f120xl/project1/project1.c new file mode 100644 index 0000000..86290df --- /dev/null +++ b/boards/ek-lm4f120xl/project1/project1.c @@ -0,0 +1,44 @@ +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" + +#include "driverlib/sysctl.h" +#include "driverlib/gpio.h" +#include "driverlib/timer.h" +#include "driverlib/pin_map.h" + +int main(void) { + unsigned long ulPeriod, dutyCycle; + + // 40 MHz system clock + SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL| + SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN); + + ulPeriod = 100000; + dutyCycle = 25000; + + // Turn off LEDs + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); + GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0); + + // Configure PB6 as T0CCP0 + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + GPIOPinConfigure(GPIO_PB6_T0CCP0); + GPIOPinTypeTimer(GPIO_PORTB_BASE, GPIO_PIN_6); + + // Configure timer + SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); + TimerConfigure(TIMER0_BASE, TIMER_CFG_SPLIT_PAIR|TIMER_CFG_A_PWM); + TimerLoadSet(TIMER0_BASE, TIMER_A, ulPeriod -1); + TimerMatchSet(TIMER0_BASE, TIMER_A, dutyCycle); // PWM + TimerEnable(TIMER0_BASE, TIMER_A); + + while(1) { // The following code varies the duty cycle over time + TimerMatchSet(TIMER0_BASE, TIMER_A, dutyCycle++); + + if(dutyCycle >= ulPeriod - 1) + dutyCycle = 0; + + SysCtlDelay(50000); + } +} diff --git a/boards/ek-lm4f120xl/project1/project1.ld b/boards/ek-lm4f120xl/project1/project1.ld new file mode 100644 index 0000000..1e3b975 --- /dev/null +++ b/boards/ek-lm4f120xl/project1/project1.ld @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * project0.ld - Linker configuration file for project0. + * + * Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 9453 of the EK-LM4F120XL Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/ek-lm4f120xl/project1/startup_gcc.c b/boards/ek-lm4f120xl/project1/startup_gcc.c new file mode 100644 index 0000000..85b7513 --- /dev/null +++ b/boards/ek-lm4f120xl/project1/startup_gcc.c @@ -0,0 +1,341 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static unsigned long pulStack[64]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // CAN2 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // I2S0 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + IntDefaultHandler, // PECI 0 + IntDefaultHandler, // LPC 0 + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + IntDefaultHandler, // Fan 0 + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} -- cgit v1.3.1