From e018ceebed74b8223482bc9d1ed0b31c938381da Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Mon, 29 Oct 2012 23:04:19 +0200 Subject: New example files --- boards/ek-lm4f120xl/mpu_fault/Makefile | 91 +++ boards/ek-lm4f120xl/mpu_fault/ccs/.ccsimportspec | 8 + boards/ek-lm4f120xl/mpu_fault/ccs/.ccsproject | 12 + boards/ek-lm4f120xl/mpu_fault/ccs/.cproject | 191 +++++ boards/ek-lm4f120xl/mpu_fault/ccs/.project | 111 +++ .../ccs/.settings/org.eclipse.cdt.codan.core.prefs | 3 + .../ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.bin | Bin 0 -> 3304 bytes .../ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.out | Bin 0 -> 56469 bytes .../ek-lm4f120xl/mpu_fault/ccs/macros.ini_initial | 1 + .../ek-lm4f120xl/mpu_fault/ccs/target_config.ccxml | 13 + .../ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.bin | Bin 0 -> 2408 bytes .../ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.out | Bin 0 -> 41212 bytes boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.axf | Bin 0 -> 37025 bytes boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.bin | Bin 0 -> 2324 bytes boards/ek-lm4f120xl/mpu_fault/mpu_fault.c | 383 ++++++++++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewd | 614 ++++++++++++++++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewp | 789 +++++++++++++++++++++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.icf | 78 ++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.ld | 57 ++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.sct | 47 ++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.sgxx | Bin 0 -> 4858 bytes boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvopt | 303 ++++++++ boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvproj | 429 +++++++++++ boards/ek-lm4f120xl/mpu_fault/mpu_fault_ccs.cmd | 70 ++ .../mpu_fault/mpu_fault_sourcerygxx.ld | 39 + boards/ek-lm4f120xl/mpu_fault/readme.txt | 28 + boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.axf | Bin 0 -> 18216 bytes boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.bin | Bin 0 -> 2272 bytes .../mpu_fault/sourcerygxx/mpu_fault.axf | Bin 0 -> 504997 bytes .../mpu_fault/sourcerygxx/mpu_fault.bin | Bin 0 -> 2536 bytes boards/ek-lm4f120xl/mpu_fault/startup_ccs.c | 298 ++++++++ boards/ek-lm4f120xl/mpu_fault/startup_ewarm.c | 332 +++++++++ boards/ek-lm4f120xl/mpu_fault/startup_gcc.c | 348 +++++++++ boards/ek-lm4f120xl/mpu_fault/startup_rvmdk.S | 358 ++++++++++ .../ek-lm4f120xl/mpu_fault/startup_sourcerygxx.S | 75 ++ 35 files changed, 4678 insertions(+) create mode 100644 boards/ek-lm4f120xl/mpu_fault/Makefile create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/.ccsimportspec create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/.ccsproject create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/.cproject create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/.project create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.bin create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.out create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/macros.ini_initial create mode 100644 boards/ek-lm4f120xl/mpu_fault/ccs/target_config.ccxml create mode 100644 boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.bin create mode 100644 boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.out create mode 100644 boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.axf create mode 100644 boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.bin create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.c create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewd create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewp create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.icf create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.ld create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.sct create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.sgxx create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvopt create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvproj create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault_ccs.cmd create mode 100644 boards/ek-lm4f120xl/mpu_fault/mpu_fault_sourcerygxx.ld create mode 100644 boards/ek-lm4f120xl/mpu_fault/readme.txt create mode 100644 boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.axf create mode 100644 boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.bin create mode 100644 boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.axf create mode 100644 boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.bin create mode 100644 boards/ek-lm4f120xl/mpu_fault/startup_ccs.c create mode 100644 boards/ek-lm4f120xl/mpu_fault/startup_ewarm.c create mode 100644 boards/ek-lm4f120xl/mpu_fault/startup_gcc.c create mode 100644 boards/ek-lm4f120xl/mpu_fault/startup_rvmdk.S create mode 100644 boards/ek-lm4f120xl/mpu_fault/startup_sourcerygxx.S (limited to 'boards/ek-lm4f120xl/mpu_fault') diff --git a/boards/ek-lm4f120xl/mpu_fault/Makefile b/boards/ek-lm4f120xl/mpu_fault/Makefile new file mode 100644 index 0000000..14bdeab --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/Makefile @@ -0,0 +1,91 @@ +#****************************************************************************** +# +# Makefile - Rules for building the MPU example. +# +# Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +# +#****************************************************************************** + +# +# Defines the part type that this project uses. +# +PART=LM4F120H5QR + +# +# Set the processor variant. +# +VARIANT=cm4f + +# +# The base directory for StellarisWare. +# +ROOT=../../.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find source files that do not live in this directory. +# +VPATH=../../../utils + +# +# Where to find header files that do not live in the source directory. +# +IPATH=../../.. +IPATH+=../../.. + +# +# The default rule, which causes the MPU example to be built. +# +all: ${COMPILER} +all: ${COMPILER}/mpu_fault.axf + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +# +# The rule to create the target directory. +# +${COMPILER}: + @mkdir -p ${COMPILER} + +# +# Rules for building the MPU example. +# +${COMPILER}/mpu_fault.axf: ${COMPILER}/mpu_fault.o +${COMPILER}/mpu_fault.axf: ${COMPILER}/startup_${COMPILER}.o +${COMPILER}/mpu_fault.axf: ${COMPILER}/uartstdio.o +${COMPILER}/mpu_fault.axf: ${ROOT}/driverlib/${COMPILER}-cm4f/libdriver-cm4f.a +${COMPILER}/mpu_fault.axf: mpu_fault.ld +SCATTERgcc_mpu_fault=mpu_fault.ld +ENTRY_mpu_fault=ResetISR +CFLAGSgcc=-DTARGET_IS_BLIZZARD_RA1 + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/.ccsimportspec b/boards/ek-lm4f120xl/mpu_fault/ccs/.ccsimportspec new file mode 100644 index 0000000..2bef69c --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/.ccsimportspec @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/.ccsproject b/boards/ek-lm4f120xl/mpu_fault/ccs/.ccsproject new file mode 100644 index 0000000..56793f4 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/.cproject b/boards/ek-lm4f120xl/mpu_fault/ccs/.cproject new file mode 100644 index 0000000..6322c5f --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/.cproject @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/.project b/boards/ek-lm4f120xl/mpu_fault/ccs/.project new file mode 100644 index 0000000..2893d12 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/.project @@ -0,0 +1,111 @@ + + + mpu_fault + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -k + + + org.eclipse.cdt.make.core.buildCommand + ${CCS_UTILS_DIR}/bin/gmake + + + org.eclipse.cdt.make.core.buildLocation + ${BuildDirectory} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + mpu_fault.c + 1 + SW_ROOT/boards/ek-lm4f120xl/mpu_fault/mpu_fault.c + + + mpu_fault_ccs.cmd + 1 + SW_ROOT/boards/ek-lm4f120xl/mpu_fault/mpu_fault_ccs.cmd + + + startup_ccs.c + 1 + SW_ROOT/boards/ek-lm4f120xl/mpu_fault/startup_ccs.c + + + utils/uartstdio.c + 1 + SW_ROOT/utils/uartstdio.c + + + + + SW_ROOT + $%7BPARENT-4-PROJECT_LOC%7D + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/.settings/org.eclipse.cdt.codan.core.prefs b/boards/ek-lm4f120xl/mpu_fault/ccs/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.bin b/boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.bin new file mode 100644 index 0000000..9eda234 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.bin differ diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.out b/boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.out new file mode 100644 index 0000000..a3d5fb9 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/ccs/Debug/mpu_fault.out differ diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/macros.ini_initial b/boards/ek-lm4f120xl/mpu_fault/ccs/macros.ini_initial new file mode 100644 index 0000000..588017d --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/macros.ini_initial @@ -0,0 +1 @@ +SW_ROOT = ../../../.. diff --git a/boards/ek-lm4f120xl/mpu_fault/ccs/target_config.ccxml b/boards/ek-lm4f120xl/mpu_fault/ccs/target_config.ccxml new file mode 100644 index 0000000..469eea0 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/ccs/target_config.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.bin b/boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.bin new file mode 100644 index 0000000..88938a4 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.bin differ diff --git a/boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.out b/boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.out new file mode 100644 index 0000000..dfac41d Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/ewarm/Exe/mpu_fault.out differ diff --git a/boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.axf b/boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.axf new file mode 100644 index 0000000..3f757d7 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.axf differ diff --git a/boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.bin b/boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.bin new file mode 100644 index 0000000..bd10968 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/gcc/mpu_fault.bin differ diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.c b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.c new file mode 100644 index 0000000..38ab1aa --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.c @@ -0,0 +1,383 @@ +//***************************************************************************** +// +// mpu_fault.c - MPU example. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/fpu.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" +#include "driverlib/mpu.h" +#include "driverlib/pin_map.h" +#include "driverlib/rom.h" +#include "driverlib/sysctl.h" +#include "utils/uartstdio.h" + +//***************************************************************************** +// +//! \addtogroup example_list +//!

MPU (mpu_fault)

+//! +//! This example application demonstrates the use of the MPU to protect a +//! region of memory from access, and to generate a memory management fault +//! when there is an access violation. +//! +//! UART0, connected to the Stellaris virtual serial port and running at +//! 115,200, 8-N-1, is used to display messages from this application. +// +//***************************************************************************** + + +//***************************************************************************** +// +// Variables to hold the state of the fault status when the fault occurs and +// the faulting address. +// +//***************************************************************************** +static volatile unsigned long g_ulMMAR; +static volatile unsigned long g_ulFaultStatus; + +//***************************************************************************** +// +// A counter to track the number of times the fault handler has been entered. +// +//***************************************************************************** +static volatile unsigned long g_ulMPUFaultCount; + +//***************************************************************************** +// +// A location for storing data read from various addresses. Volatile forces +// the compiler to use it and not optimize the access away. +// +//***************************************************************************** +static volatile unsigned long g_ulValue; + +//***************************************************************************** +// +// The error routine that is called if the driver library encounters an error. +// +//***************************************************************************** +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +//***************************************************************************** +// +// The exception handler for memory management faults, which are caused by MPU +// access violations. This handler will verify the cause of the fault and +// clear the NVIC fault status register. +// +//***************************************************************************** +void +MPUFaultHandler(void) +{ + // + // Preserve the value of the MMAR (the address causing the fault). + // Preserve the fault status register value, then clear it. + // + g_ulMMAR = HWREG(NVIC_MM_ADDR); + g_ulFaultStatus = HWREG(NVIC_FAULT_STAT); + HWREG(NVIC_FAULT_STAT) = g_ulFaultStatus; + + // + // Increment a counter to indicate the fault occurred. + // + g_ulMPUFaultCount++; + + // + // Disable the MPU so that this handler can return and cause no more + // faults. The actual instruction that faulted will be re-executed. + // + ROM_MPUDisable(); +} + +//***************************************************************************** +// +// This example demonstrates how to configure MPU regions for different levels +// of memory protection. The following memory map is set up: +// +// 0000.0000 - 0000.1C00 - rgn 0: executable read-only, flash +// 0000.1C00 - 0000.2000 - rgn 0: no access, flash (disabled sub-region 7) +// 2000.0000 - 2000.4000 - rgn 1: read-write, RAM +// 2000.4000 - 2000.6000 - rgn 2: read-only, RAM (disabled sub-rgn 4 of rgn 1) +// 2000.6000 - 2000.7FFF - rgn 1: read-write, RAM +// 4000.0000 - 4001.0000 - rgn 3: read-write, peripherals +// 4001.0000 - 4002.0000 - rgn 3: no access (disabled sub-region 1) +// 4002.0000 - 4006.0000 - rgn 3: read-write, peripherals +// 4006.0000 - 4008.0000 - rgn 3: no access (disabled sub-region 6, 7) +// E000.E000 - E000.F000 - rgn 4: read-write, NVIC +// 0100.0000 - 0100.FFFF - rgn 5: executable read-only, ROM +// +// The example code will attempt to perform the following operations and check +// the faulting behavior: +// +// - write to flash (should fault) +// - read from the disabled area of flash (should fault) +// - read from the read-only area of RAM (should not fault) +// - write to the read-only section of RAM (should fault) +// +//***************************************************************************** +int +main(void) +{ + unsigned int bFail = 0; + + // + // Enable lazy stacking for interrupt handlers. This allows floating-point + // instructions to be used within interrupt handlers, but at the expense of + // extra stack usage. + // + ROM_FPULazyStackingEnable(); + + // + // Set the clocking to run directly from the crystal. + // + ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | + SYSCTL_XTAL_16MHZ); + + // + // Initialize the UART and write status. + // + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + GPIOPinConfigure(GPIO_PA0_U0RX); + GPIOPinConfigure(GPIO_PA1_U0TX); + ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + UARTStdioInit(0); + UARTprintf("\033[2JMPU example\n"); + + // + // Configure an executable, read-only MPU region for flash. It is a 16 KB + // region with the last 2 KB disabled to result in a 14 KB executable + // region. This region is needed so that the program can execute from + // flash. + // + ROM_MPURegionSet(0, FLASH_BASE, + MPU_RGN_SIZE_16K | MPU_RGN_PERM_EXEC | + MPU_RGN_PERM_PRV_RO_USR_RO | MPU_SUB_RGN_DISABLE_7 | + MPU_RGN_ENABLE); + + // + // Configure a read-write MPU region for RAM. It is a 32 KB region. There + // is a 4 KB sub-region in the middle that is disabled in order to open up + // a hole in which different permissions can be applied. + // + ROM_MPURegionSet(1, SRAM_BASE, + MPU_RGN_SIZE_32K | MPU_RGN_PERM_NOEXEC | + MPU_RGN_PERM_PRV_RW_USR_RW | MPU_SUB_RGN_DISABLE_4 | + MPU_RGN_ENABLE); + + // + // Configure a read-only MPU region for the 4 KB of RAM that is disabled in + // the previous region. This region is used for demonstrating read-only + // permissions. + // + ROM_MPURegionSet(2, SRAM_BASE + 0x4000, + MPU_RGN_SIZE_2K | MPU_RGN_PERM_NOEXEC | + MPU_RGN_PERM_PRV_RO_USR_RO | MPU_RGN_ENABLE); + + // + // Configure a read-write MPU region for peripherals. The region is 512 KB + // total size, with several sub-regions disabled to prevent access to areas + // where there are no peripherals. This region is needed because the + // program needs access to some peripherals. + // + ROM_MPURegionSet(3, 0x40000000, + MPU_RGN_SIZE_512K | MPU_RGN_PERM_NOEXEC | + MPU_RGN_PERM_PRV_RW_USR_RW | MPU_SUB_RGN_DISABLE_1 | + MPU_SUB_RGN_DISABLE_6 | MPU_SUB_RGN_DISABLE_7 | + MPU_RGN_ENABLE); + + // + // Configure a read-write MPU region for access to the NVIC. The region is + // 4 KB in size. This region is needed because NVIC registers are needed + // in order to control the MPU. + // + ROM_MPURegionSet(4, NVIC_BASE, + MPU_RGN_SIZE_4K | MPU_RGN_PERM_NOEXEC | + MPU_RGN_PERM_PRV_RW_USR_RW | MPU_RGN_ENABLE); + + // + // Configure an executable, read-only MPU region for ROM. It is a 64 KB + // region. This region is needed so that ROM library calls work. + // + ROM_MPURegionSet(5, (unsigned long)ROM_APITABLE & 0xFFFF0000, + MPU_RGN_SIZE_64K | MPU_RGN_PERM_EXEC | + MPU_RGN_PERM_PRV_RO_USR_RO | MPU_RGN_ENABLE); + + // + // Need to clear the NVIC fault status register to make sure there is no + // status hanging around from a previous program. + // + g_ulFaultStatus = HWREG(NVIC_FAULT_STAT); + HWREG(NVIC_FAULT_STAT) = g_ulFaultStatus; + + // + // Enable the MPU fault. + // + ROM_IntEnable(FAULT_MPU); + + // + // Enable the MPU. This will begin to enforce the memory protection + // regions. The MPU is configured so that when in the hard fault or NMI + // exceptions, a default map will be used. Neither of these should occur + // in this example program. + // + ROM_MPUEnable(MPU_CONFIG_HARDFLT_NMI); + + // + // Attempt to write to the flash. This should cause a protection fault due + // to the fact that this region is read-only. + // + UARTprintf("Flash write... "); + g_ulMPUFaultCount = 0; + HWREG(0x100) = 0x12345678; + + // + // Verify that the fault occurred, at the expected address. + // + if((g_ulMPUFaultCount == 1) && (g_ulFaultStatus == 0x82) && + (g_ulMMAR == 0x100)) + { + UARTprintf(" OK\n"); + } + else + { + bFail = 1; + UARTprintf("NOK\n"); + } + + // + // The MPU was disabled when the previous fault occurred, so it needs to be + // re-enabled. + // + ROM_MPUEnable(MPU_CONFIG_HARDFLT_NMI); + + // + // Attempt to read from the disabled section of flash, the upper 2 KB of + // the 16 KB region. + // + UARTprintf("Flash read... "); + g_ulMPUFaultCount = 0; + g_ulValue = HWREG(0x3820); + + // + // Verify that the fault occurred, at the expected address. + // + if((g_ulMPUFaultCount == 1) && (g_ulFaultStatus == 0x82) && + (g_ulMMAR == 0x3820)) + { + UARTprintf(" OK\n"); + } + else + { + bFail = 1; + UARTprintf("NOK\n"); + } + + // + // The MPU was disabled when the previous fault occurred, so it needs to be + // re-enabled. + // + ROM_MPUEnable(MPU_CONFIG_HARDFLT_NMI); + + // + // Attempt to read from the read-only area of RAM, the middle 4 KB of the + // 32 KB region. + // + UARTprintf("RAM read... "); + g_ulMPUFaultCount = 0; + g_ulValue = HWREG(0x20004440); + + // + // Verify that the RAM read did not cause a fault. + // + if(g_ulMPUFaultCount == 0) + { + UARTprintf(" OK\n"); + } + else + { + bFail = 1; + UARTprintf("NOK\n"); + } + + // + // The MPU should not have been disabled since the last access was not + // supposed to cause a fault. But if it did cause a fault, then the MPU + // will be disabled, so re-enable it here anyway, just in case. + // + ROM_MPUEnable(MPU_CONFIG_HARDFLT_NMI); + + // + // Attempt to write to the read-only area of RAM, the middle 4 KB of the + // 32 KB region. + // + UARTprintf("RAM write... "); + g_ulMPUFaultCount = 0; + HWREG(0x20004460) = 0xabcdef00; + + // + // Verify that the RAM write caused a fault. + // + if((g_ulMPUFaultCount == 1) && (g_ulFaultStatus == 0x82) && + (g_ulMMAR == 0x20004460)) + { + UARTprintf(" OK\n"); + } + else + { + bFail = 1; + UARTprintf("NOK\n"); + } + + // + // Display the results of the example program. + // + if(bFail) + { + UARTprintf("Failure!\n"); + } + else + { + UARTprintf("Success!\n"); + } + + // + // Disable the MPU, so there are no lingering side effects if another + // program is run. + // + ROM_MPUDisable(); + + // + // Loop forever. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewd b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewd new file mode 100644 index 0000000..b8eeac7 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewd @@ -0,0 +1,614 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewp b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewp new file mode 100644 index 0000000..218dedd --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ewp @@ -0,0 +1,789 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Libraries + + $PROJ_DIR$\..\..\..\driverlib\ewarm-cm4f\Exe\driverlib-cm4f.a + + + + Source + + $PROJ_DIR$\mpu_fault.c + + + $PROJ_DIR$\startup_ewarm.c + + + $PROJ_DIR$\..\..\..\utils\uartstdio.c + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.icf b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.icf new file mode 100644 index 0000000..ccee9c4 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.icf @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// mpu_fault.icf - Linker configuration file for mpu_fault. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0003ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20007fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Indicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place the RAM vector table at the start of SRAM. +// +place at start of SRAM { section VTABLE }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ld b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ld new file mode 100644 index 0000000..5d0fbcb --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.ld @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * mpu_fault.ld - Linker configuration file for mpu_fault. + * + * Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 9453 of the EK-LM4F120XL Firmware Package. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.sct b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.sct new file mode 100644 index 0000000..9fa08ac --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.sct @@ -0,0 +1,47 @@ +;****************************************************************************** +; +; mpu_fault.sct - Linker configuration file for mpu_fault. +; +; Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +; +;****************************************************************************** + +LR_IROM 0x00000000 0x00040000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00040000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00008000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.sgxx b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.sgxx new file mode 100644 index 0000000..2c79b62 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.sgxx differ diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvopt b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvopt new file mode 100644 index 0000000..7ea7e45 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvopt @@ -0,0 +1,303 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mpu_fault + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\rvmdk\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Luminary\LM4F120H5QR.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + lmidk-agdi + -O4614 -S3 -FO29 + + + 0 + DLGTARM + + + + 0 + ARMDBGFLAGS + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\mpu_fault.c + mpu_fault.c + + + 1 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_rvmdk.S + startup_rvmdk.S + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\utils\uartstdio.c + uartstdio.c + + + + + Libraries + 1 + 0 + 0 + + 2 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\driverlib\rvmdk-cm4f\driverlib-cm4f.lib + driverlib-cm4f.lib + + + + + Documentation + 1 + 0 + 0 + + 3 + 5 + 5 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + .\readme.txt + readme.txt + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 0 + 0 + 729 + 300 + + + + + + + 1 + 0 + + 100 + 0 + + + .\readme.txt + 0 + 1 + 1 + + + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvproj b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvproj new file mode 100644 index 0000000..acf5a41 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault.uvproj @@ -0,0 +1,429 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + mpu_fault + 0x4 + ARM-ADS + + + LM4F120H5QR + Texas Instruments + IRAM(0x20000000-0x20007FFF) IROM(0-0x3FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_256 -FS00 -FL040000) + 5919 + LM4Fxxxx.H + + + + + + + + + + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\rvmdk\ + mpu_fault + 1 + 0 + 0 + 1 + 1 + .\rvmdk\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\rvmdk\mpu_fault.bin .\rvmdk\mpu_fault.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 4 + + + + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + BIN\lmidk-agdi.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + rvmdk PART_LM4F120H5QR TARGET_IS_BLIZZARD_RA1 + + ..\..\..;..\..\..; + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + mpu_fault.sct + + + --entry Reset_Handler + + + + + + + + Source + + + mpu_fault.c + 1 + .\mpu_fault.c + + + startup_rvmdk.S + 2 + .\startup_rvmdk.S + + + uartstdio.c + 1 + ..\..\..\utils\uartstdio.c + + + + + Libraries + + + driverlib-cm4f.lib + 4 + ..\..\..\driverlib\rvmdk-cm4f\driverlib-cm4f.lib + + + + + Documentation + + + readme.txt + 5 + .\readme.txt + + + + + + + + diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault_ccs.cmd b/boards/ek-lm4f120xl/mpu_fault/mpu_fault_ccs.cmd new file mode 100644 index 0000000..89e020e --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault_ccs.cmd @@ -0,0 +1,70 @@ +/****************************************************************************** + * + * mpu_fault_ccs.cmd - CCS linker configuration file for mpu_fault. + * + * Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 9453 of the EK-LM4F120XL Firmware Package. + * + *****************************************************************************/ + +--retain=g_pfnVectors + +/* The following command line options are set as part of the CCS project. */ +/* If you are building using the command line, or for some reason want to */ +/* define them here, you can uncomment and modify these lines as needed. */ +/* If you are using CCS for building, it is probably better to make any such */ +/* modifications in your CCS project and leave this file alone. */ +/* */ +/* --heap_size=0 */ +/* --stack_size=256 */ +/* --library=rtsv7M3_T_le_eabi.lib */ + +/* The starting address of the application. Normally the interrupt vectors */ +/* must be located at the beginning of the application. */ +#define APP_BASE 0x00000000 +#define RAM_BASE 0x20000000 + +/* System memory map */ + +MEMORY +{ + /* Application stored in and executes from internal flash */ + FLASH (RX) : origin = APP_BASE, length = 0x00040000 + /* Application uses internal RAM for data */ + SRAM (RWX) : origin = 0x20000000, length = 0x00008000 +} + +/* Section allocation in memory */ + +SECTIONS +{ + .intvecs: > APP_BASE + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .vtable : > RAM_BASE + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} + +__STACK_TOP = __stack + 256; diff --git a/boards/ek-lm4f120xl/mpu_fault/mpu_fault_sourcerygxx.ld b/boards/ek-lm4f120xl/mpu_fault/mpu_fault_sourcerygxx.ld new file mode 100644 index 0000000..fb09767 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/mpu_fault_sourcerygxx.ld @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * mpu_fault_sourcerygxx.ld - Scatter file for Sourcery CodeBench + * + * Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 9453 of the EK-LM4F120XL Firmware Package. + * + *****************************************************************************/ + +/****************************************************************************** + * + * Define the end of the heap space, which determines the beginning of the + * stack space. + * + *****************************************************************************/ +__cs3_heap_end = __cs3_region_end_ram - 256; + +/****************************************************************************** + * + * Define the interrupt handlers used by the application. + * + *****************************************************************************/ +EXTERN(MPUFaultHandler) +__cs3_isr_mpu_fault = MPUFaultHandler; diff --git a/boards/ek-lm4f120xl/mpu_fault/readme.txt b/boards/ek-lm4f120xl/mpu_fault/readme.txt new file mode 100644 index 0000000..2b9f716 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/readme.txt @@ -0,0 +1,28 @@ +MPU + +This example application demonstrates the use of the MPU to protect a +region of memory from access, and to generate a memory management fault +when there is an access violation. + +UART0, connected to the Stellaris virtual serial port and running at +115,200, 8-N-1, is used to display messages from this application. + +------------------------------------------------------------------------------- + +Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + +Texas Instruments (TI) is supplying this software for use solely and +exclusively on TI's microcontroller products. The software is owned by +TI and/or its suppliers, and is protected under applicable copyright +laws. You may not combine this software with "viral" open-source +software in order to form a larger program. + +THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, FOR ANY REASON WHATSOEVER. + +This is part of revision 9453 of the EK-LM4F120XL Firmware Package. diff --git a/boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.axf b/boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.axf new file mode 100644 index 0000000..02cb5ec Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.axf differ diff --git a/boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.bin b/boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.bin new file mode 100644 index 0000000..514c805 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/rvmdk/mpu_fault.bin differ diff --git a/boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.axf b/boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.axf new file mode 100644 index 0000000..68c9216 Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.axf differ diff --git a/boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.bin b/boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.bin new file mode 100644 index 0000000..dac317e Binary files /dev/null and b/boards/ek-lm4f120xl/mpu_fault/sourcerygxx/mpu_fault.bin differ diff --git a/boards/ek-lm4f120xl/mpu_fault/startup_ccs.c b/boards/ek-lm4f120xl/mpu_fault/startup_ccs.c new file mode 100644 index 0000000..eeaa019 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/startup_ccs.c @@ -0,0 +1,298 @@ +//***************************************************************************** +// +// startup_ccs.c - Startup code for use with TI's Code Composer Studio. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern unsigned long __STACK_TOP; + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void MPUFaultHandler(void); + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".intvecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)&__STACK_TOP), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + MPUFaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // CAN2 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // I2S0 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + IntDefaultHandler, // PECI 0 + IntDefaultHandler, // LPC 0 + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + IntDefaultHandler, // Fan 0 + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Jump to the CCS C initialization routine. This will enable the + // floating-point unit as well, so that does not need to be done here. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f120xl/mpu_fault/startup_ewarm.c b/boards/ek-lm4f120xl/mpu_fault/startup_ewarm.c new file mode 100644 index 0000000..243b4d4 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/startup_ewarm.c @@ -0,0 +1,332 @@ +//***************************************************************************** +// +// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, +// version 5. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void MPUFaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static unsigned long pulStack[64] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + MPUFaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // CAN2 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // I2S0 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + IntDefaultHandler, // PECI 0 + IntDefaultHandler, // LPC 0 + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + IntDefaultHandler, // Fan 0 + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + __iar_program_start(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f120xl/mpu_fault/startup_gcc.c b/boards/ek-lm4f120xl/mpu_fault/startup_gcc.c new file mode 100644 index 0000000..751397a --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/startup_gcc.c @@ -0,0 +1,348 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void MPUFaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static unsigned long pulStack[64]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + MPUFaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // CAN2 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // I2S0 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + IntDefaultHandler, // PECI 0 + IntDefaultHandler, // LPC 0 + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + IntDefaultHandler, // Fan 0 + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f120xl/mpu_fault/startup_rvmdk.S b/boards/ek-lm4f120xl/mpu_fault/startup_rvmdk.S new file mode 100644 index 0000000..d13b6a0 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/startup_rvmdk.S @@ -0,0 +1,358 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000100 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; External declaration for the interrupt handler used by the application. +; +;****************************************************************************** + EXTERN MPUFaultHandler + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD MPUFaultHandler ; The MPU fault handler + DCD IntDefaultHandler ; The bus fault handler + DCD IntDefaultHandler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall handler + DCD IntDefaultHandler ; Debug monitor handler + DCD 0 ; Reserved + DCD IntDefaultHandler ; The PendSV handler + DCD IntDefaultHandler ; The SysTick handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD IntDefaultHandler ; UART0 Rx and Tx + DCD IntDefaultHandler ; UART1 Rx and Tx + DCD IntDefaultHandler ; SSI0 Rx and Tx + DCD IntDefaultHandler ; I2C0 Master and Slave + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder 0 + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog timer + DCD IntDefaultHandler ; Timer 0 subtimer A + DCD IntDefaultHandler ; Timer 0 subtimer B + DCD IntDefaultHandler ; Timer 1 subtimer A + DCD IntDefaultHandler ; Timer 1 subtimer B + DCD IntDefaultHandler ; Timer 2 subtimer A + DCD IntDefaultHandler ; Timer 2 subtimer B + DCD IntDefaultHandler ; Analog Comparator 0 + DCD IntDefaultHandler ; Analog Comparator 1 + DCD IntDefaultHandler ; Analog Comparator 2 + DCD IntDefaultHandler ; System Control (PLL, OSC, BO) + DCD IntDefaultHandler ; FLASH Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; Quadrature Encoder 1 + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD IntDefaultHandler ; CAN2 + DCD IntDefaultHandler ; Ethernet + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + DCD IntDefaultHandler ; ADC1 Sequence 0 + DCD IntDefaultHandler ; ADC1 Sequence 1 + DCD IntDefaultHandler ; ADC1 Sequence 2 + DCD IntDefaultHandler ; ADC1 Sequence 3 + DCD IntDefaultHandler ; I2S0 + DCD IntDefaultHandler ; External Bus Interface 0 + DCD IntDefaultHandler ; GPIO Port J + DCD IntDefaultHandler ; GPIO Port K + DCD IntDefaultHandler ; GPIO Port L + DCD IntDefaultHandler ; SSI2 Rx and Tx + DCD IntDefaultHandler ; SSI3 Rx and Tx + DCD IntDefaultHandler ; UART3 Rx and Tx + DCD IntDefaultHandler ; UART4 Rx and Tx + DCD IntDefaultHandler ; UART5 Rx and Tx + DCD IntDefaultHandler ; UART6 Rx and Tx + DCD IntDefaultHandler ; UART7 Rx and Tx + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; I2C2 Master and Slave + DCD IntDefaultHandler ; I2C3 Master and Slave + DCD IntDefaultHandler ; Timer 4 subtimer A + DCD IntDefaultHandler ; Timer 4 subtimer B + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; Timer 5 subtimer A + DCD IntDefaultHandler ; Timer 5 subtimer B + DCD IntDefaultHandler ; Wide Timer 0 subtimer A + DCD IntDefaultHandler ; Wide Timer 0 subtimer B + DCD IntDefaultHandler ; Wide Timer 1 subtimer A + DCD IntDefaultHandler ; Wide Timer 1 subtimer B + DCD IntDefaultHandler ; Wide Timer 2 subtimer A + DCD IntDefaultHandler ; Wide Timer 2 subtimer B + DCD IntDefaultHandler ; Wide Timer 3 subtimer A + DCD IntDefaultHandler ; Wide Timer 3 subtimer B + DCD IntDefaultHandler ; Wide Timer 4 subtimer A + DCD IntDefaultHandler ; Wide Timer 4 subtimer B + DCD IntDefaultHandler ; Wide Timer 5 subtimer A + DCD IntDefaultHandler ; Wide Timer 5 subtimer B + DCD IntDefaultHandler ; FPU + DCD IntDefaultHandler ; PECI 0 + DCD IntDefaultHandler ; LPC 0 + DCD IntDefaultHandler ; I2C4 Master and Slave + DCD IntDefaultHandler ; I2C5 Master and Slave + DCD IntDefaultHandler ; GPIO Port M + DCD IntDefaultHandler ; GPIO Port N + DCD IntDefaultHandler ; Quadrature Encoder 2 + DCD IntDefaultHandler ; Fan 0 + DCD 0 ; Reserved + DCD IntDefaultHandler ; GPIO Port P (Summary or P0) + DCD IntDefaultHandler ; GPIO Port P1 + DCD IntDefaultHandler ; GPIO Port P2 + DCD IntDefaultHandler ; GPIO Port P3 + DCD IntDefaultHandler ; GPIO Port P4 + DCD IntDefaultHandler ; GPIO Port P5 + DCD IntDefaultHandler ; GPIO Port P6 + DCD IntDefaultHandler ; GPIO Port P7 + DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) + DCD IntDefaultHandler ; GPIO Port Q1 + DCD IntDefaultHandler ; GPIO Port Q2 + DCD IntDefaultHandler ; GPIO Port Q3 + DCD IntDefaultHandler ; GPIO Port Q4 + DCD IntDefaultHandler ; GPIO Port Q5 + DCD IntDefaultHandler ; GPIO Port Q6 + DCD IntDefaultHandler ; GPIO Port Q7 + DCD IntDefaultHandler ; GPIO Port R + DCD IntDefaultHandler ; GPIO Port S + DCD IntDefaultHandler ; PWM 1 Generator 0 + DCD IntDefaultHandler ; PWM 1 Generator 1 + DCD IntDefaultHandler ; PWM 1 Generator 2 + DCD IntDefaultHandler ; PWM 1 Generator 3 + DCD IntDefaultHandler ; PWM 1 Fault + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Enable the floating-point unit. This must be done here to handle the + ; case where main() uses floating-point and the function prologue saves + ; floating-point registers (which will fault if floating-point is not + ; enabled). Any configuration of the floating-point unit using + ; DriverLib APIs must be done here prior to the floating-point unit + ; being enabled. + ; + ; Note that this does not use DriverLib since it might not be included + ; in this project. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/boards/ek-lm4f120xl/mpu_fault/startup_sourcerygxx.S b/boards/ek-lm4f120xl/mpu_fault/startup_sourcerygxx.S new file mode 100644 index 0000000..b720839 --- /dev/null +++ b/boards/ek-lm4f120xl/mpu_fault/startup_sourcerygxx.S @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// startup_sourcerygxx.S - Startup code for Sourcery CodeBench. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + + .syntax unified + .thumb + +//***************************************************************************** +// +// Place this code into the .cs3.reset section so that it can be executed prior +// to the startup code in Sourcery CodeBench. +// +//***************************************************************************** + .section .cs3.reset,"x" + +//***************************************************************************** +// +// The reset handler, which overrides the one provided by CS3. +// +//***************************************************************************** + .globl __cs3_reset + .thumb_func +__cs3_reset: + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + movw r0, #0xed88 + movt r0, #0xe000 + ldr r1, [r0] + orr r1, #0x00f00000 + str r1, [r0] + + // + // Branch to the normal CS3 startup code. + // + .extern __cs3_reset_ekc_lm4f232 + ldr r0, =__cs3_reset_ekc_lm4f232 + bx r0 + + // + // Place the literal pool here. + // + .ltorg + + // + // The end of the file. + // + .end -- cgit v1.3.1