From cf0dc0a31634bf18eef97d73fa9640abf0382f08 Mon Sep 17 00:00:00 2001 From: Yuval Adam Date: Thu, 16 May 2013 14:02:38 +0300 Subject: Added stellaris-vga subproject --- boards/ek-lm4f120xl/stellaris-vga/Makefile | 103 ++++++ .../stellaris-vga/gcc/stellaris-vga.axf | Bin 0 -> 67981 bytes .../stellaris-vga/gcc/stellaris-vga.bin | Bin 0 -> 2828 bytes boards/ek-lm4f120xl/stellaris-vga/main.c | 77 +++++ boards/ek-lm4f120xl/stellaris-vga/startup_gcc.c | 344 +++++++++++++++++++++ boards/ek-lm4f120xl/stellaris-vga/stellaris-vga.ld | 33 ++ boards/ek-lm4f120xl/stellaris-vga/vga.S | 213 +++++++++++++ 7 files changed, 770 insertions(+) create mode 100644 boards/ek-lm4f120xl/stellaris-vga/Makefile create mode 100755 boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.axf create mode 100755 boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.bin create mode 100644 boards/ek-lm4f120xl/stellaris-vga/main.c create mode 100644 boards/ek-lm4f120xl/stellaris-vga/startup_gcc.c create mode 100644 boards/ek-lm4f120xl/stellaris-vga/stellaris-vga.ld create mode 100644 boards/ek-lm4f120xl/stellaris-vga/vga.S diff --git a/boards/ek-lm4f120xl/stellaris-vga/Makefile b/boards/ek-lm4f120xl/stellaris-vga/Makefile new file mode 100644 index 0000000..283c57d --- /dev/null +++ b/boards/ek-lm4f120xl/stellaris-vga/Makefile @@ -0,0 +1,103 @@ +#****************************************************************************** +# +# Makefile - Rules for building the Project Zero Example. +# +# Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +# Software License Agreement +# +# Texas Instruments (TI) is supplying this software for use solely and +# exclusively on TI's microcontroller products. The software is owned by +# TI and/or its suppliers, and is protected under applicable copyright +# laws. You may not combine this software with "viral" open-source +# software in order to form a larger program. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, FOR ANY REASON WHATSOEVER. +# +# This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +# +#****************************************************************************** + +# +# Defines the part type that this project uses. +# +PART=LM4F120H5QR + +# +# Set the processor variant. +# +VARIANT=cm4f + +# +# The base directory for StellarisWare. +# +ROOT=../../.. + +# +# Include the common make definitions. +# +include ${ROOT}/makedefs + +# +# Where to find source files that do not live in this directory. +# +VPATH=${ROOT}/boards/ek-lm4f120xl/drivers +VPATH+=${ROOT}/utils + +# +# Where to find header files that do not live in the source directory. +# +IPATH=.. +IPATH+=${ROOT} + +# +# The default rule, which causes the Project Zero Example to be built. +# +all: ${COMPILER} +all: ${COMPILER}/stellaris-vga.axf + +# +# The rule to clean out all the build products. +# +clean: + @rm -rf ${COMPILER} ${wildcard *~} + +flash: + lm4flash gcc/stellaris-vga.bin + +debug: clean +debug: CFLAGS += -g -D DEBUG +debug: ${COMPILER} +debug: ${COMPILER}/stellaris-vga.axf +debug: + ../../scripts/debug_nemiver.sh + + +# +# The rule to create the target directory. +# +${COMPILER}: + @mkdir -p ${COMPILER} + +# +# Rules for building the Project Zero Example. +# +${COMPILER}/stellaris-vga.axf: ${COMPILER}/main.o +${COMPILER}/stellaris-vga.axf: ${COMPILER}/startup_gcc.o +${COMPILER}/stellaris-vga.axf: ${COMPILER}/vga.o +${COMPILER}/stellaris-vga.axf: ${ROOT}/driverlib/${COMPILER}-cm4f/libdriver-cm4f.a +${COMPILER}/stellaris-vga.axf: stellaris-vga.ld +SCATTERgcc_stellaris-vga=stellaris-vga.ld +ENTRY_stellaris-vga=ResetISR +CFLAGSgcc=-DTARGET_IS_BLIZZARD_RA2 + +# +# Include the automatically generated dependency files. +# +ifneq (${MAKECMDGOALS},clean) +-include ${wildcard ${COMPILER}/*.d} __dummy__ +endif diff --git a/boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.axf b/boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.axf new file mode 100755 index 0000000..613751e Binary files /dev/null and b/boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.axf differ diff --git a/boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.bin b/boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.bin new file mode 100755 index 0000000..1e0c024 Binary files /dev/null and b/boards/ek-lm4f120xl/stellaris-vga/gcc/stellaris-vga.bin differ diff --git a/boards/ek-lm4f120xl/stellaris-vga/main.c b/boards/ek-lm4f120xl/stellaris-vga/main.c new file mode 100644 index 0000000..81554c7 --- /dev/null +++ b/boards/ek-lm4f120xl/stellaris-vga/main.c @@ -0,0 +1,77 @@ +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/fpu.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" +#include "driverlib/pin_map.h" +#include "driverlib/rom.h" +#include "driverlib/sysctl.h" +#include "driverlib/timer.h" +#include "utils/uartstdio.h" + +void Timer0IntHandlerC() +{ + TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT); + // TIMER0_BASE 0x40030000 + // TIMER_TIMA_TIMEOUT 0x00000001 + // TIMER_O_ICR 0x00000024 + + // update this reg 0x40030024 = 0x00000001 + + __asm__("nop"); +} + +void main() +{ + /* run at 40 mhz */ + SysCtlClockSet(SYSCTL_SYSDIV_5 | + SYSCTL_USE_PLL | + SYSCTL_OSC_MAIN | + SYSCTL_XTAL_16MHZ); + + /* enable led */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1); + GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2); + GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3); + + /* enable vga rgb ping */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); + GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_1); // r + GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_2); // g + GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_3); // b + GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_4); // i + + /* enable vga sync pins */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0); // vsync + GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_1); // hsync + + /* enable & configure timer + interrupt */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); + IntMasterEnable(); + TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC); + TimerLoadSet(TIMER0_BASE, + TIMER_A, + 1056); /* 26.4us (1056 cycles @ 40 mhz) */ + IntEnable(INT_TIMER0A); + TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT); + TimerEnable(TIMER0_BASE, TIMER_A); + + + while (1) + { + /* blink led */ + int i = 0xffff; + + +while(i--); + GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 0xff); + SysCtlDelay(SysCtlClockGet() / 100); +while(i--); + GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 0); + SysCtlDelay(SysCtlClockGet() / 100); + } +} diff --git a/boards/ek-lm4f120xl/stellaris-vga/startup_gcc.c b/boards/ek-lm4f120xl/stellaris-vga/startup_gcc.c new file mode 100644 index 0000000..7535b67 --- /dev/null +++ b/boards/ek-lm4f120xl/stellaris-vga/startup_gcc.c @@ -0,0 +1,344 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 9453 of the EK-LM4F120XL Firmware Package. +// +//***************************************************************************** + +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +static unsigned long pulStack[64]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +extern void Timer0IntHandler(void); +extern void Timer0IntHandlerC(void); + +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + Timer0IntHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // CAN2 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // I2S0 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // Wide Timer 0 subtimer A + IntDefaultHandler, // Wide Timer 0 subtimer B + IntDefaultHandler, // Wide Timer 1 subtimer A + IntDefaultHandler, // Wide Timer 1 subtimer B + IntDefaultHandler, // Wide Timer 2 subtimer A + IntDefaultHandler, // Wide Timer 2 subtimer B + IntDefaultHandler, // Wide Timer 3 subtimer A + IntDefaultHandler, // Wide Timer 3 subtimer B + IntDefaultHandler, // Wide Timer 4 subtimer A + IntDefaultHandler, // Wide Timer 4 subtimer B + IntDefaultHandler, // Wide Timer 5 subtimer A + IntDefaultHandler, // Wide Timer 5 subtimer B + IntDefaultHandler, // FPU + IntDefaultHandler, // PECI 0 + IntDefaultHandler, // LPC 0 + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + IntDefaultHandler, // Quadrature Encoder 2 + IntDefaultHandler, // Fan 0 + 0, // Reserved + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // PWM 1 Generator 0 + IntDefaultHandler, // PWM 1 Generator 1 + IntDefaultHandler, // PWM 1 Generator 2 + IntDefaultHandler, // PWM 1 Generator 3 + IntDefaultHandler // PWM 1 Fault +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the floating-point unit. This must be done here to handle the + // case where main() uses floating-point and the function prologue saves + // floating-point registers (which will fault if floating-point is not + // enabled). Any configuration of the floating-point unit using DriverLib + // APIs must be done here prior to the floating-point unit being enabled. + // + // Note that this does not use DriverLib since it might not be included in + // this project. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/boards/ek-lm4f120xl/stellaris-vga/stellaris-vga.ld b/boards/ek-lm4f120xl/stellaris-vga/stellaris-vga.ld new file mode 100644 index 0000000..80efb56 --- /dev/null +++ b/boards/ek-lm4f120xl/stellaris-vga/stellaris-vga.ld @@ -0,0 +1,33 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/boards/ek-lm4f120xl/stellaris-vga/vga.S b/boards/ek-lm4f120xl/stellaris-vga/vga.S new file mode 100644 index 0000000..286d954 --- /dev/null +++ b/boards/ek-lm4f120xl/stellaris-vga/vga.S @@ -0,0 +1,213 @@ + .file "vga.S" + + .data + .align 2 + .globl LineCount + +LineCount: .word 0 + + .text + .align 2 + .globl Timer0IntHandler + .type Timer0IntHandler, %function + +Timer0IntHandler: + @ horizontal timing + @ hfp 40 (1-40) + @ hsp 128 (41-168) + @ hbp 88 (169-256) + @ hpx 800 (257-1056) + @ total = 1056 + + @ vertical timing + @ vsp 4 (1-4) + @ vbp 23 (5-27) + @ vln 600 (28-627) + @ vfp 1 (628) + @ total = 628 + + @ ********* + @ ** hfp ** [40 cycles] + @ ********* + + @ prologue [3 cycles] + push {r3, lr} + + @ save regs [7 cycles] + push {r1, r2, r3, r4, r5, r6} + + @ clear interrupt timer [5 cycles] + mov r1, #1 @ TIMER_TIMA_TIMEOUT + ldr r0, =0x40030000 @ TIMER0_BASE + str r1, [r0, #0x24] @ *(TIMER0_BASE + TIMER_O_ICR) = TIMER_TIMA_TIMEOUT + + @ ptr to GPIO_PORTB_BASE in r0 [3 cycles] + @ (this will be persisted) + ldr r0, =0x40005000 @ GPIO_PORTB_BASE + nop + + @ ptr to GPIO_PORTB_BASE in r1 [3 cycles] + @ (this will be persisted) + ldr r1, =0x40024000 @ GPIO_PORTE_BASE + nop + + @ ptr to line counter [3 cycles] + @ (this will be persisted) + ldr r2, =LineCount + nop + + @ waste cycles [16 cycles] + mov r3, #0 +loop_0: @ {3*4-1=11 cycles} + add r3, #1 + cmp r3, #3 + bne loop_0 @2 + + @ hsync setup [4 cycles] + ldrb r3,[r0] + mov r4, #0xfd + and r3, r4 + + @ ********* + @ ** hsp ** [128 cycles] + @ ********* + + @ set hsync low [2 cycles] + str r3, [r0] @ GPIO_PIN_1 clear + + @ reset line counter [8 cycles] + ldr r4, =629 + cmp r3, r4 + beq .Lline_reset + nop + nop + b .Lno_reset +.Lline_reset: + mov r3, #0 + str r3, [r2] +.Lno_reset: + + @ inc line counter [5 cycles] + ldr r3, [r2] + add r3, #1 + str r3, [r2] + + @ vsync on at line 1 [9 cycles] + cmp r3, #1 @ now at start of vsp + beq .Lvsync_on + nop + nop + nop + nop + nop + b .Lcont_0 +.Lvsync_on: @ {6 cycles} + ldrb r3,[r0] + mov r4, #0xfe + and r3, r4 + str r3, [r0] @ GPIO_PIN_0 clear +.Lcont_0: + + @ vsync off at line 5 [11 cycles] + ldr r3, [r2] + cmp r3, #5 + beq .Lvsync_off + nop + nop + nop + nop + nop + b .Lcont_1 +.Lvsync_off: @ {6 cycles} + ldrb r3,[r0] + mov r4, #1 + orr r3, r4 + str r3, [r0] @ GPIO_PIN_0 set +.Lcont_1: + + @ activate pixels on line 28 [6 cycles] + ldr r3, [r2] + cmp r3, #28 + beq .Lactivate_px + b .Lcont_2 +.Lactivate_px: @ {1 cycle} + mov r6, #1 +.Lcont_2: + + @ deactivate pixels on line 628 [7 cycles] + ldr r3, [r2] + ldr r4, =628 + cmp r3, r4 + beq .Ldeactivate_px + b .Lcont_3 +.Ldeactivate_px: @ {1 cycle} + mov r6, #0 +.Lcont_3: + + @ waste cycles [74 cycles] + mov r0, #0 +.Lwasteloop_1: @ {18*4-1=71 cycles} + add r0, #1 + cmp r0, #14 + bne .Lwasteloop_1 @2 + nop + nop + + @ hsync off [6 cycles] + ldrb r3,[r0] + mov r4, #2 + orr r3, r4 @ GPIO_PIN_1 set + str r3, [r0] + + @ ********* + @ ** hbp ** [88 cycles] + @ ********* + @ exit on vblank [3 cycles] + cmp r6, #0 + beq end + nop + + @ waste cycles [83 cycles] + mov r3, #0 +.Lwasteloop_2: @ {20*4-1=79 cycles} + add r3, #1 + cmp r3, #19 + bne .Lwasteloop_2 + nop + nop + nop + + @ set up color counter [1 cycle] + mov r4, #0 + + @ set initial rgb [1 cycle] + mov r3, #0 + + @ ********* + @ ** hpx ** [800 cycles] + @ ********* + + @ output pattern [800 cycles] +.Lcolor_loop: @ {100*8-1=799} + str r3, [r1] + add r3, #1 + add r4, #1 + cmp r4, #100 + nop + bne .Lcolor_loop + nop + + @ ********* + + @ horizontal blanking + mov r3, #0 + str r3, [r1] + +end: + @ restore regs [7 cycles] + pop {r1, r2, r3, r4, r5, r6} + + @ return from interrupt [4 cycles] + pop {r3, pc} + .word 0x40030000 @addmi r0, r3, r0 + -- cgit v1.3.1