diff options
| author | Yuval Adam <_@yuv.al> | 2021-04-23 15:11:59 +0300 |
|---|---|---|
| committer | Yuval Adam <_@yuv.al> | 2021-04-23 15:11:59 +0300 |
| commit | 7641e0d8e75ac5de285935311e27c4529e69e154 (patch) | |
| tree | e3835ce1272512f65e53256f055ddee8a6b6dd45 /src | |
| parent | a3ec09ac29b26ebd1cc1235f7ecdcd6a3d74cd60 (diff) | |
Add more r82xx functions and cleanup some errors
Diffstat (limited to 'src')
| -rw-r--r-- | src/tuners/fc0013.rs | 2 | ||||
| -rw-r--r-- | src/tuners/r820t.rs | 82 | ||||
| -rw-r--r-- | src/usb.rs | 2 |
3 files changed, 66 insertions, 20 deletions
diff --git a/src/tuners/fc0013.rs b/src/tuners/fc0013.rs index d486f87..c3683e1 100644 --- a/src/tuners/fc0013.rs +++ b/src/tuners/fc0013.rs @@ -41,7 +41,7 @@ impl Tuner for FC0013 { unimplemented!() } - fn set_bandwidth(&self, _bw: u32, _handle: &RtlSdrDeviceHandle) { + fn set_bandwidth(&self, _bw: u16, _rate: u32, _handle: &RtlSdrDeviceHandle) { unimplemented!() } diff --git a/src/tuners/r820t.rs b/src/tuners/r820t.rs index c083a05..1cd3d0e 100644 --- a/src/tuners/r820t.rs +++ b/src/tuners/r820t.rs @@ -8,7 +8,7 @@ const I2C_ADDR: u8 = 0x34; const CHECK_ADDR: u8 = 0x00; const CHECK_VAL: u8 = 0x69; const IF_FREQ: u32 = 3570000; -const REG_SHADOW_START: u8 = 5; +const REG_SHADOW_START: usize = 5; const NUM_REGS: usize = 30; const NUM_IMR: usize = 5; const IMR_TRIAL: u8 = 9; @@ -36,22 +36,6 @@ enum XtalCapValue { XtalHighCap0P, } -pub struct R820T { - pub device: TunerInfo, - regs: [u8; NUM_REGS], - buf: [u8; NUM_REGS + 1], - xtal_cal_sel: XtalCapValue, - pll: u16, // kHz - int_freq: u32, - fil_cal_code: u8, - input: u8, - has_lock: i16, // bool? - init_done: i16, // bool? - delsys: u32, - tuner_type: TunerType, - bw: u32, // MHz -} - pub struct FreqRange { freq: u32, open_d: u8, @@ -70,6 +54,22 @@ pub struct Config { use_predetect: i16, // bool? } +pub struct R820T { + pub device: TunerInfo, + regs: [u8; NUM_REGS], + buf: [u8; NUM_REGS + 1], + xtal_cal_sel: XtalCapValue, + pll: u16, // kHz + int_freq: u32, + fil_cal_code: u8, + input: u8, + has_lock: i16, // bool? + init_done: i16, // bool? + delsys: u32, + tuner_type: TunerType, + bw: u32, // MHz +} + pub const TUNER_INFO: TunerInfo = TunerInfo { id: TUNER_ID, name: TUNER_NAME, @@ -122,10 +122,56 @@ const XTAL_CAPS: [(u8, XtalCapValue); 5] = [ impl R820T { pub fn new(handle: &RtlSdrDeviceHandle) -> R820T { - let tuner = R820T { device: TUNER_INFO }; + let tuner = R820T { + device: TUNER_INFO, + regs: [u8; NUM_REGS], + buf: [u8; NUM_REGS + 1], + xtal_cal_sel: XtalCapValue::XtalHighCap0P, + pll: u16, // kHz + int_freq: u32, + fil_cal_code: u8, + input: u8, + has_lock: i16, // bool? + init_done: i16, // bool? + delsys: u32, + tuner_type: TunerType, + bw: u32, // MHz + }; tuner.init(handle); tuner } + + fn shadow_store(&self, reg: u8, val: u8, len: usize) { + let r = reg as usize - REG_SHADOW_START; + if r < 0 { + len = len + r; + } + } + + fn write(&self, reg: u8, val: u8) -> u8 {} + + fn write_reg() {} + + fn read_cache_reg(&self, reg: u8) -> Option<u8> { + let reg: usize = reg as usize - REG_SHADOW_START; + match reg >= 0 && reg < NUM_REGS { + true => Some(self.regs[reg]), + false => None, + } + } + + fn write_reg_mask(&self, reg: u8, val: u8, bit_mask: u8) -> u8 { + let rc = self.read_cache_reg(reg).unwrap(); + let val = (rc & !bit_mask) | (val & bit_mask); + self.write(reg, val) + } + + fn bitrev(byte: usize) -> u8 { + const lut: [u8; 16] = [ + 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf, + ]; + (lut[byte & 0xf] << 4) | lut[byte >> 4] + } } impl Drop for R820T { @@ -326,7 +326,7 @@ impl RtlSdrDeviceHandle { info!("Exact sample rate is: {} Hz", real_rate); self.set_i2c_repeater(true); - self.tuner.as_ref().unwrap().set_bw(real_rate as u32, &self); + // self.tuner.as_ref().unwrap().set_bw(real_rate as u32, &self); self.set_i2c_repeater(false); let mut tmp: u16 = (rsamp_ratio >> 16).try_into().unwrap(); |
