From 7ebe66c198cc1f76d55bd42d81ae724f74b832a9 Mon Sep 17 00:00:00 2001 From: "Lukas F. Hartmann" Date: Wed, 7 Sep 2022 06:23:35 +0200 Subject: [PATCH 3/6] lcdif-fix-pcie-interference --- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 34 ++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 3bcc9c0..5b5b01f 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -303,7 +303,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, mxsfb_set_formats(mxsfb, bus_format); - clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); + clk_set_rate(mxsfb->clk, m->crtc_clock * 660); mxsfb_set_mode(mxsfb, bus_flags); } @@ -662,12 +662,44 @@ static const uint64_t mxsfb_modifiers[] = { * Initialization */ +void imx8mq_pcie_qos_for_lcdif(void) +{ + void __iomem *qosc = ioremap(0x307f0000, 0x2100); + // clock and unlock QoSC registers + writel(0x0, qosc); + writel(0x1, qosc); + writel(0x0, qosc+0x60); + + // limit number of outstanding transactions for PCIe1 + writel(0x0, qosc+0x1000); + writel(0x1, qosc+0x1000); + writel(0x01010100, qosc+0x1050); + writel(0x01010100, qosc+0x1060); + writel(0x01010100, qosc+0x1070); + writel(0x1, qosc+0x1000); + + // limit number of outstanding transactions for PCIe2 + writel(0x0, qosc+0x2000); + writel(0x1, qosc+0x2000); + writel(0x01010100, qosc+0x2050); + writel(0x01010100, qosc+0x2060); + writel(0x01010100, qosc+0x2070); + writel(0x1, qosc+0x2000); + + iounmap(qosc); +} + int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb) { struct drm_encoder *encoder = &mxsfb->encoder; struct drm_crtc *crtc = &mxsfb->crtc; int ret; + /* + FIXME Workaround to fix PCIe interfering with LCDIF refresh (MNT Reform) + */ + imx8mq_pcie_qos_for_lcdif(); + drm_plane_helper_add(&mxsfb->planes.primary, &mxsfb_plane_primary_helper_funcs); ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1, -- 2.39.0