From e33e36ae11c7acef805335406c72558e595a08b4 Mon Sep 17 00:00:00 2001 From: Yuval Adam <_@yuv.al> Date: Fri, 29 Aug 2025 20:29:49 +0200 Subject: Cleanup imports and names --- 99-alchitry-xilinx.rules | 2 +- README.md | 8 ++-- blinky.py | 21 +++++----- platform_alchitry_pt.py | 98 ------------------------------------------- platform_alchitry_pt_v2.py | 101 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 116 insertions(+), 114 deletions(-) delete mode 100644 platform_alchitry_pt.py create mode 100644 platform_alchitry_pt_v2.py diff --git a/99-alchitry-xilinx.rules b/99-alchitry-xilinx.rules index 4b443f7..9c7a65c 100644 --- a/99-alchitry-xilinx.rules +++ b/99-alchitry-xilinx.rules @@ -1,4 +1,4 @@ -# Alchitry Pt v2 and Xilinx programming cables udev rules +# Alchitry Pt V2 and Xilinx programming cables udev rules # Install to /etc/udev/rules.d/ and run: sudo udevadm control --reload-rules && sudo udevadm trigger # FTDI FT2232 (used by Alchitry boards) diff --git a/README.md b/README.md index 1a3367b..fbbb1fb 100644 --- a/README.md +++ b/README.md @@ -1,13 +1,13 @@ -# Hello Alchitry Pt v2 +# Hello Alchitry Pt V2 -A basic Amaranth HDL blinky example for the Alchitry Pt v2 development board with XC7A100T-2FGG484I FPGA. +A basic Amaranth HDL blinky example for the Alchitry Pt V2 development board with XC7A100T-2FGG484I FPGA. ## Requirements - Python 3.13+ - uv package manager - Xilinx Vivado (with `vivado` command in PATH) -- Alchitry Pt v2 board connected via USB +- Alchitry Pt V2 board connected via USB ## Setup @@ -58,7 +58,7 @@ platform.build(Blinky(), do_program=False) ## Files - `blinky.py` - Main blinky example that blinks LED 0 -- `platform_alchitry_pt.py` - Alchitry Pt v2 platform definition with official pin mappings +- `platform_alchitry_pt.py` - Alchitry Pt V2 platform definition with official pin mappings - `pyproject.toml` - Project dependencies - `99-alchitry-xilinx.rules` - udev rules for USB programming access diff --git a/blinky.py b/blinky.py index 424bf5f..d43d466 100644 --- a/blinky.py +++ b/blinky.py @@ -1,29 +1,28 @@ -#!/usr/bin/env python3 - -from amaranth import * +from amaranth import Elaboratable, Module, Signal from amaranth.build import Platform -from platform_alchitry_pt import AlchitryPtPlatform + +from platform_alchitry_pt_v2 import AlchitryPtV2Platform class Blinky(Elaboratable): def elaborate(self, platform: Platform) -> Module: m = Module() - + # Get the LED pins led = platform.request("led", 0) - + # Create a counter for timing counter = Signal(24) - + # Increment counter every clock cycle m.d.sync += counter.eq(counter + 1) - + # Connect the MSB of counter to LED (blinks at ~12Hz at 100MHz) m.d.comb += led.o.eq(counter[-1]) - + return m if __name__ == "__main__": - platform = AlchitryPtPlatform() - platform.build(Blinky(), do_program=True) \ No newline at end of file + platform = AlchitryPtV2Platform() + platform.build(Blinky(), do_program=True) diff --git a/platform_alchitry_pt.py b/platform_alchitry_pt.py deleted file mode 100644 index d7e5f0e..0000000 --- a/platform_alchitry_pt.py +++ /dev/null @@ -1,98 +0,0 @@ -from amaranth.build import * -from amaranth.vendor import XilinxPlatform - - -__all__ = ["AlchitryPtPlatform"] - - -class AlchitryPtPlatform(XilinxPlatform): - device = "xc7a100t" - package = "fgg484" - speed = "2" - default_clk = "clk100" - - resources = [ - # 100MHz clock - using official pin from Alchitry Labs - Resource("clk100", 0, Pins("W19", dir="i"), - Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")), - - # LEDs - official pins from Alchitry Labs - Resource("led", 0, Pins("P19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 1, Pins("P20", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 2, Pins("T21", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 3, Pins("R19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 4, Pins("V22", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 5, Pins("U21", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 6, Pins("T20", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - Resource("led", 7, Pins("W20", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - - # Reset button - official pin from Alchitry Labs - Resource("rst_n", 0, Pins("N15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")), - - # A-Bank IO pins - official pins from Alchitry Labs (subset for convenience) - Resource("io", 0, Pins("AB22", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A3 - Resource("io", 1, Pins("AB21", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A5 - Resource("io", 2, Pins("E3", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A9 - Resource("io", 3, Pins("F3", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A11 - Resource("io", 4, Pins("M2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A15 - Resource("io", 5, Pins("M3", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A17 - Resource("io", 6, Pins("J6", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A21 - Resource("io", 7, Pins("K6", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A23 - Resource("io", 8, Pins("AB18", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A4 - Resource("io", 9, Pins("AA18", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A6 - Resource("io", 10, Pins("N2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A10 - Resource("io", 11, Pins("P2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A12 - Resource("io", 12, Pins("L1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A16 - Resource("io", 13, Pins("M1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A18 - Resource("io", 14, Pins("D2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A22 - Resource("io", 15, Pins("E2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A24 - - # B-Bank IO pins - official pins from Alchitry Labs (subset) - Resource("io", 16, Pins("AB13", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B3 - Resource("io", 17, Pins("AA13", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B5 - Resource("io", 18, Pins("AB12", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B9 - Resource("io", 19, Pins("AB11", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B11 - Resource("io", 20, Pins("AA11", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B4 - Resource("io", 21, Pins("AA10", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B6 - Resource("io", 22, Pins("Y14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B10 - Resource("io", 23, Pins("W14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B12 - - # C-Bank IO pins - official pins from Alchitry Labs - Resource("io", 24, Pins("U18", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C29 - Resource("io", 25, Pins("U17", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C31 - Resource("io", 26, Pins("V2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C33 - Resource("io", 27, Pins("U2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C35 - Resource("io", 28, Pins("Y1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C30 - Resource("io", 29, Pins("W1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C32 - Resource("io", 30, Pins("R14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C34 - Resource("io", 31, Pins("P14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C36 - ] - - connectors = [] - - def toolchain_program(self, products, name, **kwargs): - import subprocess - import os - - with products.extract("{}.bit".format(name)) as bitstream_filename: - # Create TCL script for programming - tcl_content = f""" -open_hw_manager -connect_hw_server -open_hw_target -set_property PROGRAM.FILE {{{bitstream_filename}}} [get_hw_devices xc7a100t_0] -set_property PROBES.FILE {{}} [get_hw_devices xc7a100t_0] -set_property FULL_PROBES.FILE {{}} [get_hw_devices xc7a100t_0] -current_hw_device [get_hw_devices xc7a100t_0] -program_hw_devices [get_hw_devices xc7a100t_0] -close_hw_manager -exit -""" - tcl_script = "program_fpga.tcl" - tcl_full_path = os.path.join("build", tcl_script) - with open(tcl_full_path, "w") as f: - f.write(tcl_content) - - # Run vivado to program the FPGA - subprocess.run(["vivado", "-mode", "batch", "-source", tcl_script], - cwd="build", check=True) \ No newline at end of file diff --git a/platform_alchitry_pt_v2.py b/platform_alchitry_pt_v2.py new file mode 100644 index 0000000..b2760d5 --- /dev/null +++ b/platform_alchitry_pt_v2.py @@ -0,0 +1,101 @@ +from amaranth.build import Resource, Pins, Attrs, Clock +from amaranth.vendor import XilinxPlatform + + +__all__ = ["AlchitryPtV2Platform"] + + +class AlchitryPtV2Platform(XilinxPlatform): + device = "xc7a100t" + package = "fgg484" + speed = "2" + default_clk = "clk100" + + resources = [ + # 100MHz clock - using official pin from Alchitry Labs + Resource( + "clk100", + 0, + Pins("W19", dir="i"), + Clock(100e6), + Attrs(IOSTANDARD="LVCMOS33"), + ), + # LEDs - official pins from Alchitry Labs + Resource("led", 0, Pins("P19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 1, Pins("P20", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 2, Pins("T21", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 3, Pins("R19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 4, Pins("V22", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 5, Pins("U21", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 6, Pins("T20", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("led", 7, Pins("W20", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), + # Reset button - official pin from Alchitry Labs + Resource("rst_n", 0, Pins("N15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")), + # A-Bank IO pins - official pins from Alchitry Labs (subset for convenience) + Resource("io", 0, Pins("AB22", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A3 + Resource("io", 1, Pins("AB21", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A5 + Resource("io", 2, Pins("E3", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A9 + Resource("io", 3, Pins("F3", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A11 + Resource("io", 4, Pins("M2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A15 + Resource("io", 5, Pins("M3", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A17 + Resource("io", 6, Pins("J6", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A21 + Resource("io", 7, Pins("K6", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A23 + Resource("io", 8, Pins("AB18", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A4 + Resource("io", 9, Pins("AA18", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A6 + Resource("io", 10, Pins("N2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A10 + Resource("io", 11, Pins("P2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A12 + Resource("io", 12, Pins("L1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A16 + Resource("io", 13, Pins("M1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A18 + Resource("io", 14, Pins("D2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A22 + Resource("io", 15, Pins("E2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # A24 + # B-Bank IO pins - official pins from Alchitry Labs (subset) + Resource("io", 16, Pins("AB13", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B3 + Resource("io", 17, Pins("AA13", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B5 + Resource("io", 18, Pins("AB12", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B9 + Resource("io", 19, Pins("AB11", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B11 + Resource("io", 20, Pins("AA11", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B4 + Resource("io", 21, Pins("AA10", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B6 + Resource("io", 22, Pins("Y14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B10 + Resource("io", 23, Pins("W14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # B12 + # C-Bank IO pins - official pins from Alchitry Labs + Resource("io", 24, Pins("U18", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C29 + Resource("io", 25, Pins("U17", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C31 + Resource("io", 26, Pins("V2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C33 + Resource("io", 27, Pins("U2", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C35 + Resource("io", 28, Pins("Y1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C30 + Resource("io", 29, Pins("W1", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C32 + Resource("io", 30, Pins("R14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C34 + Resource("io", 31, Pins("P14", dir="io"), Attrs(IOSTANDARD="LVCMOS33")), # C36 + ] + + connectors = [] + + def toolchain_program(self, products, name, **kwargs): + import subprocess + import os + + with products.extract("{}.bit".format(name)) as bitstream_filename: + # Create TCL script for programming + tcl_content = f""" +open_hw_manager +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {{{bitstream_filename}}} [get_hw_devices xc7a100t_0] +set_property PROBES.FILE {{}} [get_hw_devices xc7a100t_0] +set_property FULL_PROBES.FILE {{}} [get_hw_devices xc7a100t_0] +current_hw_device [get_hw_devices xc7a100t_0] +program_hw_devices [get_hw_devices xc7a100t_0] +close_hw_manager +exit +""" + tcl_script = "program_fpga.tcl" + tcl_full_path = os.path.join("build", tcl_script) + with open(tcl_full_path, "w") as f: + f.write(tcl_content) + + # Run vivado to program the FPGA + subprocess.run( + ["vivado", "-mode", "batch", "-source", tcl_script], + cwd="build", + check=True, + ) -- cgit v1.3.1